74VCX16500 (Fairchild Semiconductor)
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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March 1998
Revised April 1999
74VCX16500
Low Voltage 18-Bit Universal Bus Transceivers with
3.6V Tolerant Inputs and Outputs
General Description
Features
The VCX16500 is an 18-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (A to B, B to A)
2.9 ns max for 3.0V to 3.6V VCC
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
3.5 ns max for 2.3V to 2.7V VCC
7.0 ns max for 1.65V to 1.95V VCC
s Power-down high impedance inputs and outputs
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
Data flow for B to A is similar to that of A to B but uses
±18 mA @ 2.3V VCC
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
±6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
The VCX16500 is designed for low voltage (1.65V to 3.6V) s Latchup performance exceeds 300 mA
VCC applications with I/O capability up to 3.6V.
s ESD performance:
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The 74VCX16500 is fabricated with an advanced CMOS
Human body model > 2000V
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OEBA should be tied to VCC through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistors; the minimum value of
the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16500MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS500089.prf
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74VCX16500 (Fairchild Semiconductor)
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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Connection Diagram
Pin Descriptions
Pin Names
Description
OEAB
Output Enable Input for A to B Direction
(Active HIGH)
OEBA
Output Enable Input for B to A Direction
(Active LOW)
LEAB, LEBA Latch Enable Inputs
CLKAB,
CLKBA
Clock Inputs
A1–A18
B1–B18
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Function Table (Note 2)
Inputs
Outputs
OEAB LEAB CLKAB An
Bn
LXXX
Z
HHX L
L
HHXH
H
HLL
L
HLH
H
H L H X B0 (Note 3)
H L L X B0 (Note 4)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,
LEBA and CLKBA. OEBA is active LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
Note 4: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
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74VCX16500 (Fairchild Semiconductor)
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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Logic Diagram
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74VCX16500 (Fairchild Semiconductor)
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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Absolute Maximum Ratings(Note 5)
Supply Voltage (VCC)
DC Input Voltage (VI)
Output Voltage (VO)
Outputs 3-STATE
Outputs Active (Note 6)
DC Input Diode Current (IIK) VI < 0V
DC Output Diode Current (IOK)
VO < 0V
VO > VCC
DC Output Source/Sink Current
(IOH/IOL)
DC VCC or Ground Current per
Supply Pin (ICC or Ground)
Storage Temperature Range (TSTG)
0.5V to +4.6V
0.5V to +4.6V
0.5V to +4.6V
0.5 to VCC + 0.5V
50 mA
50 mA
+50 mA
±50 mA
±100 mA
65°C to +150°C
Recommended Operating
Conditions (Note 7)
Power Supply
Operating
1.65V to 3.6V
Data Retention Only
1.2V to 3.6V
Input Voltage
0.3V to 3.6V
Output Voltage (VO)
Output in Active States
Output in 3-STATE
0V to VCC
0.0V to 3.6V
Output Current in IOH/IOL
VCC = 3.0V to 3.6V
VCC = 2.3V to 2.7V
VCC = 1.65V to 2.3V
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (t/V)
±24 mA
±18 mA
±6 mA
40°C to +85°C
VIN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 5: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditions tables will define the condi-
tions for actual device operation.
Note 6: IO Absolute Maximum Rating must be observed.
Note 7: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
DC Electrical Characteristics (2.7V < VCC 3.6V)
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF Power Off Leakage Current
ICC Quiescent Supply Current
ICC
Increase in ICC per Input
Note 8: Outputs disabled or 3-STATE only.
Conditions
IOH = −100 µA
IOH = −12 mA
IOH = −18 mA
IOH = −24 mA
IOL = 100 µA
IOL = 12 mA
IOL = 18 mA
IOL = 24 mA
0V VI 3.6V
0V VO 3.6V
VI = VIH or VIL
0V (VI, VO) 3.6V
VI = VCC or GND
VCC (VI, VO) 3.6V (Note 8)
VIH = VCC 0.6V
VCC
(V)
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
3.0
2.7–3.6
2.7
3.0
3.0
2.7–3.6
2.7–3.6
0
2.7–3.6
2.7–3.6
2.7–3.6
Min
2.0
VCC 0.2
2.2
2.4
2.2
Max
0.8
Units
V
V
V
0.2
0.4
0.4
0.55
±5.0
±10
10
20
±20
750
V
µA
µA
µA
µA
µA
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74VCX16500 (Fairchild Semiconductor)
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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DC Electrical Characteristics (2.3V VCC 2.7V)
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF Power Off Leakage Current
ICC Quiescent Supply Current
Note 9: Outputs disabled or 3-STATE only.
Conditions
IOH = −100 µA
IOH = −6 mA
IOH = −12 mA
IOH = −18 mA
IOL = 100 µA
IOL = 12 mA
IOL = 18 mA
0 VI 3.6V
0 VO 3.6V
VI = VIH or VIL
0 (VI, VO) 3.6V
VI = VCC or GND
VCC (VI, VO) 3.6V (Note 9)
VCC
(V)
2.3–2.7
2.3–2.7
2.3–2.7
2.3
2.3
2.3
2.3–2.7
2.3
2.3
2.3–2.7
2.3–2.7
0
2.3–2.7
2.3–2.7
Min
1.6
VCC 0.2
2.0
1.8
1.7
Max
0.7
Units
V
V
V
0.2
0.4
0.6
±5.0
±10
10
20
±20
V
µA
µA
µA
µA
DC Electrical Characteristics (1.65V VCC < 2.3V)
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF Power Off Leakage Current
ICC Quiescent Supply Current
Note 10: Outputs disabled or 3-STATE only.
Conditions
IOH = −100 µA
IOH = −6 mA
IOL = 100 µA
IOL = 6 mA
0 VI 3.6V
0 VO 3.6V
VI = VIH or VIL
0 (VI, VO) 3.6V
VI = VCC or GND
VCC (VI, VO) 3.6V (Note 10)
VCC
(V)
1.65 - 2.3
1.65 - 2.3
1.65 - 2.3
1.65
1.65 - 2.3
1.65
1.65 - 2.3
Min Max
0.65 × VCC
VCC 0.2
1.25
0.35 × VCC
0.2
0.3
±5.0
1.65 - 2.3
±10
0
1.65 - 2.3
1.65 - 2.3
10
20
±20
Units
V
V
V
V
µA
µA
µA
µA
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74VCX16500 (Fairchild Semiconductor)
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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AC Electrical Characteristics (Note 11)
TA = −40°C to +85°C, CL = 30 pF, RL = 500
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5 ± 0.2V
VCC = 1.8 ± 0.15V
Units
Min Max Min Max Min Max
fMAX
Maximum Clock Frequency
250
200
100 MHz
tPHL Propagation Delay
tPLH Bus to Bus
0.6 2.9 0.8 3.5 1.5 7.0
ns
tPHL Propagation Delay
tPLH Clock to Bus
0.6 4.2 0.8 5.3 1.5 9.8
ns
tPHL Propagation Delay
tPLH LE to Bus
0.6 3.8 0.8 4.9 1.5 9.8
ns
tPZL
tPZH
Output Enable Time
0.6 3.8 0.8 4.9 1.5 9.8
ns
tPLZ
tPHZ
Output Disable Time
0.6 3.7 0.8 4.2 1.5 7.6
ns
tS Setup Time
1.5 1.5 2.5 ns
tH Hold Time
1.0 1.0 1.0 ns
tW Pulse Width
1.5 1.5 4.0 ns
tOSHL
tOSLH
Output to Output
Skew (Note 12)
0.5
0.5
0.75
ns
Note 11: For CL = 50pF, add approximately 300ps to the AC maximum specification.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
VOLV
VOHV
Quiet Output Dynamic
Peak VOL
Quiet Output Dynamic
Valley VOL
Quiet Output Dynamic
Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCC
TA = +25°C
Units
(V) Typical
1.8 0.25
2.5 0.6
3.3 0.8
V
1.8 0.25
2.5 0.6
3.3 0.8
V
1.8 1.5
2.5 1.9
3.3 2.2
V
Capacitance
Symbol
Parameter
CIN Input Capacitance
CI/O Output Capacitance
CPD Power Dissipation Capacitance
Conditions
VI = 0V or VCC
VCC = 1.8V, 2.5V, or 3.3V,
VI = 0V, or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz
VCC = 1.8V, 2.5V or 3.3V
TA = +25°C Units
6 pF
7 pF
20 pF
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74VCX16500 (Fairchild Semiconductor)
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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AC Loading and Waveforms
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
FIGURE 1. AC Test Circuit
SWITCH
Open
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8 ± 0.15V
GND
FIGURE 2. Waveform for Inverting and
Non-inverting Functions
FIGURE 4. 3-STATE Output Low Enable and
Disable Times for Low Voltage Logic
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
trec Waveforms
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic
Symbol
Vmi
Vmo
VX
VY
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH 0.3V
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH 0.15V
1.8 ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH 0.15V
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74VCX16500 (Fairchild Semiconductor)
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.




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