MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

19-3280; Rev 2; 8/04
EVAALVUAAILTAIOBNLEKIT
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
General Description
The MAX1020–MAX1023/MAX1057/MAX1058 integrate a
multichannel, 10-bit, analog-to-digital converter (ADC)
and an octal, 10-bit, digital-to-analog converter (DAC) in a
single IC. These devices also include a temperature sen-
sor and configurable general-purpose I/O ports (GPIOs)
with a 25MHz SPI™-/QSPI™-/MICROWIRE™-compatible
serial interface. The ADC is available in 8/12/16 input-
channel versions. The octal DAC outputs settle within
2.0µs, and the ADC has a 300ksps conversion rate.
All devices include an internal reference (2.5V or 4.096V)
providing a well-regulated, low-noise reference for both
the ADC and DAC. Programmable reference modes for
the ADC and the DAC allow the use of an internal refer-
ence, an external reference, or a combination of both.
Features such as an internal ±1°C accurate temperature
sensor, FIFO, scan modes, programmable internal
or external clock modes, data averaging, and
AutoShutdown™ allow users to minimize both power con-
sumption and processor requirements. The low glitch
energy (4nVs) and low digital feedthrough (0.5nVs) of
the integrated octal DACs make these devices ideal for
digital control of fast-response closed-loop systems.
The devices are guaranteed to operate with a supply volt-
age from +2.7V to +3.6V (MAX1021/MAX1023/MAX1057)
and from +4.75V to +5.25V (MAX1020/MAX1022/
MAX1058). The devices consume 2.5mA at 300ksps
throughput, only 22µA at 1ksps throughput, and under
0.2µA in the shutdown mode. The MAX1057/MAX1058
feature 12 GPIOs, while the MAX1020/MAX1021 offer 4
GPIOs that can be configured as inputs or outputs.
The MAX1057/MAX1058 are available in 48-pin thin QFN
packages. The MAX1020–MAX1023 are available in 36-
pin thin QFN packages. All devices are specified over the
-40°C to +85°C temperature range.
Applications
Controls for Optical Components
Base-Station Control Loops
System Supervision and Control
Data-Acquisition Systems
Features
10-Bit, 300ksps ADC
Analog Multiplexer with True-Differential
Track/Hold (T/H)
16 Single-Ended Channels or 8 Differential
Channels (Unipolar or Bipolar)
12 Single-Ended Channels or 6 Differential
Channels (Unipolar or Bipolar)
8 Single-Ended Channels or 4 Differential
Channels (Unipolar or Bipolar)
Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB DNL
10-Bit, Octal, 2µs Settling DAC
Ultra-Low Glitch Energy (4nVs)
Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: ±1 LSB INL
Internal Reference or External Single-Ended/
Differential Reference
Internal Reference Voltage 2.5V or 4.096V
Internal ±1°C Accurate Temperature Sensor
On-Chip FIFO Capable of Storing 16 ADC
Conversion Results and One Temperature Result
On-Chip Channel-Scan Mode and Internal
Data-Averaging Features
Analog Single-Supply Operation
+2.7V to +3.6V or +4.75V to +5.25V
25MHz, SPI/QSPI/MICROWIRE Serial Interface
AutoShutdown Between Conversions
Low-Power ADC
2.5mA at 300ksps
22µA at 1ksps
0.2µA at Shutdown
Low-Power DAC: 1.5µA
Evaluation Kit Available (Order MAX1258EVKIT)
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Ordering Information/Selector Guide
PART
TEMP RANGE
PIN-PACKAGE
REF
VOLTAGE
(V)
ANALOG
SUPPLY
VOLTAGE (V)
RESOLUTION
BITS***
ADC
DAC
CHANNELS CHANNELS
GPIOs
MAX1020BETX -40°C to +85°C 36 Thin QFN-EP** 4.096
4.75 to 5.25
10
8 84
MAX1021BETX* -40°C to +85°C 36 Thin QFN-EP** 2.5
2.7 to 3.6
10
8 84
MAX1022BETX* -40°C to +85°C 36 Thin QFN-EP** 4.096
4.75 to 5.25
10
12 8 0
MAX1023BETX* -40°C to +85°C 36 Thin QFN-EP** 2.5
2.7 to 3.6
10
12 8 0
MAX1057BETM -40°C to +85°C 48 Thin QFN-EP** 2.5
2.7 to 3.6
10
16 8 12
MAX1058BETM -40°C to +85°C 48 Thin QFN-EP** 4.096
*Future product—contact factory for availability.
**EP = Exposed pad.
***Number of resolution bits refers to both DAC and ADC.
4.75 to 5.25
10
16 8
Pin Configurations appear at end of data sheet.
12
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
DVDD to AVDD .......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V)
Analog Inputs, Analog Outputs and REF_
to AGND...............................................-0.3V to (AVDD + 0.3V)
Maximum Current into Any Pin (except AGND, DGND, AVDD,
DVDD, and OUT_) ...........................................................50mA
Maximum Current into OUT_.............................................100mA
Continuous Power Dissipation (TA = +70°C)
36-Pin Thin QFN (6mm x 6mm)
(derate 26.3mW/°C above +70°C) ......................2105.3mW
48-Pin Thin QFN (7mm x 7mm)
(derate 26.3mW/°C above +70°C) ......................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note: If the package power dissipation is not exceeded, one output at a time may be shorted to AVDD, DVDD, AGND, or DGND
indefinitely
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD =
DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz
(50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057),
AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
DC ACCURACY (Note 1)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Gain Temperature Coefficient
Channel-to-Channel Offset
SYMBOL
INL
DNL
(Note 2)
CONDITIONS
ADC
MIN
TYP
MAX
UNITS
10 Bits
±0.5 ±1.0
LSB
±0.5 ±1.0
LSB
±0.25 ±2.0
LSB
±0.025 ±2.0
LSB
±1.4
ppm/°C
±0.1
LSB
DYNAMIC SPECIFICATIONS (10kHz sine wave input, VIN = 2.5VP-P (MAX1021/MAX1023/MAX1057), VIN = 4.096VP-P
(MAX1020/MAX1022/MAX1058), 300ksps, fSCLK = 4.8MHz)
Signal-to-Noise Plus Distortion
SINAD
61
dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)
THD
-70 dBc
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Linear Bandwidth
Full-Power Bandwidth
CONVERSION RATE (Note 3)
SFDR
IMD
fin1 = 9.9kHz, fin2 = 10.2kHz
SINAD > 70dB
-3dB point
External reference
66 dBc
72 dBc
100 kHz
1 MHz
0.8 µs
Power-Up Time
tPU Internal reference (Note 4)
Conversion
218 Clock
Cycles
2 _______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD =
DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz
(50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057),
AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Acquisition Time
Conversion Time
tACQ
tCONV
(Note 5)
Internally clocked
Externally clocked
0.6
3.5
2.7
µs
µs
Internal Clock Frequency
Internally clocked conversion
4.3 MHz
External Clock Frequency
Duty Cycle
fCLK Externally clocked conversion (Note 5)
0.1
40
4.8 MHz
60 %
Aperture Delay
30 ns
Aperture Jitter
<50 ps
ANALOG INPUTS
Input Voltage Range (Note 6)
Input Leakage Current
Unipolar
Bipolar
0
-VREF / 2
±0.01
VREF
VREF / 2
±1
V
µA
Input Capacitance
24 pF
INTERNAL TEMPERATURE SENSOR
Measurement Error (Notes 5, 7)
Temperature Resolution
TA = +25°C
TA = TMIN to TMAX
±0.7
±1.0
1/8
±3.0
°C
°C/LSB
INTERNAL REFERENCE
REF1 Output Voltage (Note 8)
MAX1021/MAX1023/MAX1057
MAX1020/MAX1022/MAX1058
2.482
4.066
2.50
4.096
2.518
4.126
V
REF1 Voltage Temperature
Coefficient
TCREF
±30 ppm/°C
REF1 Output Impedance
REF1 Short-Circuit Current
EXTERNAL REFERENCE
VREF = 2.5V
VREF = 4.096V
6.5
0.39
0.63
k
mA
REF1 Input Voltage Range
VREF1 REF mode 11 (Note 4)
1
AVDD +
V
0.05
REF2 Input Voltage Range
(Note 4)
VREF2
REF mode 01
REF mode 11
1
AVDD +
0.05
V
01
_______________________________________________________________________________________ 3


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD =
DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz
(50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057),
AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
REF1 Input Current (Note 9)
IREF1
VREF = 2.5V
(MAX1021/MAX1023/MAX1057),
fSAMPLE = 300ksps
VREF = 4.096V
(MAX1020/MAX1022/MAX1058),
fSAMPLE = 300ksps
Acquisition between conversions
25 80
40
±0.01
80
±1
µA
REF2 Input Current
DC ACCURACY (Note 10)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset-Error Drift
Gain Error
Gain Temperature Coefficient
DAC OUTPUT
Output-Voltage Range
DC Output Impedance
Capacitive Load
IREF2
VREF = 2.5V
(MAX1021/MAX1023/MAX1057),
fSAMPLE = 300ksps
VREF = 4.096V
(MAX1020/MAX1022/MAX1058),
fSAMPLE = 300ksps
Acquisition between conversions
DAC
INL
DNL
VOS
Guaranteed monotonic
(Note 8)
GE (Note 8)
No load
10kload to either rail
(Note 11)
25 80
40
±0.01
80
±1
µA
10 Bits
±0.5
±1
±0.5
LSB
LSB
±3 ±10
mV
±10 ppm of
FS/°C
±1.25 ±10
LSB
±8
ppm of
FS/°C
0.02
0.1
AVDD -
0.02
AVDD -
0.1
0.5
1
V
nF
Resistive Load to AGND
AVDD = 2.7V, VREF = 2.5V
(MAX1021/MAX1023/MAX1057),
gain error < 1%
RL
AVDD = 4.75V, VREF = 4.096V
(MAX1020/MAX1022/MAX1058),
gain error < 2%
2000
500
4 _______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD =
DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz
(50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057),
AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Wake-Up Time (Note 12)
1kOutput Termination
From power-down mode, AVDD = 5V
From power-down mode, AVDD = 2.7V
Programmed in power-down mode
100kOutput Termination
At wake-up or programmed in
power-down mode
DYNAMIC PERFORMANCE (Notes 5, 13)
Output-Voltage Slew Rate
SR Positive and negative
Output-Voltage Settling Time
Digital Feedthrough
tS To 1 LSB, 400 - C00 hex (Note 7)
Code 0, all digital inputs from 0 to DVDD
Major Code Transition Glitch
Impulse
Between codes 2047 and 2048
Output Noise (0.1Hz to 50MHz)
Output Noise (0.1Hz to 500kHz)
From VREF
Using internal reference
From VREF
Using internal reference
DAC-to-DAC Transition
Crosstalk
INTERNAL REFERENCE
REF1 Output Voltage (Note 8)
REF1 Temperature Coefficient
TCREF
REF1 Short-Circuit Current
EXTERNAL-REFERENCE INPUT
MAX1021/MAX1023/MAX1057
MAX1020/MAX1022/MAX1058
VREF = 2.5V
VREF = 4.096V
REF1 Input Voltage Range
VREF1 REF modes 01, 10, and 11 (Note 4)
REF1 Input Impedance
RREF1
DIGITAL INTERFACE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC)
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input Leakage Current
IL
Input Capacitance
CIN
DIGITAL OUTPUT (DOUT) (Note 14)
DVDD = 2.7V to 5.25V
DVDD = 3.6V to 5.25V
DVDD = 2.7V to 3.6V
Output-Voltage Low
VOL ISINK = 2mA
MIN
3
2.482
4.066
0.7
70
2.4
TYP
25
21
1
100
MAX
25
0.5
4
660
720
260
320
0.5
2.50
4.096
±30
0.39
0.63
2.518
4.126
AVDD
100 130
±0.01
15
0.8
0.6
±10
0.4
UNITS
µs
k
k
V/µs
µs
nVs
nVs
µVP-P
µVP-P
nVs
V
ppm/°C
mA
V
k
V
V
µA
pF
V
_______________________________________________________________________________________ 5


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD =
DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz
(50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057),
AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output-Voltage High
VOH
Tri-State Leakage Current
Tri-State Output Capacitance
COUT
DIGITAL OUTPUT (EOC) (Note 14)
Output-Voltage Low
VOL
Output-Voltage High
VOH
ISOURCE = 2mA
ISINK = 2mA
ISOURCE = 2mA
DVDD -
0.5
15
DVDD -
0.5
±10
0.4
V
µA
pF
V
V
Tri-State Leakage Current
Tri-State Output Capacitance
COUT
DIGITAL OUTPUTS (GPIO_) (Note 14)
GPIOB_, GPIOC_ Output-
Voltage Low
GPIOB_, GPIOC_ Output-
Voltage High
GPIOA_ Output-Voltage Low
GPIOA_ Output-Voltage High
Tri-State Leakage Current
Tri-State Output Capacitance
COUT
POWER REQUIREMENTS (Note 15)
Digital Positive-Supply Voltage
DVDD
Digital Positive-Supply Current
DIDD
Analog Positive-Supply Voltage AVDD
Analog Positive Supply Current
AIDD
ISINK = 2mA
ISINK = 4mA
ISOURCE = 2mA
ISINK = 15mA
ISOURCE = 15mA
Idle, all blocks shut down
Only ADC on, external reference
MAX1021/MAX1023/MAX1057
MAX1020/MAX1022/MAX1058
Idle, all blocks shut down
Only ADC on,
fSAMPLE = 300ksps
external reference fSAMPLE = 100ksps
All DACs on, no load, internal reference
DVDD -
0.5
DVDD -
0.8
2.70
2.7
4.75
15
15
0.2
1
0.2
2.8
2.6
1.5
±10
0.4
0.8
0.8
±10
AVDD
4
3.6
5.25
1
4.2
4.0
µA
pF
V
V
V
V
µA
pF
V
µA
mA
V
µA
mA
REF1 Positive-Supply Rejection
PSRR
AVDD = 2.7V
MAX1021/MAX1023/MAX1057
AVDD = 4.75V
MAX1020/MAX1022/MAX1058
-77
dB
-80
DAC Positive-Supply Rejection
PSRD
MAX1021/MAX1023/MAX1057
Output AVDD = 2.7V to 3.6V
code =
FFFhex MAX1020/MAX1022/MAX1058
AVDD = 4.75V to 5.25V
±0.1 ±0.5
±0.1 ±0.5
mV
6 _______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD =
DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz
(50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057),
AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
ADC Positive-Supply Rejection
PSRA
Full-
scale
input
MAX1021/MAX1023/
MAX1057 AVDD = 2.7V to 3.6V
MAX1020/MAX1022/
MAX1058 AVDD = 4.75V to 5.25V
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period
tCP
SCLK Pulse-Width High
tCH 40/60 duty cycle
SCLK Pulse-Width Low
tCL 60/40 duty cycle
GPIO Output Rise/Fall After
CS Rise
tGOD CLOAD = 20pF
GPIO Input Setup Before CS Fall
LDAC Pulse Width
SCLK Fall to DOUT Transition
(Note 16)
SCLK Rise to DOUT Transition
(Notes 16, 17)
CS Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CS Pulse-Width High
CS Rise to DOUT Disable
CS Fall to DOUT Enable
EOC Fall to CS Fall
tGSU
tLDACPWL
tDOT
tDOT
tCSS
tCSH
tDS
tDH
tCSPWH
tDOD
tDOE
tRDS
CLOAD = 20pF, SLOW = 0
CLOAD = 20pF, SLOW = 1
CLOAD = 20pF, SLOW = 0
CLOAD = 20pF, SLOW = 1
CLOAD = 20pF
CLOAD = 20pF
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
CS or CNVST Rise to EOC Fall
tDOV
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
CKSEL = 01 (voltage conversion)
CKSEL = 10 (voltage conversion),
internal reference on
MIN
40
16
16
0
20
1.8
10
1.8
10
10
0
10
0
50
1.5
30
TYP
±0.06
MAX
±0.5
±0.06 ±0.5
100
12.0
40
12.0
40
25
25.0
55
120
8
8
UNITS
mV
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CNVST Pulse Width
tCSW
CKSEL = 10 (voltage conversion),
internal reference initially off
CKSEL = 00, CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
40
1.4
80
ns
µs
_______________________________________________________________________________________ 7


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 2.7V to 3.6V (MAX1021/MAX1023/MAX1057), external reference VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD =
DVDD = 4.75V to 5.25V (MAX1020/MAX1022/MAX1058), external reference VREF = 4.096V (MAX1020/MAX1022/MAX1058), fSCLK = 4.8MHz
(50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057),
AVDD = DVDD = 5V (MAX1020/MAX1022/MAX1058), TA = +25°C. Outputs are unloaded, unless otherwise noted.)
Note 1: Tested at DVDD = AVDD = +3.6V (MAX1021/MAX1023/MAX1057), DVDD = AVDD = +5.25V (MAX1020/MAX1022/MAX1058).
Note 2: Offset nulled.
Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Note 4: See Table 5 for reference-mode details.
Note 5: Not production tested. Guaranteed by design.
Note 6: See the ADC/DAC References section.
Note 7: Fast automated test, excludes self-heating effects.
Note 8: Specified over the -40°C to +85°C temperature range.
Note 9: REFSEL[1:0] = 00 or when DACs are not powered up.
Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Note 11: The DAC buffers are guaranteed by design to be stable with a 500pF load.
Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Note 13: All DAC dynamic specifications are valid for a load of 1nF and 10k.
Note 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Note 15: All digital inputs at either DVDD or DGND. DVDD should not exceed AVDD.
Note 16: See the Reset Register section and Table 9 for details on programming the SLOW bit.
Note 17: Clock mode 11 only.
Typical Operating Characteristics
(AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V
(MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE
= 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)
SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
0.30
SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
0.20
SHUTDOWN CURRENT
vs. TEMPERATURE
0.6
0.25 0.18
0.5
0.20
0.15
0.10
0.05
MAX1020/MAX1022/MAX1058
0
4.75 4.85 4.95 5.05
5.15
SUPPLY VOLTAGE (V)
5.25
0.16
0.14
0.12
MAX1021/MAX1023/MAX1057
0.10
2.7 3.0 3.3
SUPPLY VOLTAGE (V)
0.4
0.3
0.2
0.1
0
3.6 -40 -15 10 35 60 85
TEMPERATURE (°C)
8 _______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V
(MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE
= 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)
INTERNAL OSCILLATOR FREQUENCY
vs. ANALOG SUPPLY VOLTAGE
4.5
INTERNAL OSCILLATOR FREQUENCY
vs. ANALOG SUPPLY VOLTAGE
4.90
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
5.0
4.4
4.3
4.2
4.1
MAX1020/MAX1022/MAX1058
4.0
4.75 4.85 4.95 5.05
5.15
SUPPLY VOLTAGE (V)
5.25
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.3
4.85
4.80
4.75
4.70
4.65
MAX1021/MAX1023/MAX1057
4.60
2.7 3.0 3.3
SUPPLY VOLTAGE (V)
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.3
3.6
4.8
4.6
MAX1021/MAX1023/MAX1057
4.4
4.2
4.0 MAX1020/MAX1022/MAX1058
3.8
-40
-15 10 35 60
TEMPERATURE (°C)
85
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.3
0.2 0.2
0.2
0.1 0.1
0.1
00
0
-0.1 -0.1
-0.1
-0.2
MAX1020/MAX1022/MAX1058
-0.3
0 256 512
OUTPUT CODE
768
1024
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.3
-0.2
MAX1021/MAX1023/MAX1057
-0.3
0 256 512
OUTPUT CODE
768
1024
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
-0.4
-0.2
MAX1020/MAX1022/MAX1058
-0.3
0 256 512
OUTPUT CODE
768
1024
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
0
0.2
-0.5 -0.5
0.1
0 -0.6 -1.0
-0.1
-0.2
MAX1021/MAX1023/MAX1057
-0.3
0 256 512
OUTPUT CODE
768
1024
-0.7
MAX1020/MAX1022/MAX1058
-0.8
4.75 4.85 4.95 5.05
5.15
SUPPLY VOLTAGE (V)
5.25
-1.5
MAX1021/MAX1023/MAX1057
-2.0
2.7 3.0 3.3
SUPPLY VOLTAGE (V)
3.6
_______________________________________________________________________________________ 9


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V
(MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE
= 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)
ADC OFFSET ERROR
vs. TEMPERATURE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
0 0.050 0.50
MAX1020/MAX1022/MAX1058
-0.5
-1.0
MAX1021/MAX1023/MAX1057
-1.5
-2.0
-40
1.00
-15 10 35 60
TEMPERATURE (°C)
ADC GAIN ERROR
vs. TEMPERATURE
85
0.025
0
-0.025
-0.050
MAX1020/MAX1022/MAX1058
-0.075
4.75 4.85 4.95 5.05
5.15
SUPPLY VOLTAGE (V)
5.25
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATE
60
0.45
0.40
0.35
0.30
0.25
MAX1021/MAX1023/MAX1057
0.20
2.7 3.0 3.3
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT
vs. SAMPLING RATE
3.0
3.6
0.75
0.50
0.25
MAX1021/MAX1023/MAX1057
0
50
40
MAX1020/MAX1022/MAX1058
30
20
2.5
MAX1020/MAX1022/MAX1058
2.0
1.5
1.0
-0.25
-0.50
-40
MAX1020/MAX1022/MAX1058
-15 10 35 60
TEMPERATURE (°C)
85
10
0
0
MAX1021/MAX1023/MAX1057
50 100 150 200 250 300
SAMPLING RATE (ksps)
0.5 MAX1021/MAX1023/MAX1057
0
0 50 100 150 200 250 300
SAMPLING RATE (ksps)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
2.8
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
2.6
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
2.7
2.7
2.6
2.5
2.4
2.3
MAX1020/MAX1022/MAX1058
2.2
4.75 4.85 4.95 5.05
5.15
SUPPLY VOLTAGE (V)
5.25
2.5
2.4
2.3
2.2
2.1
2.0
MAX1021/MAX1023/MAX1057
1.9
2.7 3.0 3.3
SUPPLY VOLTAGE (V)
2.6
2.5
2.4
MAX1020/MAX1022/MAX1058
2.3
3.6 -40 -15 10 35 60 85
TEMPERATURE (°C)
10 ______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V
(MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE
= 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
2.16
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.3
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.3
2.15 0.2 0.2
2.14 0.1 0.1
2.13 0 0
2.12 -0.1 -0.1
2.11
MAX1021/MAX1023/MAX1057
2.10
-40 -15 10 35
TEMPERATURE (°C)
60
85
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.10
-0.2
MAX1020/MAX1022/MAX1058
-0.3
0 256 512
OUTPUT CODE
768
1024
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.10
-0.2
MAX1021/MAX1023/MAX1057
-0.3
0 256 512
OUTPUT CODE
768
1024
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
0.04
0.05 0.05 0.03
0 0 0.02
-0.05 -0.05
0.01
MAX1020/MAX1022/MAX1058
-0.10
1023 1026 1029 1032 1035 1038
OUTPUT CODE
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
-0.50
-0.55
-0.60
-0.65
MAX1021/MAX1023/MAX1057
-0.70
2.7 3.0 3.3
SUPPLY VOLTAGE (V)
3.6
MAX1021/MAX1023/MAX1057
-0.10
1023 1026 1029 1032 1035 1038
OUTPUT CODE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
2.0
1.5 INTERNAL REFERENCE
1.0
0.5
0
EXTERNAL REFERENCE = 4.096V
-0.5
MAX1020/MAX1022/MAX1058
-1.0
-40 -15 10 35
TEMPERATURE (°C)
60
85
MAX1020/MAX1022/MAX1058
0
4.75 4.85 4.95 5.05
5.15
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR
vs. TEMPERATURE
0
-0.25
-0.50
EXTERNAL REFERENCE = 2.500V
-0.75
-1.00
INTERNAL REFERENCE
-1.25
-1.50
-1.75
MAX1021/MAX1023/MAX1057
-2.00
-40 -15 10 35
TEMPERATURE (°C)
60
5.25
85
______________________________________________________________________________________ 11


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V
(MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE
= 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
1.00
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
0
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
1
0.75 -0.5
0.50
-1.0
0.25
0 -1.5
0
-1
-0.25
-0.50
-0.75
MAX1020/MAX1022/MAX1058
-1.00
0123
4
REFERENCE VOLTAGE (V)
5
-2.0
-2.5
MAX1021/MAX1023/MAX1057
-3.0
0 0.5 1.0 1.5 2.0
2.5
REFERENCE VOLTAGE (V)
3.0
-2
-3
MAX1020/MAX1022/MAX1058
-4
0 5 10 15 20
LOAD CURRENT (mA)
25
30
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
1
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
4.12
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.52
0
-1
-2
-3
MAX1021/MAX1023/MAX1057
-4
0 0.5 1.0 1.5 2.0
LOAD CURRENT (mA)
2.5
3.0
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
43.0
4.11
4.10
4.09
MAX1020/MAX1022/MAX1058
4.08
-40 -15 10 35
TEMPERATURE (°C)
60
85
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
25.8
2.51
2.50
2.49
MAX1021/MAX1023/MAX1057
2.48
-40 -15 10 35
TEMPERATURE (°C)
60
85
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
50
42.8
42.6
42.4
42.2
MAX1020/MAX1022/MAX1058
42.0
4.75 4.85 4.95 5.05
5.15
SUPPLY VOLTAGE (V)
5.25
25.7
25.6
25.5
MAX1021/MAX1023/MAX1057
25.4
2.7 3.0 3.3
SUPPLY VOLTAGE (V)
48
46
44
42
MAX1020/MAX1022/MAX1058
40
3.6 -40 -15 10 35 60 85
TEMPERATURE (°C)
12 ______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V
(MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE
= 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
27.00
26.75
26.50
26.25
26.00
0
-20
-40
-60
-80
ADC FFT PLOT
fSAMPLE = 32.768kHz
fANALOG_)N = 10.080kHz
fCLK = 5.24288MHz
SINAD = 61.21dBc
SNR = 61.21dBc
THD = 73.32dBc
SFDR = 81.25dBc
0
-20
-40
-60
-80
ADC IMD PLOT
fCLK = 5.24288MHz
fIN1 = 9.0kHz
fIN2 = 11.0kHz
AIN = -6dBFS
IMD = 78.0dBc
25.75
-100
-100
25.50
-120
-120
25.25
25.00
-40
MAX1021/MAX1023/MAX1057
-15 10 35 60
TEMPERATURE (°C)
85
-140
-160
0
50 100 150
ANALOG INPUT FREQUENCY (kHz)
200
-140
-160
0
50 100 150
ANALOG INPUT FREQUENCY (kHz)
200
0
-20
-40
-60
-80
-100
-120
-140
-160
0
ADC CROSSTALK PLOT
fCLK = 5.24288MHz
fIN1 = 10.080kHz
fIN2 = 8.0801kHz
SNR = 61.11dBc
THD = 73.32dBc
ENOB = 9.86 BITS
SFDR = 86.34dBc
50 100 150
ANALOG INPUT FREQUENCY (kHz)
200
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
2.08
2.07
2.06
2.05
2.04
2.03 SINKING
2.02 SOURCING
2.01 DAC OUTPUT = MIDSCALE
MAX1020/MAX1022/MAX1058
2.00
-30 0 30
60
OUTPUT CURRENT (mA)
90
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
1.29
1.28
1.27
1.26
1.25
1.24 SINKING
1.23 SOURCING
1.22 DAC OUTPUT = MIDSCALE
MAX1021/MAX1023/MAX1057
1.21
-30 -20 -10 0 10
OUTPUT CURRENT (mA)
20
30
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
5
MAX1020/MAX1022/MAX1058
4
GPIO OUTPUT VOLTAGE
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
vs. SINK CURRENT
3.0 1500
MAX1021/MAX1023/MAX1057
GPIOB0–B3, C0–C3
2.5 GPIOA0–A3 OUTPUTS
1200
OUTPUTS
2.0
3 GPIOA0–A3 OUTPUTS
1.5
2
1.0
GPIOB0–B3,
1
C0–C3 OUTPUTS
0.5
GPIOB0–B3, C0–C3
OUTPUTS
900
600
300
GPIOA0–A3 OUTPUTS
0
0 20 40 60 80 100
SOURCE CURRENT (mA)
0
0 20 40 60 80 100
SOURCE CURRENT (mA)
MAX1020/MAX1022/MAX1058
0
0 20 40 60 80 100
SINK CURRENT (mA)
______________________________________________________________________________________ 13


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V
(MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE
= 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
1500
GPIOB0–B3, C0–C3
OUTPUTS
1200
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
1.00
0.75
0.50
DAC-TO-DAC CROSSTALK
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc51
VOUTA
1V/div
900
600
300
0
0
GPIOA0–A3 OUTPUTS
MAX1021/MAX1023/MAX1057
10 20 30 40 50
SINK CURRENT (mA)
60
0.25
0
-0.25
-0.50
-0.75
-1.00
-40
-15 10 35 60
TEMPERATURE (°C)
85
MAX1021/MAX1023/MAX1057
100µs
VOUTB
10mV/div
AC-COUPLED
DAC-TO-DAC CROSSTALK
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc52
VOUTA
2V/div
DYNAMIC RESPONSE RISE TIME
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc53
MAX1021/MAX1023/MAX1057
VOUT
1V/div
DYNAMIC RESPONSE RISE TIME
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc54
CS
2V/div
MAX1020/MAX1022/MAX1058
100µs
VOUTB
10mV/div
AC-COUPLED
CS
1V/div
1µs
DYNAMIC RESPONSE FALL TIME
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc55
MAX1021/MAX1023/MAX1057
VOUT
1V/div
DYNAMIC RESPONSE FALL TIME
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc56
CS
2V/div
MAX1020/MAX1022/MAX1058
1µs
VOUT
2V/div
MAJOR CARRY TRANSITION
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc57
CS
1V/div
CS
1V/div
MAX1020/MAX1022/MAX1058
VOUT
2V/div
MAX1021/MAX1023/MAX1057
1µs 1µs 1µs
14 ______________________________________________________________________________________
VOUT
10mV/div
AC-COUPLED


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V (MAX1021/MAX1023/MAX1057), external VREF = 2.5V (MAX1021/MAX1023/MAX1057), AVDD = DVDD = 5V
(MAX1020/MAX1022/MAX1058), external VREF = 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 4.8MHz (50% duty cycle), fSAMPLE
= 300ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.)
MAJOR CARRY TRANSITION
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc58
DAC DIGITAL FEEDTHROUGH (RLOAD = 10k,
CLOAD = 100pF, CS = HIGH, DIN = LOW)
MAX1020 toc59
DAC DIGITAL FEEDTHROUGH (RLOAD = 10k,
CLOAD = 100pF, CS = HIGH, DIN = LOW)
MAX1020 toc60
CS
2V/div
SCLK
1V/div
SCLK
2V/div
MAX1020/MAX1022/MAX1058
1µs
VOUT
20mV/div
AC-COUPLED
MAX1021/MAX1023/MAX1057
200ns
VOUT
100mV/div
AC-COUPLED
MAX1020/MAX1022/MAX1058
200ns
VOUT
100mV/div
AC-COUPLED
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc61
MAX1021/MAX1023/MAX1057
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc62
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc63
MAX1021/MAX1023/MAX1057
VOUT
1V/div
VLDAC
2V/div
VOUT_
2V/div
VLDAC
1V/div
MAX1020/MAX1022/MAX1058
1µs 2µs
VOUT_
1V/div
VLDAC
1V/div
1µs
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc64
VLDAC
2V/div
ADC REFERENCE FEEDTHROUGH
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc65
VREF2
1V/div
ADC REFERENCE FEEDTHROUGH
RLOAD = 10k, CLOAD = 100pF
MAX1020 toc66
VREF2
2V/div
VOUT_
2V/div
MAX1020/MAX1022/MAX1058
1µs
MAX1021/MAX1023/MAX1057
ADC REFERENCE SWITCHING
VDAC-OUT
10mV/div
AC-COUPLED
200µs
MAX1020/MAX1022/MAX1058
ADC REFERENCE SWITCHING
VDAC-OUT
2mV/div
AC-COUPLED
200µs
______________________________________________________________________________________ 15


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description
MAX1020/ MAX1022/ MAX1057/
MAX1021 MAX1023 MAX1058
NAME
FUNCTION
1, 2 —
— GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
334
EOC
Active-Low End-of-Conversion Output. Data is valid after the falling edge
of EOC.
447
DVDD
Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF
capacitor.
558
DGND
Digital Ground. Connect DGND to AGND.
669
DOUT
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
7
7 10
SCLK
cycle must be 40% to 60%.) See Table 5 for details on programming the
clock mode.
8 8 11
9–12,
16–19
9–12,
16–19
12–15,
22–25
13 13 18
14 14
15, 23, 32, 2, 15, 24, 32
33 32
19
20 20 26
21 21 27
22
24, 25
22
28
DIN
Serial-Data Input. DIN data is latched into the serial interface on the
falling edge of SCLK.
OUT0–OUT7 DAC Outputs
AVDD
AGND
Positive Analog Power Input. Bypass AVDD to AGND with a 0.1µF
capacitor.
Analog Ground
N.C.
No Connection. Not internally connected.
LDAC
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
CS
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
RES_SEL
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100kresistor to GND or set RES_SEL high to
wake up the DAC outputs with a 100kresistor to VREF. Set RES_SEL
high to power up the DAC input register to FFFh. Set RES_SEL low to
power up the DAC input register to 000h.
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.
16 ______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description (continued)
MAX1020/ MAX1022/ MAX1057/
MAX1021 MAX1023 MAX1058
NAME
FUNCTION
26 26
27–31, 34
35
Reference 1 Input. Reference voltage; leave unconnected to use the
internal reference (2.5V for the MAX1021/MAX1023/MAX1057 or 4.096V
35
REF1
for the MAX1020/MAX1022/MAX1058). REF1 is the positive reference in
ADC external differential reference mode. Bypass REF1 to AGND with a
0.1µF capacitor in external reference mode only. See the ADC/DAC
References section.
— AIN0–AIN5 Analog Inputs
Reference 2 Input/Analog-Input Channel 6. See Table 5 for details on
— REF2/AIN6 programming the setup register. REF2 is the negative reference in the
ADC external differential reference.
36 — — CNVST/AIN7 Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details
on programming the setup register.
1
CNVST/AIN11
Active-Low Conversion-Start Input/Analog Input 11. See Table 5 for
details on programming the setup register.
23, 25,
— 27–31, —
33, 34, 35
AIN0–AIN9 Analog Inputs
Reference 2 Input/Analog-Input Channel 10. See Table 5 for details on
— 36 — REF2/AIN10 programming the setup register. REF2 is the negative reference in the
ADC external differential reference.
——
1 CNVST/AIN15 Active-Low Conversion-Start Input/Analog Input 15. See Table 5 for
details on programming the setup register.
— — 2, 3, 5, 6 GPIOA0–GPIOA3 General-Purpose I/O A0–A3. GPIOA0–GPIOA3 can sink and source 15mA.
— — 16, 17, GPIOB0–GPIOB3 General-Purpose I/O B0–B3. GPIOB0–GPIOB3 can sink 4mA and
20, 21
source 2mA.
— — 29–32 GPIOC0–GPIOC3 General-Purpose I/O C0–C3. GPIOC0–GPIOC3 can sink 4mA and
source 2mA.
33, 34,
AIN0–AIN13 Analog Inputs
36–47
Reference 2 Input/Analog-Input Channel 14. See Table 5 for details on
— — 48 REF2/AIN14 programming the setup register. REF2 is the negative reference in the
ADC external differential reference.
———
EP
Exposed Paddle. Must be externally connected to AGND. Do not use as
a ground connect.
______________________________________________________________________________________ 17


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Detailed Description
The MAX1020–MAX1023/MAX1057/MAX1058 integrate
a multichannel, 10-bit ADC and an octal, 10-bit DAC in
a single IC. These devices also include a temperature
sensor and configurable GPIOs with a 25MHz SPI-
/QSPI-/MICROWIRE-compatible serial interface. The
ADC is available in 8/12/16 input-channel versions. The
octal DAC outputs settle within 2.0µs, and the ADC has
a 300ksps conversion rate.
All devices include an internal reference (2.5V or
4.096V) providing a well-regulated, low-noise reference
for both the ADC and DAC. Programmable reference
modes for the ADC and DAC allow the use of an inter-
nal reference, an external reference, or a combination
of both. Features such as an internal ±1°C accurate
temperature sensor, FIFO, scan modes, programmable
internal or external clock modes, data averaging, and
AutoShutdown allow users to minimize both power con-
sumption and processor requirements. The low glitch
energy (4nVs) and low digital feedthrough (0.5nVs) of
the integrated octal DACs make these devices ideal for
digital control of fast-response closed-loop systems.
The devices are guaranteed to operate with a supply
voltage from +2.7V to +3.6V (MAX1021/MAX1023/
MAX1057) and from +4.5V to +5.5V (MAX1020/
MAX1022/MAX1058), they consume 25mA at 300ksps
throughput, only 22µA at 1ksps throughput, and under
0.2µA in the shutdown mode. The MAX1057/MAX1058
feature 12 GPIOs, while the MAX1020/MAX1021 offer 4
GPIOs that can be configured as inputs or outputs.
Figure 1 shows the MAX1057/MAX1058 functional dia-
gram. The MAX1020/MAX1021 only include the GPIO
A0, A1, GPIO C0, C1 block. The MAX1022/MAX1023
exclude the GPIOs. The output-conditioning circuitry
takes the internal parallel data bus and converts it to a
serial data format at DOUT, with the appropriate wake-
up timing. The arithmetic logic unit (ALU) performs the
averaging function.
SPI-Compatible Serial Interface
The MAX1020–MAX1023/MAX1057/MAX1058 feature a
serial interface that is compatible with SPI and
MICROWIRE devices. For SPI, ensure the SPI bus mas-
ter (typically a microcontroller (µC)) runs in master
mode so that it generates the serial clock signal. Select
the SCLK frequency of 25MHz or less, and set the
clock polarity (CPOL) and phase (CPHA) in the µC con-
trol registers to the same value. The MAX1020–
MAX1023/MAX1057/MAX1058 operate with SCLK idling
high or low, and thus operate with CPOL = CPHA = 0 or
CPOL = CPHA = 1. Set CS low to latch any input data
at DIN on the falling edge of SCLK. Output data at
DOUT is updated on the falling edge of SCLK in clock
modes 00, 01, and 10. Output data at DOUT is updated
on the rising edge of SCLK in clock mode 11. See
Figures 6–11. Bipolar true-differential results and tem-
perature-sensor results are available in two’s comple-
ment format, while all other results are in binary.
A high-to-low transition on CS initiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CS low between the command
byte and the second and third byte. The ADC averag-
ing register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interface section
and Tables 10, 20, and 21.
Write to the GPIOs (if applicable) by issuing a com-
mand byte to the appropriate register. Writing to the
MAX1020/MAX1021 GPIOs requires 1 additional byte
18 ______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
GPIOA0– GPIOB0– GPIOC0–
GPIOA3 GPIOB3 GPIOC3
AVDD DVDD
SCLK
CS
DIN
DOUT
USER-PROGRAMMABLE
I/O
GPIO
CONTROL
OSCILLATOR
SPI
PORT
TEMPERATURE
SENSOR
EOC
AIN0
AIN13
REF2/
AIN14
CNVST/
AIN15
CNVST
LOGIC
CONTROL
T/H
10-BIT
SAR
ADC
FIFO AND
ALU
REF2
INTERNAL
REF1 REFERENCE
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
10-BIT
DAC
MAX1057
MAX1058
BUFFER
OUTPUT
CONDITIONING
OUT0
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT1
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT2
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT3
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT4
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT5
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT6
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT7
LDAC
AGND
DGND
RES_SEL
Figure 1. MAX1057/MAX1058 Functional Diagram
______________________________________________________________________________________ 19


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 1. Command Byte (MSB First)
REGISTER NAME
Conversion
Setup
ADC Averaging
DAC Select
Reset
GPIO Configure*
GPIO Write*
GPIO Read*
No Operation
BIT 7
1
0
0
0
0
0
0
0
0
BIT 6
CHSEL3
1
0
0
0
0
0
0
0
BIT 5
CHSEL2
CKSEL1
1
0
0
0
0
0
0
BIT 4
CHSEL1
CKSEL0
AVGON
1
0
0
0
0
0
X = Don’t care.
*Only applicable on the MAX1020/MAX1021/MAX1057/MAX1058.
BIT 3
CHSEL0
REFSEL1
NAVG1
X
1
0
0
0
0
BIT 2
SCAN1
REFSEL0
NAVG0
X
RESET
0
0
0
0
BIT 1
SCAN0
DIFFSEL1
NSCAN1
X
SLOW
1
1
0
0
BIT 0
TEMP
DIFFSEL0
NSCAN0
X
FBGON
1
0
1
0
following the command byte. Writing to the MAX1057/
MAX1058 requires 2 additional bytes following the
command byte. See Tables 12–19 for details on GPIO
configuration, writes, and reads. See the GPIO
Command section. Command bytes written to the
GPIOs on devices without GPIOs are ignored.
Power-Up Default State
The MAX1020–MAX1023/MAX1057/MAX1058 power up
with all blocks in shutdown (including the reference). All
registers power up in state 00000000, except for the
setup register and the DAC input register. The setup
register powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high and it powers up to 000h
when RES_SEL is low.
10-Bit ADC
The MAX1020–MAX1023/MAX1057/MAX1058 ADCs
use a fully differential successive-approximation regis-
ter (SAR) conversion technique and on-chip track-and-
hold (T/H) circuitry to convert temperature and voltage
signals into 10-bit digital results. The analog inputs
accept both single-ended and differential input signals.
Single-ended signals are converted using a unipolar
transfer function, and differential signals are converted
using a selectable bipolar or unipolar transfer function.
See the ADC Transfer Functions section for more data.
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 4.8MHz for
externally timed acquisitions to achieve sampling rates
up to 300ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the
last requested operation and is waiting for the next
command byte. EOC goes high when CS or CNVST go
low. EOC is always high in clock mode 11.
Single-Ended or Differential Conversions
The MAX1020–MAX1023/MAX1057/MAX1058 use a
fully differential ADC for all conversions. When a pair of
inputs are connected as a differential pair, each input is
connected to the ADC. When configured in single-
ended mode, the positive input is the single-ended
channel and the negative input is referred to AGND.
See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from
the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
AIN14/AIN15. AIN0–AIN7 are available on all devices.
AIN0–AIN11 are available on the MAX1022/MAX1023.
20 ______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
AIN0–AIN15 are available on the MAX1057/MAX1058.
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
Unipolar or Bipolar Conversions
Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
sets the differential input range from 0 to VREF1. A nega-
tive differential analog input in unipolar mode causes
the digital output code to be zero. Selecting bipolar
mode sets the differential input range to ±VREF1 / 2. The
digital output code is binary in unipolar mode and two’s
complement in bipolar mode.
In single-ended mode, the MAX1020–MAX1023/
MAX1057/MAX1058 always operate in unipolar mode.
The analog inputs are internally referenced to AGND
with a full-scale input range from 0 to the selected ref-
erence voltage.
Analog Input (T/H)
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1020–MAX1023/MAX1057/
MAX1058. In track mode, a positive input capacitor is
connected to AIN0–AIN15 in single-ended mode and
AIN0, AIN2, and AIN4–AIN14 (only positive inputs) in
AIN0–AIN15
(SINGLE-ENDED),
AIN0, AIN2,
AIN4–AIN14
(DIFFERENTIAL)
ACQ
REF1
AGND
CIN+
DAC
HOLD
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5–AIN15
(DIFFERENTIAL)
ACQ
CIN-
HOLD
AVDD / 2
Figure 2. Equivalent Input Circuit
ACQ
COMPARATOR
HOLD
differential mode. A negative input capacitor is con-
nected to AGND in single-ended mode or AIN1, AIN3,
and AIN5–AIN15 (only negative inputs) in differential
mode. For external T/H timing, use clock mode 01.
After the T/H enters hold mode, the difference between
the sampled positive and negative input voltages is
converted. The input capacitance charging rate deter-
mines the time required for the T/H to acquire an input
signal. If the input signal’s source impedance is high,
the required acquisition time lengthens.
Any source impedance below 300does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening tACQ (only in clock mode 01) or by placing
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, making it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band of interest.
Analog-Input Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AVDD and AGND, allowing
the inputs to swing from (AGND - 0.3V) to (AVDD +
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AVDD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
Internal FIFO
The MAX1020–MAX1023/MAX1057/MAX1058 contain a
first-in/first-out (FIFO) buffer that holds up to 16 ADC
results plus one temperature result. The internal FIFO
allows the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros and the LSB followed by 2 sub-bits. After
each falling edge of CS, the oldest available pair of
bytes of data is available at DOUT, MSB first. When the
FIFO is empty, DOUT is zero.
______________________________________________________________________________________ 21


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If
another temperature measurement is performed before
the first temperature result is read out, the old measure-
ment is overwritten by the new result. Temperature
results are in degrees Celsius (two’s complement), at a
resolution of 8 LSB per degree. See the Temperature
Measurements section for details on converting the dig-
ital code to a temperature.
10-Bit DAC
In addition to the 10-bit ADC, the MAX1020–MAX1023/
MAX1057/MAX1058 also include eight voltage-output,
10-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential non-
linearity error. Each DAC has a 2µs settling time and
ultra-low glitch energy (4nVs). The 10-bit DAC code is
unipolar binary with 1 LSB = VREF / 4096.
DAC Digital Interface
Figure 1 shows the functional diagram of the MAX1057/
MAX1058. The shift register converts a serial 16-bit
word to parallel data for each input register operating
with a clock rate up to 25MHz. The SPI-compatible digi-
tal interface to the shift register consists of CS, SCLK,
DIN, and DOUT. Serial data at DIN is loaded on the
falling edge of SCLK. Pull CS low to begin a write
sequence. Begin a write to the DAC by writing
0001XXXX as a command byte. The last 4 bits of the
DAC select register are don’t-care bits. See Table 10.
Write another 2 bytes to the DAC interface register fol-
lowing the command byte to select the appropriate DAC
and the data to be written to it. See Tables 20 and 21.
The eight double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The eight 10-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAC low or by writing the
appropriate DAC command sequence at DIN. See
Table 20. The outputs of the DACs are buffered through
eight rail-to-rail op amps.
The MAX1020–MAX1023/MAX1057/MAX1058 DAC out-
put-voltage range is based on the internal reference or
an external reference. Write to the setup register (see
Table 5) to program the reference. If using an external
voltage reference, bypass REF1 with a 0.1µF capacitor
to AGND. The MAX1021/MAX1023/MAX1057 internal
reference is 2.5V. The MAX1020/MAX1022/MAX1058
internal reference is 4.096V. When using an external
reference on any of these devices, the voltage range is
0.7V to AVDD.
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AVDD or
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kinternal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AVDD to wake up all DAC outputs
at FFFh. While RES_SEL is high, the 100kpullup
resistor pulls the DAC outputs to VREF1 and the output
buffers are powered down.
DAC Power-Up Modes
See Table 21 for a description of the DAC power-up
and power-down modes.
GPIOs
In addition to the internal ADC and DAC, the
MAX1057/MAX1058 also provide 12 general-purpose
input/output channels, GPIOA0–GPIOA3, GPIOB0–
Table 2. DAC Output Code Table
DAC CONTENTS
MSB
LSB
ANALOG OUTPUT
11 1111 1111
+VREF
1023
 1024
10 0000 0001
+VREF
513
 1024
10
0000
0000
+VREF
512
 1024
=

+VREF
2

01 0111 0111
+VREF
511
 1024
00 0000 0001
00 0000 0000
+VREF
1
 1024
0
22 ______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
GPIOB3, and GPIOC0–GPIOC3. The MAX1020/MAX1021
include four GPIO channels (GPIOA0, GPIOA1, GPIOC0,
GPIOC1). Read and write to the GPIOs as detailed in
Table 1 and Tables 12–19. Also, see the GPIO Command
section. See Figures 11 and 12 for GPIO timing.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1020/MAX1021 following the command byte. Write
2 bytes to the MAX1057/MAX1058 following the com-
mand byte.
The GPIOs can sink and source current. The
MAX1057/MAX1058 GPIOA0–GPIOA3 can sink and
source up to 15mA. GPIOB0–GPIOB3 and GPIOC0–
GPIOC3 can sink 4mA and source 2mA. The MAX1020/
MAX1021 GPIOA0 and GPIOA1 can sink and source up
to 15mA. The MAX1020/MAX1021 GPIOC0 and GPIOC1
can sink 4mA and source 2mA. See Table 3.
Clock Modes
Internal Clock
The MAX1020–MAX1023/MAX1057/MAX1058 can
operate from an internal oscillator. The internal oscilla-
tor is active in clock modes 00, 01, and 10. Figures 6,
7, and 8 show how to start an ADC conversion in the
three internally timed conversion modes.
Read out the data at clock speeds up to 25MHz
through the SPI interface.
External Clock
Set CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Table 5. Pulse SCLK at speeds from 0.1MHz to
4.8MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figure 9 for clock mode 11 timing. See the ADC
Conversions in Clock Mode 11 section.
ADC/DAC References
Address the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to pro-
gram the ADC for internal reference. Set REFSEL[1:0] =
10 to program the DAC for external reference, REF1.
When using REF1 or REF2/AIN_ in external-reference
mode, connect a 0.1µF capacitor to AGND. Set REF-
SEL[1:0] = 01 to program the ADC and DAC for exter-
nal-reference mode. The DAC uses REF1 as its external
reference, while the ADC uses REF2 as its external ref-
erence. Set REFSEL[1:0] = 11 to program the ADC for
external differential reference mode. REF1 is the posi-
tive reference and REF2 is the negative reference in the
ADC external differential mode.
When REFSEL [1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL [1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
Temperature Measurements
Issue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
See Table 4. The MAX1020–MAX1023/MAX1057/
MAX1058 perform temperature measurements with an
internal diode-connected transistor. The diode bias cur-
rent changes from 68µA to 4µA to produce a tempera-
ture-dependent bias voltage difference. The second
conversion result at 4µA is subtracted from the first at
68µA to calculate a digital value that is proportional to
absolute temperature. The output data appearing at
DOUT is the digital code above, minus an offset to
adjust from Kelvin to Celsius.
The reference voltage used for the temperature mea-
surements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8 of a
degree Celsius. On every scan where a temperature
measurement is requested, the temperature conversion
is carried out first. The first 2 bytes of data read from
the FIFO contain the result of the temperature measure-
ment. If another temperature measurement is per-
formed before the first temperature result is read out,
the old measurement is overwritten by the new result.
Temperature results are in degrees Celsius (two’s com-
plement). See the Applications Information section for
information on how to perform temperature measure-
ments in each clock mode.
Register Descriptions
The MAX1020–MAX1023/MAX1057/MAX1058 commu-
nicate between the internal registers and the external
Table 3. GPIO Maximum Sink/Source Current
CURRENT
SINK CURRENT
SOURCE CURRENT
GPIOA0–GPIOA3
15mA
15mA
MAX1057/MAX1058
GPIOB0–GPIOB3
4mA
2mA
GPIOC0–GPIOC3
4mA
2mA
MAX1020/MAX1021
GPIOA0, GPIOA1 GPIOC0, GPIOC1
15mA
4mA
15mA
2mA
______________________________________________________________________________________ 23


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
circuitry through the SPI-compatible serial interface.
Table 1 details the command byte, the registers, and
the bit names. Tables 4–12 show the various functions
within the conversion register, setup register, unipolar-
mode register, bipolar-mode register, ADC averaging
register, DAC select register, reset register, and GPIO
command register, respectively.
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by issuing
a command byte to the conversion register. Table 4
details channel selection, the four scan modes, and
how to request a temperature measurement. Start a
scan by writing to the conversion register when in clock
mode 10 or 11, or by applying a low pulse to the
CNVST pin when in clock mode 00 or 01. See Figures 6
and 7 for timing specifications for starting a scan with
CNVST.
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been con-
figured as CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel.
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
Setup Register
Issue a command byte to the setup register to config-
ure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acqui-
sition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog-input
channels for differential operation.
The ADC reference is always on if any of the following
conditions are true:
Table 4. Conversion Register*
BIT
NAME
BIT
FUNCTION
— 7 (MSB) Set to one to select conversion register.
CHSEL3 6 Analog-input channel select.
CHSEL2 5 Analog-input channel select.
CHSEL1 4 Analog-input channel select.
CHSEL0 3 Analog-input channel select.
SCAN1
2 Scan-mode select.
SCAN0
1 Scan-mode select.
TEMP
0 (LSB)
Set to one to take a single temp-
erature measurement. The first
conversion result of a scan contains
temperature information.
*See below for bit details.
CHSEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CHSEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CHSEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CHSEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SELECTED
CHANNEL
(N)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
SCAN1
0
0
1
1
SCAN0
0
1
0
1
SCAN MODE
(CHANNEL N IS SELECTED BY
BITS CHSEL3–CHSEL0)
Scans channels 0 through N.
Scans channels N through the highest
numbered channel.
Scans channel N repeatedly. The ADC
averaging register sets the number of
results.
No scan. Converts channel N once only.
24 ______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 5. Setup Register*
BIT NAME
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
*See below for bit details.
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
FUNCTION
Set to zero to select setup register.
Set to one to select setup register.
Clock mode and CNVST configuration; resets to one at power-up.
Clock mode and CNVST configuration.
Reference-mode configuration.
Reference-mode configuration.
Unipolar-/bipolar-mode register configuration for differential mode.
Unipolar-/bipolar-mode register configuration for differential mode.
Table 5a. Clock Modes (see the Clock Mode section)
CKSEL1
0
0
1
1
CKSEL0
0
1
0
1
CONVERSION CLOCK
Internal
Internal
Internal
External (4.8MHz max)
ACQUISITION/SAMPLING
Internally timed.
Externally timed by CNVST.
Internally timed.
Externally timed by SCLK.
CNVST CONFIGURATION
CNVST
CNVST
AIN15/AIN11/AIN7
AIN15/AIN11/AIN7
Table 5b. Clock Modes 00, 01, and 10
REFSEL1 REFSEL0
VOLTAGE
REFERENCE
OVERRIDE
CONDITIONS
AUTOSHUTDOWN
REF2
CONFIGURATION
Internal reference turns off after scan is complete. If
AIN internal reference is turned off, there is a programmed
0
0
Internal (DAC
and ADC)
delay of 218 internal-conversion clock cycles.
Internal reference required. There is a programmed
AIN14/AIN10/AIN6
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
External single-
AIN Internal reference not used.
0
1
ended (REF1
Internal reference required. There is a programmed
for DAC and Temperature delay of 244 internal-conversion clock cycles for the
REF2
REF2 for ADC)
internal reference to settle after wake-up.
Default reference mode. Internal reference turns off
Internal (ADC)
AIN
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 internal-
1 0 and external
conversion clock cycles.
AIN14/AIN10/AIN6
REF1 (DAC)
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
External
AIN Internal reference not used.
1
1
differential
Internal reference required. There is a programmed
(ADC), external Temperature delay of 244 internal-conversion clock cycles for the
REF2
REF1 (DAC)
internal reference to settle after wake-up.
______________________________________________________________________________________ 25


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
1)The FBGON bit is set to one in the reset register.
2)At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.
3)At least one DAC is powered down through the
100kto VREF and REFSEL[1:0] = 00.
If any of the above conditions exist, the ADC reference
is always on, but there is a 188 clock-cycle delay
before temperature-sensor measurements begin, if
requested.
Table 5c. Clock Mode 11
REFSEL1 REFSEL0
VOLTAGE
REFERENCE
OVERRIDE
CONDITIONS
AUTOSHUTDOWN
REF2
CONFIGURATION
Internal reference turns off after scan is complete. If
AIN internal reference is turned off, there is a programmed
delay of 218 external conversion clock cycles.
0
0
Internal (DAC
and ADC)
Internal reference required. There is a programmed
AIN14/AIN10/AIN6
Temperature
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
AIN Internal reference not used.
External single-
0
1
ended (REF1
for DAC and
REF2 for ADC)
Temperature
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
REF2
at DOUT after 188 further external clock cycles.
Default reference mode. Internal reference turns off
AIN
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 external
Internal (ADC)
conversion clock cycles.
1 0 and external
AIN14/AIN10/AIN6
REF1 (DAC)
Internal reference required. There is a programmed
Temperature
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
AIN Internal reference not used.
External
1
1
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
Temperature
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
REF2
at DOUT after 188 further external clock cycles.
Table 5d. Differential Select Modes
DIFFSEL1 DIFFSEL0
FUNCTION
0 0 No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
0 1 No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
1 0 1 byte of data follows the command setup byte and is written to the unipolar-mode register.
1 1 1 byte of data follows the command setup byte and is written to the bipolar-mode register.
26 ______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 6. Unipolar-Mode Register (Addressed Through the Setup Register)
BIT NAME
UCH0/1
UCH2/3
UCH4/5
UCH6/7
UCH8/9
UCH10/11
UCH12/13
UCH14/15
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
FUNCTION
Configure AIN0 and AIN1 for unipolar differential conversion.
Configure AIN2 and AIN3 for unipolar differential conversion.
Configure AIN4 and AIN5 for unipolar differential conversion.
Configure AIN6 and AIN7 for unipolar differential conversion.
Configure AIN8 and AIN9 for unipolar differential conversion.
Configure AIN10 and AIN11 for unipolar differential conversion.
Configure AIN12 and AIN13 for unipolar differential conversion.
Configure AIN14 and AIN15 for unipolar differential conversion.
Table 7. Bipolar-Mode Register (Addressed Through the Setup Register)
BIT NAME
BCH0/1
BIT
7 (MSB)
FUNCTION
Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar
single-ended conversion.
BCH2/3
Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits
6 in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar
single-ended conversion.
BCH4/5
Set to one to configure AIN4 and AIN5 for bipolar differential conversion. Set the corresponding bits
5 in the unipolar-mode and bipolar-mode registers to zero to configure AIN4 and AIN5 for unipolar
single-ended conversion.
BCH6/7
Set to one to configure AIN6 and AIN7 for bipolar differential conversion. Set the corresponding bits
4 in the unipolar-mode and bipolar-mode registers to zero to configure AIN6 and AIN7 for unipolar
single-ended conversion.
BCH8/9
Set to one to configure AIN8 and AIN9 for bipolar differential conversion. Set the corresponding bits
3 in the unipolar-mode and bipolar-mode registers to zero to configure AIN8 and AIN9 for unipolar
single-ended conversion.
BCH10/11
Set to one to configure AIN10 and AIN11 for bipolar differential conversion. Set the corresponding
2 bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN10 and AIN11 for
unipolar single-ended conversion.
BCH12/13
Set to one to configure AIN12 and AIN13 for bipolar differential conversion. Set the corresponding
1 bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN12 and AIN13 for
unipolar single-ended conversion.
BCH14/15
0 (LSB)
Set to one to configure AIN14 and AIN15 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN14 and AIN15 for
unipolar single-ended conversion.
______________________________________________________________________________________ 27


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unipolar-/bipolar-mode address registers. Set
DIFFSEL[1:0] = 10 to write to the unipolar-mode regis-
ter. Set bits DIFFSEL[1:0] = 11 to write to the bipolar-
mode register. In both cases, the setup command byte
must be followed by 1 byte of data that is written to the
unipolar-mode register or bipolar-mode register. Hold
CS low and run 16 SCLK cycles before pulling CS high.
Table 8. Unipolar/Bipolar Channel Function
UNIPOLAR-
MODE
REGISTER BIT
0
0
1
1
BIPOLAR-MODE
REGISTER BIT
0
1
0
1
CHANNEL PAIR
FUNCTION
Unipolar single-ended
Bipolar differential
Unipolar differential
Unipolar differential
If the last 2 bits of the setup register are 00 or 01, nei-
ther the unipolar-mode register nor the bipolar-mode
register is written. Any subsequent byte is recognized
as a new command byte. See Tables 6, 7, and 8 to pro-
gram the unipolar- and bipolar-mode registers.
Both registers power up at all zeros to set the inputs as
16 unipolar single-ended channels. To configure a
channel pair as single-ended unipolar, bipolar differen-
tial, or unipolar differential, see Table 8.
In unipolar mode, AIN+ can exceed AIN- by up to
VREF. The output format in unipolar mode is binary. In
bipolar mode, either input can exceed the other by up
to VREF/2. The output format in bipolar mode is two’s
complement (see the ADC Transfer Functions section).
ADC Averaging Register
Write a command byte to the ADC averaging register to
configure the ADC to average up to 32 samples for
each requested result, and to independently control the
number of results requested for single-channel scans.
Table 9. ADC Averaging Register*
BIT NAME
BIT
— 7 (MSB)
—6
—5
AVGON
4
NAVG1
3
NAVG0
2
NSCAN1
1
NSCAN0
0 (LSB)
*See below for bit details.
FUNCTION
Set to zero to select ADC averaging register.
Set to zero to select ADC averaging register.
Set to one to select ADC averaging register.
Set to one to turn averaging on. Set to zero to turn averaging off.
Configures the number of conversions for single-channel scans.
Configures the number of conversions for single-channel scans.
Single-channel scan count. (Scan mode 10 only.)
Single-channel scan count. (Scan mode 10 only.)
AVGON
0
1
1
1
1
NAVG1
X
0
0
1
1
NAVG0
X
0
1
0
1
FUNCTION
Performs one conversion for each requested result.
Performs four conversions and returns the average for each requested result.
Performs eight conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
NSCAN1
0
0
1
1
NSCAN0
0
1
0
1
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
Scans channel N and returns four results.
Scans channel N and returns eight results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
28 ______________________________________________________________________________________


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN [1:0] = 11 and SCAN [1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 9) to set up the DAC inter-
face and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
byte controls the DAC serial interface. See Table 20
and the DAC Serial Interface section.
Table 10. DAC Select Register
BIT
NAME
X
X
X
X
BIT FUNCTION
7 (MSB) Set to zero to select DAC select register.
6 Set to zero to select DAC select register.
5 Set to zero to select DAC select register.
4 Set to one to select DAC select register.
3 Don’t care.
2 Don’t care.
1 Don’t care.
0 Don’t care.
Table 11. Reset Register
BIT
NAME
BIT
FUNCTION
— 7 (MSB) Set to zero to select ADC reset register.
— 6 Set to zero to select ADC reset register.
— 5 Set to zero to select ADC reset register.
— 4 Set to zero to select ADC reset register.
— 3 Set to one to select ADC reset register.
RESET
Set to zero to clear the FIFO only. Set to
2 one to set the device in its power-on
condition.
SLOW
1 Set to one to turn on slow mode.
Set to one to force internal bias block and
FBGON 0 (LSB) bandgap reference to be always powered
up.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or to reset all registers to their default
states. Set the RESET bit to one to reset the FIFO. Set
the RESET bit to zero to return the MAX1020–MAX1023/
MAX1057/MAX1058 to their default power-up state. All
registers power up in state 00000000, except for the
setup register that powers up in clock mode 10
(CKSEL1 = 1). Set the SLOW bit to one to add a 15ns
delay in the DOUT signal path to provide a longer hold
time. Writing a one to the SLOW bit also clears the con-
tents of the FIFO. Set the FBGON bit to one to force the
bias block and bandgap reference to power up regard-
less of the state of the DAC and activity of the ADC
block. Setting the FBGON bit high also removes the
programmed wake-up delay between conversions in
clock modes 01 and 11. Setting the FBGON bit high
also clears the FIFO.
GPIO Command
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1020/MAX1021. The 16 SCLK cycles
Table 12. GPIO Command Register
BIT NAME
GPIOSEL1
GPIOSEL2
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
FUNCTION
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
GPIO configuration bit.
GPIO write bit.
GPIOSEL1 GPIOSEL2
FUNCTION
GPIO configuration; written data is
1 1 entered in the GPIO configuration
register.
1 0 GPIO write; written data is entered
in the GPIO write register.
GPIO read; the next 8/16 SCLK
0 1 cycles transfer the state of all GPIO
drivers into DOUT.
______________________________________________________________________________________ 29


MAX1023 (Maxim)
10-Bit / Multichannel ADCs/DACs with FIFO / Temperature Sensing / and GPIO Ports

No Preview Available !

Click to Download PDF File for PC

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
following the command byte load data from DIN to the
GPIO configuration register in the MAX1057/MAX1058.
See Tables 13 and 14. The register bits are updated
after the last CS rising edge. All GPIOs default to inputs
upon power-up.
The data in the register controls the function of each
GPIO, as shown in Tables 13–19.
GPIO Write
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the
command byte load data from DIN into the GPIO write
register in the MAX1020/MAX1021. The 16 SCLK
cycles following the command byte load data from DIN
into the GPIO write register in the MAX1057/MAX1058.
See Tables 15 and 16. The register bits are updated
after the last CS rising edge.
Table 13. MAX1020/MAX1021 GPIO Configuration
DATA PIN
DIN
DOUT
GPIO COMMAND BYTE
00000011
00000000
GPIOC1
0
GPIOC0
0
DATA BYTE
GPIOA1 GPIOA0
00
XXXX
0000
Table 14. MAX1057/MAX1058 GPIO Configuration
DATA PIN
GPIO COMMAND BYTE
DATA BYTE 1
DATA BYTE 2
DIN 0 0 0 0 0 0 1 1
XXXX
DOUT
000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 15. MAX1020/MAX1021 GPIO Write
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN 0 0 0 0 0 0 1 0 GPIOC1 GPIOC0 GPIOA1 GPIOA0 X X X X
DOUT
00000000
0
0 0 0 0 000
Table 16. MAX1057/MAX1058 GPIO Write
DATA PIN
GPIO COMMAND BYTE
DATA BYTE 1
DATA BYTE 2
DIN 0 0 0 0 0 0 1 0
XXXX
DOUT
000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
30 ______________________________________________________________________________________




MAX1023.pdf
Click to Download PDF File