M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITMSUITBSIUSHBISLHSIIsLSIs
M5M4V4265CJM,5TMP4V-452,6-56C,J-,7TP,--55,-S6,,--76,-5SS,,--67SS,-7S
EDOED(HOY(PHEYRPPEARGPEA)GMEO) DMEO4D1E9431094-3B0I4T-B(2IT62(124642-1W44O-WRDORBDY 1B6Y-B1I6T-)BDITY)NDAYMNIACMRICAMRAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
FEATURES
Type name
RAS
CAS Address
access access access
time time time
OE Cycle
access
time
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M4V4265CXX-5,-5S 50
13
25 13
90 408
M5M4V4265CXX-6,-6S 60 15 30 15 110 363
M5M4V4265CXX-7,-7S 70 20 35 20 130 333
XX=TP,J
Standard 40 pin SOJ, 44 pin TSOP (II)
Single 3.3±0.3V supply
Low stand-by power dissipation
CMOS Input level
1.8mW (Max)
CMOS Input level
360µW (Max) *
Operating power dissipation
M5M4V4265CXX-5,-5S
486mW (Max)
M5M4V4265CXX-6,-6S
432mW (Max)
M5M4V4265CXX-7,-7S
396mW (Max)
Self refresh capability *
Self refresh current
100µA (Max)
Extended refresh capability
Extended refresh current
100µA (Max)
EDO mode (512-column random access), Read-modify-write, RAS-
only refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
-7S : option) only
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
memory for CRT
PIN DESCRIPTION
Pin name
A0~A8
DQ1~DQ16
RAS
LCAS
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
UCAS
Upper byte control
column address strobe input
W Write control input
OE Output enable input
VCC Power supply (+3.3V)
VSS Ground (0V)
1
M5M4V4265CJ,TP-5,-5S:under development
PIN CONFIGURATION (TOP VIEW)
(3.3V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(3.3V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
W 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
(3.3V)VCC 20
40 VSS(0V)
39 DQ16
38 DQ15
37 DQ14
36 DQ13
35 VSS(0V)
34 DQ12
33 DQ11
32 DQ10
31 DQ9
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS(0V)
Outline 40P0K (400mil SOJ)
(3.3V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(3.3V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
44 VSS(0V)
43 DQ16
42 DQ15
41 DQ14
40 DQ13
39 VSS(0V)
38 DQ12
37 DQ11
36 DQ10
35 DQ9
NC 13
NC 14
W 15
RAS 16
NC 17
A0 18
A1 19
A2 20
A3 21
(3.3V)VCC 22
32 NC
31 LCAS
30 UCAS
29 OE
28 A8
27 A7
26 A6
25 A5
24 A4
23 VSS(0V)
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC : NO CONNECTION


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to EDO Mode, normal read, write and read-modify-
write operations the M5M4V4265CXX provides a number of other
functions, e.g., RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
RAS
Inputs
LCAS UCAS
Lower byte read
Upper byte read
ACT
ACT
ACT
NAC
NAC
ACT
Word read
ACT ACT ACT
Lower byte write
ACT ACT NAC
Upper byte write
ACT NAC ACT
Word write
ACT ACT ACT
RAS only refresh
ACT NAC NAC
Hidden refresh
ACT ACT ACT
CAS before RAS (Extended *) refresh ACT
ACT
ACT
Self refresh *
ACT ACT ACT
Stand-by
NAC DNC DNC
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
DNC
OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
DNC
DQ1~DQ8
DOUT
OPN
DOUT
DIN
DNC
DIN
OPN
DOUT
OPN
OPN
OPN
Input/Output
DQ9~DQ16
OPN
DOUT
DOUT
DNC
DIN
DIN
OPN
DOUT
OPN
OPN
OPN
BLOCK DIAGRAM
ROW ADDRESS
STROBE INPUT RAS
LOWER BYTE CONTROL
COLUMN ADDRESS LCAS
STROBE INPUT
UPPER BYTE CONTROL UCAS
COLUMN ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
W
CLOCK GENERATOR
CIRCUIT
LOWER
UPPER
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A0~A8
COLUMN DECODER
ROW &
COLUMN
ADDRESS
BUFFER A0~
ROW
A8 DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
MEMORY CELL
(4,194,304 BITS)
(8)LOWER
DATA IN
BUFFER
(8)LOWER
DATA OUT
BUFFER
(8)UPPER
DATA IN
BUFFER
(8)UPPER
DATA OUT
BUFFER
2 M5M4V4265CJ,TP-5,-5S:under development
VCC (3.3V)
VSS (0V)
DQ1
DQ2
DQ8
LOWER DATA
INPUTS /
OUTPUTS
VCC (3.3V)
VSS (0V)
DQ9
DQ10
DQ16
UPPER DATA
INPUTS /
OUTPUTS
VCC (3.3V)
VSS (0V)
OE
OUTPUT
INPUT
ENABLE


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
VO
IO
Pd
Topr
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to VSS
Ta=25˚C
Ratings
-0.5~4.6
-0.5~4.6
-0.5~4.6
50
1000
0~70
-65~150
Unit
V
V
V
mA
mW
˚C
˚C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) (Note 1)
Symbol
Parameter
VCC Supply voltage
VSS Supply voltage
VIH High-level input voltage, all inputs
VIL Low-level input voltage, all inputs
Note 1 : All voltage values are with respect to VSS.
Limits
Min Nom Max
3.0 3.3 3.6
00
0
2.0 VCC+0.3
-0.3 0.8
Unit
V
V
V
V
ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted) (Note 2)
Symbol
VOH
VOL
IOZ
II
ICC1(AV)
Parameter
Test conditions
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc, operating
(Note 3,4,5)
M5M4V4265C-5,-5S
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
IOH=-2mA
IOL=2mA
Q floating 0VVOUTVCC
0VVINVCC+0.3V, Other inputs pins=0V
RAS, CAS cycling
tRC=tWC=min.
output open
RAS= CAS =VIH, output open
Limits
Min Typ Max
2.4 VCC
0 0.4
-5 5
-5 5
135
120
110
2
ICC2 Supply current from VCC, stand-by (Note 6) RAS= CASVCC -0.2V
output open
0.5
0.1 *
ICC3(AV)
Average supply current M5M4V4265C-5,-5S
from Vcc, RAS only
M5M4V4265C-6,-6S
refresh mode (Note 3,5) M5M4V4265C-7,-7S
RAS cycling, CAS=VIH
tRC=min.
output open
125
110
95
ICC4(AV)
ICC6(AV)
Average supply current M5M4V4265C-5,-5S
from Vcc EDO mode
M5M4V4265C-6,-6S
(Note 3,4,5) M5M4V4265C-7,-7S
Average supply current M5M4V4265C-5,-5S
from Vcc
CAS before RAS refresh
M5M4V4265C-6,-6S
mode
(Note 3,5) M5M4V4265C-7,-7S
RAS=VIL, CAS cycling
tPC=min.
output open
CAS before RAS refresh cycling
tRC=min.
output open
125
110
95
115
100
85
ICC8(AV) *
Average supply current
from VCC
Extended-refresh mode
(Note 6)
RAS cycling CAS0.2V or CAS
before RAS refresh cycling
RAS0.2V or VCC-0.2V
CAS0.2V or VCC-0.2V
W0.2V orVCC-0.2V
OE0.2V or VCC-0.2V
A0~A8 0.2V or VCC-0.2V,
DQ=open
tRC=250µs, tRAS=tRAS min~1µs
100
ICC9(AV) *
Average supply current from VCC
Self-refresh mode
RAS=CAS0.2V
(Note 6) output open
100
Note 2 : Current flowing into an IC is positive, out is negative.
3 : ICC1(AV), ICC3(AV), ICC4(AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4 : ICC1(AV) and ICC4(AV) are dependent on output loading. Specified values are obtained with the output open.
5 : Column Address can be changed once or less while RAS=VIL and CAS=VIH.
3
M5M4V4265CJ,TP-5,-5S:under development
Unit
V
V
µA
µA
mA
mA
mA
mA
mA
µA
µA


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted)
Symbol
CI (A)
CI (CLK)
CI / O
Parameter
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Test conditions
VI=VSS
f=1MHz
VI=25mVrms
Limits
Min Typ Max
5
7
7
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Symbol
Parameter
tCAC
tRAC
tAA
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
(Note 13)
(Note 7)
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
M5M4V4265C-5,-5S
Min Max
13
50
25
28
13
5
5
5
13
13
13
13
Limits
M5M4V4265C-6,-6S
Min Max
15
60
30
33
15
5
5
5
15
15
15
15
M5M4V4265C-7,-7S
Min Max
20
70
35
38
20
5
5
5
20
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6 : An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7 : Measured with a load circuit equivalent to 50pF, VOH (IOH=-2mA) and VOL(IOL=2mA). The reference levels for measuring of output signals are
2.0V(VOH) and 0.8V(VOL).
8 : Assumes that tRCDtRCD(max) and tASCtASC(max) and tCPtCP(max).
9 : Assumes that tRCDtRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC
will increase by amount that tRCD exceeds the value shown.
10 : Assumes that tRADtRAD(max) and tASCtASC(max).
11 : Assumes that tCPtCP(max) and tASCtASC(max).
12 : tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT±5µA ) and is not
reference to VOH(min) or VOL(max).
13 : Output is disabled after both RAS and CAS go to high.
4 M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and EDO Mode Cycles)
(Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted, see notes 14,15)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Min Max Min Max Min Max
tREF Refresh cycle time
8.2 8.2 8.2 ms
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
Refresh cycle time *
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
128 128 128
30 40 50
(Note 16) 18
32 20
45 20
50
5 55
0 00
8 10 10
(Note 17) 13 25 15
30 15
35
ms
ns
ns
ns
ns
ns
ns
tASR Row address setup time before RAS low
0 00
ns
tASC
Column address setup time before CAS low
(Note 18) 0
10
0 13
0
13
ns
tRAH Row address hold time after RAS low
8 10 10
tCAH Column address hold time after CAS low
8 10 10
tDZC Delay time, data to CAS low
(Note 19) 0
00
tDZO Delay time, data to OE low
(Note 19) 0
00
tRDD
Delay time, RAS high to data
(Note 20) 13 15 20
tCDD
Delay time, CAS high to data
(Note 20) 13 15 20
ns
ns
ns
ns
ns
ns
tODD
tT
Delay time, OE high to data
Transition time
(Note 20)
(Note 21)
13
1
15
50 1
20
50 1
50
ns
ns
Note 14 : The timing requirements are assumed tT=2ns.
Note 15 : VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Note 16 : tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Note 17 : tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA.
Note 18 : tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC.
Note 19 : Either tDZC or tDZO must be satisfied.
Note 20 : Either tRDD or tCDD or tODD must be satisfied.
Note 21 : tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read setup time before CAS low
tRCH
Read hold time after CAS high
tRRH
Read hold time after RAS high
tRAL Column address to RAS hold time
tCAL Column address to CAS hold time
tORH
RAS hold time after OE low
tOCH
CAS hold time after OE low
Note 22 : Either tRCH or tRRH must be satisfied for a read cycle.
(Note 22)
(Note 22)
M5M4V4265C-5,-5S
Min Max
90
50 10000
8 10000
40
13
0
0
0
25
13
13
13
Limits
M5M4V4265C-6,-6S
Min Max
110
60 10000
10 10000
48
15
0
0
0
30
18
15
15
M5M4V4265C-7,-7S
Min Max
130
70 10000
13 10000
55
20
0
0
0
35
23
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
(Note 24)
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S
Min Max Min Max
90 110
50 10000 60 10000
8 10000 10 10000
40 48
13 15
00
8 10
8 10
8 10
8 10
00
8 10
M5M4V4265C-7,-7S
Min Max
130
70 10000
10 10000
55
20
0
13
13
13
13
0
13
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read-Write and Read-Modify-Write Cycles
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Min Max Min Max Min Max
tRWC
Read write/read modify write cycle time
(Note 23) 109
133
161
ns
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read setup time before CAS low
75 10000
38 10000
70
38
0
89 10000 107 10000
44 10000 57 10000
82 99
44 57
00
ns
ns
ns
ns
ns
tCWD
Delay time, CAS low to W low
(Note 24) 28 32 42
ns
tRWD
Delay time, RAS low to W low
(Note 24) 65 77 92
ns
tAWD
Delay time, address to W low
(Note 24) 40 47 57
ns
tOEH
OE hold time after W low
13 15 20
ns
Note 23 : tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
Note 24 : tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins
will remain high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD(min), tAWDtAWD(min) and tCPWDtCPWD(min)
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
6
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Cycle
(Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Min Max Min Max Min Max
tHPC Hyper page mode read/write cycle time
(Note 26) 20
25
30
tHPRWC Hyper page mode read write/read modify write cycle time
57
66
79
tDOH
Output hold time from CAS low
555
tRAS RAS low pulse width for read or write cycle (Note 27) 65 100000 77 100000 92 100000
tCP CAS high pulse width
(Note 28) 8 13
10 16
10 16
tCPRH
RAS hold time after CAS precharge
28 33 38
tCPWD
Delay time, CAS precharge to W low
(Note 24) 43
50
60
tCHOL
Hold time to maintain the data Hi-Z until CAS access
7
7
7
tOEPE
OE pulse width (Hi-Z control)
777
tWPE
W pulse width (Hi-Z control)
777
tHCWD
Delay time, CAS low to W low after read
28 32 42
tHAWD
Delay time, Address to W low after read
40 47 57
tHPWD
Delay time, CAS precharge to W low after read
43 50 60
tHCOD
Delay time, CAS low to OE high after read
13 15 20
tHAOD
Delay time, Address to OE high after read
25 30 35
tHPOD
Delay time, CAS precharge to OE high after read
28 33 38
Note 25 : All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle.
Note 26 : tHPC(min) is specified in the case of read-only and early write-only in EDO mode.
Note 27 : tRAS(min) is specified as two cycles of CAS input are performed.
Note 28 : tCP(max) is specified as a reference point only.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS before RAS Refresh Cycle (Note 29)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Min Max Min Max Min Max
tCSR CAS setup time before RAS low
5 55
tCHR
tCAS
CAS hold time after RAS low
CAS low pulse width
10 10 15
17 17 22
Note 29 : Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Unit
ns
ns
ns
Self Refresh Cycle * (Note 30)
Symbol
Parameter
tRASS
tRPS
tCHS
CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time
M5M4V4265C-5,-5S
Min Max
100
90
-50
Limits
M5M4V4265C-6,-6S
Min Max
100
110
-50
M5M4V4265C-7,-7S
Min Max
100
130
-50
Unit
µs
ns
ns
7
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams (Note 31)
Read Cycle
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRC
tRAS
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tRAH
tRAD
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRAL
tCAL
tRCS
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
tRRH
tRCH
Hi-Z
tDZC
tCDD
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tOEA
Hi-Z
tREZ
tOHR
tWEZ
tOFF
tOHC
DATA VALID
tOCH
tOEZ
tODD
Hi-Z
tORH
Note 31
Indicates the don't care input.
VIH(min)VINVIH(max) or VIL(min)VINVIL(max)
Indicates the invalid output.
8
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

Byte Read Cycle
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
A0~A8
VIH
VIL
VIH
W
VIL
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
tCRP
tRCD
tRAS
tRC
tCSH
tRSH
tCAS
tRAD
tASR tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRCS
tRAL
tCAL
tRP
tRPC
tCRP
tCPN
tASR
tRRH
ROW
ADDRESS
tRCH
DQ1~DQ8 VIH
(or DQ9~DQ16)
(INPUTS) VIL
DQ1~DQ8 VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
D(oQr 9D~QD1Q~1D6Q8)VIH
(INPUTS) VIL
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
VIH
OE
VIL
Hi-Z
Hi-Z
tDZC
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tCDD
tREZ
tOHR
tOFF
tOHC
DATA VALID
tWEZ
Hi-Z
tOCH
tOEZ
tODD
tORH
9
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

Early Write Cycle
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tCRP
tRCD
tRAS
tWC
tCSH
tRSH
tCAS
tASR tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tWCS
tWCH
tDS tDH
DATA VALID
Hi-Z
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
10 M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Early Write Cycle
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
A0~A8
VIH
VIL
VIH
W
VIL
tCRP
tRCD
tWC
tRAS
tCSH
tRSH
tCAS
tASR tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tWCS
tWCH
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
DQ1~DQ8 VIH
(or DQ9~DQ16)
(INPUTS) VIL
DQ1~DQ8 VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
(DoQr 9D~QD1Q~1D6Q8)VIH
(INPUTS) VIL
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
Hi-Z
tDS tDH
DATA VALID
Hi-Z
VIH
OE
VIL
11
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Delayed Write Cycle
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tCRP
tRCD
tWC
tRAS
tCSH
tRSH
tCAS
tRP
tRPC
tCRP
tASR
tRAH
ROW
ADDRESS
tASC
tRCS
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWP
Hi-Z
tDZC
Hi-Z
tCLZ
tWCH
tDS
tDH
DATA
VALID
tDZO
tOEZ
tODD
tOEH
Hi-Z
tASR
ROW
ADDRESS
12 M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Delayed Write Cycle
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
A0~A8
VIH
VIL
VIH
W
VIL
tCRP
tRCD
tWC
tRAS
tCSH
tRSH
tRP
tRPC
tCRP
tCAS
tASR
tRAH
ROW
ADDRESS
tASC
tRCS
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWP
tASR
ROW
ADDRESS
DQ1~DQ8 VIH
(or DQ9~DQ16)
(INPUTS) VIL
DQ1~DQ8 VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
(DoQr 9D~QD1Q~1D6Q8)VIH
(INPUTS) VIL
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
VIH
OE
VIL
Hi-Z
Hi-Z
tDZC
Hi-Z
tCLZ
tWCH
tDS tDH
DATA
VALID
tDZO
tOEZ
tODD
tOEH
Hi-Z
13
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRWC
tRAS
tCRP
tRCD
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tRCS
tCSH
tRSH
tCAS
tCAH
COLUMN
ADDRESS
tAWD
tCWD
tRWD
tCWL
tRWL
tWP
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
Hi-Z
tDZC
Hi-Z
tCAC
tAA
tCLZ
tDS
tRAC
tDZO
DATA
VALID
tOEA
tODD
tOEZ
tDH
DATA VALID
tOEH
Hi-Z
14
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Read-Write, Read-Modify-Write Cycle
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
A0~A8
VIH
VIL
VIH
W
VIL
tCRP
tRCD
tRWC
tRAS
tCSH
tRSH
tRP
tRPC
tCRP
tCAS
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tRCS
tCAH
COLUMN
ADDRESS
tAWD
tCWD
tRWD
tCWL
tRWL
tWP
tASR
ROW
ADDRESS
D(oQr 1D~QD9Q~8DQ16V) IH
(INPUTS) VIL
DQ1~DQ8 VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
(DoQr 9D~QD1Q~1D6Q8)VIH
(INPUTS) VIL
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
VIH
OE
VIL
Hi-Z
Hi-Z
tDZC
tRAC
tDS
Hi-Z
tCAC
tAA
tCLZ
DATA
VALID
tDZO
tOEA
tODD
tOEZ
tDH
DATA VALID
Hi-Z
tOEH
15
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRAS
tRP
tCRP
tCSH
tRCD
tCAS
tHPC
tCP tCAS
tRSH
tCP tCAS
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN-1
tRCS
tCAL
tASC tCAH
COLUMN-2
tCAL
tASC
tCPRH
tCAH
COLUMN-3
tRAL
tCAL
tASR
tRRH
ROW
ADDRESS
tRCH
tDZC
Hi-Z
tCAC
tAA
tCLZ
Hi-Z
tCAC
tAA
tDOH
tCAC
tAA
tDOH
tRAC
tDZO
DATA
VALID-1
tOEA
tOCH
tCPA
DATA
VALID-2
tCPA
tWEZ
tRDD
tCDD
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tOEZ
tODD
16
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read Cycle
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
tCRP
tRCD
tCSH
tRAS
tHPC
tCP tCAS
UCAS
(or LCAS)
VIH
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ8 VIH
(or DQ9~DQ16)
(INPUTS) VIL
DQ1~DQ8 VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
D(oQr 9D~QD1Q~1D6Q8)VIH
(INPUTS) VIL
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
VIH
OE
VIL
tCAS
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN-1
tRCS
tCAL
tASC
tCAH
COLUMN-2
tCAL
tDZC
Hi-Z
tDZC
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tOCH
tCAC
tAA
tCLZ
tCPA
Hi-Z
DATA
VALID-1
17 M5M4V4265CJ,TP-5,-5S:under development
tRSH
tCP
tRP
tCAS
tCRP
tASC
tCPRH
tCAH
COLUMN-3
tRAL
tCAL
tASR
tRRH
ROW
ADDRESS
tRCH
Hi-Z
DATA
VALID-2
tREZ
tOHR
tRDD
tCDD
tCAC
tAA
tDOH
tCPA
tWEZ
tOFF
tOHC
DATA
VALID-3
tOEZ
tODD


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Early Write Cycle
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
tRAS
tRP
tCRP
tCSH
tRCD
tCAS
tHPC
tCP tCAS
tRSH
tCP tCAS
tCRP
tASR tRAH
ROW
ADDRESS
tASC tCAH
COLUMN-1
tWCS tWCH
tASC
tCAL
tCAH
COLUMN-2
tWCS tWCH
tASC
tCAL
tCAH
COLUMN-3
tWCS tWCH
tASR
ROW
ADDRESS
tDS tDH
DATA
VALID-1
tDS tDH
DATA
VALID-2
tDS tDH
DATA
VALID-3
DQ1~DQ16 VOH
(OUTPUTS) VOL
Hi-Z
VIH
OE
VIL
18
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Early Write Cycle
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ8 VIH
(or DQ9~DQ16)
(INPUTS) VIL
tCRP
tCSH
tRAS
tHPC
tRSH
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tASR tRAH
ROW
ADDRESS
tASC tCAH
COLUMN-1
tWCS tWCH
tASC
tCAL
tCAH
COLUMN-2
tWCS tWCH
tASC
tCAL
tCAH
COLUMN-3
tWCS tWCH
tDS tDH
DATA
VALID-1
tDS tDH
DATA
VALID-3
tRP
tCRP
tASR
ROW
ADDRESS
DQ1~DQ8 VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
D(oQr 9D~QD1Q~1D6Q8)VIH
(INPUTS) VIL
Hi-Z
tDS tDH
DATA
VALID-2
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
Hi-Z
VIH
OE
VIL
19 M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read-Write, Read-Modify-Write Cycle
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRAS
tRP
tCRP
tRCD
tCSH
tCAS
tHPRWC
tRWL
tCRP
tCP tCAS
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN-1
tRCS
tAWD
tCWD
tASC
tCAH
COLUMN-2
tCWL
tWP tRCS
tAWD
tCWD
tCWL
tASR
ROW
ADDRESS
tWP
Hi-Z
tDZC
tRWD
tCPWD
tDS tDH tDZC
tDS
tDH
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
DATA
VALID-1
tOEA
DATA
VALID-1
Hi-Z
tCAC
tAA
DATA
VALID-2
tODD
tOEZ
Hi-Z
tCLZ
DATA
VALID-2
tCPA
tDZO
tOEA
tODD
tOEZ
Hi-Z
tOEH
20
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read-Write, Read-Modify-Write Cycle
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ8 VIH
(or DQ9~DQ16)
(INPUTS) VIL
DQ1~DQ8 VOH
(or DQ9~DQ16)
(OUTPUTS) VOL
D(oQr 9D~QD1Q~1D6Q8)VIH
(INPUTS) VIL
DQ9~DQ16 VOH
(or DQ1~DQ8)
(OUTPUTS) VOL
VIH
OE
VIL
tCRP
tCSH
tRAS
tRP
tRWL
tRCD
tCAS
tHPRWC
tCP tCAS
tCRP
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN-1
tRCS
tAWD
tCWD
tASC
tCAH
COLUMN-2
tCWL
tWP tRCS
tAWD
tCWD
tCWL
tASR
ROW
ADDRESS
tWP
tRWD
tCPWD
Hi-Z
Hi-Z
tDZC
tDS tDH tDZC
tDS tDH
Hi-Z
tCAC
tAA
DATA
VALID-1
Hi-Z
tCAC
tAA
DATA
VALID-2
tCLZ
tRAC
tDZO
DATA
VALID-1
tOEA
tODD
tOEZ
Hi-Z
tCLZ
DATA
VALID-2
tCPA
tDZO
tOEA
tODD
tOEZ
Hi-Z
tOEH
21
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (1)
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRAS
tRWL
tRP
tCRP
tCSH
tRCD
tCAS
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN-1
tRCS
tCAL
tHPC
tCP tCAS
tCP
tHPRWC
tCAS
tCWL
tCRP
tASC tCAH
tASC tCAH
COLUMN-2
tWCS
tWCH
tCAL
COLUMN-3
tCPWD
tAWD
tCWD
tASR
ROW
ADDRESS
tWP
Hi-Z
tDZC
tDH
tDS
tCAC
tAA
tCLZ
DATA
VALID-2
tWEZ
tRAC
tDZO
DATA
VALID-1
tOEA
tOCH
tOEZ
tDZC
tDS tDH
tAA
tCAC
tCLZ
DATA
VALID-3
tCPA
tDZO tOEA tOEZ
DATA
VALID-3
tOEH
tODD
tODD
22 M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (2)
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tCP
tASC
tCAS
tCAH
COLUMN-1
tCAL
tASC
tCAS
tCAH
tRCH
COLUMN-2
tWCS
tCAL
tWCH
tASC
tCAH
COLUMN-3
tHCWD
tHAWD
tHPWD
Hi-Z
tCAC
tAA
tCPA
tHCOD
tHAOD
tHPOD
tDH
tDS
DATA
VALID-2
tWEZ
DATA
VALID-1
tOEZ
tODD
Hi-Z
tDZC
Hi-Z
tAA
tCPA
tCAC
tCLZ
DATA
VALID-3
tDZC
tOEA
23
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by OE)
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRAS
tRP
tCRP
tRCD
tCSH
tCAS
tHPC
tCP tCAS
tRSH
tCP tCAS
tCRP
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN-1
tRCS
tASC tCAH
COLUMN-2
tCPRH
tASC tCAH
COLUMN-3
tRAL
tASR
ROW
ADDRESS
tRRH
tRCH
tDZC
Hi-Z
tCAC
tAA
tCLZ
Hi-Z
tCAC
tAA
tDOH
tCAC
tAA
tCLZ
tRAC
tDZO
DATA
VALID-1
DATA
VALID-1
tOEA
tOEZ
tCPA
tOCH
tOEA
DATA
VALID-2
Hi-Z
tCPA
tCHOL
tOEZ
tOEPE
tOEPE
tWEZ
tRDD
tCDD
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tOEZ
tODD
24 M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by W)
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRAS
tRP
tCRP
tRCD
tCSH
tCAS
tHPC
tCP tCAS
tRSH
tCP tCAS
tCRP
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN-1
tRCS
tASC tCAH
COLUMN-2
tRCH
tCPRH
tASC tCAH
COLUMN-3
tRAL
tRCS
tASR
ROW
ADDRESS
tRRH
tRCH
tDZC
tWPE
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tOCH
Hi-Z
tCAC
tAA
tDOH
tWEZ
tCAC
tAA
tCLZ
DATA
VALID-1
tCPA
DATA
VALID-2
Hi-Z
tCPA
tWEZ
tRDD
tCDD
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tOEZ
tODD
25 M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
tRAS
tRC
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
Hi-Z
VIH
OE
VIL
26
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle, Extended Refresh Cycle *
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
tRC
tRP tRAS
tRAS
tRC
tRP
tRPC tCSR
tCHR
tCPN
tRRH
tRCH
tRPC tCSR
tCHR
tRPC
tCRP
tASR
ROW
COLUMN
ADDRESS ADDRESS
tRCS
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tREZ
tOHR
tOFF
tOHC
tOEZ
Hi-Z
27 M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 32)
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRC
tRAS
tRP
tRC
tRAS
tCRP
tRCD
tRSH
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
tRCS
COLUMN
ADDRESS
tRAL
tRRH
tCHR
tRP
tASR
ROW
ADDRESS
tDZC
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tORH
Hi-Z
DATA VALID
tCDD
tRDD
tREZ
tOHR
tOFF
tOHC
Hi-Z
tOEZ
tODD
Note 32 : Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
28
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh Cycle * (Note 30)
RAS
VIH
VIL
VIH
LCAS/UCAS
VIL
A0~A8
VIH
VIL
VIH
W
VIL
DQ1~DQ16 VIH
(INPUTS) VIL
DQ1~DQ16 VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRP
tRPC tCSR
tCPN
tRRH
tRCH
tRDD
tCDD
Hi-Z
tREZ
tOHR
tOFF
tOHC
tOEZ
tODD
tRASS
tRPS
tRPC
tCHS
tCRP
tASR
ROW
ADDRESS
tRCS
Hi-Z
29
M5M4V4265CJ,TP-5,-5S:under development


M5M4V4265CTP-5S (Mitsubishi)
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Note 30 : Self refresh sequence
Two refreshing methods should be used properly depending on
the low pulse width (tRASS) of RAS signal during self refresh
period.
1. Distributed refresh during Read/Write operation
(A) Timing Diagram
Read / Write Cycle
tNSD
Self Refresh Cycle
tRASS100µs
RAS
Table 2
Read / Write Cycle
CBR distributed
refresh
RAS only
distributed refresh
last
refresh cycle
Read / Write
Self Refresh
tNSD250µs
tNSD16µs
Self Refresh
Read / Write
tSND250µs
tSND16µs
Read / Write Cycle
tSND
first
refresh cycle
(B) Definition of distributed refresh
tREF / 512
tREF
tREF / 512
RAS
refresh
cycle
read/write
cycles
refresh
cycle
refresh
cycle
read/write
cycles
Definition of CBR distributed refresh
(Including extended refresh)
The CBR distributed refresh performs more than 512
constant period (250µs max.) CBR cycles within 128 ms.
Definition of RAS only distributed refresh
All combinations of nine row address signals (A0 ~ A8) are
selected during 512 constant period (16µs max.) RAS only
refresh cycles within 8.2 ms.
Note:
Hidden refresh may be used instead of CBR refresh.
RAS/CAS refresh may be used instead of RAS only refresh.
1.1 CBR distributed refresh
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the last
CBR refresh cycle during read/write operation period to the falling
edge of RAS signal at the start of self refresh operation should be
set within tNSD (shown in table 2).
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period should
be set within tSND (shown in table 2).
1.2 RAS only distributed refresh
Switching from read/write operation to self refresh operation.
The time interval t NSD from the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period to
the falling edge of RAS signal at the start of self refresh
operation should be set within 16µs.
Switching from self refresh operation to read/write operation.
The time interval tSND from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the first CBR refresh cycle during read/write operation period
should be set within 16µs.
30
M5M4V4265CJ,TP-5,-5S:under development




M5M4V4265CTP-5S.pdf
Click to Download PDF File