M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
The M5M467405/465405DJ,DTP is a 16777216-word by 4-bit, M5M467805/465805DJ,DTP is a 8388608-word by 8-bit, and
M5M465165DJ,DTP is a 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and are
suitable for large-capacity memory systems with high speed and low power dissipation.
FEATURES
Type name
RAS
CAS Address OE Cycle
access access access access
time
time time
time
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M467405DXX-5,5S
M5M467805DXX-5,5S
50
13
25
13
84 300
M5M467405DXX-6,6S
M5M467805DXX-6,6S
60
15
30
15 104 250
M5M465405DXX-5,5S
M5M465805DXX-5,5S
50
13
25
13
84 390
M5M465405DXX-6,6S
M5M465805DXX-6,6S
60
15
30
15 104 325
XX=J,TP
Type name
M5M465165DXX-5,5S
M5M465165DXX-6,6S
RAS
CAS Address OE
access access access access
time
time time
time
Cycle
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
50 13 25 13 84 420
60 15 30 15 104 390
Standard 32 pin SOJ, 32 pin TSOP (M5M467405Dxx/M5M465405Dxx/M5M467805Dxx/M5M465805Dxx)
Standard 50 pin SOJ, 50 pin TSOP (M5M465165Dxx)
Single 3.3 ± 0.3V supply
Low stand-by power dissipation
1.8mW (Max)
LVCMOS input level
Low operating power dissipation
M5M467405Dxx-5,5S / M5M467805Dxx-5,5S
360.0mW (Max)
M5M467405Dxx-6,6S / M5M467805Dxx-6,6S
324.0mW (Max)
M5M465405Dxx-5,5S / M5M465805Dxx-5,5S
468.0mW (Max)
M5M465405Dxx-6,6S / M5M465805Dxx-6,6S
432.0mW (Max)
M5M465165Dxx-5,5S
504.0mW (Max)
M5M465165Dxx-6,6S
468.0mW (Max)
Self refresh capability*
Self refresh current
400µA (Max)
EDO mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode , OE and W to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
* :Applicable to self refresh version(M5M467405/465405/467805/465805/465165DJ,DTP-5S,-6S:option) only
ADDRESS
Part No.
Row Add. Col. Add.
Refresh
Refresh Cycle
Normal S-version
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467405Dxx A0-A12 A0-A10
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465405Dxx A0-A11
A0-A11
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
M5M467805Dxx A0-A12 A0-A9
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465805Dxx A0-A11
M5M465165Dxx A0-A11
A0-A10
A0-A9
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
1 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PIN DESCRIPTION
M5M467405Dxx / M5M465405Dxx
Pin Name Function
A0-A12
Address Inputs
DQ1-DQ4 Data Inputs / Outputs
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+3.3V)
Vss Ground (0V)
NC No Connection
M5M467805Dxx / M5M465805Dxx
Pin Name Function
A0-A12
Address Inputs
DQ1-DQ8 Data Inputs / Outputs
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+3.3V)
Vss Ground (0V)
NC No Connection
M5M465165Dxx
Pin Name Function
A0-A11
Address Inputs
DQ1-DQ16 Data Inputs / Outputs
RAS
UCAS
LCAS
Row Address Strobe Input
Upper byte control
Column Address Strobe Input
Lower byte control
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+3.3V)
Vss Ground (0V)
NC No Connection
XX=J, TP
M5M467400/465400DJ, DTP PIN CONFIGURATION (TOP VIEW)
Vcc
DQ1
DQ2
NC
NC
NC
NC
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ4
30 DQ3
29 NC
28 NC
27 NC
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Outline 32P0N (400mil SOJ)
Vcc
DQ1
DQ2
NC
NC
NC
NC
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ4
30 DQ3
29 NC
28 NC
27 NC
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467405Dxx, NC...M5M465405Dxx
NC : NO CONNECTION
2 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467805/465805DJ, DTP PIN CONFIGURATION (TOP VIEW)
Vcc 1
DQ1 2
DQ2 3
DQ3
DQ4
NC
Vcc
4
5
6
7
W8
RAS
A0
A1
A2
9
10
11
12
A3 13
A4 14
A5 15
Vcc 16
32 Vss
31 DQ8
30 DQ7
29 DQ6
28 DQ5
27 Vss
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Vcc
DQ1
DQ2
DQ3
DQ4
NC
Vcc
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ8
30 DQ7
29 DQ6
28 DQ5
27 Vss
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Outline 32P0N (400mil SOJ)
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467800Dxx, NC...M5M465800Dxx
NC : NO CONNECTION
M5M465165DJ, DTP
PIN CONFIGURATION (TOP VIEW)
Vcc 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
Vcc 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
Vcc 12 12
W 13
RAS 14
NC 15
NC 16
NC 17
NC 18
A0 19
A1 20
A2 21
A3 22
A4 23
A5 24
Vcc 25
50 Vss
49 DQ16
48 DQ15
47 DQ14
46 DQ13
45 Vss
44 DQ12
43 DQ11
42 DQ10
41 DQ9
40 NC
39 Vss
38 LCAS
37 UCAS
36 OE
35 NC
34 NC
33 NC
32 A11
31 A10
30 A9
29 A8
28 A7
27 A6
26 Vss
Vcc 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
Vcc 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
Vcc 12 12
W 13
RAS 14
NC 15
NC 16
NC 17
NC 18
A0 19
A1 20
A2 21
A3 22
A4 23
A5 24
Vcc 25
50 Vss
49 DQ16
48 DQ15
47 DQ14
46 DQ13
45 Vss
44 DQ12
43 DQ11
42 DQ10
41 DQ9
40 NC
39 Vss
38 LCAS
37 UCAS
36 OE
35 NC
34 NC
33 NC
32 A11
31 A10
30 A9
29 A8
28 A7
27 A6
26 Vss
Outline 50P0G (400mil SOJ)
Outline 50P3G (400mil TSOP Normal Bend)
NC : NO CONNECTION
3 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
The M5M467405(805)/465405(805,165)DJ, DTP provide, in addition to normal read, write, and read-modify-write operations,
a number of other functions, e.g., EDO mode, CAS before RAS refresh, and delayed-write.
The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
M5M467405Dxx / M5M465405Dxx / M5M467805Dxx / M5M465805Dxx
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Standby
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
Inputs
W
NAC
ACT
ACT
ACT
DNC
NAC
NAC
DNC
OE
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
APD
DNC
DNC
DNC
Column
address
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Input/Output
Input
OPN
VLD
VLD
VLD
OPN
OPN
DNC
DNC
Output
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
Refresh Remark
NO
NO
NO
NO
YES
YES
YES
NO
EDO mode
identical
M5M465165Dxx
Operation
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Stand-by
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
LCAS
ACT
NAC
ACT
ACT
NAC
ACT
NAC
ACT
ACT
DNC
Inputs
UCAS
NAC
ACT
ACT
NAC
ACT
ACT
NAC
ACT
ACT
DNC
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
Column
address
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Input/Output
DQ1~DQ8 DQ9~DQ16
VLD
OPN
OPN
VLD
VLD
VLD
DIN DNC
DNC
DIN
DIN
OPN
DIN
OPN
VLD
VLD
OPN
OPN
OPN
OPN
Refresh Remark
NO
NO
NO
NO
NO
NO
YES
YES
YES
NO
EDO mode
identical
4 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467405Dxx / M5M465405Dxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A11
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
M5M467805Dxx / M5M465805Dxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A10
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
5 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M465165Dxx
BLOCK DIAGRAM
ROW ADDRESS
STROBE INPUT
RAS
LOWER BYTE CONTROL LCAS
COLUMN ADDRESS
STROBE INPUT
UPPER BYTE CONTROL UCAS
COLUMN ADDRESS
STROBE INPUT
WRITE CONTROL INPUT W
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
CLOCK GENERATOR
CIRCUIT
LOWER
UPPER
A0~A9
A0 ~
A11
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O
CONTROL
MEMORY CELL
(67108864BITS)
VCC (3.3V)
VSS (0V)
DQ1
DQ2
LOWER DATA
INPUTS / OUTPUTS
DQ8
DQ9
DQ10
UPPER DATA
INPUTS / OUTPUTS
DQ16
OE OUTPUT ENABLE
INPUT
6 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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Click to Download PDF File for PC

(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc
VI
V0
I0
Pd
Topr
Tstg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to Vss
Ta=25 C
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
1000
0 ~ 70
-65 ~ 150
Unit
V
V
V
mA
mW
C
C
RECOMMENDED OPERATING CONDITIONS (Ta=0 ~70 C, unless otherwise noted) (Note 1)
Symbol
Parameter
Limits
Min Nom Max
Unit
Vcc Supply voltage
Vss Supply voltage
VIH High-level input voltage, all inputs
3.0 3.3
3.6
00
0
2.0 Vcc+0.3
V
V
V
VIL Low-level input voltage, all inputs
-0.3 0.8 V
Note 1 : All voltage values are with respect to Vss.
ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted) (Note 2)
[M5M467405D / M5M467805D]
Symbol
Parameter
Test conditions
VOH
VOL
IOZ
II
ICC1 (AV)
ICC2 (AV)
ICC4 (AV)
ICC6 (AV)
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc
operating
(Note 3,4,5)
Average supply current
from Vcc
stand-by
(Note 6)
Average supply current
from Vcc
EDO-Mode
(Note 3,4,5)
Average supply current
from Vcc
CAS before RAS refresh
mode
(Note 3,5)
IOH=-2mA
M5M467405D-5,5S
M5M467805D-5,5S
M5M467405D-6,6S
M5M467805D-6,6S
M5M467405D-5,5S
-6,6S
M5M467805D-5,5S
-6,6S
IOL=2mA
Q floating 0V VOUT Vcc
0VVIN Vcc+0.3V, Other input pins=0V
RAS, CAS cycling
tRC=tWC=min.
output open
RAS= CAS =VIH, output open
M5M467405D-5,6
M5M467805D-5,6
M5M467405D-5S,6S
RAS= CAS Vcc -0.2V,output open
M5M467805D-5S,6S
M5M467405D-5,5S
M5M467805D-5,5S
M5M467405D-6,6S
M5M467805D-6,6S
RAS=VIL, CAS cycling
tHPC=min.
output open
M5M467405D-5,5S
M5M467805D-5,5S
M5M467405D-6,6S
M5M467805D-6,6S
CAS before RAS refresh cycling
tRC=min.
output open
Limits
Min Typ Max
2.4 Vcc
0 0.4
-10 10
-10 10
100
90
1
0.5
0.3
100
90
130
120
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column Address can be changed once or less while RAS=VIL and CAS=VIH.
Unit
V
V
µA
µA
mA
mA
mA
mA
7 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
~ELECTRICAL CHARACTERISTICS (Ta=0 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted) (Note 2)
[M5M465405D / M5M465805D]
Symbol
Parameter
Test conditions
Limits
Min Typ Max
VOH
VOL
IOZ
II
ICC1 (AV)
ICC2 (AV)
ICC4 (AV)
ICC6 (AV)
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc
operating
(Note 3,4,5)
Average supply current
from Vcc
stand-by
(Note 6)
Average supply current
from Vcc
EDO-Mode
(Note 3,4,5)
Average supply current
from Vcc
CAS before RAS refresh
mode
(Note 3,5)
IOH=-2mA
IOL=2mA
Q floating 0V VOUT Vcc
0VVIN Vcc+0.3V, Other input pins=0V
M5M465405D-5,5S
M5M465805D-5,5S
M5M465405D-6,6S
M5M465805D-6,6S
RAS, CAS cycling
tRC=tWC=min.
output open
M5M465405D-5,5S
-6,6S
M5M465805D-5,5S
-6,6S
RAS= CAS =VIH, output open
M5M465405D-5,6
M5M465805D-5,6
M5M465405D-5S,6S
M5M465805D-5S,6S
RAS= CAS Vcc -0.2V,output open
M5M465405D-5,5S
M5M465805D-5,5S
M5M465405D-6,6S
M5M465805D-6,6S
RAS=VIL, CAS cycling
tHPC=min.
output open
M5M465405D-5,5S
M5M465805D-5,5S
M5M465405D-6,6S
M5M465805D-6,6S
CAS before RAS refresh cycling
tRC=min.
output open
2.4
0
-10
-10
Vcc
0.4
10
10
130
120
1
0.5
0.3
100
90
130
120
Unit
V
V
µA
µA
mA
mA
mA
mA
[M5M465165D]
Symbol
Parameter
Test conditions
Limits
Min Typ Max
VOH High-level output voltage
IOH=-2mA
2.4 Vcc
VOL Low-level output voltage
IOZ Off-state output current
I I Input current
IOL=2mA
Q floating 0V VOUT Vcc
0V VIN Vcc+0.3V, Other input pins=0V
0
-10
-10
0.4
10
10
ICC1 (AV)
ICC2 (AV)
Average supply current
from Vcc
operating
(Note 3,4,5)
Average supply current
from Vcc
stand-by
(Note 6)
M5M465165D-5,5S
M5M465165D-6,6S
M5M465165D-5,5S
-6,6S
M5M465165D-5,6
M5M465165D-5S,6S
RAS, CAS cycling
tRC=tWC=min.
output open
RAS= CAS =VIH, output open
RAS= CAS Vcc -0.2V, output open
140
130
1
0.5
0.3
ICC4 (AV)
ICC6 (AV)
Average supply current
M5M465165D-5,5S
from Vcc
EDO-Mode
(Note 3,4,5) M5M465165D-6,6S
Average supply current
from Vcc
CAS before RAS refresh
mode
(Note 3,5)
M5M465165D-5,5S
M5M465165D-6,6S
RAS=VIL, CAS cycling
tHPC=min.
output open
CAS before RAS refresh cycling
tRC=min.
output open
120
110
140
130
Unit
V
V
µA
µA
mA
mA
mA
mA
8 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
~CAPACITANCE (Ta=0 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted)
Symbol
Parameter
Test conditions
CI (A)
CI (OE)
CI (W)
CI (RAS)
CI (CAS)
CI / O
Input capacitance,address inputs
Input capacitance, OE input
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports
VI=Vss
f=1MHZ
Vi=25mVrms
Limits
Min Typ Max
5
7
7
7
7
7
Unit
pF
pF
pF
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Limits
Symbol
Parameter
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S Unit
M5M465165D-5,5S M5M465165D-6,6S
Min
Max
Min
Max
tCAC Access time from CAS
(Note 7,8)
13 15 ns
tRAC Access time from RAS
(Note 7,9)
50 60 ns
tAA Column address access time
(Note 7,10)
25 30 ns
tCPA Access time from CAS precharge
(Note 7,11)
28 33 ns
tOEA Access time from OE
(Note 7)
13 15 ns
tOHC Output hold time from CAS
5 5 ns
tOHR Output hold time from RAS
(Note 13)
5
5 ns
tCLZ Output low impedance time from CAS low (Note 7)
5
5 ns
tOEZ Output disable time after OE high
(Note 12)
13 15 ns
tWEZ Output disable time after W high
(Note 12)
13 15 ns
tOFF Output disable time after CAS high
(Note 12,13)
13
15 ns
tREZ Output disable time after RAS high
(Note 12,13)
13
15 ns
Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing RAS-only refresh or CAS before RAS refresh).
Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are VOH=2.0V and VOL=0.8V.
8: Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP tCP(max).
9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD tRAD(max) and tASC tASC(max).
11: Assumes that tCP tCP(max) and tASC tASC(max).
12: tOEZ(max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT ± 10 µA) and is
not reference to VOH(min) or VOL(max).
13: Output is disabled after both RAS and CAS go to high.
9 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and EDO Mode Cycles)
(Ta=0 ~ 70 C , Vcc=3.3 ±0.3V, Vss=0V, unless otherwise noted See notes 14,15)
Symbol
Parameter
tREF
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tWED
tT
Refresh cycle time
Refresh cycle time (S-version only)
RAS high pulse width
Delay time, RAS low to CAS low
(Note16)
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
(Note17)
Row address setup time before RAS low
Column address setup time before CAS low (Note18)
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, RAS high to data
Delay time, CAS high to data
(Note19)
(Note19)
(Note20)
(Note20)
Delay time, OE high to data
(Note20)
Delay time, W low to data
Transition time
(Note20)
(Note21)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Unit
Min
Max
Min
Max
64 64 ms
128 128 ms
30 40 ns
14 37 14 45 ns
5 5 ns
0 0 ns
8 10 ns
10 25 12 30 ns
0
0 10
0 ns
0 13 ns
8 10 ns
8 10 ns
0 0 ns
0 0 ns
13 15 ns
13 15 ns
13 15 ns
13 15 ns
1 50
1 50 ns
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA.
17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD or tWED must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read Setup time before CAS low
tRCH Read hold time after CAS high
tRRH Read hold time after RAS high
tRAL Column address to RAS hold time
tCAL Column address to CAS hold time
tORH RAS hold time after OE low
tOCH CAS hold time after OE low
(Note 22)
(Note 22)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Min Max Min Max
84 104
50 10000 60 10000
8 10000 10 10000
35 40
13 15
00
00
00
25 30
13 18
13 15
13 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
10 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
(Note 24)
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Min Max Min Max
84 104
50 10000 60 10000
8 10000 10 10000
35 40
13 15
00
8 10
8 10
8 10
8 10
00
8 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
OE hold time after W low
(Note23)
(Note24)
(Note24)
(Note24)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S Unit
M5M465165D-5,5S M5M465165D-6,6S
Min Max Min Max
109 133 ns
75 10000
89 10000 ns
38 10000
70
44 10000 ns
82 ns
38 44 ns
0 0 ns
28 32 ns
65 77 ns
40 47 ns
13 15 ns
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min)
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi-
nate.
11 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle,
Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25)
Symbol
Parameter
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Unit
Min
Max
Min
Max
tHPC
tHPRWC
tDOH
tRAS
tCP
tCPRH
tCPWD
tCHOL
tOEPE
tWPE
tHCWD
tHAWD
tHPWD
tHCOD
tHAOD
tHPOD
EDO mode read/write cycle time
EDO Mode read write / read modify write cycle time
Output hold time from CAS low
RAS low pulse width for read write cycle
(Note26)
CAS high pulse width
(Note27)
RAS hold time after CAS precharge
Delay time, CAS precharge to W low
(Note24)
Hold time to maintain the data Hi-Z until CAS access
OE Pulse Width (Hi-Z control)
W Pulse Width (Hi-Z control)
Delay time, CAS low to W low after read
Delay time, Address to W low after read
Delay time, CAS precharge to W low after read
Delay time, CAS low to OE high after read
Delay time, Address to OE high after read
Delay time, CAS precharge to OE high after read
20
55
5
65
8
28
43
7
7
7
28
40
43
13
25
28
25 ns
66 ns
5 ns
100000 77 100000 ns
13 10 16 ns
33 ns
50 ns
7 ns
7 ns
7 ns
32 ns
47 ns
50 ns
15 ns
30 ns
33 ns
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle.
26: tRAS(min) is specified as two cycles of CAS input are performed.
27: tCP(max) is specified as a reference point only. If tCP tCP(max) , access time is controlled exclusively by tCAC.
CAS before RAS Refresh Cycle (Note 28)
Symbol
Parameter
tCSR CAS setup time before RAS low
tCHR CAS hold time after RAS low
tRSR Read setup time before RAS low
tRHR Read hold time after RAS low
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Unit
Min
Max
Min
Max
5 5 ns
10 10 ns
10 10 ns
10 10 ns
Note 28: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
12 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item, like -5S / -6S . The other characteristics
and requirements than the below are same as normal devices.
ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V ± 0.3V, Vss=0V, unless otherwise noted) (Note 2)
Symbol
Parameter
Test conditions
Limits
Min Typ Max
ICC8 (AV)
Average supply current M5M46X405D-5S,6S
from Vcc
M5M46X805D-5S,6S
Extended - Refresh cycle M5M465165D-5S,6S
(note 5,6)
CAS before RAS refresh cycling
input
input
high
low
level
level
≤≥
Vcc-0.2V
0.2V
output = OPEN , tRC = 31.25µs
tRAS = tRAS(min) ~ 300ns
500
ICC9 (AV)
Average supply current
from Vcc
Self - Refresh cycle
(note 6)
M5M46X405D-5S,6S
M5M46X805D-5S,6S
M5M465165D-5S,6S
RAS = CAS 0.2V
output = OPEN
400
Unit
µA
µA
TIMING REQUIREMENTS (Ta=0 ~ 70 C , Vcc=3.3V ± 0.3V, Vss=0V, unless otherwise noted See notes 14,15)
Symbol
Parameter
Limits
M5M46X405D-5S M5M46X405D-6S
M5M46X805D-5S M5M46X805D-6S
M5M465165D-5S M5M465165D-6S
Unit
tRASS
tRPS
tCHS
Self Refresh RAS low pulse width
Self Refresh RAS high precharge time
Self Refresh CAS hold time
Min Max
100
84
- 50
Min Max
100
104
- 50
µS
ns
ns
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of CBR distributed refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS 128 ms and tSN 128 ms.
tNS tSN
DISTRIBUTED REFRESH
< 128 ms >
Self refresh period
DISTRIBUTED REFRESH
< 128 ms >
(2) In case of burst refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS 16 ms and tSN 16 ms.
tNS tSN
BURST REFRESH
< 128 ms >
Self refresh period
BURST REFRESH
< 128 ms >
13 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams (Note 29)
Read Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tRAS
tRC
tCRP
tRCD
tCSH
tRSH
tCAS
tASR tRAH
ROW
ADDRESS
tRAD
tASC
tCAH
COLUMN
ADDRESS
tRCS
tRAL
tCAL
tRP
tRPC
tCPN
tCRP
tRRH
tRCH
tASR
ROW
ADDRESS
Hi-Z
tDZC
Hi-Z
tCDD
tRDD
tCAC
tAA
tCLZ
tREZ
tWEZ
tOFF
tOHC
tOHR
tRAC
tDZO
DATA VALID
tOEA
tOCH
tORH
tOEZ
tODD
Hi-Z
Note 29:
Indicates the don't care input.
VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max)
Indicates the invalid output.
Indicates the skew of the two inputs. (at M5M465165Dxx only)
14 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
tCRP
tRCD
tRAS
tWC
tCSH
tRSH
tCAS
tASR
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRP
tRPC tCRP
tASR
ROW
ADDRESS
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
tWCS
tWCH
tDS tDH
DATA VALID
VOH
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
VOL
Hi-Z
VIH
OE
VIL
15 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Delayed Write)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
tRAS
tWC
tRP
tCRP
tRCD
tCSH
tRSH
tCAS
tRPC tCRP
tASR
tRAH
ROW
ADDRESS
tASC
tRCS
tCAH
COLUMN
ADDRESS
tCWL
tWP
tRWL
tDZC
tWCH
Hi-Z
tCLZ
tDS tDH
DATA
VALID
tASR
ROW
ADDRESS
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
Hi-Z
tDZO
tOEZ
tODD
tOEH
Hi-Z
16 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tRWC
tRAS
tRP
tCRP
tRCD
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tRCS
tCSH
tRSH
tCAS
tCAH
COLUMN
ADDRESS
tAWD
tCWD
tRWD
tRPC tCRP
tCWL
tRWL
tWP
tASR
ROW
ADDRESS
Hi-Z
tDZC
tDS tDH
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
DATA
VALID
tOEA
tODD
tOEZ
DATA VALID
tOEH
Hi-Z
17 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tRAS
tRP
tCRP
tRCD
tCSH
tCAS
tHPC
tCP tCAS
tRSH
tRPC
tCP tCAS
tCRP
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS-1
tRCS
tCAL
tASC
tCAH
COLUMN
ADDRESS-2
tCAL
tASC
tCPRH
tCAH
COLUMN
ADDRESS-3
tRAL
tCAL
tASR
ROW
ADDRESS
tRRH
tRCH
tDZC
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tOCH
Hi-Z
tCAC
tAA
tDOH
DATA
VALID-1
tCPA
tCAC
tAA
tDOH
DATA
VALID-2
tCPA
tWEZ
tRDD
tCDD
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tOEZ
tODD
18 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Write Cycle (Early Write)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
tRAS
tRP
tCRP
tCSH
tRCD
tCAS
tHPC
tCP tCAS
tRSH
tRPC
tCP tCAS
tCRP
tASR tRAH
ROW
ADDRESS
tASC
tCAL
tCAH
COLUMN
ADDRESS-1
tWCS tWCH
tASC
tCAL
tCAH
COLUMN
ADDRESS-2
tWCS
tWCH
tASC
tCAL
tCAH
COLUMN
ADDRESS-3
tWCS tWCH
tASR
ROW
ADDRESS
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
tDS tDH
DATA
VALID-1
tDS tDH
DATA
VALID-2
tDS tDH
DATA
VALID-3
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
Hi-Z
VIH
OE
VIL
19 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read-Write, Read-Modify-Write Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tCRP
tRCD
tRAS
tCSH
tCAS
tCP
tHPRWC
tCAS
tRP
tRPC
tRWL
tCRP
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS-1
tRCS
tAWD
tCWD
tASC
tCAH
tCWL
tWP
COLUMN
ADDRESS-2
tRCS
tAWD
tCWD
tCWL
tASR
ROW
ADDRESS
tWP
Hi-Z
tDZC
tRWD
tDS
tCPWD
tDH tDZC
tDS
tDH
Hi-Z
tCAC
tAA
DATA
VALID-1
tCLZ
tRAC
tDZO
DATA
VALID
-1
tOEA
tODD
tOEZ
Hi-Z
tOEH
Hi-Z
tCAC
tAA
DATA
VALID-2
tCLZ
tCPA
tDZO
tOEA
DATA
VALID
-2
Hi-Z
tODD
tOEZ
tOEH
20 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (1) (Note 30)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tCRP
tCSH
tRCD
tCAS
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS-1
tRCS
tCAL
tRAS
tHPC
tCP tCAS
tCP
tRWL
tHPRWC
tCAS
tCWL
tRP
tRPC
tCRP
tASC
tCAH
tASC
tCAH
COLUMN
ADDRESS-2
tWCS
tWCH
tCAL
COLUMN
ADDRESS-3
tCPWD
tAWD
tCWD
tASR
ROW
ADDRESS
tWP
tDZC
tDS tDH
Hi-Z
tRAC
tDZO
tCAC
tAA
tCLZ
DATA
VALID-2
tWED
tWEZ
DATA
VALID
-1
tOEA
tOCH
tOEZ
tDZC
tDS tDH
tAA
tCAC
tCLZ
DATA
VALID-3
tCPA
tDZO tOEA
DATA
VALID
-3
tOEZ
tOEH
tODD
tODD
Note 30: OE=L; W Hi-Z control
OE=H; OE Hi-Z control
21 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (2) (Note 30)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tHPC
tCP
tASC
tCAS
tCAH
COLUMN
ADDRESS-1
tCAL
tRCH
tASC
tCAS
tCAH
COLUMN
ADDRESS-2
tWCS
tCAL
tWCH
tHCWD
tHAWD
tHPWD
tDH
tDS
Hi-Z
tCAC
tAA
tCPA
tHCOD
tHAOD
tHPOD
DATA
VALID-2
tWEZ
DATA
VALID-1
tWED
tOEZ
tODD
Hi-Z
tASC
tCAH
COLUMN
ADDRESS-3
tDZC
Hi-Z
tAA
tCPA
tCAC
tCLZ
DATA
VALID-3
tDZC
tOEA
Note 30: OE=L; W Hi-Z control
OE=H; OE Hi-Z control
22 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by OE)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tRAS
tRP
tCRP
tRCD
tCSH
tCAS
tHPC
tRSH
tRPC
tCP tCAS
tCP
tCAS
tCRP
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS-1
tRCS
tASC
tCAH
COLUMN
ADDRESS-2
tCPRH
tASC
tCAH
COLUMN
ADDRESS-3
tRAL
tASR
ROW
ADDRESS
tRRH
tRCH
tDZC
Hi-Z
tCAC
tAA
tCLZ
Hi-Z
tCAC
tAA
tDOH
tCAC
tAA
tCLZ
tRAC
tDZO
DATA
VALID-1
tOEA
tOEZ
DATA
VALID
-1
tCPA
tOCH
tOEA
DATA
VALID-2
Hi-Z
tCHOL
tCPA
tOEZ
tOEPE
tOEPE
tWEZ
tRDD
tCDD
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tOEZ
tODD
23 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by W)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tRAS
tRP
tCRP
tRCD
tCSH
tCAS
tHPC
tCP tCAS
tRSH
tRPC
tCP tCAS
tCRP
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS-1
tRCS
tASC
tCAH
COLUMN
ADDRESS-2
tRCH
tASC
tCPRH
tCAH
COLUMN
ADDRESS-3
tRAL
tRCS
tASR
ROW
ADDRESS
tRRH
tRCH
tDZC
tWPE
Hi-Z
tCAC
tAA
tCLZ
Hi-Z
tCAC
tAA
tDOH
tCAC
tAA
tWEZ
tCLZ
tRAC
tDZO
DATA
VALID-1
tOEA
tOCH
tCPA
DATA
VALID-2
Hi-Z
tCPA
tWEZ
tRDD
tCDD
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tOEZ
tODD
24 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
RAS
VIH
VIL
CAS
VIH
(atLMC5MA4S65/1U65CDxAxSonlyV) IL
Address
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
tRAS
tRC
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS) VOL
VIH
OE
VIL
Hi-Z
25 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
tRP
tRPC tCSR
tCPN
tRRH
tRCH tRSR
tRC
tRAS
tCHR
tRHR
tRAS
tRC
tRP
tRPC tCSR
tCHR
tRPC
tCRP
tRSR
tRHR
tASR
ROW
COLUMN
ADDRESS ADDRESS
tRCS
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tCDD
tREZ
tOHR
tOFF
tOHC
tOEZ
tODD
Hi-Z
26 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 31)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
tRC
tRAS
tCRP
tRCD
tRSH
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
tRCS
COLUMN
ADDRESS
tRAL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tDZC
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tORH
tRC
tRP tRAS tRP
tCHR
tRPC
tCRP
tRRH tRSR
tRHR
tASR
ROW
ADDRESS
Hi-Z
DATA VALID
tCDD
tRDD
tREZ
tOHR
tOFF
tOHC
tOEZ
tODD
Hi-Z
Note 31: Early write, delayed write, read write, or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
27 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
Self Refresh Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465165Dxx only)
Address
VIH
VIL
VIH
W
VIL
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
tRP
tRPC tCSR
tCPN
tRRH
tRCH tRSR
tRHR
tRASS
tRPS
tRPC
tCHS
tCRP
tASR
ROW
ADDRESS
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
VIH
OE
VIL
tCDD
tREZ
tOHR
tOFF
tOHC
tOEZ
Hi-Z
28 Aug. 1999
MITSUBISHI ELECTRIC


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Read Cycle
(at M5M465165Dxx only)
tRAS
tRC
tRP
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
Address
VIH
VIL
VIH
W
VIL
tCRP
tRCD
tCSH
tRSH
tCAS
tASR tRAH
ROW
ADDRESS
tRAD
tASC
tCAH
tRAL
tCAL
COLUMN
ADDRESS
tRCS
tRPC
tCRP
tRPC
tCPN
tRRH
tASR
ROW
ADDRESS
tRCH
D(oQr 1D~Q9D~QD8 Q16)VIH
(INPUTS)
VIL
(DoQr D1 ~Q9D~QD8 Q16)VOH
(OUTPUTS) VOL
DQ9 ~ DQ16
(or DQ1~ DQ8)
VIH
(INPUTS)
VIL
(DoQr D9 ~Q1D~QD16Q8) VOH
(OUTPUTS) VOL
VIH
OE
VIL
29
Hi-Z
Hi-Z
tDZC
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tOCH
tCDD
tRDD
tOFF
tREZ
tOHR
tOHC
DATA VALID
tWEZ
Hi-Z
tOEZ
tODD
tORH
MITSUBISHI ELECTRIC
Aug. 1999


M5M467805DTP-6 (Mitsubishi)
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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Click to Download PDF File for PC

(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Write Cycle (Early Write)
(at M5M465165Dxx only)
tWC
tRAS
RAS
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
tCRP
tRCD
tCSH
tRSH
tCAS
UCAS
(or LCAS)
VIH
VIL
Address
VIH
VIL
tASR
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRP
tRPC tCRP
tRPC tCRP
tASR
ROW
ADDRESS
VIH
W
VIL
tWCS
tWCH
D(oQr 1D~Q9D~QD8 Q16)VIH
(INPUTS)
VIL
(DoQr D1 ~Q9D~QD8 Q16)VOH
(OUTPUTS) VOL
DQ9 ~ DQ16 VIH
(or DQ1~ DQ8)
(INPUTS)
VIL
DQ9 ~ DQ16 VOH
(or DQ1~ DQ8)
(OUTPUTS) VOL
VIH
OE
VIL
30
Hi-Z
tDS tDH
DATA VALID
Hi-Z
MITSUBISHI ELECTRIC
Aug. 1999




M5M467805DTP-6.pdf
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