M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
The M5M467400/465400BJ,BTP is organized 16777216-word by 4-bit, M5M467800/465800BJ,BTP is organized 8388608-word by
8-bit, and M5M465160BJ,BTP is organized 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS
process, and are suitable for large-capacity memory systems with high speed and low power dissipation.
The use of double-layer aluminum process combined with CMOS technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density. Multiplexed address inputs permit both a reduction in pins and an increase in system
densities.
FEATURES
Type name
RAS
CAS Address OE Cycle
access access access access
time
time time
time
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M467400BXX-5,5S
M5M467800BXX-5,5S
50
13
25
13
90 300
M5M467400BXX-6,6S
M5M467800BXX-6,6S
60
15
30
15 110 250
M5M465400BXX-5,5S
M5M465800BXX-5,5S
50
13
25
13
90 390
M5M465400BXX-6,6S
M5M465800BXX-6,6S
60
15
30
15 110 325
XX=J,TP
Type name
M5M465160BXX-5,5S
M5M465160BXX-6,6S
RAS
access
time
CAS Address OE
access access access
time time
time
Cycle
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
50 13 25 13 90 420
60 15 30 15 110 390
Standard 32 pin SOJ, 32 pin TSOP (M5M467400Bxx/M5M465400Bxx/M5M467800Bxx/M5M465800Bxx)
Standard 50 pin SOJ, 50 pin TSOP (M5M465160Bxx)
Single 3.3 ± 0.3V supply
Low stand-by power dissipation
1.8mW (Max)
LVCMOS input level
Low operating power dissipation
M5M467400Bxx-5,5S / M5M467800Bxx-5,5S
360.0mW (Max)
M5M467400Bxx-6,6S / M5M467800Bxx-6,6S
324.0mW (Max)
M5M465400Bxx-5,5S / M5M465800Bxx-5,5S
468.0mW (Max)
M5M465400Bxx-6,6S / M5M465800Bxx-6,6S
432.0mW (Max)
M5M465160Bxx-5,5S
504.0mW (Max)
M5M465160Bxx-6,6S
468.0mW (Max)
Self refresh capability*
Self refresh current
400µA (Max)
Fast-page mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode and OE to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
* :Applicable to self refresh version(M5M467400/465400/467800/465800/465160BJ,BTP-5S,-6S:option) only
ADDRESS
Part No.
Row Add Col Add
Refresh
Refresh Cycle
Normal S-version
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467400Bxx A0-A12 A0-A10
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465400Bxx
A0-A11
A0-A11
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467800Bxx A0-A12 A0-A9
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465800Bxx
A0-A11
A0-A10
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
M5M465160Bxx A0-A11 A0-A9
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
1
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PIN DESCRIPTION
M5M467400Bxx / M5M465400Bxx
Pin Name Function
A0-A12
Address Inputs
DQ1-DQ4 Data Inputs / Outputs
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+3.3V)
Vss Ground (0V)
NC No Connection
M5M467800Bxx / M5M465800Bxx
Pin Name Function
A0-A12
Address Inputs
DQ1-DQ8 Data Inputs / Outputs
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+3.3V)
Vss Ground (0V)
NC No Connection
M5M465160Bxx
Pin Name Function
A0-A11
Address Inputs
DQ1-DQ16 Data Inputs / Outputs
RAS
UCAS
LCAS
Row Address Strobe Input
Upper byte control
Column Address Strobe Input
Lower byte control
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+3.3V)
Vss Ground (0V)
NC No Connection
XX=BJ,BTP
M5M467400/465400BJ,BTP PIN CONFIGURATION (TOP VIEW)
Vcc
DQ1
DQ2
NC
NC
NC
NC
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ4
30 DQ3
29 NC
28 NC
27 NC
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Outline 32P0N (400mil SOJ)
Vcc
DQ1
DQ2
NC
NC
NC
NC
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ4
30 DQ3
29 NC
28 NC
27 NC
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467400Bxx, NC...M5M465400Bxx
NC : NO CONNECTION
2
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467800/465800BJ,BTP PIN CONFIGURATION (TOP VIEW)
Vcc 1
DQ1 2
DQ2 3
DQ3
DQ4
NC
Vcc
4
5
6
7
W8
RAS
A0
A1
A2
9
10
11
12
A3 13
A4 14
A5 15
Vcc 16
32 Vss
31 DQ8
30 DQ7
29 DQ6
28 DQ5
27 Vss
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Vcc
DQ1
DQ2
DQ3
DQ4
NC
Vcc
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ8
30 DQ7
29 DQ6
28 DQ5
27 Vss
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Outline 32P0N (400mil SOJ)
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467800Bxx, NC...M5M465800Bxx
NC : NO CONNECTION
M5M465160BJ,BTP
PIN CONFIGURATION (TOP VIEW)
Vcc 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
Vcc 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
Vcc 12 12
W 13
RAS 14
NC 15
NC 16
NC 17
NC 18
A0 19
A1 20
A2 21
A3 22
A4 23
A5 24
Vcc 25
50 Vss
49 DQ16
48 DQ15
47 DQ14
46 DQ13
45 Vss
44 DQ12
43 DQ11
42 DQ10
41 DQ9
40 NC
39 Vss
38 LCAS
37 UCAS
36 OE
35 NC
34 NC
33 NC
32 A11
31 A10
30 A9
29 A8
28 A7
27 A6
26 Vss
Vcc 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
Vcc 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
Vcc 12 12
W 13
RAS 14
NC 15
NC 16
NC 17
NC 18
A0 19
A1 20
A2 21
A3 22
A4 23
A5 24
Vcc 25
50 Vss
49 DQ16
48 DQ15
47 DQ14
46 DQ13
45 Vss
44 DQ12
43 DQ11
42 DQ10
41 DQ9
40 NC
39 Vss
38 LCAS
37 UCAS
36 OE
35 NC
34 NC
33 NC
32 A11
31 A10
30 A9
29 A8
28 A7
27 A6
26 Vss
Outline 50P0G (400mil SOJ)
Outline 50P3G (400mil TSOP Normal Bend)
NC : NO CONNECTION
3
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
The M5M467400(800)/465400(800,160)BJ, BTP provide, in addition to normal read, write, and read-modify-write operations,
a number of other functions, e.g., Fast page mode, CAS before RAS refresh, and delayed-write.
The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
M5M467400Bxx / M5M465400Bxx / M5M467800Bxx / M5M465800Bxx
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Standby
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
Inputs
W
NAC
ACT
ACT
ACT
DNC
DNC
NAC
DNC
OE
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
APD
DNC
DNC
DNC
Column
address
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Input/Output
Input
OPN
VLD
VLD
VLD
OPN
OPN
DNC
DNC
Output
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
Refresh Remark
NO
NO
NO
NO
YES
YES
YES
NO
FAST PAGE
mode
identical
M5M465160Bxx
Operation
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Stand-by
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
LCAS
ACT
NAC
ACT
ACT
NAC
ACT
NAC
ACT
ACT
DNC
Inputs
UCAS
NAC
ACT
ACT
NAC
ACT
ACT
NAC
ACT
ACT
DNC
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
Column
address
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Input/Output
DQ1~DQ8 DQ9~DQ16
VLD
OPN
OPN
VLD
VLD
VLD
DIN DNC
DNC
DIN
DIN
OPN
DIN
OPN
VLD
VLD
OPN
OPN
OPN
OPN
Refresh Remark
NO
NO
NO
NO
NO
NO
YES
YES
YES
NO
FAST PAGE
mode
identical
4
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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Click to Download PDF File for PC

(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467400Bxx / M5M465400Bxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A11
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
M5M467800Bxx / M5M465800Bxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A10
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
5
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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Click to Download PDF File for PC

(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M465160Bxx
BLOCK DIAGRAM
ROW ADDRESS RAS
STROBE INPUT
LOWER BYTE CONTROL LCAS
COLUMN ADDRESS
STROBE INPUT
UPPER BYTE CONTROL UCAS
COLUMN ADDRESS
STROBE INPUT
WRITE CONTROL INPUT W
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
CLOCK GENERATOR
CIRCUIT
LOWER
UPPER
A0~A9
A0 ~
A11
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O
CONTROL
MEMORY CELL
(67108864BITS)
VCC (3.3V)
VSS (0V)
DQ1
DQ2
LOWER DATA
INPUTS / OUTPUTS
DQ8
DQ9
DQ10
UPPER DATA
INPUTS / OUTPUTS
DQ16
OE OUTPUT ENABLE
INPUT
6
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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Click to Download PDF File for PC

(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc
VI
V0
I0
Pd
Topr
Tstg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to Vss
Ta=25 C
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
1000
0 ~ 70
-65 ~ 150
Unit
V
V
V
mA
mW
C
C
RECOMMENDED OPERATING CONDITIONS (Ta=0 ~70 C, unless otherwise noted) (Note 1)
Symbol
Parameter
Limits
Min Nom Max
Unit
Vcc Supply voltage
Vss Supply voltage
VIH High-level input voltage, all inputs
3.0 3.3
3.6
00
0
2.0 Vcc+0.3
V
V
V
VIL Low-level input voltage, all inputs
-0.3 0.8 V
Note 1 : All voltage values are with respect to Vss.
ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted) (Note 2)
[M5M467400B / M5M467800B]
Symbol
Parameter
Test conditions
VOH
VOL
IOZ
II
ICC1 (AV)
ICC2 (AV)
ICC4 (AV)
ICC6 (AV)
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc
operating
(Note 3,4,5)
Average supply current
from Vcc
stand-by
(Note 6)
Average supply current
from Vcc
Fast-Page-Mode
(Note 3,4,5)
Average supply current
from Vcc
CAS before RAS refresh
mode
(Note 3,5)
M5M467400B-5,5S
M5M467800B-5,5S
M5M467400B-6,6S
M5M467800B-6,6S
M5M467400B-5,5S
-6,6S
M5M467800B-5,5S
-6,6S
M5M467400B-5,6
M5M467800B-5,6
M5M467400B-5S,6S
M5M467800B-5S,6S
M5M467400B-5,5S
M5M467800B-5,5S
M5M467400B-6,6S
M5M467800B-6,6S
M5M467400B-5,5S
M5M467800B-5,5S
M5M467400B-6,6S
M5M467800B-6,6S
IOH=-2mA
IOL=2mA
Q floating 0V VOUT Vcc
0VVIN Vcc+0.3V, Other input pins=0V
RAS, CAS cycling
tRC=tWC=min.
output open
RAS= CAS =VIH, output open
RAS= CAS Vcc -0.2V,output open
RAS=VIL, CAS cycling
tPC=min.
output open
CAS before RAS refresh cycling
tRC=min.
output open
Limits
Min Typ Max
2.4 Vcc
0 0.4
-10 10
-10 10
100
90
1
0.5
0.3
100
90
130
120
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column Address can be changed once or less while RAS=VIL and CAS=VIH.
Unit
V
V
µA
µA
mA
mA
mA
mA
7
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

No Preview Available !

Click to Download PDF File for PC

(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
~ELECTRICAL CHARACTERISTICS (Ta=0 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted) (Note 2)
[M5M465400B / M5M465800B]
Symbol
Parameter
Test conditions
Limits
Min Typ Max
VOH
VOL
IOZ
II
ICC1 (AV)
ICC2 (AV)
ICC4 (AV)
ICC6 (AV)
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc
operating
(Note 3,4,5)
Average supply current
from Vcc
stand-by
(Note 6)
Average supply current
from Vcc
Fast-Page-Mode
(Note 3,4,5)
Average supply current
from Vcc
CAS before RAS refresh
mode
(Note 3,5)
IOH=-2mA
IOL=2mA
Q floating 0V VOUT Vcc
0VVIN Vcc+0.3V, Other input pins=0V
M5M465400B-5,5S
M5M465800B-5,5S
M5M465400B-6,6S
M5M465800B-6,6S
RAS, CAS cycling
tRC=tWC=min.
output open
M5M465400B-5,5S
-6,6S
M5M465800B-5,5S
-6,6S
RAS= CAS =VIH, output open
M5M465400B-5,6
M5M465800B-5,6
M5M465400B-5S,6S
M5M465800B-5S,6S
RAS= CAS Vcc -0.2V,output open
M5M465400B-5,5S
M5M465800B-5,5S
M5M465400B-6,6S
M5M465800B-6,6S
RAS=VIL, CAS cycling
tPC=min.
output open
M5M465400B-5,5S
M5M465800B-5,5S
M5M465400B-6,6S
M5M465800B-6,6S
CAS before RAS refresh cycling
tRC=min.
output open
2.4
0
-10
-10
Vcc
0.4
10
10
130
120
1
0.5
0.3
100
90
130
120
Unit
V
V
µA
µA
mA
mA
mA
mA
[M5M465160B]
Symbol
Parameter
Test conditions
Limits
Min Typ Max
VOH High-level output voltage
IOH=-2mA
2.4 Vcc
VOL Low-level output voltage
IOZ Off-state output current
I I Input current
IOL=2mA
Q floating 0V VOUT Vcc
0V VIN Vcc+0.3V, Other input pins=0V
0
-10
-10
0.4
10
10
ICC1 (AV)
ICC2 (AV)
Average supply current
M5M465160B-5,5S RAS, CAS cycling
from Vcc
tRC=tWC=min.
operating
(Note 3,4,5) M5M465160B-6,6S output open
Average supply current
from Vcc
stand-by
(Note 6)
M5M465160B-5,5S
-6,6S RAS= CAS =VIH, output open
M5M465160B-5,6
RAS= CAS Vcc -0.2V, output open
M5M465160B-5S,6S
140
130
1
0.5
0.3
ICC4 (AV)
ICC6 (AV)
Average supply current
M5M465160B-5,5S
from Vcc
Fast-Page-Mode (Note 3,4,5) M5M465160B-6,6S
Average supply current
from Vcc
CAS before RAS refresh
mode
(Note 3,5)
M5M465160B-5,5S
M5M465160B-6,6S
RAS=VIL, CAS cycling
tPC=min.
output open
CAS before RAS refresh cycling
tRC=min.
output open
105
95
140
130
Unit
V
V
µA
µA
mA
mA
mA
mA
8
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
~CAPACITANCE (Ta=0 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted)
Symbol
Parameter
Test conditions
CI (A)
CI (OE)
CI (W)
CI (RAS)
CI (CAS)
CI / O
Input capacitance,address inputs
Input capacitance, OE input
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports
VI=Vss
f=1MHZ
Vi=25mVrms
Limits
Min Typ Max
5
7
7
7
7
7
Unit
pF
pF
pF
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
Limits
Symbol
Parameter
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S Unit
M5M465160B-5,5S M5M465160B-6,6S
Min
Max
Min
Max
tCAC Access time from CAS
(Note 7,8)
tRAC Access time from RAS
(Note 7,9)
tAA Column address access time
(Note 7,10)
tCPA Access time from CAS precharge
(Note 7,11)
tOEA Access time from OE
(Note 7)
tCLZ Output low impedance time from CAS low (Note 7)
tOFF Output disable time after CAS high
(Note 12)
tOEZ Output disable time after OE high
(Note 12)
13 15 ns
50 60 ns
25 30 ns
30 35 ns
13 15 ns
5 5 ns
0 13 0 15 ns
0 13 0 15 ns
Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing RAS-only refresh or CAS before RAS refresh).
Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are VOH=2.0V and VOL=0.8V.
8: Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP tCP(max).
9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD tRAD(max) and tASC tASC(max).
11: Assumes that tCP tCP(max) and tASC tASC(max).
12: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT ± 10 µA) and is not reference
to VOH(min) or VOL(max).
9
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 C , Vcc=3.3 ±0.3V, Vss=0V, unless otherwise noted See notes 13,14)
Symbol
Parameter
tREF
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Refresh cycle time
Refresh cycle time (S-version only)
RAS high pulse width
Delay time, RAS low to CAS low
(Note15)
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
(Note16)
Row address setup time before RAS low
Column address setup time before CAS low (Note17)
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, CAS high to data
(Note18)
(Note18)
(Note19)
Delay time, OE high to data
Transition time
(Note19)
(Note20)
Limits
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S
M5M465160B-5,5S M5M465160B-6,6S
Unit
Min
Max
Min
Max
64 64 ms
128 128 ms
30 40 ns
18 37 20 45 ns
5 10 ns
0 0 ns
8 10 ns
13 25 15 30 ns
0 0 ns
0 7 0 10 ns
8 10 ns
13 15 ns
0 0 ns
0 0 ns
13 15 ns
13 15 ns
1 50
1 50 ns
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. VIH(min) and VIL(max) of the switching characteristics are
2.0V and 0.8V respectively.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tT+tASC(min).
16: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read Setup time before CAS low
tRCH Read hold time after CAS high
tRRH Read hold time after RAS high
tRAL Column address to RAS hold time
tOCH CAS hold time after OE low
tORH RAS hold time after OE low
(Note 21)
(Note 21)
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Limits
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S
M5M465160B-5,5S M5M465160B-6,6S
Min Max Min Max
90 110
50 10000 60 10000
13 10000 15 10000
50 60
13 15
00
00
10 10
25 30
13 15
13 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
(Note 23)
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
Limits
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S
M5M465160B-5,5S M5M465160B-6,6S
Unit
Min Max Min Max
90 110 ns
50 10000
60 10000 ns
13 10000
15 10000 ns
50 60 ns
13 15 ns
0 0 ns
8 10 ns
13 15 ns
13 15 ns
8 10 ns
0 0 ns
8 10 ns
13 15 ns
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
tDS
tDH
tOEH
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
(Note22)
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
CAS hold time after W low
RAS hold time after W low
(Note23)
(Note23)
(Note23)
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
Limits
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S
M5M465160B-5,5S M5M465160B-6,6S
Unit
Min Max Min Max
126 150 ns
85 10000
95 10000 ns
50 10000
50 10000 ns
85 95 ns
50 50 ns
0 0 ns
30 30 ns
65 75 ns
40 45 ns
13 15 ns
13 15 ns
8 10 ns
0 0 ns
8 10 ns
13 15 ns
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
23: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min)
(for Fast Page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi-
nate.
11
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Fast-Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle) (Note 24)
Symbol
tPC
tPRWC
tRAS
tCP
tCPRH
tCPWD
Parameter
Limits
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S
M5M465160B-5,5S M5M465160B-6,6S
Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time
RAS low pulse width for read write cycle
(Note25)
CAS high pulse width
(Note26)
RAS hold time after CAS precharge
Delay time, CAS precharge to W low
(Note23)
Min
35
70
85
8
30
30
Max
125000
12
Min
40
75
100
10
35
35
Max
125000
15
Unit
ns
ns
ns
ns
ns
ns
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.
25: tRAS(min) is specified as two cycles of CAS input are performed.
26: tCP(max) is specified as a reference point only. If tCP tCP(max) , access time is controlled exclusively by tCAC.
CAS before RAS Refresh Cycle (Note 27)
Symbol
Parameter
tCSR CAS setup time before RAS low
tCHR CAS hold time after RAS low
tRSR Read setup time before RAS low
tRHR Read hold time after RAS low
Limits
M5M46X400B-5,5S M5M46X400B-6,6S
M5M46X800B-5,5S M5M46X800B-6,6S
M5M465160B-5,5S M5M465160B-6,6S
Unit
Min
Max
Min
Max
5 5 ns
10 10 ns
10 10 ns
10 10 ns
Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
12
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item, like -5S / -6S . The other characteristics
and requirements than the below are same as normal devices.
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
(Ta=0 ~ 70 C, Vcc=3.3V ± 0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions
Limits
Min Typ Max
ICC8 (AV)
Average supply current M5M46X400B-5S,6S
from Vcc
M5M46X800B-5S,6S
Extended - Refresh cycle M5M465160B-5S,6S
(note 5,6)
CAS before RAS refresh cycling
input
input
high
low
level
level
≤≥
Vcc-0.2V
0.2V
output = OPEN , tRC = 31.25µs
tRAS = tRAS(min) ~ 300ns
500
ICC9 (AV)
Average supply current
from Vcc
Self - Refresh cycle
(note 6)
M5M46X400B-5S,6S
M5M46X800B-5S,6S
M5M465160B-5S,6S
RAS = CAS 0.2V
output = OPEN
400
Unit
µA
µA
TIMING REQUIREMENTS (Ta=0 ~ 70 C, Vcc=3.3V ± 0.3V, Vss=0V, unless otherwise noted See notes 13,14)
Limits
Symbol
Parameter
M5M46X400B-5S M5M46X400B-6S
M5M46X800B-5S M5M46X800B-6S
M5M465160B-5S M5M465160B-6S
Unit
tRASS
tRPS
tCHS
Self Refresh RAS low pulse width
Self Refresh RAS high precharge time
Self Refresh CAS hold time
Min Max
100
90
- 50
Min Max
100
110
- 50
µS
ns
ns
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of CBR distributed refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS 128 ms and tSN 128 ms.
tNS tSN
DISTRIBUTED REFRESH
< 128 ms >
Self refresh period
DISTRIBUTED REFRESH
< 128 ms >
(2) In case of burst refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS 16 ms and tSN 16 ms.
tNS tSN
BURST REFRESH
< 128 ms >
Self refresh period
BURST REFRESH
< 128 ms >
13
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams (Note 28)
Read Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRAS
tRC
tRSH
tCRP
tRCD
tASR
tRAD
tRAH
tASC
tCSH
tCAS
tCAH
tRAL
ROW
ADDRESS
COLUMN
ADDRESS
tRCS
tRP
tRPC
tCRP
tCPN
tASR
tRRH
tRCH
ROW
ADDRESS
tDZC
Hi-Z
tDZO
tCAC
tAA
tCLZ
Hi-Z
tRAC
tOEA
tOCH
tORH
tCDD
tOFF
DATA VALID
tOEZ
tODD
Hi-Z
Note 28:
14
Indicates the don't care input.
VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max)
Indicates the invalid output.
Indicates the skew of the two inputs. (at M5M465160xx only)
MITSUBISHI
ELECTRIC
Jun. 1999


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
VOH
DQ1 ~ DQ4 (8,16)
(OUTPUTS) VOL
tCRP
tRCD
tRAS
tWC
tCSH
tRSH
tCAS
tASR
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tWCS
tWCH
tDS tDH
DATA VALID
Hi-Z
VIH
OE
VIL
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
15
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Delayed Write)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS) VOL
VIH
OE
VIL
tCRP
tRCD
tWC
tRAS
tCSH
tRSH
tCAS
tASR
tRAH
ROW
ADDRESS
tASC
tRCS
tDZC
tDZO
tCAH
COLUMN
ADDRESS
tWCH
tDS
tCWL
tRWL
tWP
tDH
Hi-Z
DATA VALID
tCLZ
Hi-Z
tOEZ
tODD
tOEH
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
16
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRWC
tRAS
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tCWD
tAWD
tRWD
tCWL
tRWL
tRCS
tRAC
tDZC
tAA
Hi-Z
tCAC
tCLZ
tWP
tDS tDH
DATA VALID
Hi-Z
tDZO
tOEA
DATA
VALID
tODD
tOEZ
Hi-Z
tOEH
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
17
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Read Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
VIH
Address
VIL
tCSH
tCRP
tRCD
tCAS
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS-1
VIH
W
VIL
tRCS
tRAS
tPC
tCP tCAS
tASC
tCAH
COLUMN
ADDRESS-2
tRCH
tRCS
tAA
tCPRH
tRSH
tRP
tRPC
tCP
tCAS
tCRP
tRAL
tASC
tCAH
COLUMN
ADDRESS-3
tAA
tRCH
tRCS
tASR
ROW
ADDRESS
tRRH
tRCH
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1
~
DQ4
VOH
(8,16)
(OUTPUTS) VOL
VIH
OE
VIL
tDZC
tCDD
tDZC
Hi-Z
tCDD
tDZC
tCDD
Hi-Z
tCAC
tCLZ
tAA
tRAC
tDZO
tOEA
tOCH
tOFF
DATA
VALID-1
tCAC
tCLZ
tOFF
DATA
VALID-2
tCLZ
tCAC
tOFF
DATA
VALID-3
tCPA
tOEZ
tDZO
tODD
tOEA
tOCH
tOEZ
tCPA
tORH
tDZO
tOEA
tODD
tOCH
tOEZ
tODD
18
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
RAS
VIH
VIL
CAS VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
Address VIH
VIL
tCRP
tCSH
tRCD
tCAS
tASR
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS-1
tRAS
tPC
tCP tCAS
tASC
tCAH
COLUMN
ADDRESS-2
tRP
tRSH
tRPC
tCRP
tCP tCAS
tASC
tCAH
COLUMN
ADDRESS-3
tASR
ROW
ADDRESS
VIH
W
VIL
DQ1
~
DQ4
VIH
(8,16)
(INPUTS)
VIL
DQ1
~
DQ4
VOH
(8,16)
(OUTPUTS) VOL
VIH
OE
VIL
tWCS
tWCH
tDS tDH
DATA VALID-1
tWCS
tWCH
tDS tDH
DATA VALID-2
Hi-Z
tWCS
tWCH
tDS tDH
DATA VALID-3
19
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Write Cycle (Delayed Write)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
Address VIH
VIL
VIH
W
VIL
DQ1
~
DQ4
VIH
(8,16)
(INPUTS)
VIL
DQ1
~
DQ4
VOH
(8,16)
(OUTPUTS) VOL
VIH
OE
VIL
tCSH
tRAS
tRSH
tPC
tRP
tCRP
tRCD
tCAS
tCP tCAS
tRPC
tCRP
tASR
tRAD
tRAH
tASC
tCAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS-1
COLUMN
ADDRESS-2
tRCS
tWCH
tCWL
tRCS
tWP
tWCH
tRWL
tCWL
tWP
tASR
ROW
ADDRESS
tDZC
tDZO
tCLZ
tDS tDH tDZC
DATA
VALID-1
tDZO
Hi-Z
tCLZ
tDS tDH
DATA
VALID-2
tOEZ
tODD
tOEH
tOEZ
tODD
tOEH
20
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Read-Write, Read-Modify-Write Cycle
RAS
VIH
VIL
CAS VIH
VIL
LCAS / UCAS
(at M5M465160Bxx only)
VIH
Address
VIL
VIH
W
VIL
DQ1 ~ DQ4 VIH
(8,16)
(INPUTS) VIL
DQ1 ~ DQ4 VOH
(8,16)
(OUTPUTS) VOL
VIH
OE
VIL
tCSH
tRAS
tCRP
tRCD
tCAS
tCP
tRSH
tPRWC
tCAS
tRP
tRPC
tCRP
tASR
tRAD
tRAH
tASC
tCAH
tASC
tCAH
tRWL
tASR
ROW
ADDRESS
COLUMN
ADDRESS-1
COLUMN
ADDRESS-2
tRCS
tRWD
tWCH
tAWD
tCWL
tRCS
tRAC
tDZC
tCWD
tWP
tAA
tCAC
tDS tDH tDZC
DATA
VALID-1
tDZO
tDZO
tCLZ
tOEA
tOEZ
tODD
DATA
VALID-1
Hi-Z
tOEH
tAWD
tWCH
tCPA
tAA
tCWD
tCPWD
tDS
tCWL
tWP
tDH
tCAC
DATA
VALID-2
tCLZ
DATA
VALID-2
tOEA
tOEZ
tODD
tOEH
ROW
ADDRESS
21
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
tCRP
Address
VIH
VIL
tASR
tRAH
ROW
ADDRESS
W VIH
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS) VOL
VIH
OE
VIL
tRC
tRAS
Hi-Z
tRP
tRPC tCRP
tASR
ROW
ADDRESS
22
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1
~
DQ4
VOH
(8,16)
(OUTPUTS) VOL
VIH
OE
VIL
tRC
tRP
tRAS
tRPC
tCPN
tCSR
tCHR
tRPC
tCSR
tRC
tRAS
tRP
tCHR
tRPC
tCRP
tRCH tRSR
tRHR
tRSR
tRHR
tASR
ROW
ADDRESS
tRCS
tOFF
tCDD
tOEZ
tODD
Hi-Z
23
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 29)
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
Address
VIH
VIL
VIH
W
VIL
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1
~
DQ4
VOH
(8,16)
(OUTPUTS) VOL
VIH
OE
VIL
tRC
tRAS
tCRP
tRCD
tRSH
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
tRCS
tRAL
tDZC
tAA
tRAC
tCLZ
Hi-Z
tCAC
tDZO
tOEA
tORH
tRC
tRP tRAS
tRP
tCHR
tRPC
tCRP
tRRH
tRSR
tRHR
tASR
ROW
ADDRESS
Hi-Z
DATA VALID
tCDD
tOFF
tOEZ
tODD
Hi-Z
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
24
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh Cycle
RAS
VIH
VIL
CAS
VIH
LCAS / UCAS VIL
(at M5M465160Bxx only)
Address
VIH
VIL
VIH
W
VIL
tRP
tRPC tCSR
tCPN
tRCH tRSR
tRHR
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
DQ1
~
DQ4
VOH
(8,16)
(OUTPUTS) VOL
VIH
OE
VIL
tOFF
tOEZ
tRASS
tRPS
tRPC
tCHS
tCRP
tASR
ROW
ADDRESS
Hi-Z
25
MITSUBISHI
Jun. 1999
ELECTRIC


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Read Cycle
(at M5M465160Bxx only)
RAS
VIH
VIL
tRC
tRAS
tRSH
tRP
UCAS
(or LCAS)
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
Address
VIH
VIL
VIH
W
VIL
tCRP
tRCD
tCSH
tCAS
tCRP
tCAH
tRAD
tASR
tRAH
ROW
ADDRESS
tASC
COLUMN
ADDRESS
tRAL
tRCS
tCPN
tRPC
tCRP
tRPC
tCRP
tRCH
tASR
ROW
ADDRESS
tRRH
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
DQ1 ~ DQ8
VOH
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
DQ9 ~ DQ16 VIH
(or DQ1~ DQ8)
(INPUTS)
VIL
D(oQr 9D~Q1D~QD16Q8) VOH
(OUTPUTS) VOL
VIH
OE
VIL
26
Hi-Z
tDZC
Hi-Z
tDZO
tCAC
Hi-Z
tAA
tCLZ
tRAC
tOEA
tOCH
tCDD
tOFF
DATA VALID
tOEZ
tODD
tORH
MITSUBISHI
ELECTRIC
Jun. 1999


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Write Cycle (Early Write)
(at M5M465160Bxx only)
RAS
VIH
VIL
UCAS
(or LCAS)
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
Address
VIH
VIL
tRAS
tWC
tCRP
tRCD
tCRP
tCSH
tRSH
tCAS
tASR
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRP
tRPC tCRP
tRPC
tCRP
tASR
ROW
ADDRESS
VIH
W
VIL
DQ1 ~ DQ8
(or DQ9 ~ DQ16)
VIH
(INPUTS)
VIL
D(oQr 1D~Q9D~QD8 Q16)VOH
(OUTPUTS) VOL
DQ9 ~ DQ16
(or DQ1~ DQ8)
VIH
(INPUTS)
VIL
DQ9 ~DQ16
(or DQ1 ~ DQ8)
VOH
(OUTPUTS) VOL
VIH
OE VIL
27
tWCS
tWCH
Hi-Z
tDS tDH
DATA VALID
Hi-Z
MITSUBISHI
ELECTRIC
Jun. 1999


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Write Cycle (Delayed Write)
(at M5M465160Bxx only)
RAS
VIH
VIL
tRAS
tWC
tRP
tCSH
tCRP
tRCD
tRSH
tRPC tCRP
UCAS
(or LCAS)
VIH
VIL
tCRP
tCAS
tRPC
tCRP
LCAS
(or UCAS)
VIH
VIL
Address
VIH
VIL
VIH
W
VIL
tASR
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tRCS
tWCH
tCWL
tRWL
tWP
tASR
ROW
ADDRESS
DQ1 ~ DQ8
(or DQ9 ~ DQ16)
VIH
(INPUTS)
VIL
D(oQr 1D~Q9D~QD8 Q16)VOH
(OUTPUTS) VOL
DQ9 ~ DQ16 VIH
(or DQ1~ DQ8)
(INPUTS)
VIL
DQ9 ~ DQ16
(or DQ1~ DQ8)
VOH
(OUTPUTS) VOL
OE
28
VIH
VIL
tDZC
Hi-Z
tCLZ
tDZO
tOEZ
tODD
Hi-Z
tDS tDH
DATA VALID
Hi-Z
tOEH
MITSUBISHI
ELECTRIC
Jun. 1999


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper/(Lower) Byte Read-Write, Upper/(Lower) Byte Read-Modify-Write Cycle
(at M5M465160Bxx only)
tRWC
tRAS
RAS
VIH
VIL
tRP
UCAS
(or LCAS)
VIH
VIL
LCAS
(or UCAS)
VIH
VIL
tCRP
tCRP
tRCD
tCSH
tCAS
tRSH
tRPC
tCRP
tRPC tCRP
Address
VIH
VIL
VIH
W
VIL
tASR
tRAH
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
tCWD
tAWD
tRWD
tRCS
tCWL
tRWL
tWP
tASR
ROW
ADDRESS
DQ1~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
DQ1 ~ DQ8
VOH
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
DQ9 ~ DQ16
VIH
(or DQ1~ DQ8)
(INPUTS)
VIL
DQ9 ~ DQ16 VOH
(or DQ1 ~ DQ8)
(OUTPUTS) VOL
VIH
OE
VIL
29
tRAC
Hi-Z
tDZC
tDZO
Hi-Z
tAA
Hi-Z
tCAC
tCLZ
tOEA
DATA
VALID
tOEZ
tODD
tDS tDH
DATA VALID
Hi-Z
tOEH
MITSUBISHI
ELECTRIC
Jun. 1999


M5M465800BTP-6 (Mitsubishi)
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM

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(Rev. 1.1)
MITSUBISHI LSIs
M5M467400/465400BJ,BTP -5,-6,-5S,-6S
M5M467800/465800BJ,BTP -5,-6,-5S,-6S
M5M465160BJ,BTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Fast Page Mode Upper / (Lower) Byte Read Cycle
(at M5M465160Bxx only)
tRAS
RAS
VIH
VIL
tCSH
tPC
tCPRH
tRSH
tRP
tRPC
tCRP
tRCD
tCAS
tCP
tCAS
tCP tCAS
tCRP
UCAS
VIH
(or LCAS) VIL
LCAS
VIH
(or UCAS) VIL
tCRP
tRPC
tCRP
VIH
Address
VIL
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS-1
VIH
W
VIL
tRCS
tASC
tCAH
COLUMN
ADDRESS-2
tRCH tRCS
tAA
tRAL
tASC
tCAH
COLUMN
ADDRESS-3
tRCH
tAA
tRCS
tASR
ROW
ADDRESS
tRRH
tRCH
D(oQr 1D~Q9D~QD8 Q16)VIH
(INPUTS)
VIL
DQ1 ~ DQ8 VOH
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
DQ9 ~ DQ16 VIH
(or DQ1~ DQ8)
(INPUTS) VIL
DQ9 ~ DQ16 VOH
(or DQ1~ DQ8)
(OUTPUTS) VOL
VIH
OE
VIL
30
tDZC
tCDD
tDZC
Hi-Z
Hi-Z
tDZC
tCDD
tCDD
Hi-Z
tCAC
tCLZ
tAA
tRAC
tDZO
tOEA
tOCH
tOFF
tCAC
tCLZ
tOFF
tCAC
tCLZ
tOFF
DATA
VALID-1
tCPA
DATA
VALID-2
tCPA tORH
DATA
VALID-3
tOEZ
tDZO
tODD
tOEA
tOCH
tOEZ
tDZO
tODD
tOEA
tOCH
tOEZ
tODD
MITSUBISHI
ELECTRIC
Jun. 1999




M5M465800BTP-6.pdf
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