MC-4532CD646 (NEC)
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532CD646
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-4532CD646 is a 33,554,432 words by 64 bits synchronous dynamic RAM module on which 16 pieces of
128M SDRAM: µPD45128841 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
33,554,432 words by 64 bits organization
Clock frequency and access time from CLK
Part number
MC-4532CD646EF-A80
MC-4532CD646EF-A10
5 MC-4532CD646PF-A80
5 MC-4532CD646PF-A10
/CAS latency
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
Clock frequency
(MAX.)
125 MHz
100 MHz
100 MHz
77 MHz
125 MHz
100 MHz
100 MHz
77 MHz
Access time from CLK
(MAX.)
6 ns
6 ns
6 ns
7 ns
6 ns
6 ns
6 ns
7 ns
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
Programmable burst-length (1, 2, 4, 8 and full page)
Programmable wrap sequence (Sequential / Interleave)
Programmable /CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
All DQs have 10 Ω ±10 % of series resistor
Single 3.3 V ± 0.3 V power supply
LVTTL compatible
4,096 refresh cycles/64 ms
Burst termination by Burst Stop command and Precharge command
168-pin dual in-line memory module (Pin pitch = 1.27 mm)
Unbuffered type
Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13681EJ4V0DS00 (4th edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark shows major revised points.
©
1998


MC-4532CD646 (NEC)
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

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MC-4532CD646
Ordering Information
Part number
Clock frequency
MHz (MAX.)
Package
Mounted devices
MC-4532CD646EF-A80
125 MHz
168-pin Dual In-line Memory Module 16 pieces of µPD45128841G5 (Rev. E)
MC-4532CD646EF-A10 100 MHz (Socket Type)
(10.16 mm (400) TSOP (II))
5 MC-4532CD646PF-A80 125 MHz Edge connector : Gold plated
5 MC-4532CD646PF-A10 100 MHz 34.93 mm height
16 pieces of µPD45128841G5 (Rev. P)
(10.16 mm (400) TSOP (II))
2 Data Sheet M13681EJ4V0DS00


MC-4532CD646 (NEC)
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

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MC-4532CD646
5 Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
85 VSS
86 DQ32
87 DQ33
88 DQ34
89 DQ35
90 Vcc
91 DQ36
92 DQ37
93 DQ38
94 DQ39
VSS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
1
2
3
4
5
6
7
8
9
10
95 DQ40
DQ8
11
96 VSS
VSS 12
97 DQ41
DQ9
13
98 DQ42 DQ10 14
99 DQ43 DQ11 15
100 DQ44 DQ12 16
101 DQ45 DQ13 17
102 Vcc
Vcc 18
103 DQ46
DQ14
19
104 DQ47
DQ15
20
105 NC
NC 21
106 NC
NC 22
107 VSS
VSS 23
108 NC
NC 24
109 NC
NC 25
110 Vcc
Vcc 26
111 /CAS
/WE 27
112
DQMB4
DQMB0
28
113
DQMB5
DQMB1
29
114 /CS1
/CS0
30
115 /RAS
NC 31
116 VSS
VSS 32
117 A1
A0 33
118 A3
A2 34
119 A5
A4 35
120 A7
A6 36
121 A9
A8 37
122
BA0 (A13)
A10
38
123 A11 BA1 (A12) 39
124 Vcc
Vcc 40
125 CLK1
Vcc 41
126 NC
CLK0
42
127 VSS
VSS 43
128 CKE0
NC 44
129 /CS3
/CS2
45
130
DQMB6
DQMB2
46
131
DQMB7
DQMB3
47
132 NC
NC 48
133 Vcc
Vcc 49
134 NC
NC 50
135 NC
NC 51
136 NC
NC 52
137 NC
NC 53
138 VSS
VSS 54
139 DQ48 DQ16 55
140 DQ49 DQ17 56
141 DQ50 DQ18 57
142 DQ51 DQ19 58
143 Vcc
Vcc 59
144 DQ52 DQ20 60
145 NC
NC 61
146 NC
NC 62
147 NC
CKE1
63
148 VSS
VSS 64
149 DQ53 DQ21 65
150 DQ54 DQ22 66
151 DQ55 DQ23 67
152 VSS
VSS 68
153 DQ56 DQ24 69
154 DQ57 DQ25 70
155 DQ58 DQ26 71
156 DQ59 DQ27 72
157 Vcc
Vcc 73
158 DQ60 DQ28 74
159 DQ61 DQ29 75
160 DQ62 DQ30 76
161 DQ63 DQ31 77
162 VSS
VSS 78
163 CLK3
CLK2
79
164 NC
NC 80
165 SA0
WP 81
166 SA1
SDA
82
167 SA2
SCL 83
168 Vcc
Vcc 84
/xxx indicates active low signal.
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A9]
BA0 (A13), BA1 (A12)
: SDRAM Bank Select
DQ0 - DQ63
: Data Inputs/Outputs
CLK0 - CLK3
: Clock Input
CKE0, CKE1
: Clock Enable Input
/CS0 - /CS3
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE : Write Enable
DQMB0 - DQMB7 : DQ Mask Enable
SA0 - SA2
: Address Input for EEPROM
SDA
: Serial Data I/O for PD
SCL : Clock Input for PD
VCC : Power Supply
VSS : Ground
WP : Write Protect
NC : No Connection
Data Sheet M13681EJ4V0DS00
3


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32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

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MC-4532CD646
5 Block Diagram
/WE
/CS0
DQMB0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQMB1
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQMB4
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQMB5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
/CS1
/CS2
DQMB2
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
DQ 3
D0
DQ 2
DQ 1
DQ 0
/WE
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
DQ 4
D8
DQ 5
DQ 6
DQ 7
/WE
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
DQ 3
D1
DQ 2
DQ 1
DQ 0
/WE
DQMB3
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
DQ 4
D9
DQ 5
DQ 6
DQ 7
/WE
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 4 DQM /CS
DQ 7
DQ 6
DQ 5
DQ 3
D4
DQ 2
DQ 1
DQ 0
/WE
DQMB6
DQ 3 DQM /CS
DQ 0
DQ 1
DQ 2
DQ 4
D12
DQ 5
DQ 6
DQ 7
/WE
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQ 5 DQM /CS
DQ 7
DQ 6
DQ 4
DQ 3
D5
DQ 2
DQ 1
DQ 0
/WE
DQMB7
DQ 2 DQM /CS
DQ 0
DQ 1
DQ 3
DQ 4
D13
DQ 5
DQ 6
DQ 7
/WE
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
/CS3
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
DQ 3
D2
DQ 2
DQ 1
DQ 0
/WE
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
DQ 4
D10
DQ 5
DQ 6
DQ 7
/WE
DQ 4 DQM /CS
DQ 7
DQ 6
DQ 5
DQ 3
D3
DQ 2
DQ 1
DQ 0
/WE
DQ 3 DQM /CS
DQ 0
DQ 1
DQ 2
DQ 4
D11
DQ 5
DQ 6
DQ 7
/WE
DQ 7DQM /CS
DQ 6
DQ 5
DQ 4
DQ 3
D6
DQ 2
DQ 1
DQ 0
/WE
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
DQ 4
D14
DQ 5
DQ 6
DQ 7
/WE
DQ 7 DQM /CS
DQ 6
DQ 5
DQ 4
DQ 3
D7
DQ 2
DQ 1
DQ 0
/WE
DQ 0 DQM /CS
DQ 1
DQ 2
DQ 3
DQ 4
D15
DQ 5
DQ 6
DQ 7
/WE
SERIAL PD
SDA
SCL
A0 A1 A2
WP
47 k
SA0 SA1 SA2
CLK0
CLK1
CLK: D0, D1, D4, D5
3.3 pF
CLK2
CLK: D8, D9, D12, D13 CLK3
3.3 pF
CLK: D2, D3, D6, D7
3.3 pF
CLK: D10, D11, D14, D15
3.3 pF
A0 - A11
BA0, BA1
VCC
V SS
A0 - A11: D0 - D15
A13, A12: D0 - D15
D0 - D15
C
D0 - D15
/RAS
/CAS
CKE0
/RAS: D0 - D15
/CAS: D0 - D15
CKE: D0 - D7
CKE1
10 k
CKE: D8-D15
Remarks 1. The value of all resistors is 10 except CKE1 and WP.
2. D0 - D15: µPD45128841 (4M words × 8 bits × 4 banks)
4 Data Sheet M13681EJ4V0DS00


MC-4532CD646 (NEC)
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

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MC-4532CD646
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Voltage on power supply pin relative to GND VCC
Voltage on input pin relative to GND
VT
Short circuit output current
IO
Power dissipation
PD
Operating ambient temperature
TA
Storage temperature
Tstg
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
16
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
High level input voltage
Low level input voltage
Operating ambient temperature
Symbol
VCC
VIH
VIL
TA
Condition
MIN.
3.0
2.0
0.3
0
TYP.
3.3
MAX.
3.6
VCC + 0.3
+0.8
70
Unit
V
V
V
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Data input/output capacitance
Symbol
Test condition
CI1 A0 - A11, BA0 (A13), BA1 (A12),
/RAS, /CAS, /WE
CI2 CLK0 - CLK3
CI3 CKE0, CKE1
CI4 /CS0 - /CS3
CI5 DQMB0 - DQMB7
CI/O DQ0 - DQ63
MIN.
58
24
32
17
10
11
TYP.
MAX.
94
40
52
29
17
19
Unit
pF
pF
Data Sheet M13681EJ4V0DS00
5


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32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

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MC-4532CD646
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
Grade MIN. MAX. Unit Notes
Operating current
ICC1 Burst length = 1
tRC tRC(MIN.), IO = 0 mA
/CAS latency = 2 -A80
-A10
1,040 mA
1,040
1
/CAS latency = 3 -A80
-A10
Precharge standby current in ICC2P CKE VIL(MAX.), tCK = 15 ns
power down mode
ICC2PS CKE VIL(MAX.), tCK =
Precharge standby current in ICC2N CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.),
non power down mode
Input signals are changed one time during 30 ns.
1,040
1,040
16 mA
16
320 mA
ICC2NS CKE VIH(MIN.), tCK =
Input signals are stable.
96
Active standby current in
power down mode
Active standby current in
non power down mode
ICC3P CKE VIL(MAX.), tCK = 15 ns
ICC3PS CKE VIL(MAX.), tCK =
ICC3N CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.),
Input signals are changed one time during 30 ns.
80 mA
64
400 mA
ICC3NS CKE VIH(MIN.), tCK = , Input signals are stable.
320
Operating current
(Burst mode)
ICC4
tCK tCK(MIN.)
IO = 0 mA
CBR (Auto) refresh current
ICC5 tRC tRC(MIN.)
/CAS latency = 2 -A80
-A10
/CAS latency = 3 -A80
-A10
/CAS latency = 2 -A80
-A10
/CAS latency = 3 -A80
-A10
1,200 mA
1,000
1,400
1,240
2,080 mA
2,080
2,080
2,080
2
3
Self refresh current
Input leakage current
ICC6 CKE 0.2 V
II(L) VI = 0 to 3.6 V, All other pins not under test = 0 V
32 mA
– 16 + 16 µA
Input leakage current (CKE1)
– 500 +500
Output leakage current
IO(L) DOUT is disabled, VO = 0 to 3.6 V
– 3 + 3 µA
High level output voltage
VOH IO = – 4.0 mA
2.4 V
Low level output voltage
VOL IO = + 4.0 mA
0.4 V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6 Data Sheet M13681EJ4V0DS00


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MC-4532CD646
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
5 Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
2.4 V
CLK 1.4 V
0.4 V
Input
2.4 V
1.4 V
0.4 V
Output
Value
2.4 / 0.4
1.4
1
1.4
tCK
tCH tCL
tSETUP tHOLD
tAC
tOH
Unit Notes
V
V
ns
V
Data Sheet M13681EJ4V0DS00
7


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MC-4532CD646
Synchronous Characteristics
Parameter
Symbol
-A 80
MIN.
MAX.
-A 10
MIN.
MAX.
Unit Note
Clock cycle time
/CAS latency = 3
/CAS latency = 2
Access time from CLK
/CAS latency = 3
/CAS latency = 2
CLK high level width
CLK low level width
Data-out hold time
Data-out low-impedance time
Data-out high-impedance time /CAS latency = 3
/CAS latency = 2
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
CKE setup time (Power down exit)
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
tCK3
tCK2
tAC3
tAC2
tCH
tCL
tOH
tLZ
tHZ3
tHZ2
tDS
tDH
tAS
tAH
tCKS
tCKH
tCKSP
tCMS
tCMH
8 (125 MHz) 10 (100 MHz) ns
10 (100 MHz) 13
(77 MHz) ns
6 6 ns
6 7 ns
3 3 ns
3 3 ns
3 3 ns
0 0 ns
3 6 3 6 ns
3 6 3 7 ns
2 2 ns
1 1 ns
2 2 ns
1 1 ns
2 2 ns
1 1 ns
2 2 ns
2 2 ns
1 1 ns
1
1
1
5 Note 1. Output load
Output
Z = 50
50 pF
Remark These specifications are applied to the monolithic device.
8 Data Sheet M13681EJ4V0DS00


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MC-4532CD646
Asynchronous Characteristics
Parameter
Symbol
-A 80
-A 10
MIN.
MAX.
MIN.
MAX.
ACT to REF/ACT command period (Operation)
tRC 70
70
REF to REF/ACT command period (Refresh)
tRC1 70
78
ACT to PRE command period
tRAS 48 120,000 50 120,000
PRE to ACT command period
tRP 20
20
Delay time ACT to READ/WRITE command
tRCD
20
20
ACT(one) to ACT(another) command period
tRRD
16
20
Data-in to PRE command period
tDPL 8
10
Data-in to ACT(REF) command period /CAS latency = 3 tDAL3 1CLK+20
1CLK+20
(Auto precharge)
/CAS latency = 2 tDAL2 1CLK+20
1CLK+20
Mode register set cycle time
tRSC
2
2
Transition time
tT 0.5 30 1 30
Refresh time (4,096 refresh cycles)
tREF 64 64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
ns
ms
Note
Data Sheet M13681EJ4V0DS00
9


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MC-4532CD646
Serial PD
(1/2)
Byte No.
Function Described
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
0 Defines the number of bytes written into 80H 1 0 0 0 0 0 0 0 128 bytes
serial PD memory
1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes
2 Fundamental memory type
04H 0 0 0 0 0 1 0 0 SDRAM
3 Number of rows
0CH 0 0 0 0 1 1 0 0 12 rows
4 Number of columns
0AH 0 0 0 0 1 0 1 0 10 columns
5 Number of banks
02H 0 0 0 0 0 0 1 0 2 banks
6 Data width
40H 0 1 0 0 0 0 0 0 64 bits
7 Data width (continued)
00H 0 0 0 0 0 0 0 0 0
8 Voltage interface
01H 0 0 0 0 0 0 0 1 LVTTL
9 CL = 3 Cycle time
-A80 80H 1 0 0 0 0 0 0 0 8 ns
-A10 A0H 1 0 1 0 0 0 0 0 10 ns
10 CL = 3 Access time
-A80 60H 0 1 1 0 0 0 0 0 6 ns
-A10 60H 0 1 1 0 0 0 0 0 6 ns
11 DIMM configuration type
00H 0 0 0 0 0 0 0 0 None
12 Refresh rate/type
80H 1 0 0 0 0 0 0 0 Normal
13 SDRAM width
08H 0 0 0 0 1 0 0 0 ×8
14 Error checking SDRAM width
00H 0 0 0 0 0 0 0 0 None
15 Minimum clock delay
01H 0 0 0 0 0 0 0 1 1 clock
16 Burst length supported
8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
17 Number of banks on each SDRAM
04H 0 0 0 0 0 1 0 0 4 banks
18 /CAS latency supported
06H 0 0 0 0 0 1 1 0 2, 3
19 /CS latency supported
01H 0 0 0 0 0 0 0 1 0
20 /WE latency supported
01H 0 0 0 0 0 0 0 1 0
21 SDRAM module attributes
00H 0 0 0 0 0 0 0 0
22 SDRAM device attributes : General
0EH 0 0 0 0 1 1 1 0
23 CL = 2 Cycle time
-A80 A0H 1 0 1 0 0 0 0 0 10 ns
-A10 D0H 1 1 0 1 0 0 0 0 13 ns
24 CL = 2 Access time
-A80 60H 0 1 1 0 0 0 0 0 6 ns
-A10 70H 0 1 1 1 0 0 0 0 7 ns
25-26
00H 0 0 0 0 0 0 0 0
27 tRP(MIN.)
-A80 14H 0 0 0 1 0 1 0 0 20 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
28 tRRD(MIN.)
-A80 10H 0 0 0 1 0 0 0 0 16 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
29 tRCD(MIN.)
-A80 14H 0 0 0 1 0 1 0 0 20 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
30 tRAS(MIN.)
-A80 30H 0 0 1 1 0 0 0 0 48 ns
-A10 32H 0 0 1 1 0 0 1 0 50 ns
31 Module bank density
20H 0 0 1 0 0 0 0 0 128M bytes
10 Data Sheet M13681EJ4V0DS00


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MC-4532CD646
(2/2)
Byte No.
Function Described
32 Command and address signal input
setup time
33 Command and address signal input
hold time
34 Data signal input setup time
35 Data signal input hold time
36-61
62 SPD revision
63 Checksum for bytes 0 - 62
-A80
-A10
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel specification frequency
127 Intel specification /CAS
-A80
latency support
-A10
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
20H 0 0 1 0 0 0 0 0 2 ns
10H 0 0 0 1 0 0 0 0 1 ns
20H 0 0 1 0 0 0 0 0 2 ns
10H 0 0 0 1 0 0 0 0 1 ns
00H 0 0 0 0 0 0 0 0
12H 0 0 0 1 0 0 1 0 1.2
F1H 1 1 1 1 0 0 0 1
57H 0 1 0 1 0 1 1 1
64H 0 1 1 0 0 1 0 0 100 MHz
FFH 1 1 1 1 1 1 1 1
FDH 1 1 1 1 1 1 0 1
Timing Chart
Refer to the SYNCHORONOUS DRAM MODULE TIMING CHART Information (M13348E).
Data Sheet M13681EJ4V0DS00
11


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MC-4532CD646
5 Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
R2
F1
R1
J
M2 (AREA A)
M1 (AREA B)
A (AREA B)
Y1
Y2
Z1
Z2 F2
N
AH
B
B
I
G
K
C
D
A1 (AREA A)
S
(OPTIONAL HOLES)
E
detail of A part
W
V
X
detail of B part
D2
P
D1
Q
M
L
U1 U2
T
ITEM
A
A1
B
C
D
D1
D2
E
F1
F2
G
H
I
J
K
L
M
M1
M2
N
P
Q
R1
R2
S
T
U1
U2
V
W
X
Y1
Y2
Z1
Z2
MILLIMETERS
133.35
133.35±0.13
11.43
36.83
6.35
2.0
3.125
54.61
2.44
3.18
6.35
1.27 (T.P.)
8.89
24.495
42.18
17.78
34.93±0.13
15.15
19.78
4.0 MAX.
1.0
R2.0
4.0±0.10
9.53
φ 3.0
1.27±0.1
4.0 MIN.
4.0 MIN.
0.2±0.15
1.0±0.05
2.54±0.10
3.0 MIN.
2.26
3.0 MIN.
2.26
M168S-50A78
12 Data Sheet M13681EJ4V0DS00


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Data Sheet M13681EJ4V0DS00
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14 Data Sheet M13681EJ4V0DS00


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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M13681EJ4V0DS00
15


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CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8




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