IA6805E2 (InnovASIC)
Microprocessor Unit

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IA6805E2
Microprocessor Unit
Preliminary Data Sheet
FEATURES
Form, Fit, and Function Compatible with the Harris© CDP6805E2CE and Motorola©
MC146805E2
Internal 8-bit Timer with 7-Bit Programmable
Prescaler
On-chip Clock
Memory Mapped I/O
Versatile Interrupt Handling
True Bit Manipulation
Bit Test and Branch Instruction
Vectored Interrupts
Power-saving STOP and WAIT Modes
Fully Static Operation
112 Bytes of RAM
The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces
replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This
technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible
with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon
technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable
timing.
Functional Block Diagram
RESET_N
IRQ_N
LI
DS
RW_N
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
A12
A11
A10
A9
A8
VSS
(1) IA6805E2
(2)
40 Pin DIP
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
VDD
OSC1
OSC2
TIMER
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
B1
B2
B3
B4
B5
B6
B7
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
NC
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
IA6805E2
44 Pin LCC
(39) PB1
(38) PB2
(37) PB3
(36) PB4
(35) PB5
(34) PB6
(33) PB7
(32) B0
(31) B1
(30) B2
(29) B3
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Microprocessor Unit

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IA6805E2
Preliminary Data Sheet
Microprocessor Unit
Figure 1 illustrates the IA6805E2. The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low
cost, low power MPU. It features a CPU, on-chip RAM, parallel I/O compatibility with pins
programmable as input or output. The following paragraphs will further describe this system block
diagram and design in more detail.
Figure 1: System Block Diagram
TIMER
PRESCALER
TIMER/
COUNTER
TIMER CONTROL
OSC1 OSC2
OSCILLATOR
PA0
PORT
A
I/O
LINES
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PORT
A
REG
DATA
DIR
REG
PORT
B
I/O
LINES
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PORT
B
REG
DATA
DIR
REG
ACCUMULATOR
8A
INDEX
REGISTER
8X
CONDITION
CODE
5 REGISTER CC
STACK
POINTER
6 SP
PROGRAM
COUNTER
5 HIGH PCH
PROGRAM
COUNTER
8 LOW PCL
CPU
RESET_N
LI
IRQ_N
CPU
CONTROL
ALU
112x8
RAM
MUX
BUS
DRIVE
B0
B1
B2 MULTIPLEXED
B3 ADDRESS
B4 DATA
BUS
B5
B6
B7
ADDRESS
DRIVE
A8
A9
A10
ADDRESS
BUS
A11
A12
BUS
CONTROL
AS
DS
RW_N
ADDRESS STROBE
DATA STROBE
READ/WRITE
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Microprocessor Unit

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IA6805E2
Microprocessor Unit
Preliminary Data Sheet
Functional Overview
I/O Signal Description
The table below describes the I/O characteristics for each signal on the IC. The signal names correspond to
the signal names on the pinout diagrams provided.
SIG N A L N A M E
V DD and V SS
(Power and Ground)
RESET_n
(R e s e t )
IR Q _ n
(Interrupt Request)
LI
(Load Instruction)
DS
(D a ta Strobe)
RW_n
(R e a d / W rite)
AS
(Address Strobe)
PA0-PA7/PB0-PB7
(Input/Output Lines)
A8-A12
(H igh Order Address Lines)
B0-B7
(Address/Data Bus)
T im e r
OSC1, OSC2
(System C lock)
C rystal
External Clock
I/O
N/A
I
I
O
O
O
O
I/O
O
I/O
I
I/O
DESCRIPTION
S o u r c e : T h e s e t w o pins provide p o w e r to the chip. V D D provides + 5 volts (±0.5) p o w e r
a n d V SS is ground.
T T L : I n p u t pin t h a t c a n b e u s e d to r e s e t t h e M P U 's i n t e r n a l state b y p u l l i n g t h e r e s e t _ n
pin low.
T T L : I n p u t pin t h a t is level a n d e d g e s e n s i t i v e . C a n b e u s e d to r e q u e s t a n i n t e r r u p t
sequence.
T T L w ith s l e w rate c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h a t a n e x t o p c o d e fetch is in
p r o g r e s s . U s e d o n l y f o r certain d e b u g g i n g a n d test s y s t e m s . N o t c o n n e c t e d in n o r m a l
o p e r a t i o n . O v e r l a p s D ata S t r o b e ( D S ) signal. T h i s o u t p u t is c a p a b l e o f driving o n e
standard TTL load and 50pF.
T T L w ith slew rate c o n t r o l : O u t p u t pin u s e d to transfer data to o r from a peripheral o r
m e m o r y . D S occurs anytim e t h e M P U d o e s a data read o r w rite a n d during data transfer
to o r f r o m i n t e r n a l m e m o r y . D S is available a t f O S C ÷ 5 w h e n t h e M P U is n o t in t h e W A I T
or STOP mode. This output is capable of driving one standard TTL load and 130pF.
T T L w ith slew rate c o n t r o l : O u t p u t pin used to indicate t h e direction o f d a t a transfer
from internal memory, I/O registers, and external peripheral devices and memories.
I n d i c a t e s to a s e l e c t e d p e r i p h e r a l w h e t h e r t h e M P U is to r e a d (R W _ n h i g h ) o r w r i t e
(R W _ n l o w ) d a t a o n t h e n e x t d a t a s t r o b e . T h i s o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d
TTL load and 130pF.
T T L w ith slew rate control: O u t p u t strobe used to indicate the presence o f an address
o n t h e 8-bit m u l t i p l e x e d b u s . T h e A S line is u s e d to d e m u l t i p l e x t h e e i g h t least s i g n i f i c a n t
a d d r e s s b i t s f r o m t h e d a t a b u s . A S is available a t fO S C ÷ 5 w h e n t h e M P U is n o t in t h e
W A I T o r S T O P m o d e s . T h i s o u t p u t is c a p a b l e o f driving o n e s t a n d a r d T T L l o a d a n d
130pF.
T T L w ith slew rate c o n t r o l : T h e s e 16 lines constitute I n p u t / O u t p u t p o r t s A a n d B .
E a c h line is i n d i v i d u a l l y p r o g r a m m e d to b e e i t h e r an i n p u t o r o u t p u t u n d e r s o f t w a r e
c o n t r o l o f t h e D ata D irection R e g i s t e r ( D D R ) as s h o w n b e l o w in T a b l e 1 a n d F i g u r e 2 .
T h e p o r t I / O is p r o g r a m m e d b y w r i t i n g t h e c o r r e s p o n d i n g b i t in t h e D D R to a " 1 " f o r
output and a "0" for input. In the output m o d e the bits are latched and appear on the
c o r r e s p o n d i n g o u t p u t p i n s . A ll t h e D D R 's are i n i t i a l i z e d to a " 0 " o n r e s e t . T h e o u t p u t
p o r t registers are n o t initialized on reset. E a c h o u t p u t is c a p a b l e o f driving o n e s t a n d a r d
TTL load and 50pF.
T T L w ith slew rate control: T h e s e five o u t p u t s constitute t h e h i g h e r o r d e r n o n -
m u l t i p l e x e d a d d r e s s l i n e s . E a c h o u t p u t is c a p a b l e o f driving o n e s t a n d a r d T T L l o a d a n d
130pF.
T T L w ith slew rate control: T h e s e bi-directional lines constitute the l o w e r o r d e r
addresses a n d data. T h e s e lines are m ultiplexed w ith a d d r e s s present at address strobe
tim e a n d d a t a p r e s e n t a t d a t a s t r o b e tim e. W h e n in t h e d a t a m o d e , t h e s e lines are bi-
directional, transferring data to a n d from m e m o r y a n d peripheral d e v i c e s as indicated b y
the R W _ n pin. A s outputs, these lines are capable o f driving o n e standard T T L load and
130pF.
T T L : Input used to control the internal tim er/counter circuitry.
T T L O scillator input/output: These pins provide control input for the on-chip clock
oscillator circuits. E ither a crystal o r external c l o c k is c o n n e c t e d to these p i n s to p r o v i d e
a s y s t e m c l o c k . T h e crystal c o n n e c t i o n is s h o w n in F i g u r e 3 . T h e O S C 1 to b u s
transitions for system designs using oscillators slower than 5M H z is shown in Figure 4.
T h e circuit s h o w n in F i g u r e 3 is r e c o m m e n d e d w h e n using a c r y s t a l . A n e x t e r n a l C M O S
o s c i l l a t o r is r e c o m m e n d e d w h e n using crystals o u t s i d e t h e s p e c i f i e d r a n g e s . T o m inim ize
output distortion and start-up stabilization tim e , the crystal and components should be
mounted as close to the input pins as possible.
W h e n an e x t e r n a l clock is u s e d , it s h o u l d b e a p p l i e d to t h e O S C 1 i n p u t w ith t h e O S C 2
input not connected, as shown in Figure 3.
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Microprocessor Unit

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IA6805E2
Microprocessor Unit
Preliminary Data Sheet
Table 1
I/O Pin Functions
R/W-n DDR
I/O Pin Functions
0 0 The I/O pin is in iput mode. Data is written
into the output data latch.
0 1 Data is written into the output data latch and
output to the I/O pin.
1 0 The state of the I/O pin is read.
1 1 the I/O pin is in an output mode. The
output data latch is read.
Figure 2: PA0-PA7/PB0-PB7 (Input/Output Lines)
I/O Port Circutry and Register Configuration:
DATA DIRECTION
REGISTER
BIT
TO
AND LATCHED
OUTPUT
FROM DATA BIT
CPU INPUT
REG
BIT
OUTPUT
I/O
PIN
INPUT
I/O
PIN
76543210
DATA DIRECTION
A(B)
REGISTER
DDA7
(DDB7)
DDA6
(DDB6)
DDA5
(DDB5)
DDA4
(DDB4)
DDA3
(DDB3)
DDA2
(DDB2)
DDA1
(DDB1)
DDA0
(DDB0)
$0004 ($0005)
PORT A(B)
REGISTER
$0000 ($0001)
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PIN
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
(PB7) (PB6) (PB5) (PB4) (PB3) (PB2) (PB1) (PB0)
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Microprocessor Unit

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IA6805E2
Microprocessor Unit
Preliminary Data Sheet
Figure 3: OSC1, OSC2 (System Clock)
Crystal Parameters Representative Frequencies:
RS max
C0
C1
Q
COSC1
COSC2
5.0 MHz
50
8 pF
0.02 pF
50 k
15-30 pF
15-25 pF
4.0 MHz
75
7 pF
0.012 pF
40 k
15-30 pF
15-25 pF
1.0 MHz
400
5 pF
0.008 pF
30 k
15-40 pF
15-30 pF
Oscillator Connections:
38
OSC2
38
OSC2
CRYSTAL CIRCUIT
L
C1 RS
39
C0
OSC1
39
OSC1
CRYSTAL OSCILLATOR CONNECTIONS
ia6805E2
10 M
38
39
OSC2
C OSC2
OSC1
C OSC1
OSC1 PIN
tOL
t
tOLOL
tOH
Figure 4: OSC1, OSC2 (System Clock)
OSC1 to Bus Transitions Timing Waveforms:
OSC1
39
OSC2
NC 38
IA6805E2
OSC1
AS
DS
RW_n
A[12:8]
B[7:0]
MPU READ
MUX ADDR
MPU
READ
DATA*
B[7:0]
MPU WRITE
MUX ADDR
MPU WRITE DATA
*READ DATA "LATCHED" ON DS FALL
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Microprocessor Unit

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IA6805E2
Microprocessor Unit
Preliminary Data Sheet
Functional Description
Memory:
The MPU is capable of addressing 8192 bytes of memory and I/O registers. The locations are
divided into internal memory space and external memory space as shown in Figure 5.
The first 128 bytes of memory contain internal port I/O locations, timer locations, and 112 bytes of
RAM. The MPU can read from or write to any of these locations. During program reads from on
chip locations, the MPU accepts data only from the addressed on chip location. Any read data
appearing on the input bus is ignored.
The shared stack area is used during interrupts or subroutine calls. A maximum of 64 bytes of RAM
is available for stack usage. The stack pointer is set to $7f at power up. The unused bytes of the stack
can be used for data storage or temporary work locations, but care must be taken to prevent it from
being overwritten due to stacking from an interrupt or subroutine call.
Figure 5: Memory Map
0
ACCESS VIA
PAGE 0
DIRECT
ADDRESS
127
128
255
256
I/O PORTS
TIMER RAM
$0000
$007F
$0080
$00FF
$0100
0 PORT A DATA REGISTER
1 PORT B DATA REGISTER
2 EXTERNAL MEMORY SPACE
3 EXTERNAL MEMORY SPACE
4 PORT A DATA DIRECTION REGISTER
5 PORT B DATA DIRECTION REGISTER
6 EXTERNAL MEMORY SPACE
7 EXTERNAL MEMORY SPACE
8 TIMER DATA REGISTER
9 TIMER CONTROL REGISTER
10
EXTERNAL MEMORY
SPACE (8064 BYTES)
EXTERNAL MEMORY SPACE
15
16
63
64
INTERRUPT
VECTORS
TIMER INTERRUPT FROM WAIT STATE ONLY $1FF6 - $1FF7
TIMER INTERRUPT
$1FF8 - $1FF9
EXTERNAL INTERRUPT
$1FFA - $1FFB
SWI $1FFC - $1FFD
8198
RESET
$1FFE - $1FFF
127
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RAM
(112 BYTES)
STACK
(64 BYTES MAX)
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Microprocessor Unit

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Microprocessor Unit
Registers:
Preliminary Data Sheet
The following paragraphs describe the registers contained in the MPU. Figure 6 shows the
programming model and Figure 7 shows the interrupt stacking order.
Figure 6: Programming Model
7
7
12
PCH
87
12 6
0000001
0
A ACCUMULATOR
0
X INDEX REGISTER
0
PCL PROGRAM COUNTER
0
SP STACK POINTER
4 CC 0
H I N Z C CONDITION CODE REGISTER
CARRY/BORROW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY
Figure 7: Interrupt Stacking Order
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
INCREASING MEMORY
ADDRESSES
1
R
E
T
U
R
N0
UNSTACK
11
CONDITION CODE
REGISTER
ACCUMULATOR
INDEX REGISTER
00
PCH
PCL
STACK
I
N
T
E
R
R
DECREASING MEMORY
ADDRESSES
U
P
T
A(Accumulator):
The accumulator is an 8-bit register used to hold operands and results of arithmetic calculations or
data manipulations.
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Microprocessor Unit

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Microprocessor Unit
X(Index Register):
Preliminary Data Sheet
The index register is an 8-bit register used during the indexed addressing mode. It contains an 8-bit
value used to create an effective address. The index register may also be used as a temporary storage
area when not performing addressing operations.
PC(Program Counter):
The program counter is a 13-bit register that holds the address of the next instruction to be
performed by the MPU.
SP(Stack Pointer):
The stack pointer is a 13-bit register that holds the address of the next free location on the stack.
During an MPU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location
$007f. The seven most significant bits of the stack pointer are permanently set to 0000001. They are
appended to the six least significant register bits to produce an address range down to location $0040.
The stack pointer gets decremented as data is pushed onto the stack and incremented as data is
removed from the stack. The stack area of RAM is used to store the return address on subroutine
calls and the machine state during interrupts. The maximum number of locations for the stack
pointer is 64 bytes. If the stack goes beyond this limit the stack pointer wraps around and points to
it’s upper limit thereby losing the previously stored information. Subroutine calls use 2 bytes of RAM
on the stack and interrupts use 5 bytes.
CC(Condition code Register):
The condition code register is a 5-bit register that indicates the results of the instruction just
executed. The bit is set if it is high. A program can individually test these bits and specific actions can
be taken as a result of their states. Following is an explanation of each bit.
C(Carry Bit):
The carry bit indicates that a carry or borrow out of the Arithmetic Logical Unit (ALU) occurred
during the last arithmetic instruction. This bit is also modified during bit test, shift, rotate, and
branch types of instructions.
Z(Zero Bit):
The zero bit indicates the result of the last arithmetic, logical, or data manipulation was zero.
N(Negative Bit):
The negative bit indicates the result to the last arithmetic, logical, or data manipulation was negative
(bit 7 in the result is high).
I(Interrupt Mask Bit)
The interrupt mask bit indicates that both the external interrupt and the timer interrupt are disabled
(masked). If an interrupt occurs while this bit is set, the interrupt is latched and is processed as soon
as the interrupt bit is cleared.
H(Half Carry Bit)
The half carry bit indicates that a carry occurred between bits 3 and 4 of the ALU during an ADD or
ADC operation.
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Microprocessor Unit
Resets:
Preliminary Data Sheet
The MPU can be reset by initial power up or by the external reset pin (reset_n).
POR(Power On Reset)
Power on reset occurs on initial power up. It is strictly for power initialization conditions and should
not be used to detect drops in the power supply voltage. There is a 1920 tCYC time out delay from the
time the oscillator is detected. If the reset_n pin is still low at the end of the delay, the MPU will
remain in the reset state until the external pin goes high.
Reset_n
The reset_n pin is used to reset the MPU. The reset pin must stay low for a minimum of tcyc to
guarantee a reset. The reset_n pin is provided with a schmitt Trigger to improve noise immunity
capability.
Interrupts:
The MPU can be interrupted with the external interrupt pin (irq_n), the internal timer interrupt
request, or the software interrupt instruction. When any of these interrupts occur, normal processing
is suspended at the end of the current instruction execution. The processor registers are saved on the
stack (stacking order shown in Figure 7) and the interrupt mask (I) is set to prevent additional
interrupts. Normal processing resumes after the RTI instruction causes the register contents to be
recovered from the stack. When the current instruction is completed, the processor checks all
pending hardware interrupts and if unmasked (I bit clear) proceeds with interrupt processing.
Otherwise, the next instruction is fetched and executed. Masked interrupts are latched for later
interrupt service. External interrupts hold higher priority than timer interrupts. At the end of an
instruction execution, if both an external interrupt and timer interrupt are pending, the external
interrupt is serviced first. The SWI gets executed with the same priority as any other instruction if the
hardware interrupts are masked (I bit set). Figure 8 shows the Reset and Interrupt processing
flowchart.
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Microprocessor Unit

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Microprocessor Unit
Figure 8: Reset and interrupt Processing Flowchart
Preliminary Data Sheet
RESET
I_CC <= 1
SP <= $007F
DDRs <= 0
CLR IRQ_N LOGIC
TIMER <= $FF
PRESCALER <= $7F
TCR <= $7f
PUT 1FFE,1FFF ON
ADDRESS BUS
SET
I BIT
?
CLEAR
IRQ_N
EDGE
?
N
Y
TCR6=0
AND
TCR7=1?
N
Y
Y
RESET_N
PIN = LOW
IN
RESET
?
N RESET_N
PIN = LOW
LOAD PC
FROM
1FFE/1FFF
FETCH
INSTRUCTION
IS FETCHED
INSTRUCTION
AN SWI?
N
Y
EXECUTE ALL
INSTRUCTION
CYCLES
CLEAR
IRQ_N
REQUEST
LATCH
IRQ_N
STACK
PC, X, A, CC
I <= 1
TIMER
LOAD PC FROM:
SWI: 1FFC/1FFD
IRQ_N: 1FFA/1FFB
TIMER: 1FF8/1FF9
TIMER WAIT:1FF6/
1FF7
PC+1=>PC
SWI
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IA6805E2
Microprocessor Unit
External Interupt:
Preliminary Data Sheet
If the external interrupt pin irq_n is “low”and the interrupt mask bit of the condition code register is
cleared, the external interrupt occurs. When the interrupt is recognized, the current state of the
machine is pushed onto the stack and the condition code register I-bit gets set masking further
interrupts until the present one is serviced. The program counter is then loaded with the contents of
the interrupt vector, which contains the location of the interrupt service routine. The contents of
$1FFA and $1FFB specify the address for this service routine. A functional diagram of the external
interrupt is shown in Figure 9 and a mode diagram of the external interrupt is shown in Figure 10.
The timing diagram shows two different treatments of the interrupt line (irq_n) to the processor. The
first shows several interrupt lines “wire ORed” to form the interrupts at the processor. If the
interrupt line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. The
second shows single pulses on the interrupt line spaced far enough apart to be serviced. The
minimum time between pulses is a function of the length of the interrupt service. After a pulse
occurs, the next pulse should not occur until an RTI has occurred. The time between pulses (tILIL) is
obtained by adding 20 instruction cycles to the total number of cycles it takes to complete the service
routine including the RTI instruction.
Figure 9: Interrupt Functional Diagram
INTERRUPT PIN
VDD
DQ
C
Q
R
Figure 10: Interrupt Mode Diagram
EXTERNAL
INTERUPT
REQUEST
I BIT (CCR)
POWER-ON RESET
EXTERNAL RESET
EXTERNAL INTERRUPT
BEING SERVICED
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Preliminary Data Sheet
Timer Interrupt:
If the timer mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared,
each time the timer decrements to zero ($01 to $00 transition) an interrupt request is generated.
When the interrupt is recognized, the current state of the machine is pushed onto the stack and the
condition code register I-bit gets set masking further interrupts until the present one is serviced. The
program counter is then loaded with the contents of the timer interrupt vector, which contains the
location of the timer interrupt service routine. The contents of $1FF8 and $1FF9 specify the address
for this service routine. If the MPU is in the wait mode and a timer interrupt occurs, then the
contents of $1FF6 and $1FF7 specify the service routine. When the timer interrupt service routine is
complete, the software executes an RTI instruction to restore the machine state and starts executing
the interrupt program.
Software Interrupt:
Software interrupt is an executable instruction regardless of the state of the interrupt mask bit (I) in
the condition code register. SWI is similar to hardware interrupts. It executes after the other
interrupts if the interrupt mask bit is zero. The contents of $1FFC and $1FFD specify the address
for this service routine.
Low Power Modes:
The low power modes consist of the stop instruction and the wait instruction. The following
paragraphs explain these modes of operation.
Stop Modes:
The stop instruction places the MPU in low power consumption mode. The stop instruction disables
clocking of most internal registers. Timer control register bits 6 and 7 (TCR6 and TCR7) are altered
to remove any pending timer interrupt requests and to disable any further timer interrupts. The DS
and AS output lines go “low” and the RW_n line goes “high”. The multiplexed address/data bus
goes to the data input state. The high order address lines remain at the address of the next
instruction. External interrupts are enabled by clearing the I bit in the condition code register. All
other registers, memory, and I/O remain unaltered. Only an external interrupt or reset will bring the
MPU out of the stop mode. Figure 11 shows a flowchart of the stop function.
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Figure 11: STOP Function Flowchart
Preliminary Data Sheet
STOP
TCR BIT 7 <= 0
TCR BIT 6 <= 1
CLEAR I BIT
N
N EXTERNAL
INTERRUPT?
Y
RESET?
Y
FETCH EXTERNAL
INTERRUPT
OR RESET VECTOR
Wait Mode:
The wait instruction places the MPU in low power consumption mode. The wait instruction disables
clocking of most internal registers. The DS and AS output lines go “low” and the RW_n line goes
“high”. The multiplexed address/data bus goes to the data input state. The high order address lines
remain at the address of the next instruction. External interrupts are enabled by clearing the I bit in
the condition code register. All other registers, memory, and I/O remain unaltered. Only an external
interrupt, timer interrupt, or reset will bring the MPU out of the wait mode. The timer may be
enabled to allow a periodic exit from the wait mode. If an external and a timer interrupt occur at the
same time, the external interrupt is serviced first. Then, if the timer interrupt request is not cleared in
the external interrupt routine, the normal timer interrupt (not the timer wait interrupt) is serviced
since the MPU is no longer in the wait mode. Figure 12 shows a flowchart of the wait function.
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Figure 12: WAIT Function Flowchart
WAIT
OSCILLATOR
ACTIVE,
CLEAR I BIT,
TIMER CLOCK
ACTIVE,
Preliminary Data Sheet
RESET?
N
Y
EXTERNAL
N
INTERRUPT?
Y TIMER
INTERRUPT?
(TCR BIT7
= 1)
Y
N
FETCH EXTERNAL
INTERRUPT, RESET,
OR TIMER
INTERRUPT (FROM
WAIT MODE ONLY)
TCR
BIT 6 = 0?
Y
N
Timer:
The MPU contains a single 8-bit software programmable counter driven by a 7-bit software
programmable prescaler. The counter may be loaded under program control and decrements to zero.
When the counter decrements to zero, the timer interrupt request bit in the timer control register
(TCR7) is set. Figure 13 shows a block diagram of the timer. If the timer mask bit (TCR6) and the
interrupt mask bit (I) of the condition code register are cleared, an interrupt request is generated.
After completion of the current instruction, the current state of the machine is pushed onto the
stack. The timer interrupt vector address is then fetched from locations $1FF8 and $1FF9 and the
interrupt routine is executed, unless the MPU was in the WAIT mode in which case the interrupt
vector address in locations $1FF6 and $1FF7 is fetched. Power-On-Reset causes the counter to set to
$FF.
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Preliminary Data Sheet
Figure 13: Timer Block Diagram
NOTE: 1. Prescaler and counter are clocked on the falling edge of the internal
clock (AS) or external input.
2. Counter is written to during Data Strobe (DS) and counts down continuously.
TIMER
(PIN 37)
INTERNAL
CLOCK
TIMER_n
EXT
CLK
2 - TO - 1
MUX
ENABLE /
DISABLE_n
INT
CLK
INTERNAL_n / EXTERNAL
PRESCALER
(7 BITS)
COUNTER
(8 BITS)
INTERRUPT
CONTROL
READ WRITE
INTERRUPT
TCR4 TCR5
TCR3 TCR2 TCR1 TCR0
SETTING TCR3 CLEARS
PRESCALER TO ÷ 1
SOFTWARE FUNCTIONS
The counter continues to count past zero, falling from $00 to $FF, and continues. The processor
may read the counter at any time without disturbing the count by reading the timer data register
(TDR). This allows a program to determine the length of time since a timer interrupt has occurred.
The timer interrupt request bit remains set until cleared by software. The interrupt is lost if this
happens before the timer interrupt is serviced.
The prescaler is a 7-bit divider used to extend the maximum length of the timer. TCR bits 0-2 are
programmed to choose the appropriate prescaler output, which is used as the count input. The
prescaler is cleared by writing a “1” into TCR bit 3, which avoids truncation errors. The processor
cannot write to or read from the prescaler.
Timer Input Mode 1:
When TCR4 = 0 and TCR5 = 0, the input to the timer is from an internal clock and the timer input
is disabled. The internal clock mode can be used for periodic interrupt generation as well as a
reference for frequency and event measurement. The internal clock is the instruction cycle clock and
is coincident with Address Strobe (AS) except during the wait instruction where it goes low. During
the wait instruction the internal clock to the timer continues to run at its normal rate.
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Timer Input Mode 2:
Preliminary Data Sheet
When TCR4 = 1 and TCR5 = 0, the internal clock and timer input signal are ANDed to form the
timer input. This mode can be used to measure external pulse widths. The external pulse turns on the
internal clock for the duration of the pulse. The count accuracy in this mode is ±1 clock. Accuracy
improves with longer input pulse widths.
Timer Input Mode 3:
When TCR4 = 0 and TCR5 = 1, all inputs to the timer are disabled.
Timer Input Mode 4:
When TCR4 = 1 and TCR5 = 1, the internal clock input to the timer is disabled and the timer input
then comes from the external TIMER pin. The external clock can be used to count external events as
well as to provide an external frequency for generating periodic interrupts.
TCR (Timer Control Register ($0009)):
An 8-bit register that controls functions such as configuring operation mode, setting ratio of the
prescaler, and generating timer interrupt request signals. All bits except bit 3 are read/write. Bits
TCR5 - TCR0 are unaffected by reset_n.
76543210
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
Reset:
01000000
TCR7 –Timer Interrupt Request
Used to indicate the timer interrupt when it is logic one.
1 –Set when the counter decrements to zero or under program control.
0 –Cleared on external reset, POR, STOP instruction, or program control.
TCR6 –Timer Interrupt Mask
Used to inhibit the timer interrupt.
1 –Interrupt inhibited. Set on external reset, POR, STOP instruction, or program control.
0 –Interrupt enabled.
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Preliminary Data Sheet
TCR5 –External or Internal
Selects input clock source. Unaffected by reset.
1 –External clock selected.
0 –Internal clock selected (AS) (fOSC/5).
TCR4 –Timer External Enable
Used to enable external timer pin or to enable the internal clock. Unaffected by reset.
1 –Enables external timer pin.
0 – Disables external timer pin.
TCR3 –Prescaler Clear
Write only bit. Writing a “1” to this bit resets the prescaler to zero. A read of this location always
indicates a zero. Unaffected by reset.
TCR2, TCR1, TCR0 –Prescaler select bits
Decoded to select one of eight outputs of the prescaler. Unaffected by reset.
TRC2
0
0
0
0
1
1
1
1
Prescaler
TRC1 TRC0
00
01
10
11
00
01
10
11
RESET
÷1
÷2
÷4
÷8
÷ 16
÷ 32
÷ 64
÷ 128
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Instruction Set Description
Preliminary Data Sheet
The MPU has 61 basic instructions divided into 5 types. The 5 types are Register/memory, read-modify-
write, branch, bit manipulation, and control.
Register/Memory Instructions:
Most of the following instructions use two operands. One is either the accumulator or the index
register and the other is obtained from memory. The jump unconditional (JMP) and jump to
subroutine (JSR) instructions have no register operand.
Function
Load A from memory
Load X from memory
Store A in memory
Store X in memory
Add memory to A
Add memory and carry to A
Subtract memory
Subtract memory from A with Borrow
AND memory to A
OR memory with A
Exclusive OR memory with A
Arithmetic compare A with memory
Arithmetic compare X with memory
Bit test memory with A (logical compare)
Jump Unconditional
Jump to subroutine
Mnemonic
LDA
LDX
STA
STX
ADD
ADC
SUB
SBC
AND
ORA
EOR
CMP
CPX
BIT
JMP
JSR
Read-Modify-Write Instructions:
These instructions read a memory or register location, modify or test its contents and then write the
modified value back to memory or the register.
Function
Increment
Decrement
Clear
Complement
Negate (2's complement)
Rotate Left Thru Carry
Rotate Right Thru Carry
Logical shift left
Logical shift right
Arithmetic shift right
Test for negative or zero
Mnemonic
INC
DEC
CLR
COM
NEG
ROL
ROR
LSL
LSR
ASR
TST
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Bit Manipulation Instructions:
Preliminary Data Sheet
The MPU is capable of altering any bits residing in the first 256 bytes of memory. An additional
feature allows the software to test and branch on the state of any bit within these locations. For test
and branch instructions the value of the bit tested is placed in the carry bit of the condition code
register.
Function
Branch if bit n set
Branch if bit n clear
Set bit n
Clear bit n
Mnemonic
n = 0… 7
BRSET n
BRCLR n
BSET n
BCLR n
Branch Instructions:
If a specific condition is met, the instruction branches. If not, no operation is performed.
Function
Branch always
Branch never
Branch if higher
Branch if lower or same
Branch if carry clear
Branch if higher or same
Branch if carry set
Branch if lower
Branch if not equal
Branch if equal
Branch if half carry clear
Branch if half carry set
Branch if plus
Branch if minus
Branch if interrupt mask bit clear
Branch if interrupt mask bit set
Branch if interrupt line low
Branch if interrupt line high
Branch to subroutine
Mnemonic
BRA
BRN
BHI
BLS
BCC
BHS
BCS
BLO
BNE
BEQ
BHCC
BHCS
BPL
BMI
BMC
BMS
BIL
BIH
BSR
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Control Instructions:
Preliminary Data Sheet
Used to control processor operation during program execution. They are register referenced
instructions.
Function
Transfer A to X
Transfer X to A
Set carry bit
Clear carry bit
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-Operation
Stop
Wait
Mnemonic
TAX
TXA
SEC
CLC
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
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Preliminary Data Sheet
Opcode Map Summary:
The following table is an opcode map for the instructions used on the MPU. The legend following
the table shows how to use the table.
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
BTB
BSC
REL DIR INH INH IX1
IX INH INH IMM DIR EXT IX2 IX1
IX
Hi 0
1 2 3 4 5 6 7 8 9 A B C D E F Hi
Low 0000
0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Low
05
0000 BRSET0
3 BTB 2
5
BSET0
BSC 2
3533659
BRA NEG NEGA NEGX NEG NEG RTI
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX 1 INH
234543
SUB SUB SUB SUB SUB SUB 0 0000
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
15
0001 BRCLR0
3 BTB 2
5
2
0010 BRSET1
3 BTB 2
35
0011 BRCLR1
3 BTB 2
4
0100
5
BRSET2
3 BTB 2
55
0101 BRCLR2
3 BTB 2
65
0110 BRSET3
3 BTB 2
7
0111
5
BRCLR3
3 BTB 2
85
1000 BRSET4
3 BTB 2
9
1001
5
BRCLR4
3 BTB 2
A5
1010 BRSET5
3 BTB 2
B5
1011 BRCLR5
3 BTB 2
C
1100
5
BRSET6
3 BTB 2
D5
1101 BRCLR6
3 BTB 2
E
1110
5
BRSET7
3 BTB 2
5
BCLR0
3
BRN
6
RTS
234543
CMP
CMP
CMP
CMP
CMP
CMP 1 0001
BSC 2
5
BSET1
REL
3
BHI
1 INH
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
234543
SBC SBC SBC SBC SBC SBC 2 0010
BSC 2
5
BCLR1
BSC 2
5
BSET2
REL
3 5 3 3 6 5 10
BLS
COM COMA COMX COM COM
SWI
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX 1 INH
353365
BCC LSR LSRA LSRX LSR LSR
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
2
CPX
3
CPX
4
CPX
5
CPX
4
CPX
3
CPX 3 0011
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
234543
AND
AND
AND
AND
AND
AND 4 0100
BSC 2
5
BCLR2
REL 2
3
BCS
DIR 1
INH 1
INH 2
IX1 1
IX
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
2
BIT
3
BIT
4
BIT
5
BIT
4
BIT
3
BIT 5 0101
BSC 2
REL
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
BSET3
353365
BNE
ROR RORA RORX ROR
ROR
234543
LDA
LDA
LDA
LDA
LDA
LDA 6 0110
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
BCLR3
3
BEQ
533
ASR ASRA ASRX
6
ASR
5
ASR
2
TAX
45654
STA STA STA STA STA 7 0111
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
5 353365
BSET4
BHCC LSL LSLA LSLX LSL
LSL
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
5 353365
BCLR4
BHCS
ROL ROLA ROLX ROL
ROL
1 INH
2 DIR 3 EXT 3 IX2 2 IX1 1
IX
2234543
CLC EOR EOR EOR EOR EOR EOR 8 1000
1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
2234543
SEC
ADC
ADC
ADC
ADC
ADC
ADC 9 1001
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
BSET5
353365
BPL
DEC DECA DECX DEC
DEC
2234543
CLI
ORA
ORA
ORA
ORA
ORA
ORA A 1010
BSC 2
5
BCLR5
REL 2
3
BMI
DIR 1
INH 1
INH 2
IX1 1
IX
1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
2234543
SEI
ADD
ADD
ADD
ADD
ADD
ADD B 1011
BSC 2
5
BSET6
BSC 2
REL
3
BMC
REL 2
533
INC INCA INCX
DIR 1 INH 1 INH 2
6
INC
IX1 1
5
INC
IX
1 INH 2
2
RSP
1 INH
IMM 2
2
DIR 3
2
JMP
DIR 3
EXT 3
3
JMP
EXT 3
IX2 2
4
JMP
IX2 2
IX1 1
3
JMP
IX1 1
IX
2
JMP C 1100
IX
5
BCLR6
3
BMS
433
TST TSTA TSTX
6
TST
4
TST
26
NOP
BSR
5
JSR
6
JSR
7
JSR
6
JSR
5
JSR D 1101
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
BSET7
3
BIL
2
STOP
234543
LDX
LDX
LDX
LDX
LDX
LDX E 1110
BSC 2
REL
1 INH
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
F5
1111 BRCLR7
3 BTB 2
5
BCLR7
BSC 2
35336522
BIH
CLR CLRA CLRX CLR
CLR WAIT TXA
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX 1 INH 1 INH
45654
STX STX STX STX STX F 1111
2 DIR 3 EXT 3 IX2 2 IX1 1
IX
Abbreviations for Address
Modes:
INH
A
X
IMM
DIR
Inherent
Accumulator
Index Register
Immediate
Direct
EXT
REL
BSC
BTB
IX
IX1
IX2
Extended
Relative
Bit set/clear
Bit test and branch
Indexed, no offset
Indexed, 1 byte offset
Indexed, 2 byte offset
Mnemonic
Bytes
F
1111
3
SUB
1
IX
# of Cycles
Legend:
0
0000
Opcode in Hexadecimal
Opcode in Binary
Address Mode
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AC/DC Parameters
Absolute maximum ratings:
Supply Voltage (VDD)........................… .… ...… … … … .… .… … … -0.3V to 6V
Input Pin Voltage (VIN)… … … … … … … … … … … … … ...-0.3 to VDD+0.3V
DC Input Current per pin (I)… … … … … … … … … … … … .… … ..… ±10mA
Operating Temperature… … … … … … … … … … … … .… … ....-40°C to 85°C
Storage temperature Range (Tstg).................… ........… .… ...… - 55°C to 125°C
Lead Temperature… ...................................................… … 300°C for 10 seconds
Preliminary Data Sheet
Note: The specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed
under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect the long-term reliability
of the device.
Electrical Specifications @ 5.0V
(VDD=2.7 to 5.5 Vdc, VSS=0, TA=TL to TH), unless otherwise specified
DC CHARACTERISTICS
Symbol Parameter
Min Max Unit
VDD
VOL
VOH
Supply Voltage
Output Voltage, I LOAD 16mA
2.7 5.5 V
- 0.4 V
2.4 - V
IOL Output Current
IOH
VIH High Level input Voltage
- 16 mA
- -16 mA
2 -V
VIL Low Level input Voltage
- 0.8 V
IIH High Level input Current
IIL Low Level input Current
IIL Input Pull-Up Current
- 1 µA
- -1 µA
-30 -110 µA
IIH Input Pull-Down Current
30 135 µA
Vt- Schmitt Negative Threshold
0.7 - V
Vt+ Schmitt Positive Threshold
- 2.1 V
Vh Schmitt Hysteresis
0.4 - V
Frequency of Operation
fOSC Crystal
fOSC External Clock
- 5 MHz
DC 5 MHz
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Preliminary Data Sheet
Electrical Specifications @ 3.0V
(VDD=2.7 to 5.5 Vdc, VSS=0, TA=TL to TH), unless otherwise specified
DC CHARACTERISTICS
Symbol Parameter
VDD
VOL
VOH
IOL
IOH
V IH
Supply Voltage
Output Voltage, ILOAD 16mA
Output Current
High Level input Voltage
VIL Low Level input Voltage
IIH High Level input Current
IIL Low Level input Current
IIL Input Pull-Up Current
IIH Input Pull-Down Current
Vt- Schmitt Negative Threshold
Vt+ Schmitt Positive Threshold
Vh Schmitt Hysteresis
Frequency of Operation
fOSC Crystal
fOSC External Clock
Min Max Unit
2 3.6 V
- 0.4 V
2.4 - V
- 16 mA
- -16 mA
2 -V
- 0.8 V
- 1 µA
- -1 µA
-30 -110 µA
30 140 µA
0.7 - V
- 2.1 V
0.4 - V
- 5 MHz
DC 5 MHz
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Control Timing
Preliminary Data Sheet
VSS=0V, TA=TL to TH
Parameters
I/O Port Timing –Input Setup Time
(Figure 14)
Input Hold Time (Figure 14)
Output Delay Time (Figure 14)
Interrupt Setup Time (Figure 15)
Crystal Oscillator Startup Time
(Figure 16)
Wait Recovery Startup Time (Figure
17)
Stop Recovery Startup Time
(Figure 18)
Required Interrupt Release (Figure 15)
Timer Pulse Width (Figure 17)
Reset Pulse Width (Figure 16)
Timer Period (Figure 17)
Interrupt Pulse Width Low (Figure10)
Interrupt Pulse Period
(Figure 10)
Oscillator Cycle Period
(1/5 of tCYC) (Figure 3)
OSC1 Pulse Width High (Figure 3)
OSC1 Pulse Width Low (Figure 3)
Sym
tPVASL
tASLPX
tASLPV
TILASL
tOXOV
tIVASH
tILASH
tDSLIH
tTH, tTL
tRL
tTLTL
tILIH
tILIL
tOLOL
tOH
tOL
VDD = 3.0V
fOSC = 1MHz
Min Typ Max
VDD = 5.0V ±10%
fOSC = 5MHz
Min Typ Max
Unit
500 -
- 250 -
- ns
100 -
- 100 -
- ns
- - 0 - - 0 ns
2 - - 0.4 - - µs
- 30 300 - 15 100 ms
- - 10 - - 2 µs
- - 10 - - 2 µs
- - 5 - - 1.0 µs
0.5 -
- 0.5 -
- tCYC
5.5 -
- 1.5 -
- µs
1.0 -
- 1.0 -
- tCYC
1.0 -
- 1.0 -
- tCYC
* - - * - - tCYC
1000 -
- 200 -
- ns
350 -
350 -
- 75 -
- 75 -
- ns
- ns
*The minimum period of tILIL should not be less than the number of tCYC cycles it takes to execute the
interrupt service routine plus 20 tCYC cycles.
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The End of Obsolescence
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IA6805E2 (InnovASIC)
Microprocessor Unit

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IA6805E2
Microprocessor Unit
Bus Timing
VSS=0V, TA=TL to TH (Figure 19)
Num
Parameters
1 Cycle Time
2 Pulse Width, DS Low
3 Pulse Width, DS High
4 Clock Transition
8 RW_n
9 Non-Muxed Address Hold
11 RW_n Delay From DS Fall
16 Non-Muxed Address Delay From AS Rise
17 MPU Read Data Setup
18 Read Data Hold
19 MPU Data Delay, Write
21 Write Data Hold
23 Muxed Address Delay From AS Rise
24 Muxed Address Valid to AS Fall
25 Muxed Address Hold
26 Delay DS Fall to AS Rise
27 Pulse Width, AS High
28 Delay, AS Fall to DS Rise
Preliminary Data Sheet
VDD = 3.0V
fOSC = 1MHz
50pF Load
Min Max
5000 DC
2800 -
1800 -
- 100
10 -
800 -
- 500
0 200
200 -
0 800
-0
800 -
0 250
600 -
250 750
800 -
850 -
800 -
VDD = 5.0V ±10%
fOSC = 5MHz
1 TTL, 130pF Load
Min Max
1000 DC
560 -
375 -
- 30
10 -
100 -
- 300
0 100
115 -
0 160
- 120
55 -
0 120
55 -
60 180
160 -
175 -
160 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 14: I/O Port Timing
VLOW = 0.8V, VHIGH = VDD –2.0V, VDD = 5.0V ±10%
TA = TL to TH, CL on Port = 50pF, fOSC = 5MHz
ADDRESS_STROBE
PORT_INPUT
PORT_OUTPUT
tPVASL
*NOTE
tASLPX
tASLPV
*Note: The address strobe of the first cycle of the next instruction.
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IA6805E2 (InnovASIC)
Microprocessor Unit

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IA6805E2
Microprocessor Unit
Figure 15: IRQ_n and TCR7_N Interrupt Timing
Preliminary Data Sheet
AS
DS
ADD_BUS_UNMUX[8:12]
IRQ_N__TCR7_N
n0 n1 n2 n3 n4 n5 n6 n7 n8 n9
NEXT OP CODE ADDRESS
T ILASL
1F (FF) 1F (FF)
(NOTE)
T DSLIH
INT ROUTINE
INT ROUTINE
LAST ADDRESS
STARTING ADDRESS
MUX_ADD_DATA[0:7]
SP PCL SP-1 PCH SP-2 X SP-3 A CCSP-4
NEW PCH
NEW PCL
NEXT OP CODE
FA (IRQ) FB (IRQ) 1ST OP
F8 (TIMER) F9 (TIMER) INT ROUTINE
80
RTI
OP CODE
RW_N
Note: tDSLIH- the interrupting device must release the IRQ_N line within this time to prevent subsequent recognition
of the same interrupt.
Figure 16: Power-On-Reset and RESET_n Timing
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IA6805E2 (InnovASIC)
Microprocessor Unit

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IA6805E2
Preliminary Data Sheet
Microprocessor Unit
Figure 17: Timer Interrupt After WAIT Instruction Timing
INT_EXT_CLK
tTL
tTH
TIMER
COUNTER=$00
tTLTL
TCR7
tIVASH
AS
n0 n1 n2 n3 n4 n5 n6 n7
DS
A[12:8]
OP CODE ADDR
ADDRESS + 1
1F (FF) 1F (FF)
B[7:0]
OP CODE
ADDRESS
ADDR + 1
8F
WAIT OP CODE
RW_N
INT ROUTINE
STARTING
ADDRESS
PCL PCH X A CC F6 F7SP
SP-1
SP-2
SP-3
SP-4
NEW PCH NEW PCL
1ST OP CODE
INT ROUTINE
Figure 18: Interrupt Recovery From STOP Instruction Timing
INT_EXT_CLK
tTL
tTH
TIMER
COUNTER=$00
tTLTL
TCRB7
tIVASH
AS
n0 n1 n2 n3 n4 n5 n6 n7
DS
A[12:8]
OP CODE ADDR
ADDRESS + 1
1F (FF) 1F (FF)
B[7:0]
OP CODE
ADDRESS
ADDR + 1
8E
STOP OP CODE
RW_N
INT ROUTINE
STARTING
ADDRESS
PCL PCH X A CC F6 F7SP
SP-1
SP-2
SP-3
SP-4
NEW PCH NEW PCL
1ST OP CODE
INT ROUTINE
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IA6805E2 (InnovASIC)
Microprocessor Unit

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IA6805E2
Microprocessor Unit
Figure 19: Bus Timing
AS
DS
RW_n
A[12:8]
B[7:0]
WRITE
18
B[7:0]
READ
26
4
8
11
9
23
21
23
44
27
28
1
2
16
25
VALID
ADDR
24 25
VALID
ADDR
Preliminary Data Sheet
4
3
4
26
4
8
11
9
19 21
VALID WRITE
DATA
17
VALID READ
DATA
18
23
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IA6805E2 (InnovASIC)
Microprocessor Unit

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IA6805E2
Microprocessor Unit
Preliminary Data Sheet
PDIP Packaging Dimensions
TOP
LEAD 1
IDENTIFIER
1
LEAD COUNT
DIRECTION
E1 E
DA
A1
L
B
B1
e
SIDE VIEW (LENGTH)
eA
eB
SIDE VIEW (WIDTH)
Lead Count
Symbol
40 (in Inches)
MIN MAX
A - .200
A1 .015
-
B .015 .020
B1 .040 .060
C .008 .012
D
1.980
2.065
E .580 .610
E1 .520 .560
e .100 TYP
eA .580 -
eB - .686
L .100 MIN
C
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IA6805E2 (InnovASIC)
Microprocessor Unit

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IA6805E2
Preliminary Data Sheet
Microprocessor Unit
PLCC Packaging Dimensions
PIN 1
IDENTIFIER & ZONE
D
D1
D3
TOP VIEW
.81 / .66
e
.53 / .33
D2 / E2
SIDE VIEW
Package Options
Copyright © 2000
innovASIC
The End of Obsolescence
SEATING PLANE
.51 MIN.
R 1.14 / .64
.10
BOTTOM VIEW
LEAD COUNT
Symbol
44 (in Millimeters)
MIN MAX
A 4.20 4.57
A1 2.29 3.04
D1
16.51
16.66
D2
14.99
16.00
D3 12.70 BSC
E1
16.51
16.66
E2
14.99
16.00
E3 12.70 BSC
e 1.27 BSC
D
17.40
17.67
E
17.40
17.65
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