IA63484 (InnovASIC)
Advanced CRT Controller

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IA63484
Advanced CRT Controller
Preliminary Data Sheet
FEATURES
innovASIC
High-speed graphics
- Drawing rate: 200 ns/pixel max (color drawing)
- Commands: 38 commands including 23 graphic drawing commands:
Dot, Line, Rectangle, Poly-line, Polygon, Circle, Ellipse, Paint, Copy, etc.
- Colors: 16 bits/word: 1,2,4,8,16 bits/pix el (5 types) monochrome to 64k colors max
- Pattern RAM: 32 bytes
- Converts logical X-Y coordinate to physical address
- Color operation and conditional drawing
- Drawing area control for hardware clipping and hitting
Large frame-memory space
- Maximum 2 Mbytes graphic memory and 128 kbytes character memory separate from
MPU memory.
- Maximum Resolution: 4096 x 4096 pixels (1 bit/pixel mode)
CRT display control
- Split Screens: three displays and one window
- Zoom: 1 to 16 times
- Scroll: vertical and horizontal
Interleaved access mode for flashless display and superimposition
External synchronization between ARTCs or between ACRTC and external device (TV system
or other controller.
DMA interface
Two programmable cursors
Three Scan modes
- Non-interlaced
- Interlace sync
- Interlace sync and video
Interrupt request to MPU
256 characters/line 32 raster/ line, 4096 rasters/screen
Maximum clock frequency: 20MHz
CMOS, single +5V power supply
The IA63484 is a "plug-and-play" drop-in replacement for the original Hitachi© HD63484. This
replacement IC has been developed using innovASIC’s MILESTM, or Managed IC Lifetime
Extension System, cloning technology. This technology produces replacement ICs far more complex
than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the
design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies
the clone against the original IC so that even the "undocumented features" are duplicated. This data
sheet documents all necessary engineering information about the IA63484 including functional and
I/O descriptions, electrical characteristics, and applicable timing.
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
68 Pin Package: PLCC PINOUT
Pin Arrangement:
Preliminary Data Sheet
dack_n
dtack_n(T)
irq(O,D)
hsync_n
vsync_n
Vcc
exsync_n
Vss
Vss
d0(T)
d1(T)
d2(T)
d3(T)
d4(T)
d5(T)
d6(T)
d7(T)
9
27
1 68
IA63484
O,D: Open Drain
T: Three State
60
chr
mrd
draw_n
as_n
mcyc
Vss
Vss
clk_2
Vcc
mad5(T)
mad6(T)
mad7(T)
mad8(T)
mad9(T)
mad10(T)
44
mad11(T)
mad12(T)
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
BLOCK DIAGRAM
Preliminary Data Sheet
Figure 1: System Block Diagram
Figure 2 illustrates the IA63484 system environment. The following paragraphs will further describe
the system block diagram and design in more detail.
MPU
(8/16b)
SYSTEM
MEMORY
DMAC
res_n
irq_n
d[15:0]
dtack_n
cs_n
ma[19:16]
as_n
mrd
L
rs
rw_n
dreq_n
dack_n
done_n
clk_2
Vss
Vcc
ACRTC
disp2_n
disp1_n
cud2_n
cud1_n
lpstb
exsync_n
vsync_n
hsync_n
mad[15:0]
FRAME
BUFFER
2MB, MAX
DOT SHIFTER
CRT
VIDEO
SIGNAL
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
Preliminary Data Sheet
I/O SIGNAL DESCRIPTION:
The diagram below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
I/O Characteristics:
Signal Name
res_n
I/O
I
d[15,0]
rw_n
cs_n
rs
dtack_n
I/O
I
I
I
O
irq_n
dreq_n
dack
done_n
clk_2
O
I
I/O
I
I/O
mad[15,0]
as_n
O
O
MA16/R 0-*
MA1 9/ R A3
RA4
chr
mcyc
mrd
draw_n
disp1, disp2
O
O
O
O
O
O
O
cud1, cud2
vsync_n
hsync_n
exsync_n
lpstb
O
I/O
I
Group
MPU
Interface
DMAC
Interface
CRT
Interface
Description
ACRTC reset:
Data bus (three state): are the bidirectional data bus to the host mpu or dmac. D 0 -D
are used in 8-bit data bus mode.
Read/write strobe: controls the direction of host/ACRTC transformers.
Chip Select: enables transfers between the host and the ACRTC.
Register Select: selects the ACRTC register to be accessed. It is usually connected to
the least significant bit of the host address bus.
Data transfer acknowledge (three state): output provides asynchronous bus cycle
timing. It is compatible with the HD68000 mpu dtack output.
Interrupt request (open drain): output generates interrupt service requests to the
host MPU.
DMA request: recieves DMA acknowledge timing from the host DMAC.
DMA acknoledge:
DMA done: terminates DMA transfer. It is compatible with the HD68450 DMAC
DONE signal.
ARTC clock: is the baasic operating clock, twice the frequency of the dot clock.
Multiplexed frame buffer address/data bus: are the multiplexed frame buffer
address/data bus.
Address strobe: output demultiplexes the address/data bus.
Higer-order address bits/character screen rastar address:MA16/R0- MA19/RA3 are
the upper bits of the graphics screen ddress multiplexed with th lower bits of the
character screen raster address.
Higer-order character screen rastar address bit: is the high bit of the character screen
raster address (up to 32 rasters.)
Graphic or character screen access: output indicates whether a graphic or character
screen is being accessed.
Frame buffer memory acess timing signal: is the frame buffer access timing output,
1/2 the frequency of clk_2.
Frame buffer memory read: output controls the frame buffer data bus direction.
Draw/refresh signal: output differentiates between drawing and CRT displayrefresh
cycles.
Display enable: programmable display enable outputs can enable, disable, and blanck
logical screens.
Coursor Display: outputs provides cursor timing programmed by ACRTC parameters
such as cursor definition, cursor mode, cursor address, etc.
CRT vertical sync pulse: outputs the crt vertical synchronization pulse.
CRT horizontal sync pulse: outputs the crt horizontal synchronization pulse.
External sync:allows synchronization between multiple ACRTSs and other videro
signal generators.
Lightpen strobe: is the lightpen input
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
Figure 2: IA63484 Block Diagram
res_n
Preliminary Data Sheet
dreq_n
dack_n
done_n
irq_n
DMA
Control
Unit
Interrupt
Control
Unit
Register
Address
Data
Drawing
Processor
20
16
draw_adrs[19:0]
draw_data[15:0]
draw_en
write
16
d[15:0]
cs_n
rs_n
rw_n
dtack_n
MPU
Interface
23 25
V cc V SS
disp_adrs[19:0]
Display
Processor
20
15
raster_adrs[4:0]
chr_int
ccud
lpstb
2
Timing
Processor 2
gcud[1:0]
hsync
vsync
exsync
disp[1:0]
m_cyc
as
clk2
16
4
CRT
Interface
2
2
draw_n
mrd
mad[15:0]
ma19_16_ra[3:0]
ra4
chr
lpstb
cud1_n, cud2_n
hsync_n
vsync_n
exsync_n
disp1_n, disp2_n
mcyc
as_n
clk_2
IA63484 System Description:
Some CRT controllers provide a single bus interface to the frame buffer that must be shared with the host
MPU. However, refreshing large frame buffers, and accessing the frame buffer for drawing operations can
quickly saturate the shared bus.
The IA63484 uses separate host MPU and frame buffer interfaces. This allows the IA63484 full access to the
frame buffer for display refresh and drawing operations and minimizes the use of the MPU system bus by the
IA63484. A related benefit is that a large frame buffer (2 MB for each IA63484) can be used, even if the host
MPU has a smaller address space or segment size restriction.
The IA63484 can use an external Direct Memory Access Controller (DMAC) to increase system throughput
when many commands, parameters and data must be transferred to the IA63484. Advanced DMAC features
such as the HD68450 “chaining” modes can be used to develop powerful graphics system architectures.
More cost-sensitive or less performance-sensitive applications might not require a DMAC. In these cases, the
interface to the IA63484 can be handled under MPU software control.
While both IA63484 bus interfaces (host MPU and frame buffer) are 16 bits wide, the IA63484 also offers an
8 bit MPU mode for easy connection to popular 8 bit busses.
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
FUNCTIONAL REQUIREMENTS:
Preliminary Data Sheet
Drawing Processor:
The Drawing Processor performs drawing operations on the frame buffer memory upon interpreting
commands and command parameters issued by the host bus (MPU or DMAC). The drawing
processor then executes IA63484 drawing algorithms and converts logical X-Y addresses to physical
frame buffer addresses.
The drawing processor uses three operation control units; the Drawing Algorithm Control unit, the
Drawing Address Generation unit and the Logical Operation unit.
The Drawing Algorithm Control Unit interprets graphic commands and parameters and executes the
appropriate micro-programmed drawing algorithm. This control unit calculates coordinates using
logical pixel X-Y addressing.
The Drawing Address Generation Unit converts logical X-Y addresses from the Drawing Algorithm
Control unit to a bit address in the frame buffer. The frame buffer is organized as sequential 16 bit
words. The bit address consists of 20 bits and bits 0-4 specifying the logical pixel bit address within
the physical frame buffer word.
Logical Operation Unit, using the address calculated in the drawing algorithm control and drawing
address generation units, performs logical operations between the existing read data in the frame
buffer and the drawing pattern in the pattern RAM, and rewrites the results into the frame buffer. A
detailed description of the Drawing Processor is contained in its module specification.
Display Processor:
The display processor manages frame buffer refresh addressing based on the user specified display
screen organization. It combines and displays as many as 4 independent screen segments (3
horizontal split screens and 1 window) using an internal high-speed address calculation unit. It
controls display refresh outputs in graphic (physical frame buffer address) or character (physical
refresh memory address and row address) modes.
Display Functions:
The IA63484 allows the frame buffer to be divided into four separate logical screens:
Upper
Base
Lower
Window
In the simplest case, only the base screen parameters must be defined. Other screens may be
selectively enabled, disabled, and blanked under software control.
The background screens (upper, base, and lower) split the screen into three horizontal partitions
whose positions are fully programmable. The window screen is unique, since the IA63484 usually
gives it higher priority than the background screens. A typical application might be to use the base
screen for the bulk of the user interaction, while using the upper screen for pull-down menus and the
lower screen for status line indicators. The exception is in the IA63484 superimpose mode, in which
the window has the same priority as the background screens. In this mode, the window and
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
Preliminary Data Sheet
background screens are superimposed on the display. Figure 3 is an example of the screen
combinations.
Figure 3: Screen Combination Examples
Screen Number
0
1
2
3
Screen Name
Upper Screen
Base Screen
Lower Screen
Window Screen
Upper
Base
Window
Screen Group
Background Screen
Base
Window
Lower
Upper
Base
Lower
Window
Upper
Base
Window
Lower
Display Control:
The IA63484 can have two types of external frame memory: 2 Mbyte frame buffer and 128 kbyte
refresh memory. The chr signal controls which memory is accessed.
Each screen has its own memory width, vertical display width, and character/graphic attribution set
by the control registers. Horizontal display control registers are set in units of memory cycles.
Vertical display control registers are set in units of rasters. Figure 4 illustrates the relation between the
frame memory and the display screens, while Figure 5 illustrates the timing.
Note that display width of registers marked with an (*) in Figure 4 is:
Display width = Register value + 1 memory cycle.
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Advanced CRT Controller

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Advanced CRT Controller
Figure 4: Frame Memory and Display Screens
Preliminary Data Sheet
Refresh Memory
(Character)
$0000
SA0
Frame Memory Image
MW0
File Name: MOS
$FFFF
MW2
SA2
Left :
Layout
Right :
Symbol
$00000
Frame Buffer
(Graphic)
SA1
MW1
MW3
SA3
$FFFFF
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File Name: MOS
Left :
Right :
Layout
Symbol
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Advanced CRT Controller

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Advanced CRT Controller
Figure 5: Display Screen Specification
hsync_n
HWS*
HSW HDS*
HC*
HWW*
HDW*
Preliminary Data Sheet
Display Screen Period
(Upper)
(Base)
(Window)
(Lower)
(Base)
Timing Processor:
The Timing Processor generates the CRT synchronization signals and signals used internally
by the IA63484. The details for this block are contained in the module specification for the
Display Processor.
CRT Interface:
The CRT Interface manages the communication between the frame buffer, the light pen and the
CRT. The frame buffer interface manages the frame buffer bus and selects display drawing or
refreshes address outputs. The light pen interface uses a 20-bit address register and a strobe input pin
(lpstb).
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Advanced CRT Controller

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Advanced CRT Controller
Preliminary Data Sheet
Frame Buffer Interface:
The IA63484 allows for two types of independent frame memories. The first type is up to a 2 Mbyte
frame buffer and the second is a 128 Kbytes refresh memory. The chr output pin can access either
the Graphic or Character screen.
The width of the frame memory is defined by setting-up the memory width register (mwr) and
independently, the horizontal display width is defined by the horizontal display register (hdr). This
allows for the frame buffer area to be bigger than the display area; reference Figure 6.
Figure 6: Frame Memory and Display Screen Area
Start Address
Memory Width
Display Screen Area
text
Vertical
Display
Width
Horizontal Display Width
The IA63484 has two ways to access the frame memory (or buffer); (1) Display Memory Access
(three types) and (2) Graphic Address Increment mode.
Display Memory Access Modes:
In Single Access Mode, a display or drawing cycle is defined as two cycles of clk_2. During the first
cycle, the frame buffer display or drawing address is output. During the second clk_2 cycle, the
frame buffer data is read (display cycles and/or drawing cycles) or written (drawing cycles).
Display and drawing cycles contend for access to the frame buffer. The IA63484 allows the priority
to be defined as display priority or drawing priority. If display has priority, drawing cycles are only
allowed to occur during the horizontal or vertical fly back periods (a ‘flash less’ display is obtained).
If drawing has priority, drawing may occur during display (display may flash).
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Advanced CRT Controller

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Advanced CRT Controller
Preliminary Data Sheet
In Interleaved Access Mode (dual access mode 0), display cycles and drawing cycles are interleaved.
A display or drawing cycle is defined as four cycles of clk_2.
During the first clk_2 cycle, the IA63484 outputs the frame buffer display address.
During the second clk_2 cycle, the display data is output from the frame buffer.
During the third clk_2, the IA63484 outputs the frame buffer drawing address.
During the fourth clk_2 cycle, the IA63484 reads or writes the drawing data.
In Superimposed Access Mode (dual access mode 1), two separate logical screens are accessed during
each display cycle. The display cycle is defined as four clk_2 cycles. If the third and fourth cycles are
not used for window display, they can be used for drawing; similar to the Interleaved Mode.
During the first clk_2 cycle, the IA63484 outputs the background screen frame buffer address.
During the second clk_2 cycle, the background screen displays data.
During the third clk_2 cycle, the IA63484 outputs the window screen frame buffer address or
the drawing frame buffer address.
During the fourth clk_2 cycle, the IA63484 reads (display or drawing) or writes (drawing) the
window screen display or drawing data.
Graphic Address Increment (GAI) Mode:
The IA63484 can be programmed to control the graphic display address in one of six ways, by
incrementing by 1, 2, 4, 8, and 16 words, 1 word every two display cycles, and no increment. Setting
GAI to increment by 2, 4, 8, or 16 words per display cycle achieves 2, 4, 8, or 16 times the video data
rate corresponding to GAI = 1. This allows the number of bits/logical pixel and logical pixel
resolution to be increased while meeting the clk_2 maximum frequency constraint.
When the frame buffer memory uses dynamic RAMs (DRAMs), the IA63484 automatically provides
DRAM refresh addressing.
During hsync_n low, the IA63484 outputs the values of an 8-bit DRAM refresh counter on the
multiplexed frame buffer address and data bus mad[15:0]. The counter is decremented on each
frame buffer access. The refresh address pin assignment (mad[15:0]) depends on the GAI mode.
The remaining mad and ma19_16_ra outputs not used for refresh addressing are cleared to a low
value.
Table 1: GAI and DRAM Refresh Addressing
Address Increment Mode
+1 (GAI = 000)
+2 (GAI = 001)
+4 (GAI = 010)
+8 (GAI = 011)
+16 (GAI = 100)
+0 (GAI = 101)
+1/2 (GAI = 11X)
Refresh Address Output Terminal
mad[7:0]
mad[8:1]
mad[9:2]
mad[10:3]
mad[11:4]
mad[7:0]
mad[7:0]
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Advanced CRT Controller

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Advanced CRT Controller
Preliminary Data Sheet
Address Space:
The IA63484 allows the host to issue commands in logical X-Y coordinates. The IA63484 then
converts the physical linear word addresses with bit field offsets in the frame buffer. Figure 7 shows
the relationship between the logical X-Y screen address and the frame buffer memory. The frame
buffer memory is organized as sequential 16 bit words. The host may specify 1, 2, 4, 8, or 16 physical
bits in the frame buffer. The system in the figure uses 4 bit logical pixels, allowing for 16 colors or
tones.
Figure 7: Logical/Physical Addressing
Physical Addressing
(Frame Buffer)
bit bit
0 15
1 pixel data
MW
Logical Addressing
SAD
Display Screen
Y
(x,y)
Origin
X
SAD
Y
(x,y)
X
MW
Up to 4 logical screens may be mapped onto the IA63484 physical address space. The four screens
are the upper, base, lower, and window screens. The host first specifies the following:
A logical screen starting address.
A logical screen physical memory width (memory words per raster).
A logical pixel physical memory width (bit per pixel).
A logical origin physical address.
Then the IA63484 converts the logical pixel X-Y addresses issued by the host MPU or the drawing
processor to physical frame buffer addresses. The device also performs bit extraction and masking
to map logical pixel operations to 16 bit word frame buffer addresses.
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Advanced CRT Controller

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Advanced CRT Controller
Preliminary Data Sheet
Memory Map:
The ACTRC has over 200 bytes of accessible registers organized as Hardware, Direct, and FIFO
Access. Figure 8 illustrates the programming memory map model.
The IA63484 registers are initialized by res_n as follows:
Drawing and display operations are stopped
Status register (SR) is initialized to $FF23
Command control register (CCR) is initialized to $8000.
Operation mode register bits MS and STR are reset to 0.
All other registers are unaffected by res_n.
The FIFO Entry (FE) pointer is cleared, and the written command/parameter and the read
data are lost.
The DRAM refresh address is placed on the mad lines determined by graphic address
increment (GAI). Refresh continues to function until the start bit (STR) is set to 1. hsync_n
is also held low during the period from res_n until str is set by the MPU.
For directly accessible registers, the register address is shown as ‘rXX’, and FIFO accessible registers
are shown as ‘PrXX’, where XX is interpreted as an 8 bit hexadecimal value. Hexadecimal numbers
are denoted by a leading ‘$’.
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Advanced CRT Controller
Figure 8: Programming Model
Address Register
Status Register
FIFO Entry
Command Control Register
Operation Mode Register
Display Control Register
Raster Counter
Horizontal Sync
Horizontal Display
Vertical Sync
Vertical Display
Split Screen Width
Blink Control
Horizontal Window Display
Vertical Window Display
Graphic Cursor
Split Screen 0
(Upper Screen)
Split Screen 1
(Base Screen)
Split Screen 2
(Lower Screen)
Split Screen 3
(Window Screen)
Block Cursor
Cursor Definition
Zoon Factor
Light Pen Address
Pattern
RAM
Drawing
Parameter
Register
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Preliminary Data Sheet
Write FIFO
Read FIFO
Command Register
16 x 16
Color 0
Color Comparison
Edge Color
Mask
Pattern RAM Control
Area Definition
Read/Write Pointer
Drawing Pointer
Current Pointer
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IA63484
Advanced CRT Controller
Preliminary Data Sheet
Hardware Access:
The IA63484 is connected to the host MPU as a standard memory-mapped peripheral that occupies
two word locations of the host’s address space. When rs=0, read operations access the status
register, and write operations access the address register.
The status register summarizes the IA63484 State; it monitors the overall state of the IA63484 for
the host MPU. When the MPU wants to access a direct access register, it puts the register’s address
into the IA63484 address register.
Direct Access:
The MPU accesses the direct access registers by loading the register address into the address register.
Then, when the MPU accesses the IA63484 with rs=1, the chosen register is accessed. The FIFO
entry register enables the MPU to access FIFO access registers using the IA63484 read and write
FIFOs.
The command control register controls overall IA63484 operations, such as aborting or pausing
commands, defining DMA protocols, and enabling/disabling interrupt sources.
The operation mode register defines basic parameters of IA63484 operation, such as frame buffer
access mode, display or drawing priority, cursor and display timing skew factors, and raster scan
mode.
The display control register independently enables and disables the four IA63484 logical address
screens (upper, base, lower, and window). It also contains 8 user-defined video attribute bits.
The timing control RAM registers define IA63484 timing, including timing specifications for CRT
control signals (hsync_n, vsync_n, etc.), logical display screen size and display period, and blink
period.
The display control RAM contains registers that define logical screen display parameters, such as start
address, raster address, and memory width. It also includes the cursor definition, zoom factor, and
lightpen registers.
FIFO Access:
For high-performance drawing, key drawing processor registers are coupled to the host MPU via the
IA63484’s 16-byte read and write FIFOs. Figure and Figure illustrate the hardware and direct access
register information.
IA63484 commands are sent from the MPU via the write FIFO to the command register. As the
IA63484 completes a command, the next command is automatically fetched from the write FIFO
and put into the command register.
The pattern RAM defines drawing and painting patterns. It is accessed with the IA63484’s Read
Pattern RAM (RPTN) and Write Pattern RAM (WPTN) register access commands.
The drawing parameter registers define detailed parameters of the drawing process, such as color
data, area control (hitting/clipping), and pattern RAM pointers. The drawing parameter registers are
accessed using the IA63484’s Read Parameter Register (RPR) and Write Parameter Register (WPR)
commands. Figure illustrates the drawing parameter registers.
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Advanced CRT Controller
Preliminary Data Sheet
Figure 9: Hardware Access and Direct Access Registers
Reg Name
Reg #
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address
Reg(AR)
Status
Reg(SR)
FIFO
Entry(FE)
Command
Control
(CCR)
AR $0
Address
ST $0 CER ARD CED LPD RFF RFR WFR WFE
$00 FIFO Entry
$02
ABT PSE DDM CDM DRC
GBM
CRE ARE CEE LPE RFE RRE WRE WEE
Operation
Mode (OMR)
$04
MS STR ACP WSS
CSK
DSK RAM
GAI
ACM
RSM
Display
Control
(DCR)
$06
DSP SE1
SE0
SE2 SE3
ATR
Undefined
$08-$7E, $9E-
$BE, $F0-$FE
$0
cs_n, rs,
rw_n
0, 0, 0
0, 0, 0
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
Raster
Count(RCR)
$80
$0
RC 0, 1, 1
Horizontal
Sync(HSR)
$82
HC
$0
HSW
0, 1, 0/1
Horizontal
Display
(HDR)
Vertical
Sync(VSR)
Vertical
Display
(VDR)
Split Screen
Width(SSW)
Blink Control
(BCR)
Horz.
Window
Disp(HWR)
Vert. Window
Disp(VDR)
Graphic
Cursor
(GCR)
$84
$86
$88
$8A
$8C
$8E
$90
$92
$94
$96
$98
$9A
$9C
HDS
$0
$0
$0
$0
BON1
VDS
BOFF1
HWS
$0
$0
CXE
$0
$0
HDW
VC
$0
SP1
SP0
SP2
BON2
VSW
BOFF2
HWW
VWS
VWW
CSY
CYE
CXS
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
Preliminary Data Sheet
Figure 10: Hardware Access and Direct Access Registers (cont.)
Reg Name
Reg #
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs_n, rs, rw_n
Raster
Addr 0
(RAR0)
Memry
Wdth 0
(MWR0)
Strt Addr 0
(SAR0)
Raster
Addr 1
(RAR1)
Mem
Width 1
(MWR1)
Strt Addr 1
(SAR1)
Raster
Addr 2
(RAR2)
Memry
Wdth 2
(MWR2)
Strt Addr 2
(SAR2)
Raster
Addr 3
(RAR3)
Memry
Wdth 3
(MWR3)
Strt Addr 3
(SAR3)
$C0(Upper
Scrn)
$C2(Upper
Scrn)
$C4(Upper
Scrn)
$C6(Upper
Scrn)
$C8(Base
Scrn)
$CA(Base
Scrn)
$CC(Base
Scrn)
$CE(Base
Scrn)
$D0(Lower
Scrn)
$D2(Lower
Scrn)
$D4(Lower
Scrn)
$DR6S(ecLgrno#)wer
$D8(Wndw
Scrn)
$DA(Wndw
Scrn)
$DC(Wndw
Scrn)
$DRESec(Wgrn#n) dw
$0
CH
R
$0
$0
$0
CH
R
$0
$0
$0
CH
R
$0
$0
$0
CH
R
$0
$0
LRA0
$0
SDA0
LRA1
MW0
$0
SA0L
$0
SDA1
LRA2
MW1
$0
SA1L
$0
SDA2
LRA3
MW2
$0
SA2L
$0
SDA3
MW3
$0
SA3L
FRA0
SA0H/SRA0
FRA1
SA1H/SRA1
FRA2
SA2H/SRA2
FRA3
SA3H/SRA3
0, 0, 0
0, 0, 0
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
cs_0n,,1r,s0,/rw1 _n
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
cs_0n,,1r,s0,/rw1 _n
Blk Cursor
1 (BCUR1)
$E0
$E2
BCW1
BCSR1
$0
BCA1
BCER1
0, 1, 0/1
0, 1, 0/1
Blk Cursor
2 (BCUR2)
$E4
$E5
BCW2
BCSR2
$0
BCA2
BCER2
0, 1, 0/1
0, 1, 0/1
Cursor Def.
(CDR)
Zoom
Factor
(ZFR)
Lightpen
Addr
(LPAR)
$E8
$EA
$EC
$EE
CM CON1
HZF
$0
COFF1
$0
CON2
COFF2
VZF
CH
R
LPAL
$0
$0
FRA3
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
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IA63484
Advanced CRT Controller
Figure 11: Drawing Parameter Registers
Preliminary Data Sheet
Reg Name
Reg # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Color 0 (CL0)
Pr00
CL0
Color 1 (CL1)
Pr01
Color Cmpr
(CCMP)
Pr02
Edge Color
(EDG)
Mask
(MASK)
Pattern RAM
Control
(PRC)
Pr03
Pr04
Pr05
Pr06
Pr07
PPY
PSY
PEY
Area
Def(ADR)->
Set 2's Comp.
for neg.
values of X
and Y axis.
Pr08
Pr09
Pr0A
PRerg0C#
15
Read Write
Pntr (RWP)
Undefined
Drawing Pntr
(DP)
Pr0C
Pr0D
Pr0E-Pr0F,
Pr14-Pr15
Pr10
Pr11
Current
Pntr(CP)->
Set 2's Comp.
for neg.
values
Pr12
Pr13
DN
DN
CL1
CCMP
EDG
MASK
PZCY
$0
PZY
$0
RWPL
$0
DPAL
XMIN
YMIN
XMAX
YMAX
PPX
PSX
PEX
$0
X
PZCX
$0
PZX
RWPH
$0
DPAH
DPD
Y
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
cs_nR, r/s,Wrw_n
R/W
R/W
R/W
R
R
R
R
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
Preliminary Data Sheet
COMMAND TRANSFER MODES:
Program Transfer and DMA Transfer are the two modes used to transfer commands and associated
parameters issued by the MPU to the IA63484.
Program Transfer:
Program transfer occurs when the MPU specifies the FIFO entry address and then writes operation
code/parameters to the write FIFO under program control. The MPU writes are normally
synchronized with IA63484 FIFO status by software polling or interrupts.
Software Polling (WFR, WFE interrupts disabled):
MPU program checks the SR for WFR=1, and then writes 1-word operation code/parameters, or
MPU program checks the SR for write WFE=1, and the writes 1- to 8-word operation
code/parameters.
Interrupt Driven (WFR, WFE interrupts enabled):
MPU WFR interrupt service routine writes 1-word operation code/parameters, or
MPU WFE interrupt service routine writes 1- to 8-word operation code/parameters.
DMA Transfer:
Commands and parameters can be transferred from MPU system memory by an external DMAC.
The MPU initiates and terminates command DMA transfer mode under software control.
Command DMA can also be terminated by assertion of the done_n input.
Using command DMA transfer, the IA63484 will issue cycle stealing DMA requests to the DMAC
when the write FIFO is empty. The DMA data is automatically sent from system memory to the
IA63484 write FIFO regardless of the contents of the address register.
Command Function:
The IA63484 commands are divided into three groups, register access commands, data transfer
commands, and graphic drawing commands.
Register access commands:
Access to the drawing processor drawing parameter registers and the pattern RAM is through the
read/write FIFOs using register access commands. When writing register access commands to an
initially empty write FIFO, the MPU does not have to synchronize to write FIFO status. The
IA63484 can fetch and execute these commands faster than the MPU can issue them.
Data transfer commands:
Data is moved between the host system memory and the frame buffer, or within the frame buffer
using the data transfer commands. Before issuing these commands, a physical 20-bit frame buffer
address must be specified in the RWP (read/write pointer) drawing parameter register.
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
Preliminary Data Sheet
Graphic Drawing Commands:
The graphic drawing commands cause the IA63484 to draw. Graphic drawing is performed by
modifying the contents of the frame buffer based on micro coded drawing algorithms in the IA63484
drawing processor. Parameters for these commands are specified using logical X-Y addressing. The
display processor performs the complex task of translating a logical pixel address to a linear frame
buffer word address, and further, selecting the proper sub field of the word.
Many instructions allow specification in either absolute or relative X-Y coordinates. In both cases,
two’s compliment numbers represent both positive and negative values.
Table 2 and Table 3 tabulate the IA63484 drawing commands and Op-Codes available.
Table 2: IA63484 Command Table
Type
Register Access Command
Data Transfer Command
Graphic Drawing Command
Mnemonic
ORG
WPR
RPR
WPTN
RPTN
DRD
DWT
DMOD
RD
WT
MOD
CLR
SCLR
CPY
SCPY
AMOVE
RMOVE
ALINE
RLINE
ARCT
RRCT
APLL
RPLL
APLG
RPLG
CRCL
ELPS
AARC
RARC
AEARC
REARC
AFRCT
RFRCT
PAINT
DOT
PTN
AGCPY
RGCPY
Command Name
Origin
Write Parameter Reg
Read Parameter Reg
Write Pattern RAM
Read Pattern RAM
DMA Read
DMA Write
DMA Modify
Read
Write
Modify
Clear
Selective Clear
Copy
Selective Copy
Absolute Move
Relative Move
Absolute Line
Relative Line
Absolute Rectangle
Relative Rectangle
Absolute Polyline
Relative Polyline
Absolute Polygon
Relative Polygon
Circle
Ellipse
Absolute Arc
Relative Arc
Absolute Ellipse Arc
Relative Ellipse Arc
Absolute Filled Rectangle
Relative Filled Rectangle
Paint
Dot
Pattern
Absolute Graphic Copy
Relative Graphic Copy
# (words)
CLK_2 Cycles
38
26
16
n+2 4n+8
2 4n+10
3 (4x+8)y+12(x*y/8 )+(62~68)
3 (4x+8)y+16(x*y/8 )+34
3 (4x+8)y+16(x*y/8 )+34
1 12
28
28
4 (2x+8)y+12
4 (4x+8)y+12
5 (6x+8)y+12
5 (6x+8)y+12
3 56
3 56
3 P*L+18
3 P*L+18
3 2P(A+B)+54
3 2P(A+B)+54
2n+2
2n+2
2n+2
2n+2
2
( P * L + 16 ) + 8
( P * L + 16 ) + 8
( P * L + 16 ) + P * Lo + 20
( P * L + 16 ) + P * Lo + 20
8d+66
4 10d+90
5 8d+18
5 8d+18
7 10d+96
7 10d+96
3 (P*A+8)B+18
3 (P*A+8)B+18
1 (18A+102)B-58(Applies to rectagular figures, varies for other shapes )
18
2 (P*A+10)B+20
5 ((P+2)A+10)B+70
5 ((P+2)A+10)B+70
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IA63484
Advanced CRT Controller
Table 3: Opcode Map
Preliminary Data Sheet
Type
Register Access Command
Data Transfer Command
Graphic Drawing Command
Mnemonic
ORG
WPR
RPR
WPTN
RPTN
DRD
DWT
DMOD
RD
WT
MOD
CLR
SCLR
CPY
SCPY
AMOVE
RMOVE
ALINE
RLINE
ARCT
RRCT
APLL
RPLL
APLG
RPLG
CRCL
ELPS
AARC
RARC
AEARC
REARC
AFRCT
RFRCT
PAINT
DOT
PTN
AGCPY
RGCPY
Operation Code
0000010000000000
0 0 0 0 1 0 0 0 0 0 0 RN
0 0 0 0 1 1 0 0 0 0 0 RN
0 0 0 1 1 0 0 0 0 0 0 0 PRA
0 0 0 1 1 1 0 0 0 0 0 0 PRA
0010010000000000
0010100000000000
0 0 1 0 1 1 0 0 0 0 0 0 0 0 MM
0100010000000000
0100100000000000
0 1 0 0 1 1 0 0 0 0 0 0 0 0 MM
0101100000000000
0 1 0 1 1 1 0 0 0 0 0 0 0 0 MM
00 1 1 0 S DSD 0 0 0 0 0 0 0 0
01 1 1 1 S DSD 0 0 0 0 0 0 MM
1000000000000000
1000010000000000
1 0 0 0 1 0 0 0 AREA COL OPM
1 0 0 0 1 1 0 0 AREA COL OPM
1 0 0 1 0 0 0 0 AREA COL OPM
1 0 0 1 0 1 0 0 AREA COL OPM
1 0 0 1 1 0 0 0 AREA COL OPM
1 0 0 1 1 1 0 0 AREA COL OPM
1 0 1 0 0 0 0 0 AREA COL OPM
1 0 1 0 0 1 0 0 AREA COL OPM
1 0 1 0 1 0 0 C AREA COL OPM
1 0 1 0 1 1 0 C AREA COL OPM
1 0 1 1 0 0 0 C AREA COL OPM
1 0 1 1 0 1 0 C AREA COL OPM
1 0 1 1 1 0 0 C AREA COL OPM
1 0 1 1 1 1 0 C AREA COL OPM
1 1 0 0 0 0 0 0 AREA COL OPM
1 1 0 0 0 1 0 0 AREA COL OPM
1 1 0 0 1 0 0 E AREA 0 0 000
1 1 0 0 1 1 0 0 AREA COL OPM
1 1 0 1 SL SD AREA COL OPM
1 1 1 0 S DSD AREA 0 0 OPM
1 1 1 1 S DSD AREA 0 0 OPM
Parameter
DPH DPL
D
n D1,...,Dn
n
AX AY
AX AY
AX AY
D
D
D AX AY
D AX AY
SAH SAL AX
AY
SAH SAL AX
AY
XY
dX dY
XY
dX dY
XY
dX dY
n X1,Y1,...XN,YN
n dX1,dY1,...dXN,dYN
n X1,Y1,...XN,YN
n dX1,dY1,...dXN,dYN
r
a b DX
Xc Yc Xe Ye
dXc dYc dXe dYe
a b Xc Yc
a b dXc dYc
XY
dX dY
Xe
dXe
Ye
dYe
SZ
Xs Ys DX DY
dXs dYs dDX dDY
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IA63484
Advanced CRT Controller
Preliminary Data Sheet
AC/DC PARAMETERS:
Absolute maximum ratings:
Operating Temperature…..…….......................………………...…..0°C to +70°C
Storage Temperature.......................................…....……....……...…- 65°C to 150°C
VCC Supply Voltage…………......................................………..…... - 0.3V to +4.6V
Input Voltage Range…...............................................…..................... - 0.3V to +4.6V
Allowable Input Current……………………………………….…………. TBD
Total Allowable Input Current……………………………………………..TBD
Recommended Operating Conditions (@ 20 MHz):
Power Supply VCC………………………………………………..4.75V to 5.25V
Input Low Voltage VIL……………………………………………..…0V to 0.8V
Input High Voltage VIH…………………………………………...….2.0V to VCC
Operating Temperature Range…………………………………….....0°C to 70°C
DC Characteristics:
Item
Input High Level
Voltage
Input Low Level
Voltage
Input Leak
Current
Hi-Z Input
Current
Output High
Level Voltage
Output Low
Level Voltage
All Inputs
All Inputs
rw_n, cs_n, rs, res_n,
dack_n, clk_2, lpstb
d[15:0], mad[15:0],
exsync_n
d[15:0], mad[15:0],
exsync_n, cud1_n,
cud2_n, dreq_n,
dtack_n, hsync_n,
vsync_n, mrd,
draw_n, as_n,
disp1_n, disp2_n, chr,
mcyc, ra4, ma16/ra0,
ma19/ra3
d[15:0], mad[15:0],
exsync_n, cud1_n,
cud2_n, dreq_n,
dtack_n, hsync_n,
vsync_n, mrd,
draw_n, as_n,
disp1_n, disp2_n, chr,
mcyc, ra4, ma16/ra0,
ma19/ra3
Symbol
VIH
VIL
Iin
ITSI
VOH
VOL
Output Leak
Current(Hi-Z)
irq_n, done_n
irq_n, done_n
VOL
ILOD
Min
2.2
-
-10
-10
3.5
Max Unit
-V
0.8 V
10 uA
10 uA
V
0.4 V
0.4
TBD
V
uA
Test Conditions
20 MHz
20 MHz
VSS to VCC
VSS to VCC
IOH = 2mA,
4mA,
8mA,
12mA,
16mA
IOL = 2mA,
4mA,
8mA,
12mA,
16mA
VOH = VCC
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
Item
Symbol Min
Input Capacitance d[15:0], mad[15:0],
CIN
exsync_n, rw_n, cs_n,
rs, res_n, dack_n,
clk_2, lpstb
Output
Capacitance
irq_n, done_n
COUT
Current-
Consumption
ICC
(VCC = 5.0V+5%, VSS = 0V, Ta = 0 to 70oC, unless otherwise noted.)
Preliminary Data Sheet
Max Unit
4 pF
Test Conditions
TBD
4
TBD
pF
mA
TBD
20 MHz
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
AC Characteristics:
Clock Timing:
Item
Operation Frequency of clk_2
Clock Cycle Time
Clock High Level Pulse Width
Clock Low Level Pulse Width
Clock Rise Time
Clock Fall Time
MPU Read / Write Cycle Timing:
Item
rw_n Setup Time
rw_n Hold Time
rs Setup Time
rs Hold Time
cs_n Setup Time
cs_n High Level Width
Read Wait Time
Read Data Access Time
Read Data Hold Time
Read Data Turn Off Time
dtack_n Delay Time (Z to L)
dtack_n Delay Time (D to L)
dtack_n Release Time (L to H)
dtack_n Turn Off Time (H to Z)
Data Bus 3-State Recovery Time 1
Write Wait Time
Write Data Setup Time
Write Data Hold Time
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Symbol
f
tCYC
t PWCH
tPWCL
tc r
tc f
Symbol
tRWS
tRWH
tRSS
tRSH
tCSS
tWCSH
tRWAI
tRDAC
tRDH
t RDZ
t DTKZL
tDTKDL
tDTKLH
tDTKZ
t DBRT1
tWWAI
tWDS
tWDH
ENG 21101041201
Page 24 of 32
Preliminary Data Sheet
Min Max
1 20
50 1000
20 500
20 500
5
5
Unit
MHz
ns
ns
ns
ns
ns
Min Max
25
0
25
0
20
30
Unit
ns
ns
ns
ns
ns
ns
0
40
5
30
35
0
40
50
0
0
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Advanced CRT Controller

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IA63484
Advanced CRT Controller
Preliminary Data Sheet
AC Characteristics (continued):
DMA Read / Write Cycle Timing:
Item
dreq_n Delay Time 1
dreq_n Delay Time 2
DMA r / w_n Setup Time
DMA r / w_n Hold Time
dack_n Setup Time
dack_n Hold Time
DMA Read Wait Time
DMA Read Data Access Time
DMA Read Data Hold Time
DMA Read Data Turn Off Time
DMA dtack_n Delay Time (Z to L)
DMA dtack_n Delay Time (D to L)
DMA dtack_n Release Time (L to H)
DMA dtack_n Turn Off Time (H to Z)
done_n Output Delay Time
done_n Output Turn Off Time
Data Bus 3-State Recovery Time 2
done_n Input Pulse Width
DMA Write Wait Time
DMA Write Data Setup Time
DMA Write Data Hold Time
Symbol
tDRQD1
tDRQD2
t DMRWS
tDMRWH
tDAKS
t WDAKH
t DRW
tDRDAC
tDRDH
tDRDZ
tDDTZL
tDDTDL
tDDTLH
t DDTHZ
tDND
tDNL2
tDBRT2
tDNPW
tDWW
tDWDS
tDWDH
Min Max
55
35
25
0
20
30
0
40
5
30
35
0
40
50
35
40
0
2
0
20
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCYC
ns
ns
ns
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IA63484
Advanced CRT Controller
AC Characteristics (continued):
Frame Memory Read / Write Cycle Timing:
Preliminary Data Sheet
Item
Symbol
Min Max
as_n "Low" Level Pulse Width
t PWASL
10
Memory Address Hold Time 2
tMAH2
5
as_n Delay Time 1
t ASD1
25
as_n Delay Time 2
t ASD2
5 20
Memory Address Delay Time
tMAD
5 25
Memory Address Hold Time 1
tMAH1
10
Memory Address Turn Off Time (A to Z)
tMAAZ
20
Memory Read Data Setup Time
tMRDS
15
Memory Read Data Hold Time
tMRDH
0
ma_ra Delay Time
tMARAD
30
ma_ra Delay Time
tMARAH
5
MCYC Delay Time
tMCYCD
5 20
mrd Delay Time
tMRDD
25
mrd Hold Time
tMRH
5
draw_n Delay Time
tDRWD
25
draw_n Hold Time
tDRWH
5
Memory Write Data Delay Time
tMWDD
25
Memory Write Data Hold Time
tMWDH
5
Memory Address Setup Time 1
tMAS1
5
Memory Address Setup Time 2
tMAS2
5
NOTE: t MAD is independent of clk_2 operation frequency (f) and timing of tASD2 and t MAS1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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ENG 21101041201
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IA63484 (InnovASIC)
Advanced CRT Controller

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IA63484
Advanced CRT Controller
AC Characteristics (continued):
Display Control Signal Output Timing:
Item
hsync_n Delay Time
vsync_n Delay Time
disp1_n, disp2_n Delay Time
cud1_n, cud2_n Delay Time
exsync_n Output Delay Time
chr delay time
exsync_n Input Timing:
Symbol
tHSD
tVSD
tDSPD
tCUDD
tEXD
tCHD
Item
exsync_n Input Pulse Width
exsync_n Input Setup Time
exsync_n Input Hold Time
lpstb Input Timing:
Symbol
tEXSW
t EXS
tEXH
Item
lpstb Uncertain Time 1
lpstb Uncertain Time 2
lpstb Input Hold Time
lpstb Input Inhibit Time
res_n and dack_n Input Timing:
Symbol
t LPD1
t LPD2
tLPH
tLPI
Item
dack_n Setup Time for res_n
dack_n Holt Time for res_n
res_n Input Pulse Width
Copyright © 2003
innov ASIC
The End of Obsolescence
Symbol
tDAKSR
tDAKHR
tRES
ENG 21101041201
Page 27 of 32
Preliminary Data Sheet
Min Max
25
25
25
25
10 25
25
Unit
ns
ns
ns
ns
ns
ns
Min Max
3
15
5
Unit
tCYC
ns
ns
Min Max
25
5
5
4
Unit
ns
ns
ns
tCYC
Unit
Min Max
50
ns
0 ns
10 tCYC
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IA63484 (InnovASIC)
Advanced CRT Controller

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IA63484
Advanced CRT Controller
Figure 12: DMA Write Cycle Timing
clk_2
dreq_n
rw_n
tDRQD1
dack_n
d[15:0]
dtack_n_ready_n
done_n(output)
done_n(input)
Preliminary Data Sheet
tDRQD2
tDAKS
tDMRWS
tDMRWH
tDWDS tDWDH
tDWW
tDDTZL
tDDTLH
tDNLZ1
tDND
tDDTHZ
tDNPW
Figure 13: Display Cycle Timing
clk_2
as_n
mad[15:0]
ma19_16_ra[3:0 ]
mcyc
mrd
draw_n
refresh_cycle
attribute_cntl_info_out_cycle
tASD2
tASD1
tPWASL
tMAA2
tMAD
tMAH1
refresh_adrs
tMARAD
tMCYCD
tMAS1
refresh_adrs
tATRD1
tATRH1
ATR
tATRH2
tATRD2
ATR
tMRDD
tMRH
tDRWD
tDRWH
Copyright © 2003
innov ASIC
The End of Obsolescence
ENG 21101041201
Page 28 of 32
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Customer Support:
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IA63484 (InnovASIC)
Advanced CRT Controller

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IA63484
Advanced CRT Controller
Preliminary Data Sheet
Figure 14: Frame Memory Refresh & Video Attributes Output Cycle Timing
clk_2
as_n
mad[15:0]
ma19_16_ra[3:0]
mcyc
mrd
draw_n
hsync_n
Refresh_cycle
Attribute_cntl_info_out_cycle
tASD2
tASD1
tPWASL
tMAA2 tMAS1
tMAD
tMAH1
refresh _adrs
refresh_adrs
tMARAD
tMCYCD
tATRH1
tATRD1
ATR
tATRD2
ATR
tATRH2
tMRDD
tMRH
tDRWD
tDRWH
tHSD
tHSD
Figure 15: Display Control Signal Output Timing
clk_2
mcyc
tMCYD
hsync_n_vsync_n
tHSD
disp1_n_disp2_n
tDSPD
cud1_n_cud2_n
tCUDD
exsync_n
tEXD
tCHD
chr
tVSD
Copyright © 2003
innov ASIC
The End of Obsolescence
ENG 21101041201
Page 29 of 32
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IA63484 (InnovASIC)
Advanced CRT Controller

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IA63484
Advanced CRT Controller
Figure 16: Input Timing exsync_n
clk_2
exsync_n
hsync_n
mcyc(phase_shifted)
mcyc(phase_not_shifted)
tEXSW
tEXH
tEXS
Preliminary Data Sheet
tHSD
Figure 17: Input Timing (Single Access Mode) lpstb
clk_2
mcyc
mad[15:0]
lpstb
Display_Cycle
M
tLPD2
tLPD1
M+1
tLPH
M+2
Figure 18: Input Timing (Dual Access Mode) lpstb
clk_2
mcyc
mad[15:0]
lpstb
lpstb
Display_Cycle
M
tLPD2
tLPD1
tLPH
tLPD2
M+1
tLP1
tLPD1
tLPH
M+2
tLP1
Copyright © 2003
innov ASIC
The End of Obsolescence
ENG 21101041201
Page 30 of 32
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