TDA9151B (NXP)
Programmable deflection controller

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INTEGRATED CIRCUITS
DATA SHEET
TDA9151B
Programmable deflection controller
Preliminary specification
Supersedes data of June 1993
File under Integrated Circuits, IC02
July 1994
Philips Semiconductors


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
FEATURES
General
6.75, 13.5 and 27 MHz clock frequency
Few external components
Synchronous logic
I2C-bus controlled
Easy interfacing
Low power
ESD protection
Flash detection with restart
Two-level sandcastle pulse.
Vertical deflection
16-bit precision vertical scan
Self adaptive or programmable fixed slope mode
DC coupled deflection to prevent picture bounce
Programmable fixed compression to 75%
Programmable vertical expansion in the fixed slope
mode
S-correction can be preset
S-correction setting independent of the field frequency
Differential output for high DC stability
Current source outputs for high EMC immunity
Programmable de-interlace phase.
East-West correction
DC coupled EW correction to prevent picture bounce
2nd and 4th order geometry correction can be preset
Trapezium correction
Geometry correction settings are independent of field
frequency
Self adaptive Bult generator prevents ringing of the
horizontal deflection
Current source output for high EMC immunity.
Horizontal deflection
Phase 2 loop with low jitter
Internal loop filter
Dual slicer horizontal flyback input
Soft start by I2C-bus
Over voltage protection/detection with selection and
status bit.
EHT correction
Input selection between aquadag or EHT bleeder
Internal filter.
GENERAL DESCRIPTION
The TDA9151B is a programmable deflection controller
contained in a 20-pin DIP package and constructed using
BIMOS technology. This high performance
synchronization and DC deflection processor has been
especially designed for use in both digital and analog
based TV receivers and monitors, and serves horizontal
and vertical deflection functions for all TV standards. The
TDA9151B uses a line-locked clock at 6.75, 13.5 or
27 MHz, depending on the line frequency and application,
and requires only a few external components. The device
can be programmed in a self-adaptive mode or in a
programmable fixed slope mode. Selection of these
modes and a large number of other functions is fully
programmable via the I2C-bus.
ORDERING INFORMATION
TYPE NUMBER
TDA9151B
PINS
20
PIN POSITION
DIP
PACKAGE
MATERIAL
plastic
CODE
SOT146-1
July 1994
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TDA9151B (NXP)
Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
VCC
ICC
Ptot
Tamb
supply voltage
supply current
total power dissipation
operating ambient temperature
fclk = 6.75 MHz
7.2
25
Inputs
V14 line-locked clock (LLC) logic level
V13 horizontal sync (HA) logic level
V12 vertical sync (VA) logic level
V5 line-locked clock select (LLCS) note 1
logic level
V18 serial clock (SCL) logic level
V17 serial data input (SDA) logic level
V1 horizontal flyback (HFB) phase FBL = logic 0
slicing level
FBL = logic 1
V1 horizontal flyback (HFB) blanking
slicing level
V3 over voltage protection (PROT)
level
V9 EHT flash detection level
Outputs
V20 horizontal output (HOUT) voltage I20 = 10 mA
(open drain)
I11I10(M)
V10,11
I6(M)
vertical differential (VOUTA, B)
output current (peak value)
vertical output voltage
EW (EWOUT) total output current
(peak value)
vertical amplitude = 100%;
I8 = 120 µA; note 2
I8 = 120 µA
440
0
V6 EW (EWOUT) output voltage
1.0
SANDCASTLE OUTPUT LEVELS (DSC)
V2 base voltage level
V2 horizontal and vertical blanking
voltage level
V2 video clamping voltage level
HORIZONTAL OFF-CENTRE SHIFT (OFCS)
V19 output voltage
I19 = 2 mA
0
Notes
1. Hard wired to ground or VCC is highly recommended.
2. DAC values: vertical amplitude = 31; EHT = 0; SHIFT = 3; SCOR = 0.
TYP.
8.0
27
220
MAX.
8.8
+70
TTL
TTL
TTL
CMOS 5 V
CMOS 5 V
CMOS 5 V
3.9
1.3
100
3.9
1.5
0.5
475 510
3.9
930
5.5
0.5
2.5
4.5
VCC
UNIT
V
mA
mW
°C
V
V
mV
V
V
V
µA
V
µA
V
V
V
V
V
July 1994
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Programmable deflection controller

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Programmable deflection controller
BLOCK DIAGRAM
Preliminary specification
TDA9151B
Fig.1 Block diagram.
July 1994
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Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
PINNING
SYMBOL PIN
DESCRIPTION
HFB
1 horizontal flyback input
DSC
2 display sandcastle input/output
PROT
3 over voltage protection input
AGND
4 analog ground
LLCS
5 line-locked clock selection input
EWOUT 6 east-west geometry output
EHT
7 EHT compensation
RCONV
FLASH
8 external resistive conversion
9 flash detection input
VOUTB
VOUTA
VA
HA
LLC
10 vertical output B
11 vertical output A
12 vertical information input
13 horizontal information input
14 line-locked clock input
DGND
15 digital ground
VCC
SDA
16 supply input (+8 V)
17 serial data input/output
SCL 18 serial clock input
OFCS
19 off-centre shift output
HOUT
20 horizontal output
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Input signals (pins 12, 13, 14, 17 and 18)
The TDA9151B requires three signals for minimum
operation (apart from the supply). These signals are the
line-locked clock (LLC) and the two I2C-bus signals (SDA
and SCL). Without the LLC the device will not operate
because the internal synchronous logic uses the LLC as
the system clock.
I2C-bus transmissions are required to enable the device to
perform its required tasks. Once started the IC will use the
HA and/or VA inputs for synchronization. If the LLC is not
present the outputs will be switched off and all operations
discarded (if the LLC is not present the line drive will be
inhibited within 2 µs, the EW output current will drop to
zero and the vertical output current will drop to 20% of the
adjusted value within 100 µs). The SDA and SCL inputs
meet the I2C-bus specification, the other three inputs are
TTL compatible.
The LLC frequency can be divided-by-two internally by
connecting LLCS (pin 5) to ground thereby enabling the
prescaler.
The LLC timing is given in the Chapter “Characteristics”.
July 1994
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Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
I2C-bus commands
Slave address: 8C HEX = 1000110X BIN
READ MODE
The format of the status byte is: PON PROT 0 0 0 0 0 0
Where:
PON is the status bit for power-on reset (POR) and after
power failure:
Logic 1:
– after the first POR and after power failure; also set to
1 after a severe voltage dip that may have disturbed
the various settings
– POR 1 to 0 transition, VCC = 6.25 V (typ.)
– POR 0 to 1 transition, VCC = 5.75 V (typ.)
Logic 0:
– after a successful read of the status byte.
PROT is the over voltage detection for the scaled EHT
input:
Logic 1:
– if the scaled EHT rises above the reference value of
3.9 V
Logic 0:
– after a successful read of the status byte and EHT
<3.9 V.
Remark: a read action is considered successful when an
End Of Data signal has been detected (i.e. no master
acknowledge).
Table 1 Write mode with auto increment; subaddress and data byte format.
FUNCTION
Vertical amplitude
Vertical S-correction
Vertical start scan
Vertical off-centre shift
EW trapezium correction
EW width/width ratio
EW parabola/width ratio
EW corner/parabola ratio
EHT compensation
Horizontal phase
Horizontal off-centre shift
Clamp shift
Control 1
Vertical slope MSB
Vertical slope LSB
Vertical wait
Control 2
DATA BYTE
SUBADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
00
X(1) X
A5 A4 A3 A2 A1 A0
01 X X A5 A4 A3 A2 A1 A0
02 X X A5 A4 A3 A2 A1 A0
03
X note 2 note 2 note 2 X
A2 A1 A0
03 X A6 A5 A4 X note 2 note 2 note 2
04 X X A5 A4 A3 A2 A1 A0
05 X X A5 A4 A3 A2 A1 A0
06 X X A5 A4 A3 A2 A1 A0
07 X X A5 A4 A3 A2 A1 A0
08 X X A5 A4 A3 A2 A1 A0
09 X X A5 A4 A3 A2 A1 A0
0A X X X X X A2 A1 A0
0B MS WS FBL VAP BLDS LFSS DINT GBS
0C A7 A6 A5 A4 A3 A2 A1 A0
0D A7 A6 A5 A4 A3 A2 A1 A0
0E A7 A6 A5 A4 A3 A2 A1 A0
0F X X X VPR CPR DIP PRD CSU
Notes
1. X = don’t care.
2. Data bit used in another function.
July 1994
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Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
Table 2 Control bits.
CONTROL BIT
LFSS
DINT
BLDS
GBS
VAP
FBL
WS
MS
CSU
PRD
DIP
CPR
VPR
LOGIC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
Line stop: EW output current becomes zero and the vertical output current is reduced
to 20% of the adjusted value. LFSS becomes logic 0 after a HIGH on PON.
Line start enabled: the soft start mechanism is now activated.
De-interlace on: the VA pulse is sampled at a position selected with control bit DIP.
De-interlace off: the VA pulse is sampled with the system clock and the detected rising
edge is used as vertical reset.
Aquadag selected.
Bleeder selected.
Becomes logic 0 after power-on.
Guard band 48/12 lines.
Positive VA edge detection.
Negative VA edge detection.
Horizontal flyback slicing level = 3.9 V.
Horizontal flyback slicing level = 1.3 V.
No wait state.
Programmable wait state (only in constant slope mode; MS = logic 1).
Adaptive mode with guardband amplitude control.
Constant slope mode (programmable).
No clamping suppression, standard mode of operation.
Clamping suppression in wait, stop and protection modes
(used in systems with e.g. TDA4680/81).
No defeat of HOUT, the over voltage information is only written in the PROT status bit.
HOUT is defeated and status bit PROT is set when over voltage is detected.
VA is sampled 42 clock pulses after the leading edge of HA.
VA is sampled 258 clock pulses after the leading edge of HA.
Nominal amplitude.
Compression to 75% of adjusted amplitude, used for display of 16 : 9 standard pictures
on 4 : 3 displays.
Nominal amplitude (100%) during wait, stop and clipping.
Amplitude reduced to 20% during wait, stop and clipping.
July 1994
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Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
Table 3 Explanation of control bits shown in Table 2.
CONTROL BITS
LFSS
DINT
BLDS
GBS
VAP
FBL
WS
MS
CSU
PRD
DIP
CPR
VPR
line frame start/stop
de-interlace
bleeder mode selection
guard band selection
polarity of VA edge detection
flyback slicing level
wait state on/off
mode select
clamping suppression mode
protection/detection mode
de-interlace phase
compression on/off
vertical power reduction mode
DESCRIPTION
Table 4 Clock frequency control bit (pin 5; note 1).
CONTROL BIT
LLCS
LOGIC
0
1
FUNCTION
prescaler on: the internal clock frequency fclk = 12fLLC
prescaler off (default by internal pull-up resistor): the internal clock frequency fclk = fLLC
Note
1. Switching of the prescaler is only allowed when LFSS is LOW. It is highly recommended to hard wire LLCS to ground
or VCC. Active switching may damage the output power transistor due to the changing HOUT pulse. This may cause
very high currents and large flyback pulses. The permitted combinations of LLC and the prescaler are shown in
Table 5.
Table 5 Line duration with prescaler.
LLC (MHz)
6.75
13.5
27
Note
1. Combination not allowed.
ON (µs)
note 1
64
32
OFF (µs)
64
32
note 1
July 1994
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Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
July 1994
Fig.3 Timing relations between LLC, HA and line counter.
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Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
Horizontal part (pins 1, 2, 13, 19 and 20
SYNCHRONIZATION PULSE
The HA input (pin 13) is a TTL-compatible CMOS input.
Pulses on this input have to fulfil the timing requirements
as illustrated in Fig.6. For correct detection the minimum
pulse width for both the HIGH and LOW periods is 2
internal clock periods.
FLYBACK INPUT PULSE
The HFB input (pin 1) is a CMOS input. The delay of the
centre of the flyback pulse to the leading edge of the HA
pulse can be set via the I2C-bus with the horizontal phase
byte (subaddress 08), as illustrated in Fig.7.
The resolution is 6-bit.
OUTPUT PULSE
The HOUT pulse (pin 20) is an open-drain NMOS output.
The duty factor for this output is typically 5248
(conducting/non-conducting) during normal operation. A
soft start causes the duty factor to increase linearly from 5
to 52% over a minimum period of 2000 lines in 2000 steps.
OFF-CENTRE SHIFT
The OFCS output (pin 19) is a push-pull CMOS output
which is driven by a pulse-width modulated DAC.
By using a suitable interface, the output signal can be used
for off-centre shift correction in the horizontal output stage.
This correction is required for HDTV tubes with a 16 × 9
aspect ratio and is useful for high performance flat square
tubes to obtain the required horizontal linearity. For
applications where off-centre correction is not required,
the output can be used as an auxiliary DAC. The OFCS
signal is phase-locked with the line frequency. The
off-centre shift can be set via the I2C-bus, subaddress 09,
with a 6-bit resolution as illustrated in Fig.8.
SANDCASTLE
The DSC input/output (pin 2) acts as a sandcastle
generating output and a guard sensing input. As an output
it provides 2 levels (apart from the base level), one for the
horizontal and vertical blanking and the other for the video
clamping. As an input it acts as a current sensor during the
vertical blanking interval for guard detection.
CLAMPING PULSE
The clamping pulse width is 21 internal clock periods. The
shift, with respect to HA can be varied from 35 to 49 clock
periods in 7 steps via the I2C-bus, clamp shift byte
subaddress 0A, as illustrated in Fig.9. It is possible to
suppress the clamping pulse during wait, stop and
protection modes with control bit CSU. This will avoid
unwanted reset of the TDA4680/81 (only used in those
circuits).
HORIZONTAL BLANKING
The start of the horizontal blanking pulse is minimum 38
and maximum 41 clock periods before the centre of the
flyback pulse, depending on the fclk/fH ratio K in
accordance with 41 (432 K).
Stop of the horizontal blanking pulse is determined by the
trailing edge of the HFB pulse at the horizontal blanking
slicing level crossing as illustrated in Fig.10.
VERTICAL BLANKING
The vertical blanking pulse starts two internal clock pulses
after the rising edge of the VA pulse. During this interval a
small guard pulse, generated during flyback by the vertical
power output stage, must be inserted. Stop vertical
blanking is effected at the end of the blanking interval only
when the guard pulse is present (see Section “Vertical
guard”).
The start scan setting determines the end of vertical
blanking with a 6-bit resolution in steps of one line via the
I2C-bus subaddress 02 (see Figs 11, 12 and 13).
VERTICAL GUARD
In the vertical blanking interval a small unblanking pulse is
inserted. This pulse must be filled-in by a blanking pulse or
guard pulse from the vertical power output stage which
was generated during the flyback period. In this condition
the sandcastle output acts as guard detection input and
requires a minimum 800 µA input current. This current is
sensed during the unblanking period. Vertical blanking is
only stopped at the end of the blanking interval when the
inserted pulse is present. In this way the picture tube is
protected against damage in the event of missing or
malfunctioning vertical deflection (see Figs 11, 12 and 13).
July 1994
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Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
Vertical part (pins 6, 8, 10, 11 and 12)
SYNCHRONIZATION PULSE
The VA input (pin 12) is a TTL-compatible CMOS input.
Pulses at this input have to fulfil the timing requirements as
illustrated in Fig.6. For correct detection the minimum
pulse width for both the HIGH and LOW period is 2 internal
clock periods. For further requirements on minimum pulse
width see also Section “De-interlace”.
VERTICAL PLACE GENERATOR
An overview of the various modes of operation of the
vertical place generator is illustrated in Fig.13.
With control bit CPR a compress to 75% of the adjusted
values is possible in all modes of operation. This control bit
is used to display 16 : 9 standard pictures on 4 : 3
displays. No new adjustment of other corrections, such as
corner and S-correction, is required.
With control bit VPR a reduction of the current during
clipping, wait and stop modes to 20% of the nominal value
can be selected, which will reduce the dissipation in the
vertical drive circuits.
Vertical place generator in adaptive mode (MS = logic 0)
The vertical start-scan data (subaddress 02) determines
the vertical placement in the total range of 64 × 432 clock
periods in 63 steps. The maximum number of
synchronized lines per scan is 910 with an equivalent field
frequency of 17.2 or 34.4 Hz for fH = 15625 or 31250 Hz
respectively.
The minimum number of synchronized lines per scan is
200 with an equivalent field frequency of 78 or 156 Hz for
fH = 15 625 or 31250 Hz respectively.
If the VA pulse is not present, the number of lines per scan
will increase to 910.2. If the LLC is not present the vertical
blanking will start within 2 µs.
Amplitude control is automatic, with a settling time of 1 to
2 new fields and an accuracy of either 16/12 or 48/12 lines
depending on the value of the GBS bit.
Differences in the number of lines per field, as can occur in
TXT or in multi-head VTR, will not affect the amplitude
setting providing the differences are less than the value
selected with GBS. This is called amplitude control
guardband. The difference sequence and the difference
sequence length are not important.
Vertical place generator in constant slope mode
(MS = logic 1)
In this mode the slope can be programmed directly with a
two byte value on subaddress 0C (MSB) and 0D (LSB).
When the actual number of lines is greater than the
programmed number of lines, the circuit will enter the stop
state in which the differential vertical output current
remains 100% or drops to 20% (programmable with
control bit VPR). The programmed value for the slope is
the required number of lines multiplied by 72. The
programming limits are; minimum 200 × 72 and maximum
910 × 72.
A vertical expansion is obtained with a combination of
slope data and a programmable wait status, at
subaddress 0E. The wait status is selected with control bit
MS and can only be activated in the constant slope mode.
The wait state is an 8-bit value, programmable from 0 to
255. The actual wait state is one line longer than the
programmed value. If blanking is applied during stop and
wait status the differential output current will be the same
with VPR selected value (20 or 100%).
DE-INTERLACE
With de-interlace on (DINT = logic 0), the VA pulse is
sampled with LLC at a position supplied by control bit DIP
(de-interlace phase).
When DIP = logic 0 sampling takes place 42 clock pulses
after the leading edge of HA (T = Tline × 42/432).
When DIP = logic 1 sampling takes place 258 clock pulses
after the leading edge of HA (T = Tline × 258/432).
The distance between the two selectable sampling points
is (Tline × (258 42)/432) which is exactly half a line, thus
de-interlace is possible in two directions.
The duration of the VA pulse must, therefore, be sufficient
to enable the HA pulse to caught, in this event an active
time of minimum of half a line (see Fig.14 which has an
integration time of Tline × 14 for the VA pulse).
With de-interlace off, the VA pulse is sampled with the
system clock. The leading edge is detected and used as
the vertical reset. Selection of the positive or negative
leading edge is achieved by the control bit VAP.
July 1994
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Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
VERTICAL GEOMETRY PROCESSING
The vertical geometry processing is DC-coupled and
therefore independent of field frequency. The external
resistive conversion (RCONV) at pin 8 sets the reference
current for both the vertical and EW geometry processing.
A useful range is 100 to 150 µA, the recommended value
is 120 µA.
VERTICAL OUTPUTS
The vertical outputs VOUTA and VOUTB on pins 10 and 11
together form a differential current output. The vertical
amplitude can be varied over the range 80 to 120% in
63 steps via the I2C-bus (subaddress 00). Vertical
S-correction is also applied to these outputs and can be
set from 0 to 16% by subaddress 01 with a 6-bit resolution.
The vertical off-centre shift (OFCS) shifts the vertical
deflection current zero crossing with respect to the EW
parabola bottom. The control range is 1.5 to +1.5%
(±18 × I8) in 7 steps set by the least significant nibble at
subaddress 03.
EW GEOMETRY PROCESSING
The EW geometry processing is DC coupled and therefore
independent of field frequency. RCONV sets the reference
current for both the vertical and EW geometry processing.
The EW output is an ESD-protected single-ended current
output.
The EW width/width ratio can be set from 100 to 80% in
63 steps via subaddress 04 and the EW parabola/width
ratio from 0 to 20% via subaddress 05. The EW
corner/EW parabola ratio has a control range of 40 to 0%
in 63 steps via subaddress 06.
The EW trapezium correction can be set from
1.5 to +1.5% in 7 steps via the most significant nibble at
subaddress 03.
BULT GENERATOR
The Bult generator makes the EW waveform continuous
(see Fig.21).
Protection input (pin 3)
The protection input (PROT) is a CMOS input.
The input voltage must be EHT scaled and has the
following characteristics:
Two modes of protection are available with the aid of
control bit PRD.
With PRD = logic 1 the protection mode is selected,
HOUT will be defeated and the PROT bit in the status
word is set if the input voltage is above 3.9 V. Thus the
deflection stops and EW output current is zero, while the
vertical output current is reduced to 20% of the adjusted
value. A new start of the circuit is I2C-bus controlled with
the user software.
With PRD = logic 0 the detection mode is selected,
HOUT will not be defeated and the over voltage
information is only written in the PROT status bit and can
be read by the I2C-bus.
All further actions, such as a write of the LFSS bit, are
achieved by the I2C-bus. They depend on the
configuration used and are defined by user software.
Flash detection/protection input (pin 9)
The FLASH input is a CMOS input with an internal pull-up
current of approximately 8 µA.
When a negative-going edge crosses the 0.75 V level a
restart will be executed with a soft start of approximately
2000 lines, such as in the soft-start mode. When the
function is not used pin 9 can be connected to ground, VCC
or left open-circuit, the internal pull-up current source will
prevent any problems. However a hard wired connection
to VCC or ground is recommended when the function is not
used.
EHT compensation (pin 7)
The EHT input is a CMOS input.
The EHT compensation input permits scan amplitude
modulation should the EHT supply not be perfect. For
correct tracking of the vertical and horizontal deflection the
gain of the EW output stage, provided by the ratio
RCONV-EW/RCONV, must be 116Vscan × Vref (see Fig.15).
The input for EHT compensation can be derived from an
EHT bleeder or from the picture tubes aquadag
(subaddress 0B, bit BLDS).
EHT compensation can be set via subaddress 07 in
63 steps allowing a scan modulation range from
10 to +9.7%.
July 1994
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Programmable deflection controller

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INTERNAL CIRCUITRY
Preliminary specification
TDA9151B
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Programmable deflection controller

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APPLICATION INFORMATION
Preliminary specification
TDA9151B
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Programmable deflection controller

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TIMING DIAGRAMS
Preliminary specification
TDA9151B
Fig.6 Timing requirements for LLC, HA and VA.
July 1994
NNNNNNNNNNNNNN
Fig.7 Horizontal phase and HOUT control range.
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Programmable deflection controller

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Preliminary specification
TDA9151B
Fig.8 OFCS duty factor.
July 1994
Fig.9 DSC clamping pulse.
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Programmable deflection controller

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Programmable deflection controller
Preliminary specification
TDA9151B
Fig.10 DSC line blanking.
July 1994
Fig.11 DCS vertical blanking with unblanking.
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Programmable deflection controller

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Preliminary specification
TDA9151B
Vertical blanking LOW period: during scan, during unblanking.
Vertical blanking HIGH period (2.5 V): during STSC, stop and wait.
Vertical blanking continuously HIGH: POR = logic 1, LFSS = logic 0, no guard detected.
Fig.12 DSC with guard interval; start scan = 24.
July 1994
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Programmable deflection controller

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Preliminary specification
TDA9151B
July 1994
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TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
I = start VA for DINT = logic 1.
D = start VA for DINT = logic 0.
Fig.14 De-interlace timing.
July 1994
Fig.15 Explanation of RCONV-EW/RCONV ratio.
20


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
PARAMETER
VCC
ICC
Ptot
Tstg
Tamb
Vsupply
II/O
VESD
supply voltage
supply current
total power dissipation
storage temperature
operating ambient temperature
voltage supplied to pins 1 to 3, 5 to 14 and 17 to 20
current in or out of any pin except pins 4, 15 and 16
electrostatic handling for all pins (note 1)
Note
1. Equivalent to discharging a 100 pF capacitor via a 1.5 kseries resistor.
MIN.
0.5
10
65
25
0.5
20
MAX.
8.8
+50
500
+150
+70
VCC + 0.5
+20
±2 000
UNIT
V
mA
mW
°C
°C
V
mA
V
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air
VALUE
70
UNIT
K/W
July 1994
21


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
CHARACTERISTICS
VCC = 8 V; Tamb = 25 °C; DGND = AGND = 0 V; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
Supply
VCC
ICC
supply voltage
supply current
Ptot total power dissipation
Vpor power-on reset
note 1;
fclk = 6.75 MHz
POR 1-to-0
transition
POR 0-to-1
transition
7.2
5.0
SDA and SCL (pins 17 and 18)
V17 SDA input voltage
VIL LOW level input voltage (pin 17)
VIH HIGH level input voltage (pin 17)
IIL LOW level input current (pin 17) V17 = VSSD
IIH HIGH level input current (pin 17) V17 = VCC
VOL LOW level output voltage (pin 17) IIL = 3 mA
V18 SCL input voltage
VIL LOW level input voltage (pin 18)
VIH HIGH level input voltage (pin 18)
IIL LOW level input current (pin 18) V18 = VSSD
IIH HIGH level input current (pin 18) V18 = VCC
0
3.5
0
3.5
Line-locked clock and line-locked clock select (pins 14 and 5)
VIL LOW level input voltage (pin 14)
VIH HIGH level input voltage (pin 14)
2.0
I14 input current
V14 = <5.5 V
10
tr rise time
0
tf fall time
0
δ0 duty factor
LLCS = logic 0;
at 1.4 V; note 2
40
δ1 duty factor
LLCS = logic 1;
at 1.4 V; note 2
25
TIMING (PRESCALER ON; fclk = 12fLLC WHERE fclk = INTERNAL CLOCK)
fLLC line-locked clock frequency
K line-locked clock frequency ratio H locked
between fLLC and fH
H unlocked
line-locked clock frequency ratio H locked
between fclk and fH
H unlocked
12.4
856
428
TYP.
MAX.
8.0 8.8
27
220
6.25 7.0
5.75
5.5
1.5
−−
− −10
10
0.4
5.5
1.5
−−
− −10
10
0.8
−−
+10
12tLLC
12tLLC
50 60
50 75
29.2
864 865
866
432 432.5
433
UNIT
V
mA
mW
V
V
V
V
V
µA
µA
V
V
V
V
µA
µA
V
V
µA
%
%
MHz
July 1994
22


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TIMING (PRESCALER OFF; fclk = fLLC WHERE fclk = INTERNAL CLOCK)
fLLC line-locked clock frequency
K line-locked clock frequency ratio H locked
between fLLC and fH
H unlocked
line-locked clock frequency ratio H locked
between fclk and fH
H unlocked
V5 LLCS input voltage
VIL LOW level input voltage (pin 5)
VIH HIGH level input voltage (pin 5)
IIL LOW level input current (pin 5) V5 = VSSD
IIH HIGH level input current (pin 5) V5 = VCC
Horizontal part
6.2
428
428
0
3.5
15.5
432 432
433
432 432
433
8.8
1.5
−−
− −150
100
MHz
V
V
V
µA
µA
INPUT SIGNALS
HA (pin 13)
VIL LOW level input voltage
VIH HIGH level input voltage
I13 input current
tr rise time
tf fall time
tWH pulse width HIGH
tWL pulse width LOW
HFB (pin 1)
V13 = 5.5 V
2.0
10
0
0
2 × tclk
2 × tclk
0.8
+10
12tLLC
12tLLC
V
V
µA
ns
ns
VPSL
phase slicing level;
FBL = logic 0
FBL = logic 1
3.7
1.1
3.9 4.1
1.3 1.5
V
V
Vblank
I1
blanking slicing level
input current
0 0.1 0.2
10 +10
V
µA
Horizontal phase (delay centre flyback pulse to leading edge of HA; where N = horizontal phase data)
CR control range
number of steps
0
N × tclk
N + (432 K)
× tclk
63
OUTPUT SIGNALS
HOUT (pin 20)
V20 output voltage
VOL LOW level output voltage
I20 input current
δ duty factor
I20 = 0
I20 = 10 mA
output off
normal operation
0
10
51
VCC
0.5
+10
52 53
V
V
µA
%
July 1994
23


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
SYMBOL
PARAMETER
CONDITIONS
Soft start (duty factor controlled line drive)
tW initial pulse width soft start
CR control range
tss soft start time
Switch-off time to the centre of the flyback pulse
CR control range
note 3
MIN.
5
1 500
0
Φ
k
σ
PSRR
control sensitivity (loop gain)
correction factor
sigma value of phase jitter
power supply rejection ratio
note 4
note 5
400
Horizontal off-centre shift (pin 19; N = off-centre shift data)
V19
VOL
VOH
δ(max)
δ
output voltage
LOW level output voltage
HIGH level output voltage
maximum duty factor
duty factor
number of steps
I19 = 2 mA
I19 = 2 mA
N <54
N 54
0
VCC 0.5
1/K
SANDCASTLE (PIN 2)
DSC output voltage
Vclamp
Vblank
Vbase
I2
video clamping voltage
horizontal and vertical blanking
voltage level
base voltage level
output current
tr rise time
tf fall time
Clamping pulse (N = clamp pulse shift data)
4.0
2.0
guard not detected
guard detected
0
1.0
0.8
tW
tclamp
clamping pulse width
clamp pulse shift w.r.t HA
35
number of steps
tstart start of horizontal blanking before
middle of flyback pulse
38
TYP.
MAX.
5
53
3000
1000
0.5
750
160
(432 K)
× tclk
10
(8N+1)/K
1
54
VCC
0.5
425/K
4.5 5.0
2.5 3.0
0.5 1.0
+0.35
2.5
60
60
21 × tclk
(2N + 35)
× tclk
7
41
(432 K)
× tclk
49
41
UNIT
%
%
lines
µs/µs
ps
ns/V
V
V
V
%
%
V
V
V
mA
mA
ns
ns
July 1994
24


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
Vertical blanking width (N = vertical start-scan data)
CR control range
K = 432
number of steps
Guard detection (N = vertical start-scan data)
tstart start interval w.r.t VA
no wait
tstop stop interval w.r.t VA
no wait
Vertical section
1 × 432tclk
1
(N + 1)
× 432tclk
63
64 × 432tclk
64
{48(N+1) +2}
× tclk
{96(N+1) +2}
× tclk
INPUT SIGNALS (PIN 12; VA)
VIL LOW level input voltage
VIH HIGH level input voltage
I12 input current
tr rise time
tf fall time
tWH pulse width HIGH
tWL pulse width LOW
tWH pulse width HIGH
tWL pulse width LOW
V12 <5.5 V
de-interlace mode
de-interlace mode
2.0
10
0
0
2 × tclk
2 × tclk
0.5 × tline
0.5 × tline
Vertical place generator in adaptive mode (N = vertical start-scan data)
CR control range
1 × 432tclk
Lmax
feq
Lmin
feq
CA
CAg
number of steps
maximum number of
synchronized lines per scan
equivalent field frequency at 910
lines/scan
minimum number of
synchronized lines per scan
equivalent field frequency at 200
lines/scan
amplitude control
amplitude control guardband
settling time
K = 432
fH = 15625 Hz
fH = 31250 Hz
fH = 15625 Hz
fH = 31250 Hz
GBS = logic 0
GBS = logic 1
1
1
0.8
−−
+10
12tLLC
12tLLC
−−
−−
−−
−−
(N + 1)
× 432tclk
63
910
64 × 432tclk
64
17.2
34.4
200
78
156
automatic
16/12
48/12
1.5
2
UNIT
lines
V
V
µA
ns
ns
lines
lines/
scan
Hz
Hz
lines/
scan
Hz
Hz
lines
lines
new
fields
July 1994
25


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
SYMBOL
PARAMETER
CONDITIONS
MIN.
Vertical place generator in constant slope mode (N = vertical wait data)
CR control range
1 × 432tclk
number of steps
programmable slope
K = 432
1
200
programmable slope data
(number of lines × 72)
2-byte instruction;
Vertical geometry processing
I(M)
D/T
vertical differential output current
between VOUTA and VOUTB
(peak value)
drift over temperature range
VA = 100%;
note 6;
I8 = 120 µA
amplitude error due to
S-correction setting
12(I10+I11)
Ios
OS/T
vertical output signal bias current
vertical output offset current
offset over temperature range
I8 = 120 µA
note 7
V10
V11
CMRR
vertical output voltage (pin 10)
vertical output voltage (pin 11)
common mode rejection ratio
LE linearity error
adjacent blocks;
note 8
non-adjacent
blocks; note 8
Vertical amplitude (N = vertical amplitude data)
CR control range
number of steps
note 9
Vertical S-correction (N = S-correction data)
CR control range
number of steps
note 9
Vertical shift
CR control range
number of steps
EW output (pin 6)
V6
I6
RR
D/T
output voltage
output current
output ripple rejection
output drift over temperature
range
note 10
I8 = 120 µA;
note 11
200 × 72
440
275
0
0
81
0
18I8
1.0
15
July 1994
26
TYP.
MAX.
UNIT
(N + 1)
× 432tclk
255
64 × 432tclk
64
910
910 × 72
lines
lines/
scan
lines
475 510
104
2
325 375
1
104
3.9
3.9
1
2.0
3.0
µA
K1
%
µA
%
K1
V
V
%/V
%
%
63
63
7
0.15
119
15
+18I8
5.5
930
1
5.104
%
%
µA
V
µA
%/V
K1


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
SYMBOL
PARAMETER
EW WIDTH/WIDTH RATIO
CR control range
Ieq(typ)
typical equivalent output current
number of steps
EW PARABOLA/WIDTH RATIO
CR control range
Ieq(typ)
typical equivalent output current
number of steps
EW CORNER/EW PARABOLA RATIO
CR
Ieq(typ)
control range
typical equivalent output current
number of steps
EW TRAPEZIUM CORRECTION
EW trapezium/width ratio
number of steps
EHT input (pin 7)
Vref reference voltage
VI
VI
mscan
mGC
input voltage w.r.t Vref
input voltage w.r.t VCC
scan modulation
modulation gain control
number of steps
II input current
RCONV input (pin 8)
VO output voltage
I8 current range
PROT input (pin 3)
VI input voltage
V3 voltage detection level
II input current
FLASH detection input (pin 9)
VI input voltage
V9 voltage detection level
H detection level hysteresis
I9 detection pull-up current
CONDITIONS
note 9
V6 = 3 V
note 9
width = 100%
width = 80%
notes 9 and 12
width = 100%
width = 80%
note 9
BLDS = logic 1
BLDS = logic 0
BLDS = logic 1
BLDS = logic 0
I8 = 120 µA
falling edge
MIN.
100
15
1
10
10
40
0
0
1.5
20
0
10
0
100
3.7
100
0
3.7
10
0
0.5
0.3
4
TYP.
MAX.
81
440
63
19
430
345
63
0
200
160
63
+1.5
7
3.9
VCC
0 +20
− −2Vref
0 +9.7
1
63
+100
3.9
120
4.1
150
VCC
3.9 4.1
+10
0.75
VCC
1.0
0.5 0.8
8 16
UNIT
%
µA
%
µA
µA
%
µA
µA
%
V
V
%
V
%
nA
V
µA
V
V
µA
V
V
V
µA
July 1994
27


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
Notes to the characteristics
1. For all other frequencies the expected supply current will be as shown in Table 6 (fclk is the internal clock frequency,
fLLC is the internal clock frequency applied to pin 14).
2. When the prescaler is on, one in two LLC HIGH periods is omitted.
3. For 16 kHz operation the minimum value of the control range is 5.7 µs. With 12tFB = 5.7 µs the minimum storage time
is 0 and the maximum is 18 µs.
For 32 kHz operation the minimum value of the control range is 0 µs. With 12tFB = 2.85 µs the minimum storage time
is 0 and the maximum is 9 µs.
4. The k factor is defined as the amount of correction of a phase step. Thus with k = 0.5 a 50% correction of the error
takes place each line. The resulting step response now becomes kn, with n the line number after the step.
5. The sigma value (σ) of the jitter with respect to LLC (HA) at fH = 32 kHz and a storage time of 5 µs.
Measurement of σ is carried out during 200 lines in the active scan, the resulting peak-to-peak value is approximately
6σ. The visible jitter on the screen will be higher than the peak-to-peak jitter, depending on the deflection stage.
6. DAC values: vertical amplitude = 31; EHT = 0; SHIFT = 3; SCOR = 0.
7. Value is a percentage of I10 I11.
8. The linearity error is measured without S-correction and based on the same measurement principle as used for the
screen. Measuring method: divide the output signal I10 I11 into 22 equal parts, ranging from 1 to 22 inclusive.
Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part
20 and 21 (block 10). Thus part 1 and 22 are unused.
Linearity error for adjacent blocks = a----k------a--a-a---v(--k-g---+---1---)-
Linearity error for non-adjacent blocks = a----m----a--a-x--a---v---ga----m----i-n-
Where a = amplitude, ak = amplitude block k and aavg = average amplitude.
9. Minimum available range.
10. Selection of test mode.
When the EW output is pulled above VCC 0.5 V a special test mode is entered in which the prescaler and the clock
detector are disabled.
11. DAC values: vertical amplitude = 31; EHT = 0.
12. The value of 40% (typically 46%) corresponds with data 3F (hexadecimal) and implies maximum 4th order
compensation.
Table 6 Supply current with prescaler on/off.
LLC (MHz)
6.75
13.5
27
Note
1. Combination not allowed.
ON (mA)
note 1
27
42
OFF (mA)
27
38
note 1
July 1994
28


TDA9151B (NXP)
Programmable deflection controller

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Philips Semiconductors
Programmable deflection controller
TEST AND APPLICATION INFORMATION
Preliminary specification
TDA9151B
I11 I10.
Fig.16 Control range amplitude.
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July 1994
Fig.17 Control range S-correction.
29


TDA9151B (NXP)
Programmable deflection controller

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Preliminary specification
Programmable deflection controller
TDA9151B
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July 1994
Fig.19 Control range EW corner/EW parabola ratio.
30




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