UPD754302 (NEC)
4-BIT SINGLE-CHIP MICROCONTROLLER

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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD754302,754304,754302(A),754304(A)
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD754304 is one of the “75XL Series” 4-bit single-chip microcontrollers with data processing capability
comparable to that of 8-bit microcontrollers. The µPD754303(A) has a higher reliability than the µPD754304.
The microcontrollers in the 75XL Series have expanded CPU functions than those of the 75X Series and can
operate at a voltage of as low as 1.8 V; therefore, they are ideal for battery-driven application systems.
As the one-time PROM version of the µPD754304, the µPD75P4308 is ideal for evaluation of a system under
development or for small-scale production of application systems.
Detailed information about functions can be found in the following document. Be sure to read the following
document before designing.
µPD754304 User’s Manual: U10123E
FEATURES
• Low-voltage operation: VDD = 1.8 to 5.5 V
• Internal memory
Program memory (ROM):
2048 × 8 bits (µPD754302, 754302(A))
4096 × 8 bits (µPD754304, 754304(A))
Data memory (RAM): 256 × 4 bits
• Variable instruction execution time effective for high-
speed operation and power saving
0.95, 1.91, 3.81, or 15.3 µs (at 4.19 MHz)
0.67, 1.33, 2.67, or 10.7 µs (at 6.0 MHz)
• Internal serial interface (1 channel)
• Powerful timer function (3 channels)
• Inherits instruction set of existing 75X Series for easy
replacement
APPLICATIONS
µPD754302, 754302(A)
Cordless telephones, TVs, VCRs, audio systems, household appliances, office machines, etc.
µPD754304, 754304(A)
Automotive appliance, etc.
The µPD754302 and 754304 differ from the µPD754302(A) and 754304(A) only in terms of their quality grade.
Unless otherwise specified, the µPD754304 is treated as a representative model in this Data Sheet.
For the models other than the µPD754304, µPD754304 can be read as the other model name.
If different descriptions are made for the µPD754302 and 754304, the (A) models correspond as follows:
µPD754302 µPD754302(A), µPD754304 µPD754304(A)
The information in this document is subject to change without notice.
Document No. U10797EJ2V0DS00 (2nd edition)
Date Published November 1996 N
Printed in Japan
The mark shows major revised points.
©
1996


UPD754302 (NEC)
4-BIT SINGLE-CHIP MICROCONTROLLER

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µPD754302, 754304, 754302(A), 754304(A)
ORDERING INFORMATION
Parts Number
µPD754302GS-×××
µPD754304GS-×××
µPD754302GS(A)-×××
µPD754304GS(A)-×××
Package
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)
Quality Grade
Standard
Standard
Special
Special
Remark × indicates a ROM code number.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Difference between µPD75430× and µPD75430×(A)
Item
Parts Number
Quality grade
µPD754302
µPD754304
Standard
µPD754302(A)
µPD754304(A)
Special
2


UPD754302 (NEC)
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µPD754302, 754304, 754302(A), 754304(A)
Functional Outline
Parameter
Instruction execution time
On-chip memory
ROM
RAM
General-purpose register
Function
• 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with system clock)
• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with system clock)
2048 × 8 bits (µPD754302)
4096 × 8 bits (µPD754304)
256 × 4 bits
• 4-bit operation: 8 × 4 banks
• 8-bit operation: 4 × 4 banks
Input/
output
port
CMOS input
CMOS input/output
8 On-chip pull-up resistors can be specified by software: 7
18 On-chip pull-up resistors can be specified by software: 18
Timer
N-ch open-drain
input/output pins
Total
Serial interface
Bit sequential buffer
Clock output (PCL)
Vectored interrupts
Test input
System clock oscillator
Standby function
Operating ambient
temperature
Power supply voltage
Package
4 13 V withstand voltage. On-chip pull-up resistors can be specified by
mask option.
30
3 channels
• 8-bit timer/event counter: 2 channels (16-bit timer/event counter)
• Basic interval timer/watchdog timer: 1 channel
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit
• 2-wire serial I/O mode
16 bits
Φ, 524, 262, 65.5 kHz (@ 4.19 MHz with system clock)
Φ, 750, 375, 93.8 kHz (@ 6.0 MHz with system clock)
External: 3, Internal: 4
External: 1
Ceramic or crystal oscillator
STOP/HALT mode
TA = –40 to +85 ˚C
VDD = 1.8 to 5.5 V
36-pin plastic shrink SOP (300 mil, 0.8-mm pitch)
3


UPD754302 (NEC)
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µPD754302, 754304, 754302(A), 754304(A)
CONTENTS
1. PIN CONFIGURATION (Top View) ······································································································ 6
2. BLOCK DIAGRAM ······························································································································· 8
3. PIN FUNCTION ···································································································································· 9
3.1 Port Pins ····································································································································· 9
3.2 Non-port Pins ···························································································································· 10
3.3 Pin Input/Output Circuits ········································································································· 11
3.4 Recommended Connections for Unused Pins ······································································· 13
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ················································ 14
4.1 Difference between Mk I and Mk II Modes ·············································································· 14
4.2 Setting Method of Stack Bank Select Register (SBS) ··························································· 15
5. MEMORY CONFIGURATION············································································································· 16
6. PERIPHERAL HARDWARE FUNCTIONS ························································································· 20
6.1 Digital Input Ports ···················································································································· 20
6.2 Clock Generator ······················································································································· 21
6.3 Clock Output Circuit ················································································································ 22
6.4 Basic Interval Timer/Watchdog Timer ···················································································· 23
6.5 Timer/Event Counter ················································································································ 24
6.6 Serial Interface ·························································································································· 27
6.7 Bit Sequential Buffer ················································································································ 29
7. INTERRUPT FUNCTION AND TEST FUNCTION ·············································································· 30
8. STANDBY FUNCTION ······················································································································· 32
9. RESET FUNCTION ···························································································································· 33
10. MASK OPTION ··································································································································· 36
11. INSTRUCTION SETS ························································································································· 37
12. ELECTRICAL SPECIFICATIONS ······································································································ 49
13. CHARACTERISTICS CURVES (REFERENCE VALUES) ································································· 61
14. PACKAGE DRAWING ······················································································································· 63
15. RECOMMENDED SOLDERING CONDITIONS ················································································· 64
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UPD754302 (NEC)
4-BIT SINGLE-CHIP MICROCONTROLLER

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µPD754302, 754304, 754302(A), 754304(A)
APPENDIX A. COMPARISON OF FUNCTIONS AMONG µPD750004, 754304, AND 75P4308 ·········· 65
APPENDIX B. DEVELOPMENT TOOLS ································································································· 67
APPENDIX C. RELATED DOCUMENTS ································································································ 70
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µPD754302, 754304, 754302(A), 754304(A)
1. PIN CONFIGURATION (Top View)
36-pin plastic shrink SOP (300 mil, 0.8-mm pitch)
µPD754302GS-×××, µPD754302GS(A)-×××
µPD754304GS-×××, µPD754304GS(A)-×××
VSS
X1
X2
RESET
P33
P32
P31
P30
P81
P80
P23
P22/PCL
P21/PTO1
P20/PTO0
P03/SI
P02/SO/SB0
P01/SCK
P00/INT4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
IC: Internally Connected (Connect directly this pin to VDD.)
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P13/TI0/TI1
P12/INT2
P11/INT1
P10/INT0
VDD
IC
6


UPD754302 (NEC)
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PIN IDENTIFICATION
P00-P03 : PORT0
P10-P13 : PORT1
P20-P23 : PORT2
P30-P33 : PORT3
P50-P53 : PORT5
P60-P63 : PORT6
P70-P73 : PORT7
P80, P81 : PORT8
KR0-KR7 : Key Return 0-7
SCK : Serial Clock
SI : Serial Input
SO : Serial Output
SB0 : Serial data Bus 0
µPD754302, 754304, 754302(A), 754304(A)
RESET
: Reset Input
TI0, TI1 : Timer Input 0, 1
PTO0, PTO1: Programmable Timer Output 0, 1
PCL
: Programmable Clock
INT0, 1, 4 : External Vectored Interrupt 0, 1, 4
INT2
: External Test Input 2
VSS : GND
X1, X2
: System Clock Oscillation 1, 2
IC : Internally Connected
VDD : Positive Power Supply
7


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TI0/TI1/P13
PTO0/P20
PTO1/P21
BASIC
INTERVAL
TIMER/
WATCHDOG TIMER
TOUT0
INTBT
INTT0
8-BIT
TIMER/EVENT CASCADED
COUNTER#0 16-BIT
TIMER/
8-BIT
EVENT
TIMER/EVENT COUNTER
COUNTER#1
INTT1
SI/P03
SO/SB0/P02
SCK/P01
CLOCKED
SERIAL
INTERFACE
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0-KR3/P60-P63
KR4-KR7/P70-P73
INTCSI TOUT0
INTERRUPT
CONTROL
8
PROGRAM
COUNTER Note1
SP (8)
CY
ALU SBS
BANK
ROM Note2
PROGRAM
MEMORY
DECODE
AND
CONTROL
GENERAL REG.
RAM
DATA
MEMORY
256 · 4 BITS
fX/2N
CPU CLOCK
F
CLOCK CLOCK
OUTPUT
CONTROL
DIVIDER
CLOCK GENERATOR
STAND BY
CONTROL
PCL/P22
X1 X2
BIT SEQ.
BUFFER (16)
4 PORT0 4 P00-P03
4 PORT1 4 P10-P13
4 PORT2 4 P20-P23
4 PORT3 4 P30-P33
4 PORT5 4 P50-P53
4 PORT6 4 P60-P63
4 PORT7 4 P70-P73
2 PORT8 2 P80, P81
IC VDD VSS RESET
Notes 1. The µPD754302 and µPD754304 program counters are 11 and 12 bits, respectively.
2. The ROM capacity of the µPD754302 is 2048 × 8 bits, and that of the µPD754304 is 4096 × 8 bits.


UPD754302 (NEC)
4-BIT SINGLE-CHIP MICROCONTROLLER

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µPD754302, 754304, 754302(A), 754304(A)
3. PIN FUNCTION
3.1 Port Pins
Pin Name Input/Output
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30
P31
P32
P33
P50-P53 Note 2
Input
Input/Output
Input/Output
Input
Input
Input/Output
Input/Output
Input/Output
P60
P61
P62
P63
P70
P71
P72
P73
P80
P81
Input/Output
Input/Output
Input/Output
Alternate
Function
INT4
SCK
SO/SB0
SI
INT0
INT1
INT2
TI0/TI1
PTO0
PTO1
PCL
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
Function
8-bit
I/O Circuit
I/O After Reset TYPE Note 1
4-bit input port (PORT0).
× Input
B
For P01 to P03, on-chip pull-up resistors
can be specified by software in 3-bit units.
F -A
F -B
B -C
4-bit input port (PORT1).
On-chip pull-up resistors can be specified
by software in 4-bit units.
Noise elimination circuit can be selected
(Only P10/INT0)
4-bit input/output port (PORT2).
On-chip pull-up resistors can be specified
by software in 4-bit units.
×
×
Input
Input
B -C
E-B
Programmable 4-bit input/output port
(PORT3).
This port can be specified for input/output
bit-wise. On-chip pull-up resistor can be
specified by software in 4-bit units.
×
Input
N-ch open-drain 4-bit input/output port
× High level
(PORT5).
(when pull-up
resistors are
A pull-up resistor can be contained bit-wise
provided) or
(mask option).
high-
Withstand voltage is 13 V in open-drain mode.
impedance
Programmable 4-bit input/output port
(PORT6).
This port can be specified for input/output
bit-wise.
On-chip pull-up resistors can be specified
by software in 4-bit units.
Input
4-bit input/output port (PORT7).
On-chip pull-up resistors can be specified
by software in 4-bit units.
Input
E-B
M-D
F -A
F -A
2-bit input/output port (PORT8).
On-chip pull-up resistors can be specified
by software in 2-bit units.
×
Input
E-B
Notes 1. Circled characters indicate the Schmitt-trigger input.
2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input
port), low level input leakage current increases when input or bit manipulation instruction is executed.
9


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µPD754302, 754304, 754302(A), 754304(A)
3.2 Non-port Pins
Pin Name
TI0/TI1
PTO0
PTO1
PCL
SCK
SO/SB0
SI
INT4
INT0
INT1
INT2
KR0-KR3
KR4-KR7
X1
X2
RESET
IC
VDD
VSS
Input/Output
Input
Output
Input/Output
Input
Input
Input
Input
Input
Input
Input
Alternate
Function
P13
P20
P21
P22
P01
P02
P03
P00
P10
P11
P12
P60-P63
P70-P73
Function
Inputs external event pulses to the timer/event
counter.
Timer/event counter output
I/O Circuit
After Reset TYPE Note
Input
B -C
Input
E-B
Clock output
Serial clock input/output
Serial data output
Serial data bus input/output
Serial data input
Edge detection vectored interrupt input (both
rising edge and falling edge detection)
Edge detection vectored
interrupt input (detection
edge can be selected).
INT0/P10 can select a
noise elimination circuit.
Asynchronous with
noise elimination
circuit can be selected
Asynchronous
Edge detection testable
input
(rising edge detection)
Asynchronous
Testable input (falling edge detection)
Input
Input
Input
Input
Input
F -A
F -B
B -C
B
B -C
B -C
F -A
Crystal/ceramic connection pin for the system
clock oscillator. When inputting the external
clock, input the external clock to pin X1, and
the inverted phase of the external clock to
pin X2.
System reset input (low-level active)
Internally connected. Connect directly to VDD.
Positive power supply
Ground potential
B
Note Circled characters indicate the Schmitt-trigger input.
10


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µPD754302, 754304, 754302(A), 754304(A)
3.3 Pin Input/Output Circuits
The µPD754304 pin input/output circuits are shown schematically.
TYPE A
TYPE D
VDD
P-ch
IN
N-ch
data
output
disable
VDD
P-ch
OUT
N-ch
CMOS specification input buffer.
TYPE B
IN
Schmitt trigger input having hysteresis characteristic.
Push-pull output that can be placed in output
high-impedance (both P-ch, N-ch off).
TYPE E-B
data
output
disable
P.U.R.
enable
Type D
VDD
P.U.R.
P-ch
IN/OUT
Type A
TYPE B-C
VDD
P.U.R.
P-ch
P.U.R.
enable
IN
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
TYPE F-A
data
output
disable
P.U.R.
enable
Type D
VDD
P.U.R.
P-ch
IN/OUT
Type B
P.U.R. : Pull-Up Resistor
11


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µPD754302, 754304, 754302(A), 754304(A)
TYPE F-B
output
disable
(P)
data
output
disable
output
disable
(N)
P.U.R.
enable
VDD
P.U.R.
P-ch
VDD
P-ch
IN/OUT
N-ch
TYPE M-D
VDD
P.U.R.
(Mask Option)
data
output
disable
Input
instruction
N-ch
(+13 V)
VDD
P-ch
P.U.R.Note
Voltage
limiting
circuit
(+13 V)
P.U.R. : Pull-Up Resistor
IN/OUT
P.U.R. : Pull-Up Resistor
Note If this pull-up resistor is not connected using the mask
option it operates only when the input instruction is
executed (if the pin is low, current flows from VDD to the
pin).
12


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µPD754302, 754304, 754302(A), 754304(A)
3.4 Recommended Connections for Unused Pins
Table 3-1. List of Recommended Connections for Unused Pins
Pin
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI
P10/INT0-P12/INT2
P13/TI0/TI1
P20/PTO0
P21/PTO1
P22/PCL
P23
P30-P33
P50-P53
P60/KR0-P63/KR3
P70/KR4-P73/KR7
P80, P81
IC
Recommended Connection
Connect to VSS or VDD
Connect to VSS or VDD through the resistor individually
Connect to VSS
Connect to VSS or VDD
Input state : Connect to VSS or VDD through the resistor
individually
Output state : Leave open
Input state : Connect to VSS
Output state : Connect to VSS (Pull-up resistor by mask
option should not be connected)
Input state : Connect to VSS or VDD through the resistor
individually
Output state : Leave open
Connect to VDD directly
13


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µPD754302, 754304, 754302(A), 754304(A)
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Difference between Mk I and Mk II Modes
The CPU of µPD754304 has the following two modes: Mk I and Mk II, either of which can be selected. The
mode can be switched by the bit 3 of the stack bank select register (SBS).
• Mk I mode: Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes.
• Mk II mode: Can be used in all the 75XL CPU’s including those products whose ROM capacity is more
than 16K bytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Number of stack bytes
for subroutine instructions
BRA !addr1 instruction
CALLA !addr1 instruction
CALL !addr instruction
CALLF !faddr instruction
2 bytes
Mk I mode
Not available
3 machine cycles
2 machine cycles
Mk II mode
3 bytes
Available
4 machine cycles
3 machine cycles
Caution
The Mk II mode supports a program area exceeding 16K bytes in the 75X and 75XL
series. This mode can improve software compatibility with products with a program
area of more than 16K bytes.
When Mk II mode is selected, the number of stack bytes when a subroutine call
instruction is executed is greater by 1 byte per stack compared with the Mk I mode.
When the CALL !addr or CALLF !faddr instruction is used, one more machine cycle is
required. To emphasize the efficiency of the RAM and processing speed rather than
software compatibility, therefore, use the Mk I mode.
14


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µPD754302, 754304, 754302(A), 754304(A)
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction.
When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using
the Mk II mode, it must be initialized to 0000B.
Figure 4-1. Stack Bank Select Register Format
Address
F84H
3 2 1 0 Symbol
SBS3 SBS2 SBS1 SBS0 SBS
Stack area specification
0 0 Memory bank 0
Other than above setting prohibited
0 0 must be set in the bit 2 position.
Mode switching specification
0 Mk II mode
1 Mk I mode
Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk
I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the
Mk II mode.
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µPD754302, 754304, 754302(A), 754304(A)
5. MEMORY CONFIGURATION
• Program Memory (ROM) .... 2048 × 8 bits (µPD754302)
.... 4096 × 8 bits (µPD754304)
• Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET
signal is generated are written. Reset and start are possible at an arbitrary address.
• Addresses 0002H-000DH
Vector table wherein the program start address and values set for the RBE and MBE by the vectored
interrupts are written. Interrupt execution can be started at an arbitrary address.
• Addresses 0020H-007FH
Table area referenced by the GETI instruction Note.
Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the program steps.
• Data Memory (RAM)
• Data area .... 256 words × 4 bits (000H-0FFH)
• Peripheral hardware area .... 128 words × 4 bits (F80H-FFFH)
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µPD754302, 754304, 754302(A), 754304(A)
Figure 5-1. Program Memory Map (1/2)
Address 7 6
0 0 0 0 H MBE RBE
5
0
0 0 0 2 H MBE RBE 0
0 0 0 4 H MBE RBE 0
0 0 0 6 H MBE RBE 0
0 0 0 8 H MBE RBE 0
0 0 0 A H MBE RBE 0
0 0 0 C H MBE RBE 0
0020H
007FH
0080H
(a) µPD754302
4
0 Internal reset start address
Internal reset start address
0 INTBT/INT4
INTBT/INT4
start address
start address
0 INT0
start address
INT0
start address
0 INT1
start address
INT1
start address
0 INTCSI
start address
INTCSI
start address
0 INTT0
start address
INTT0
start address
0 INTT1
start address
0
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
CALLF
! faddr
instruction
entry
address Branch address of
BR BCXA, BR BCDE,
BR !addr, BRA !addr1Note or
CALLA !addr1Note instruction
CALL !addr instruction
subroutine entry address
BR $addr instruction
relative branch address
_15 to _1,
+2 to +16
INTT1
start address (low-order 8 bits)
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
GETI instruction reference table
07FFH
Note Can be used in the Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
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µPD754302, 754304, 754302(A), 754304(A)
Figure 5-1. Program Memory Map (2/2)
(b) µPD754304
Address 7 6 5
0 0 0 0 H MBE RBE 0
0 0 0 2 H MBE RBE 0
0 0 0 4 H MBE RBE 0
0 0 0 6 H MBE RBE 0
0 0 0 8 H MBE RBE 0
0 0 0 A H MBE RBE 0
0 0 0 C H MBE RBE 0
4
0 Internal reset start address
Internal reset start address
0 INTBT/INT4
INTBT/INT4
start address
start address
0 INT0
start address
INT0
start address
0 INT1
start address
INT1
0 INTCSI
start address
start address
INTCSI
start address
0 INTT0
start address
INTT0
0 INTT1
start address
start address
INTT1
start address
0
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
(low-order 8 bits)
(high-order 4 bits)
CALLF
! faddr
instruction
entry
address Branch address of
BR BCXA, BR BCDE,
BR !addr, BRA !addr1Note or
CALLA !addr1Note instruction
CALL !addr instruction
subroutine entry address
BR $addr instruction
relative branch address
_15 to _1,
+2 to +16
(low-order 8 bits)
0020H
007FH
0080H
07FFH
0800H
GETI instruction reference table
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
0FFFH
Note Can be used in the Mk II mode only.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
18


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µPD754302, 754304, 754302(A), 754304(A)
Data area
static RAM
(256 × 4)
Stack area
Figure 5-2. Data Memory Map
000H
General-purpose
register area
01FH
Data memory
(32 × 4)
256 × 4
(224 × 4)
Peripheral hardware area
0FFH
F80H
Not incorporated
128 × 4
FFFH
Memory bank
0
15
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µPD754302, 754304, 754302(A), 754304(A)
6. PERIPHERAL HARDWARE FUNCTIONS
6.1 Digital Input Ports
The following three types of I/O ports are provided.
• CMOS input (Ports 0, 1)
:8
• CMOS I/O (Ports 2, 3, 6 to 8)
: 18
• N-ch open-drain I/O (Port 5)
:4
Total
30
Table 6-1. Types and Features of Digital Ports
Port Name
PORT0
PORT1
PORT2
PORT3
PORT5
PORT6
PORT7
PORT8
Function
4-bit input
4-bit I/O
4-bit I/O
(N-ch open-
drain, 13 V)
4-bit I/O
2-bit I/O
Operation, Features
When serial interface function is used, multiplexed pin
has output function depending on operation mode.
Input port.
Can be set in input or output mode in 4-bit units.
Can be set in input or output mode in 1-bit units.
Can be set in input or output mode in 4-bit units. Pull-up
resistor can be connected in 1-bit units by mask option.
Remark
Multiplexed with INT4, SCK,
SO/SB0, and SI pins
Multiplexed with INT0
through INT2 and TI0/TI1 pins.
Multiplexed with PTO0, PTO1,
and PCL pins.
Can be set in input or
output mode in 1-bit units.
Can be set in input or
output mode in 4-bit units.
Ports 6 and 7 are used in
pairs and can input or
output data in 8-bit units.
Can be set in input or output mode in 2-bit units.
Multiplexed with KR0 through
KR3 pins.
Multiplexed with KR4 through
KR7 pins.
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µPD754302, 754304, 754302(A), 754304(A)
6.2 Clock Generator
Clock generator configuration
The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration
is shown in Figure 6-1.
The operation of the clock generator is set with the processor clock control register (PCC).
The instruction execution time can be changed.
• 0.95, 1.91, 3.81, 15.3 µs (system clock operating at 4.19 MHz)
• 0.67, 1.33, 2.67, 10.7 µs (system clock operating at 6.0 MHz)
Figure 6-1. Clock Generator Block Diagram
X1
System
fX
clock oscillator
X2
Oscillation
stop
PCC
PCC0
PCC1
4
PCC2
HALTNote
PCC3
STOPNote
· Basic interval timer (BT)
· Timer/event counters 0, 1
· Serial interface
· INT0 noise eliminator
· Clock output circuit
1/2 1/4 1/16
1/1 to 1/4096
Divider
Selector
Divider
1/4 Φ
· CPU
· INT0 noise eliminator
· Clock output circuit
HALT F/F
S
RQ
PCC2,
PCC3
Clear
STOP F/F
QS
R
Note Instruction execution
Wait signal from BT
RESET signal
Standby release signal from
interrupt control circuit
Remarks 1.
2.
3.
4.
fX = System clock frequency
Φ = CPU clock
PCC: Processor Clock Control Register
One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.
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µPD754302, 754304, 754302(A), 754304(A)
6.3 Clock Output Circuit
The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to apply for remote controller
waveform output or to supply clock pulse peripheral LSIs.
• Clock output (PCL) : Φ, 524, 262, 65.5 kHz (during 4.19-MHz operation)
Φ, 750, 375, 93.8 kHz (during 6.0-MHz operation)
Figure 6-2. Clock Output Circuit Block Diagram
From clock
generator
Φ
fX/23
fX/24
fX/26
Selector
Output buffer
PCL/P22
CLOM3 0 CLOM1 CLOM0 CLOM
PORT2.2
P22
output latch
Bit 2 of PMGB
Port 2 I/O mode
specification bit
4
Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output
when switching clock output enable/disable.
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µPD754302, 754304, 754302(A), 754304(A)
6.4 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions.
• Interval timer operation to generate a reference time interrupt
• Watchdog timer operation to detect a runaway of program and reset the CPU
• Selects and counts the wait time when the standby mode is released
• Reads the contents of counting
Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram
From clock
generator
fX/25
Clear
fX/27
fX/29
fX/212
MPX
Basic interval timer
(8-bit frequency divider)
BT
3
BTM3 BTM2 BTM1 BTM0 BTM
Wait release signal
when standby is
released.
WDTM
SET1 Note
4
8
Internal bus
1
Clear
BT
Set interrupt
request flag Vectored
interrupt
IRQBT request signal
SET1 Note
Internal reset
signal
Note Instruction execution
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µPD754302, 754304, 754302(A), 754304(A)
6.5 Timer/Event Counter
The µPD754304 has two channels of timer/event counters. Its configuration is shown in Figures
6-4 and 6-5.
The timer/event counter has the following functions.
• Programmable interval timer operation
• Square wave output of any frequency to the PTOn pin (n = 0, 1)
• Event counter operation
• Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided
frequency to the PTOn pin (frequency divider operation).
• Supplies the shift clock to the serial interface circuit.
• Reads the count value.
The timer/event counter operates in the following two modes as set by the mode register.
Table 6-2. Operation Modes of Timer/Event Counter
Mode
8-bit timer/event counter mode
16-bit timer/event counter mode
Channel
Channel 0 Channel 1
√√
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Figure 6-4. Timer/Event Counter (Channel 0) Block Diagram
PORT1.3
8
TM0
TM06 TM05 TM04 TM03 TM02 TM01 TM00
Decoder
Input buffer
TI0/TI1/P13
fX/22
From clock fX/24
generator fX/26
fX/28
fX/210
MPX
Internal bus
8
TMOD0
Modulo register (8)
8 Match
Comparator (8)
8 T0
Count register (8)
CP
Clear
TOUT
F/F
Reset
16-bit timer/event counter mode
Timer operation start
Timer/event counter
(channel 1) TM12 signal
(When 16-bit timer/event
counter mode)
Timer/event counter
(channel 1) match signal
(When 16-bit timer/event
counter mode)
Timer/event counter
(channel 1) clear signal
(When 16-bit timer/event
counter mode)
TOE0
PORT 2.0 Bit 2 of PMGB
T0 P20
enable flag output latch
Port 2
I/O mode
Overflow
Output buffer
P20/PTO0
To serial interface
Timer/event counter
(channel 1) clock input
INTT0
IRQT0
set signal
IRQT0 clear signal
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Figure 6-5. Timer/Event Counter (Channel 1) Block Diagram
PORT1.3
8
TM1
— TM16 TM15 TM14 TM13 TM12 TM11 TM10
Decoder
Input buffer
TI0/TI1/P13
Timer/event counter (channel 0) output
fX/22
From clock fX/26
generator fX/28
fX/210
fX/212
MPX
CP
Internal bus
8
TMOD1
Modulo register (8)
8
Match
Comparator (8)
8
Count register (8)
Clear
T1
TOE1
T1
enable flag
TOUT
F/F
Reset
Timer operation start
16 bit timer/event counter mode
Selector
Timer/event counter (channel 0) TM02 signal
(When 16 bit timer/event counter mode)
Timer/event counter (channel 0)
match signal/operation start
(When 16-bit timer/event counter mode)
Timer/event counter (channel 0) comparator
(When 16-bit timer/event counter mode)
PORT2.1 Bit 2 of PMGB
P21
output latch
Port 2
input/output
mode
P21/PTO1
Output buffer
RESET
IRQT1 clear signal
INTT1
IRQT1
set signal


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µPD754302, 754304, 754302(A), 754304(A)
6.6 Serial Interface
The µPD754304 incorporates the clocked 8-bit serial interface, and the following three modes are provided.
• Operation stop mode
• 3-wire serial I/O mode
• 2-wire serial I/O mode
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P03/SI
P02/SO/SB0
P01/SCK
Figure 6-6. Serial Interface Block Diagram
8/4 Bit test
CSIM
Selector
Internal bus
8
88
Slave address register (SVA) (8)
Bit manipulation
SBIC
Address comparator
Matching RELT
signal
(8)
CMDT
Shift register (SIO)
SET CLR SO latch
D
(8)
Q
P01
output Iatch
Serial clock counter
Serial clock control
circuit
INTCSI
control circuit
Serial clock
selector
INTCSI
IRQCSI
set signal
fX/23
fX/24
fX/26
TOUT F/F
(from timer/event counter 0)
External SCK


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µPD754302, 754304, 754302(A), 754304(A)
6.7 Bit Sequential Buffer ....... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be
easily performed by changing the address specification and bit specification in sequence, therefore it is useful
when processing a long data bit-wise.
The data memory is composed of 16 bits and the pmem.@L addressing of a bit manipulation instruction is
possible. The bit can be specified indirectly by the L register. In this case, processing can be done by moving the
specified bit in sequence by incrementing and decrementing the L register in the program loop.
Figure 6-7. Bit Sequential Buffer Format
Address
Bit
Symbol
FC3H
FC2H
FC1H
FC0H
3 2 10 3 2 10 32 10 32 10
BSB3
BSB2
BSB1
BSB0
L register L = FH
L = CH L = BH
L = 8H L = 7H
L = 4H L = 3H
DECS L
INCS L
L = 0H
Remarks 1. In the pmem.@L addressing, the specified bit moves corresponding to the L register.
2. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification.
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µPD754302, 754304, 754302(A), 754304(A)
7. INTERRUPT FUNCTION AND TEST FUNCTION
The µPD754304 has seven kinds of interrupt sources and one kind of test source. Two types of edge detection
testable inputs are provided for INT2 of the test source.
The interrupt control circuit of the µPD754304 has the following functions.
(1) Interrupt function
• Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the
interrupt enable flag (IE×××) and interrupt master enable flag (IME).
• Can set any interrupt start address.
• Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register
(IPS).
• Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software.
• Release the standby mode. A release interrupt can be selected by the interrupt enable flag.
(2) Test function
• Test request flag (IRQxxx) generation can be checked by software.
• Release the standby mode. The test source to be released can be selected by the test enable flag.
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