XRD5412 (Exar Corporation)
5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
5V, Low Power, Voltage Output
Serial 8/10/12-Bit DAC Family
FEATURES
D 8/10/12-Bit Resolution
D Operates from a Single 5V Supply
D Buffered Voltage Output: 13ms Typical Settling Time
D 240mW Total Power Consumption (typ)
D Guaranteed Monotonic Over Temperature
D Flexible Output Range: 0V to VDD
D 8 Lead SOIC and PDIP Package
D Power On Reset
D Serial Data Output for Daisy Chaining
APPLICATIONS
D Digital Calibration
D Battery Operated Instruments
D Remote Industrial Devices
D Cellular Telephones
D Motion Control
May 2000-2
GENERAL DESCRIPTION
The XRD5408/10/12 are low power, voltage output
digital-to-analog converters (DAC) for +3V power supply
operation. The parts draw only 70mA of quiescent current
and are available in both an 8-lead PDIP and SOIC
package.
The XRD5408/10/12 have a 3 wire serial port with an
output allowing the user to daisy chain several of them
together. The serial port will support both Microwiret,
SPIt, and QSPIt standards.
The outputs of the XRD5408/10/12 are set at a gain of +2.
The output short circuit current is 7mA typical.
ORDERING INFORMATION
Part No.
XRD5408AID
XRD5408AIP
XRD5410AID
XRD5410AIP
XRD5412AID
XRD5412AIP
Package
8 Lead 150 Mil JEDEC SOIC
8 Lead 300 Mil PDIP
8 Lead 150 Mil JEDEC SOIC
8 Lead 300 Mil PDIP
8 Lead 150 Mil JEDEC SOIC
8 Lead 300 Mil PDIP
Operating
Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Rev. 1.20
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017


XRD5412 (Exar Corporation)
5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
BLOCK DIAGRAM
VREFIN
AGND
CS
SCLK
SDIN
2n Switch
Matrix
R
+
-
VOUT
R
VDD VDD
Shift Register
DOUT
Power On
Reset
Figure 1. Block Diagram
PIN CONFIGURATION
SDIN
SCLK
CS
DOUT
1
2
3
4
8 VDD
7 VOUT
6 VREFIN
5 AGND
8 Lead SOIC (Jedec, 0.150”)
SDIN
SCLK
CS
DOUT
1
2
3
4
8 VDD
7 VOUT
6 VREFIN
5 AGND
8 Lead PDIP (0.300”)
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
Symbol
SDIN
SCLK
CS
DOUT
AGND
VREFIN
VOUT
VDD
Rev. 1.20
Description
Serial Data Input
Serial Data Clock
Chip Select (Active High)
Serial Data Output
Analog Ground
Voltage Reference Input
DAC Output
Supply Voltage
2


XRD5412 (Exar Corporation)
5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
ELECTRICAL CHARACTERISTICS
Test Conditions: VDD= 5V, GND= 0V, REFIN= 2.048V (External), RL= 10kW, CL= 100pF, TA= TMIN to TMAX,
Unless Otherwise Noted.
Symbol Parameter
Static Performance XRD5408
N Resolution
INL Relative Accuracy
DNL Differential Nonlinearity
VOS
TCVOS
PSRR
Offset Error
Offset Tempco
Offset-Error Power-Supply
Rejection Ratio
GE Gain Error
TCGE Gain-Error Tempco
PSRR
Power-Supply
Rejection Ratio
Static Performance XRD5410
N Resolution
INL Relative Accuracy
DNL Differential Nonlinearity
VOS
TCVOS
PSRR
Offset Error
Offset Tempco
Offset-Error Power-Supply
Rejection Ratio
GE Gain Error
TCGE Gain-Error Tempco
PSRR
Power-Supply
Rejection Ratio
Static Performance XRD5412
N Resolution
INL Relative Accuracy
DNL Differential Nonlinearity
VOS
TCVOS
PSRR
GE
TCGE
PSRR
Offset Error
Offset Tempco
Offset-Error Power-Supply
Rejection Ratio
Gain Error
Gain-Error Tempco
Power-Supply
Rejection Ratio
Min. Typ. Max. Unit Conditions
8 Bits
0.25 0.5
LSB
0.25 0.5 ±LSB Guaranteed Monotonic
0 3 8 mV
2 ppm/°C
0.5 1 mV 4.5V ± VDD ± 5.5V
0.1 0.4 %FS
10 ppm/°C
0.1 1.25 mV 4.5V ± VDD ± 5.5V, Measured at
FS
10 Bits
0.5 1 LSB
0.25 0.5 ±LSB Guaranteed Monotonic
0 3 8 mV
2 ppm/°C
0.5 1 mV 4.5V ± VDD ± 5.5V
0.1 0.4 %FS
10 ppm/°C
0.1 1.25 mV 4.5V ± VDD ± 5.5V, Measured at
FS
12 Bits
2 4 LSB
0.5 -1 LSB Guaranteed Monotonic
+1.25 LSB
0 3 8 mV
2 ppm/°C
0.5 1 mV 4.5V ± VDD ± 5.5V
0.1 0.4 %FS
10 ppm/°C
0.1 1.25 mV 4.5V ± VDD ± 5.5V, Measured at
FS
Rev. 1.20
3


XRD5412 (Exar Corporation)
5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: VDD= 5V, GND= 0V, REFIN= 2.048V (External), RL= 10kW, CL= 100pF, TA= TMIN to TMAX,
Unless Otherwise Noted.
Symbol Parameter
Min. Typ. Max. Unit Conditions
Voltage Output (VOUT) XRD5408/10/12
VO Output Voltage Range
0
VREG Output Load Regulation
+ISC Short-Circuit Current, Sink
-ISC Short-Circuit Current, Source
Voltage Reference Input (VREFIN) XRD5408/10/12
VREFIN Voltage Range
0
RIN Input Resistance
40
TCRIN Input Resistance Tempco
CIN Input Capacitance
ACFT AC Feedthrough
Digital Inputs (SDIN, SCLK, CS) XRD5408/10/12
VDD--0.4
V
2 4 mV VOUT = 2V, RL=2kW
13 mA VOUT = VDD
7 mA VOUT = GND
65
1500
32
-80
VDD V Output Swing Limited, Not Code Dependent
kW
ppm/°C
40 pF Not Code Dependent
dB REFIN = 1kHz, 2Vp-p, SDIN=000h
VIH Input High
VIL Input Low
IIN Input Current
CIN Input Capacitance
Digital Output (DOUT) XRD5408/10/12
3.5 V
1V
±1 mA VIN=0V or VDD
10 pF
VOH Output High
VOL Output Low
Dynamic Performance XRD5408/10/12
VDD-1
V ISOURCE=4mA
0.4 V ISINK=4mA
SR Voltage-Output Slew Rate
0.13 0.21
V/ms TA=+25°C
ts Voltage-Output Settling Time
13 15 ms ±1/2LSB, VOUT=2V
DFT Digital Feedthrough
1 nV-s CS=VDD, SDIN=SCLK=100kHz
SINAD Signal-to-Noise Plus Distortion
68
dB VREFIN=1kHz, 2Vp-p F.S., SDIN=Full
Scale, --3dB BW=250kHz
Power Supply XRD5408/10/12
VDD Positive Supply Voltage
4.5
5.5 V
IDD Power Supply Current
35
60
mA
All Inputs=0V or VDD, Output=No
IREF Not Included, VO=0V (Note
Load,
1)
Switching Characteristics XRD5408/10/12
tCSS
tCSH0
tCSH1
tCH
tCL
CS Setup Time
SCLK Fall to CS Fall Hold Time
SCLK Fall to CS Rise Hold TIme
SCLK High Width
SCLK Low Width
10
5
0
20
20
20
35
35
ns
ns
ns
ns
ns
Notes:
1 Total supply current consumption = IDD + IREF + (VO / 70K.)
Rev. 1.20
4


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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: VDD= 5V, GND= 0V, REFIN= 2.048V (External), RL= 10kW, CL= 100pF, TA= TMIN to TMAX,
Unless Otherwise Noted.
Symbol
tDS
tDH
tDO
tCSW
tCS1
Parameter
DIN Setup Time
DIN Hold Time
DOUT Valid Propagation Delay
CS High Pulse Width
CS Rise to SCLK Rise Setup
Time
Min.
10
0
20
10
Typ. Max.
45
8 15
40
20
Unit Conditions
ns
ns
ns CL= 50pF
ns
ns
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, +7V
Digital Input Voltage to GND . . . . . . -0.3V, VDD +0.3V
VREFIN . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, VDD +0.3V
VOUT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD, GND
Continuous Current, Any Pin . . . . . . . . -20mA, +20mA
Package Power Dissipation Ratings (TA= +70°C)
PDIP (derate 9mW/°C above +70°C) . . . . 117mW
SOIC (derate 6mW/°C above +70°C) . . . 155mW
Operating Temperature Range . . . . . -40°C to + 85°C
Storage Temperature Range . . . . . . -65°C to +165°C
Lead Temperature (soldering, 10 sec) . . . . . . +300°C
Notes
1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100ms.
Rev. 1.20
5


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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
TIMING
CS
tCSH0
SCLK
SDIN
tDS
DOUT
tCSS
tCH
tDH
tCL
tD0
Figure 2. Timing Diagram
tCSH1
tCSW
tCS1
1111
1000
1000
0111
0000
Input
1111
0001
0000
1111
0001
(0000)
(0000)
(0000)
(0000)
(0000)
Output
+2
(VREFIN)
255
256
+2
(VREFIN)
129
256
+
2
(VREFIN)
128
256
=
+
VREFIN
+
2
(VREFIN)
127
256
+
2
(VREFIN)
1
256
0000
0000
(0000)
0V
Note:
Write 8-bit data words with four sub-LSB 0s because the DAC input latch
is 12 bits wide.
Table 1. Binary Code Table
Rev. 1.20
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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
THEORY OF OPERATION
XRD5408/10/12 Description
The XRD5408/10/12 are micro-power, voltage output,
serial daisy-chain programmable DACs operating from a
single 5V power supply. The DACs are built on a 0.6
micron CMOS process. The features of these DACs
make it well suited for industrial control, low distortion
audio, battery operated devices and cost sensitive
designs that want to minimize pin count on ICs.
Resistor String DAC
A resistor string architecture converts digital data using a
switch matrix to an analog signal as shown in Figure 3.
VREFIN
AGND
CS
SCLK
SDIN
2n Switch
Matrix
R
+
-
VOUT
R
VDD VDD
Shift Register
Power On
Reset
DOUT
Figure 3. XRD5408/10/12 DAC Architecture
The resistor string architecture provides a non-inverted
output voltage (VOUT) of the reference input (VREFIN) for
single supply operation while maintaining a constant input
resistance. Unlike inverted R-2R architectures the
reference input resistance will remain constant
independent of code. This greatly simplifies the analog
driving source requirements for the reference voltage and
minimizes distortion. Similarly input capacitance varies
only approximately 4pF over all codes.
Fixed Gain +2 Voltage Output Amplifier
A high open-loop gain operational amplifier buffers the
resistor string with a stable, fixed gain of +2. The voltage
output will settle within 13 s. The output is short circuit
protected and can regulate an output load of 2V into 2k
within 2mV at 25°C.
While the reference input will accept a voltage from
rail-to-rail, the linear input voltage range is constrained by
the output swing of the fixed +2 closed-loop gain amplifier.
Full scale output swing is achieved with an external
reference of approximately 1/2 VDD. The reference
voltage must be positive because the XRD5408/10/12
DAC is non-inverting.
Serial Daisy-Chainable Digital Interface
The three wire serial interface includes a DOUT to enable
daisy-chaining of several DACs. This minimizes pin
count necessary of digital asics or controllers to address
multiple DACS. The serial interface is designed for
CMOS logic levels. Timing is shown in Figure 2. The
binary coding table (Table 1) shows the DAC transfer
function.
A power on reset circuit forces the DAC to reset to all “0”s
on power up.
APPLICATION NOTES
Serial Interface
The XRD5408/10/12 family has a three wire serial
interface that is compatible with Microwiret, SPIt and
QSPIt standards. Typical configurations are shown in
Figure 4 and Figure 5. Maximum serial port clock rate is
limited by the minimum pulse width of tCH and tCL.
Feedthrough noise from the serial port to the analog
output (VOUT) is minimized by lowering the frequency of
the serial port and holding the digital edges to >5ns.
Rev. 1.20
7


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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
SK
Microwiret
Port
SO
I/O
+5V
MP5010
1.25V
VREFIN
SCLK
XRD5412
SDIN
VOUT
CS
GND
VDD
0-2.5V
0.1mF
+5V
Figure 4. Typical Microwiret Application Circuit
Rev. 1.20
SK
SPI t
Port
MOSI
I/O
+5V
MP5010
1.25V
VREFIN
SCLK
XRD5410
SDIN
VOUT
CS
GND
VDD
0-2.5V
0.1mF
+5V
Figure 5. Typical SPIt Application Circuit
8


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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
DAC
n
SDIN
Figure 6. Shift Register Format
MSB X X X X
DOUT
The DACs are programmed by a 16 bit word of serial data.
The format of the serial input register is shown in Figure 6.
The leading 4 bits are not used to update the DAC. If the
DAC is not daisy-chained then only a 12 bit serial word is
needed to program the DAC. The next 8, 10 or 12 bits
after the 4 leading bits are data bits. The XRD5408’s first
8 bits are valid data and the trailing 4 bits must be set to 0.
Figure 7 demonstrates the 16 bit digital word for the 8,
10,12 bit DACs.
Part
XRD5412
XRD5410
XRD5408
Leading
Unused
Bits
XXXX
XXXX
XXXX
Data Bits
MSB
LSB
XXXXXXXX
XXXXXXXX
XXXXXXXX
Trailing
“0”
Bits
None
00
0000
Table 2. 16-Bit Digital Word Register for XRD5408,
XRD5410, XRD5412.
ACFT Feedthrough (DAC Code = 0)
AC Feedthrough from VREFIN to VOUT is minimized with
low impedance grounding as shown in Figure 7. If the
DAC data is set to all “0”s then VOUT is a function of the
divider between the DAC string impedance and ground
impedance. See the Power Supply and Grounding
section for recommendations. The typical AC
feedthrough for a 1kHz 2Vpp signal with code = 0 is
-80dB.
VREFIN
RIN
XRD5408/10/12
--
VOUT
+
SCLK should be held low when CS transitions low. Data is
clocked in on the rising edge of SCLK when CS is low.
SDIN data is held in a 16 bit serial shift register. The DAC
is updated with the data bits on the rising edge of CS.
When CS is high data is not shifted into the
XRD5408/10/12.
Daisy-Chaining
The digital output port (DOUT) has a 4mA drive for greater
fan-out capability when daisy-chaining. DOUT allows
cascading of multiple DACs with the same serial data
stream. The data at SDIN appears at DOUT after 16 clock
cycles plus one clock width (tCH) and a propagation delay
(tDO). DOUT remains in the state of the last data bit when
CS is high. DOUT changes on the falling edge of SCLK
when CS is low.
Any number of DACs can be connected in this way by
connecting DOUT of one DAC to SDIN of the next DAC.
GND
RGND
Analog GND
Figure 7. ACFT Feedthrough Equivalent
Circuit, DAC Code =0
Compatible with MAX515 & MAX539
The XRD5408/10/12 family of DACs are functionally
campatible with the MAX515 & MAX539 while providing
significant improvements. The XRD5408/10/12 DACs
have lower power, faster serial ports, and a constant
reference impedance to minimize the reference driving
requirements and maximize system linearity. The DOUT
Rev. 1.20
9


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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
port also has 4mA driving capability for greater fan-out
when daisy-chaning to other digital inputs.
Monotonicity
The XRD5408/10/12 family of DACs are monotonic over
the entire temperature range.
Micro-Power Operation
The XRD5408 is the lowest power in their class. The
quiescent current rating does not include the reference
ladder current. Power can be saved when the part is not in
use by setting the DAC code to all “0”s assuming the
output load is referenced to ground. This minimizes the
DAC output load current. An analog switch placed in
series with the reference ladder can toggle the reference
voltage off when the circuit is inactive to minimize power
consumption.
PERFORMANCE CHARACTERISTICS
Power Supply and Grounding
Best parametric results are obtained by powering the
XRD5408/10/12 family of DACs from an analog +5V
power supply and analog ground. Digital power supplies
and grounds should be separated or connected to the
analog supplies and grounds only at the low-impedance
power-supply source. This is best accomplished on a
multilayer PCB with dedicated planes to ground and
power. The DACs should be locally bypassed with both
0.1 F and 2.2 F capacitors mounted as close as possible
to the power supply pin (VDD). Surface mount ceramic
capacitors are recommended for low impedance, wide
band power supply bypass. If only one +5V power supply
is available for both analog and digital circuity isolate the
analog power supply to the XRD5408/10/12 DAC with an
inductor or ferrite bead before the local bypass
capacitors.
0.4
0.2
0
--0.2
0
0.35
64 128 192
CODE
Figure 8. XRD5408 INL
255
0.2
Rev. 1.20
0.0
--0.1
0
64 128 192
CODE
Figure 9. XRD5408 DNL
255
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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
0
1mA/div
10
0
0.5V/div
VOUT (V)
Figure 10. Output Source Current
vs. Output Voltage
--15
5
1.5mA/div
0
0 0.1V/div
VOUT (V)
Figure 11. Output Sink Current
vs. Output Voltage
--14
1
Rev. 1.20
2mA/div
0
7
5 0.1V/div
VOUT (V)
Figure 12. Output Sink and Source Cur-
rent vs. Output Volatge
0
11


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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
VOUT
CS
Figure 13. Voltage Output Settling Time (ts),
VDD = 5V, VREFIN = 1V, No Load
Rev. 1.20
40
38
36
34
32
30
28
26
24
22
20
-40
-20
0 20 40 60 80 100
Temp (°C)
Figure 14. IDD vs. Temperature
12


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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
8
7
6
5
4
3
2
1
0
-1
-2
10
100
Frequency (KHz)
1000
Figure 15. Closed Loop Gain vs. Frequency
0
-20
-40
-60
-80
-100
-120
10
100
Frequency (KHz)
1000
Figure 16. Closed Loop Phase vs. Frequency
Microwiret is a trademark of National Semiconductor Corproation.
SPIt and QSPIt are trademarks of Motorola Corporation.
Rev. 1.20
13


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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
8 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
Rev. 1.00
D
85
EH
4
Seating
Plane
A1
eB
C
A
a
L
Rev. 1.20
INCHES
MILLIMETERS
SYMBOL
MIN MAX
MIN MAX
A
0.053 0.069
1.35 1.75
A1
0.004 0.010
0.10 0.25
B
0.013 0.020
0.33 0.51
C
0.007 0.010
0.19 0.25
D
0.189 0.197
4.80 5.00
E
0.150 0.157
3.80 4.00
e
0.050 BSC
1.27 BSC
H
0.228 0.244
5.80 6.20
L
0.016 0.050
0.40 1.27
a
0° 8°
0° 8°
Note: The control dimension is the millimeter column
14


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5V/ Low Power/ Voltage Output Serial 8/10/12-Bit DAC Family

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XRD5408/10/12
8 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 2.00
Seating
Plane
A
L
85
1 4 E1
D
A2
A1
B e B1
E
aC
eA
eB
INCHES
MILLIMETERS
SYMBOL
MIN MAX
MIN MAX
A
0.145 0.210
3.68 5.33
A1
0.015 0.070
0.38 1.78
A2
0.115 0.195
2.92 4.95
B
0.014 0.024
0.36 0.56
B1
0.030 0.070
0.76 1.78
C
0.008 0.014
0.20 0.38
D
0.348 0.430
8.84 10.92
E
0.300 0.325
7.62 8.26
E1
0.240 0.280
6.10 7.11
e
0.100 BSC
2.54 BSC
eA
0.300 BSC
7.62 BSC
eB
0.310 0.430
7.87 10.92
L
0.115 0.160
2.92 4.06
a
0° 15°
0°
Note: The control dimension is the inch column
15°
Rev. 1.20
15


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XRD5408/10/12
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
All trademarks and registered trademarks are property of their respective owners.
Copyright 2000 EXAR Corporation
Datasheet May 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.20
16




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