CXD1186CQ (Sony Corporation)
CD-ROM Decoder

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CXD1186CQ/CR
CD-ROM Decoder
For the availability of this product, please contact the sales office.
Description
The CXD1186C is a CD-ROM decoder LSI.
CXD1186CQ
80 pin QFP (Plastic)
CXD1186CR
80 pin LQFP (Plastic)
Features
Corresponds to CD-ROM, CD-I and CD-ROM XA
formats.
Real time error correction. (Erasure correction
using C2 pointer from CD player.)
Double speed playback.
Connection to standard SRAM up to 64 K bytes, as
buffer memory, possible.
Applications
CD-ROM driver
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta=25 °C)
Supply voltage
VDD –0.5 to +7.0 V
Input voltage
VI –0.5 to VDD +0.5 V
Output voltage
VO –0.5 to VDD +0.5 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions
Supply voltage
VDD +4.5 to +5.5 V
(standard +5.0)
Operating temperature Topr –20 to +75 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E93512A78-TE


CXD1186CQ (Sony Corporation)
CD-ROM Decoder

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Block Diagram
DATA
BCLK
C2PO
LRCK
DB0–7
A0–3
XWR
XRD
XCS
INT
CDP I/F
CONTROL REG
REGISTERS
ECC
CONTROL
DESCRAMBLE
SYNC
CONTROL
TIMING GEN
S/P
WORD CENTER
DECODE
DRIIVE ADDRESS
COUNTER
LATCH
GALOIS FIELD
REG
SYNDROME
REG
CPU
I/F
PRIORITY
RESOLVER
HOST DMA
HOST I/F REGS
DMA
SEQUENCER
CPU DMA
HOST ADDRESS
COUNTER
DMA FIFO
ADP I/F
HOST I/F REGS
+2
CXD1186CQ/CR
XRST
BA0–15
XMWR
XMOE
BDB0–7, P
GND
VDD
—2—


CXD1186CQ (Sony Corporation)
CD-ROM Decoder

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CXD1186CQ/CR
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
65 LRCK
66 DATA
67 BCLK
68 C2PO
69 DB0
70 DB1
71 DB2
72 DB3
73 VDD
74 DB4
75 DB5
76 DB6
77 DB7
78 XCS
79 XRD
80 XWR
CXD1186CQ
BA8 40
BA7 39
BA6 38
BA5 37
BA4 36
BA3 35
BA2 34
VDD 33
BA1 32
BA0 31
XAAC 30
ADRQ 29
XTC 28
XHAC 27
HDRQ 26
XRST 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61 GND
62 HCLK
63 LRCK
64 DATA
65 BCLK
66 C2PO
67 DB0
68 DB1
69 DB2
70 DB3
71 VDD
72 DB4
73 DB5
74 DB6
75 DB7
76 XCS
77 XRD
78 XWR
79 INT
80 GND
CXD1186CR
GND 40
BA9 39
BA8 38
BA7 37
BA6 36
BA5 35
BA4 34
BA3 33
BA1 32
VDD 31
BA1 30
FA0 29
XAAC 28
ADRQ 27
XTC 26
XHAC 25
HDRQ 24
XRST 23
HDRP 22
GND 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
—3—


CXD1186CQ (Sony Corporation)
CD-ROM Decoder

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CXD1186CQ/CR
Pin Description
Pin No.
CXD1186CQ CXD1186CR
1 79
2 80
31
42
53
64
75
86
97
10 8
11 9
12 10
13 11
14 12
15 13
16 14
17 15
18 16
19 17
20 18
21 19
22 20
23 21
24 22
25 23
Symbol
INT
GND
A0
A1
A2
A3
HMDS
HA0
HA1
XHCS
HINT
GND
XHRD
XHWR
HDB0
HDB1
HDB2
HDB3
HDB4
HDB5
HDB6
HDB7
GND
HDBP
XRST
26 24 HDRQ
27 25 XHAC
28 26 XTC
29 27 ADRQ
30 28 XAAC
31 29 BA0
32 30 BA1
33 31 VDD
34 32 BA2
35 33 BA3
36 34 BA4
37 35 BA5
38 36 BA8
39 37 BA7
I/O Description
O Interrupt request signal to CPU
— GND pin
I CPU address signal
I CPU address signal
I CPU address signal
I CPU address signal
I Host mode select signal
I Host address signal
I Host address signal
I Chip select negative logic signal from host
O Interrupt request negative logic signal to host
— GND pin
I/O Data read strobe signal from host or to SCSI control IC
I/O Data write strobe signal from host or to SCSI control IC
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
I/O Host data bus
— GND pin
I/O Error flag, Host data bus
I Reset negative logic signal
Data request positive logic signal to host. Or DMA
O
acknowledge negative logic signal to SCSI control IC
DMA acknowledge negative logic signal from host.
I
Or data request positive logic signal from SCSI control IC
I Terminal count negative logic signal
I DMA request positive logic signal from ADP
O DMA acknowledge negative logic signal to ADP
O Buffer memory address
O Buffer memory address
— Power (+5 V) supply pin
O Buffer memory address
O Buffer memory address
O Buffer memory address
O Buffer memory address
O Buffer memory address
O Buffer memory address
—4—


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CD-ROM Decoder

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CXD1186CQ/CR
Pin No.
CXD1186CQ CXD1186CR
40 38
41 39
42 40
43 41
44 42
45 43
46 44
47 45
48 46
49 47
50 48
51 49
52 50
53 51
54 52
55 53
56 54
57 55
58 56
59 57
60 58
61 59
62 60
63 61
64 62
65 63
66 64
67 65
68 66
69 67
70 68
71 69
72 70
73 71
74 72
75 73
76 74
77 75
78 76
Symbol
BA8
BA9
GND
BA10
BA11
BA12
BA13
BA14
BA15
XMOE
XMWR
BDB0
GND
BDB1
BDB2
BDB3
BDB4
BDB5
BDB6
BDB7
BDBP
XTL2
XTL1
GND
HCLK
LRCK
DATA
BCLK
C2PO
DB0
DB1
DB2
DB3
VDD
DB4
DB5
DB6
DB7
XCS
79 77 XRD
80 78 XWR
I/O Description
O Buffer memory address
O Buffer memory address
— GND pin
O Buffer memory address
O Buffer memory address
O Buffer memory address
O Buffer memory address
O Buffer memory address
O Buffer memory address
O Buffer memory output enable negative logic signal
O Buffer memory write negative logic signal
I/O Buffer memory data bus
— GND pin
I/O Buffer memory data bus
I/O Buffer memory data bus
I/O Buffer memory data bus
I/O Buffer memory data bus
I/O Buffer memory data bus
I/O Buffer memory data bus
I/O Buffer memory data bus
I/O Buffer memory pointer data bus
O Crystal oscillation circuit output pin
I Crystal oscillation circuit input pin
— GND pin
O 1/2 frequency divided clock signal of XTL1
I LR clock from CD player
I Serial data from CD player
I Bit clock from CD player
I C2 pointer from CD player
I/O CPU data bus
I/O CPU data bus
I/O CPU data bus
I/O CPU data bus
— Power (+5 V) supply pin
I/O CPU data bus
I/O CPU data bus
I/O CPU data bus
I/O CPU data bus
I Chip select negative logic signal from CPU
CPU strobe negative logic signal to read out this IC internal
I
register
CPU strobe negative logic signal to write in this IC internal
I
register
—5—


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CD-ROM Decoder

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CXD1186CQ/CR
Electrical Characteristics
DC characteristics
Item
Input voltage
H level
L level
TTL Schmitt hysterisis
Input current of pull up input
Input current of pull down input
Output voltage
H level
L level
Open drain output L level
Oscillation cell
H level
input voltage
L level
Logic threshold value
Feedback resistance
Output voltage
H level
L level
(VDD=5 V±10 %, VSS=0 V, Topr=–20 to +75 °C)
Symbol
Conditions
VIH1
VIL1
(Vt+)–(Vt–)
IIL VIL=0 V
IIH VIH=VDD
VOH1 IOH=–2 mA
VOL1 IOL=4 mA
VOL2 IOL=4 mA
VIH
VIL
LVth
RFB VIN=VSS or VDD
VOH IOH=–1 mA
VOL IOL=1 mA
Min.
2.2
0.2
–40
40
VDD–0.8
0.7 VDD
250 k
VDD/2
Typ.
0.4
–100
100
VDD/2
1M
Max.
0.8
–240
240
0.4
0.4
0.3 VDD
2.5 M
VDD/2
Unit
V
V
V
µA
µA
V
V
V
V
V
V
V
V
Input pin with pull up resistance
Input pin with pull down resistance
TTL Schmitt input pin
Open drain output pin
Two-way data bus always pulled up.
Oscillation cell
Input
Output
: XHCS, HA0, HA1, XTC
: C2PO, HMDS, ADRQ
: XRST
: HINT
: XTL1
: XTL2
I/O capacitance
Item
Input pin
Output pin
I/O pin
Symbol
CIN
COUT
CI/O
Min.
Typ.
VDD=VI=0 V, f=1 MHz
Max.
9
11
11
Unit
pF
pF
pF
—6—


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CD-ROM Decoder

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CXD1186CQ/CR
AC characteristics
1. CPU interface
(1) Read
(Ta=–20 to +75 °C, VDD=5 V±10 %, Output Load=50 pF, f24.576 MHz)
A0 to 3
XCS
XRD
DB0 to 7
tSAR
tRRL
tDRD
tHRA
tFRD
Item
Address setup time (vs. XCS & XRD )
Address hold time (vs. XCS & XRD )
Data delay time (vs. XCS & XRD )
Data float time (vs. XCS & XRD )
Low level XRD pulse width
Symbol
tSAR
tHRA
tDRD
tFRD
tRRL
Min.
30
20
0
100
Typ.
Max.
60
10
Unit
n
n
n
n
n
(2) Write
A0 to 3
XCS
XWR
DB0 to 7
tSAW
tWWL
tHWA
tSDW tHWD
Item
Address setup time (vs. XCS & XWR )
Address hold time (vs. XCS & XWR )
Data setup time (vs. XCS & XWR )
Data hold time (vs. XCS & XWR )
Low level XWR pulse width
Symbol
tSAW
tHWA
tSDW
tHWD
tWWL
Min.
30
20
40
10
50
Typ.
Max.
Unit
n
n
n
n
n
Where & in the chart indicates logical multiplication.
—7—


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CD-ROM Decoder

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2. Memory interface
(1) Read
CXD1186CQ/CR
BA0 to 15
XMOE
BDB0 to 7, P
tSAO
tRRL
tHOA
tSDO
tHOD
Item
Address setup time (vs. XMOE )
Address hold time (vs. XMOE )
Data setup time (vs. XMOE )
Data hold time (vs. XMOE )
Low level XMOE pulse width
(2) Write
Symbol
tSAO
tHOA
tSDO
tHOD
tRRL
Min.
Tw–22
Tw–9
45
0
2 • Tw
Typ. Max. Unit
n
n
n
n
2•Tw+16 n
BA0 to 15
XMWR
BDB0 to 7, P
tSAW
tDWD
tWWL
tHWA
tFWD
Item
Address setup time (vs. XMWR )
Address hold time (vs. XMWR )
Data delay time (vs. XMWR )
Data float time (vs. XMWR )
Low level XMWR pulse width
Symbol
tSAW
tHWA
tDWD
tFWD
tWWL
Min.
Tw–29
Tw–9
10
2 • Tw
Typ.
Where Tw=1/f.
Usually, when f=16.9344 MHz, use a RAM with access time within 120 ns.
Max.
0
Unit
n
n
n
n
n
—8—


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CD-ROM Decoder

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CXD1186CQ/CR
3. Host interface
(1) Read
HA0 to 1
XHCS
XHRD
HDB0 to 7, P
tSAR
tRRL
tDRD
tHRA
tFRD
Item
Address setup time (vs. XHCS & XHRD )
Address hold time (vs. XHCS & XHRD )
Data delay time (vs. XHCS & XHRD )
Data float time (vs. XHCS & XHRD )
Low level XHRD pulse width
Symbol
tSAR
tHRA
tDRD
tFRD
tRRL
Min.
30
20
0
100
Typ.
Max.
60
10
Unit
n
n
n
n
n
(2) Write
HA0 to 1
XHCS
XHWR
HDB0 to 7, P
tSAW
tHWA
tWWL
tSDW tHWD
Item
Address setup time (vs. XHCS & XHWR )
Address hold time (vs. XHCS & XHWR )
Data setup time (vs. XHCS & XHWR )
Data hold time (vs. XHCS & XHWR )
Low level XHWR pulse width
Symbol
tSAW
tHWA
tSDW
tHWD
tWWL
Min.
30
20
40
10
50
Typ.
Max.
Unit
n
n
n
n
n
—9—


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CXD1186CQ/CR
4. HOST DMA cycle (80 type bus)
(1) Read
HDRQ
XHAC
XHRD
HDB0 to 7, P
tDAR1
tSAR
tRRL
tDRD
tDAR2
tHRA
tFRD
Item
HDRQ fall time (vs. XHAC )
HDRQ rise time (vs. XHAC )
XHAC setup time (vs. XHRD )
XHAC hold time (vs. XHRD )
Low level XHRD pulse width
Data delay time (vs. XHRD )
Data float time (vs. XHRD )
Symbol
tDAR1
tDAR2
tSAR
tHRA
tRRL
tDRD
tFRD
Min.
5
0
100
0
Typ.
Max.
35
48
60
10
Unit
n
n
n
n
n
n
n
(2) Write
HDRQ
XHAC
XHWR
tDAR1
tSAW
HDB0 to 7, P
tWWL
tSDW
tDAR2
tHWA
tHWD
Item
HDRQ fall time (vs. XHAC )
HDRQ rise time (vs. XHAC )
XHAC setup time (vs. XHWR )
XHAC hold time (vs. XHWR )
Low level XHWR pulse width
Data setup time (vs. XHWR )
Data hold time (vs. XHWR )
Symbol
tDAR1
tDAR2
tSAW
tHWA
tWWL
tSDW
tHWD
Min.
5
0
50
40
10
Typ.
Max.
35
48
Unit
n
n
n
n
n
n
n
—10—


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5. HOST DMA cycle (SCSI bus)
(1) Read
CXD1186CQ/CR
SDRQ
XSAC
XHRD
HDB0 to 7, P
tDDA
tDAR
tRRL
tDRD
tDRA
tHRD
Item
XSAC fall time (vs. SDRQ )
XSAC delay time (vs. XHRD )
XSAC delay time (vs. XHRD )
Low level XHRD pulse width
Data delay time (vs. XHRD )
Data hold time (vs. XHRD )
Symbol
tDDA
tDAR
tDRA
tRRL
tDRD
tHRD
Min.
0
T+59
0
Typ.
Max.
Tw
Tw
90
Unit
n
n
n
n
n
n
(2) Write
SDRQ
XSAC
XHWR
HDB0 to 7, P
tDDA
tDAW
tWWL
tDWA
tSDW
tFWD
Item
XSAC fall time (vs. SDRQ )
XHWR delay time (vs. XSAC )
XSAC delay time (vs. XHWR )
Low level XHWR pulse width
Data setup time (vs. XHWR )
Data float time (vs. XHWR )
Where T in the chart indicates :
Tw for 3 cycle mode
2 • Tw for 4 cycle mode
3 • Tw for 5 cycle mode
Here Tw=1/f
Symbol
tDDA
tDAW
tDWA
tWWL
tSDW
tFWD
Min.
T
T+24
27
Typ.
Max.
Tw
Tw
Tw
Unit
n
n
n
n
n
n
—11—


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CXD1186CQ/CR
6. ADPCM DMA cycle
ADRQ
tDDA
XAAC
XHWR
HDB0 to 7, P
Item
XAAC fall time (vs. ADRQ )
XHWR delay time (vs. XAAC )
XAAC delay time (vs. XHWR )
Low level XHWR pulse width
Data setup time (vs. XHWR )
Data float time (vs. XHWR )
tDAW
tWWL
tDWA
tSDW
tFWD
Symbol
tDDA
tDAW
tDWA
tWWL
tSDW
tFWD
Min.
T
T+24
27
Where T in the chart indicates :
Tw for 3 cycle mode
2 • Tw for 4 cycle mode
3 • Tw for 5 cycle mode
Here Tw=1/f
Typ.
Max.
Tw
Tw
Tw
Unit
n
n
n
n
n
n
7. XTL1 and XTL2 pins
(1) For self oscillation
Item
Oscillation frequency
Symbol
fMAX
(Topr=–20 to +75 °C, VDD=5.0 V±10 %)
Min.
16.9344
Typ.
Max.
24.576
Unit
MHz
(2) When a pulse is input to XTL1
Item
“H” level pulse width
“L” level pulse width
Pulse period
Input “H” level
Input “L” level
Rise time, Fall time
XTL1
(Topr=–20 to +75 °C, VDD=5.0 V±10 %)
Symbol
tWHX
tWLX
tW
VIHX
VILX
tR, tF
Min.
15
15
40.7
VDD—1.0
Typ.
Max.
0.8
15
Unit
ns
ns
ns
V
V
ns
tWHX
tW
tWLX
VIHX
VIHX X0.9
VDD/2
tR tF
—12—
VIHX X0.1
tILX


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CXD1186CQ/CR
Description of Function
1. Pin description
Below is a description of pins by function.
1.1 CD player interface (4 pins)
(1) DATA (input)
Serial data from CIRC LSI (digital signal processing LSI for CD)
(2) BCLK (input)
Bit clock. Clock for DATA Strobe.
(3) LRCK (input)
LR clock. Indicates LCH and RCH of DATA input.
(4) C2PO (positive logic input)
C2 pointer signal from CIRC. Indicates an error is included in the DATA input.
Interface mode with the CD player is controlled at DRVIF register.
1.2 Buffer memory interface (27 pins)
(1) XMWR (memory write, negative logic output)
Data write strobe signal of the buffer memory.
(2) XMOE (memory output enable, negative logic output)
Data read strobe signal of the buffer memory.
(3) BA0 to 15 (Buffer memory address, output)
Address signal of the buffer memory.
(4) BDB0 to 7 (Buffer data bus, I/O)
Data bus signal of the buffer memory.
(5) BDBP (Buffer data bus, I/O)
Buffer memory data bus signal for error pointer.
1.3 CPU interface (16 pins)
(1) XWR (CPU write, negative logic input)
Write strobe signal of the CPU register.
(2) XRD (CPU read, negative logic input)
Read out strobe signal of the CPU register.
(3) XCS (CPU chip select, negative logic input)
Chip select negative logic signal from the CPU.
(4) A0 to 3 (CPU address, input)
Address signal for the CPU selection of the IC internal register.
(5) DB0 to 7 (CPU data bus, I/O)
CPU data bus signal.
(6) INT (CPU interrupt, output)
Interrupt request output to the CPU. This pin polarity is controlled at the CONFIG register.
1.4 Host interface (19 pins)
(1) HMDS (Host mode select, input)
Signal for the host mode selection. This pin is pulled down inside the IC by means of a resistor at a
standard 50 k.
“L” or open : connected to Intel 80 type host Bus.
“H” : connected to SCSI controller IC.
(2) HDRQ/XSAC (Host data request/SCSI acknowledge, output)
When HMDS is at “L”, DMA data request positive logic signal to host.
When HMDS is at “H”, DMA acknowledge negative logic signal to SCSI control IC.
—13—


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CXD1186CQ/CR
(3) XHAC/SDRQ (Host DMA acknowledge/SCSI data request, input)
When HMDS is at “L”, DMA acknowledge negative logic signal from host.
When HMDS is at “H”, DMA data request positive logic signal from SCSI control IC.
(4) XHWR (Host write, negative logic I/O)
When HMDS is at “L” and ADMAEN (DMACTL register, bit4) also at “L”, data write strobe input from
host.
When HMDS is at “H” and ADMAEN at “L”, data write strobe output to SCSI control IC.
When ADMAEN is at “H”, data write strobe output to audio processor (ADP).
(5) XHRD (Host read, negative logic I/O)
When HMDS is at “L” and ADMAEN also at “L”, data read strobe input from host.
When HMDS is at “H” and ADMAEN at “L”, data read strobe output to SCSI control IC.
When ADMAEN is at “H”, data read strobe output to ADP.
(6) XHCS (Host chip select, negative logic input)
This pin is pulled up inside the IC by means of a resistor at a standard 50 k.
When HMDS is at “L”, chip select input from host.
When HMDS is at “H”, this signal is not used. Either fix to “H” or keep open.
(7) HA0 and 1 (Host address, input)
These pins are pulled up inside the IC by means of a resistor at a standard 50 k.
When HMDS is at “L”, address input from the host.
When HMDS is at “H”, these signals are not used. Either fix to “H” or keep open.
(8) HDB0 to 7 (Host data bus, I/O)
Host data bus signal.
(9) HDBP (Host data bus, I/O)
Host data bus signal for error pointer.
(10) HINT (HOST interrupt, output)
This pin is an open drain output.
When HMDS is at “L”, interrupt request negative logic output to host.
When HMDS is at “H”, this signal is not used.
(11) XTC (Terminal count, negative logic output)
This is pulled up inside the IC by means of a resistor at a standard 50 k.
When HMDS is at “L”, data transfer complete instruction negative logic input from the host.
When HMDS is at “H”, this signal is not used. Either fix to “H” or keep open.
1.5 Audio processor (ADP) interface (2 pins)
(1) ADRQ (audio processor DMA request, positive logic input)
This pin is pulled down inside the IC by means of a resistor at a standard 50 k.
DMA data request signal to ADP. When not connected to ADP and CXD1186Q, either fix to “L” or keep
open.
(2) XAAC (audio processor DMA acknowledge, negative logic output)
DMA acknowledge signal from ADP.
1.6 Others (4 pins)
(1) XTL1 (Crystal1, input)
(2) XTL2 (Crystal2, output)
Crystal oscillator connecting pin for master clock oscillation.
(3) HCLK (halfclock, output)
Half frequency divided clock of the master clock.
(4) XRST (Reset, negative logic input)
Chip reset signal.
Pins BDB0 to 7, BDBP, DB0 to 7, HDB0 to 7 and HDBP are pulled up inside the IC by means of a
resistor at a standard 25 k.
—14—


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CXD1186CQ/CR
2. Register function
This IC is controlled from the CPU by means of 19 registers for each of write and read, respectively.
2.1 Write register
2.1.1 Drive Interface (DRVIF) register
bit0 : DIGIN (Digital IN)
“H” ; When Digital In (See fig. 2.1.1) is connected, this bit is set to “H”.
“L” ; When connected to CIRC LSI, this bit is set to “L”.
bits 2 to 5 are effective only when DIGIN is at “L”.
bit1 : LSB1ST (LSB First)
“H” ; When data is connected to CIRC LSI output through LSB first, this bit is set to “H”.
“L” ; When data is connected to CIRC LSI output through MSB first, this bit is set to “L”.
bits2 and 3 : BCKMD 0, 1 (BCLK mode 0, 1)
These bits are set according to the number of BCLK clocks output during one word by CIRC LSI.
BCKMD 1 BCKMD 0
“L” “L” 16BCLKs/Word
“L” “H” 24BCLKs/Word
“H” “X” 32BCLKs/Word
Moreover, when there are 24 or 32 clocks within 1 word, the 16 bits of data before LRCK edge, become
effective.
bit4 : BCKRED (BCLK Rising Edge)
“H” ; Data is strobed with BCLK rise.
“L” ; Data is strobed with BCLK fall.
bit5 : LCHLOW (LCH LOW)
“H” ; When LRCK is at “L”, it is determined to be LCH data.
“L” ; When LRCK is at “H”, it is determined to be LCH data.
1. When DIGIN=“H”, We automatically have LSBIST=BCKMD1=“H”, BCKRED=LCHLOW=“L”.
bit6 : DBLSPD (Double Speed)
“H” ; At double speed PB, this bit is set to “H”.
“L” ; At normal speed PB, this bit is set to “L”.
bit7 : C2PLIST (C2PO Lower-byte 1st)
“H” ; When 2 bytes of data are input to C2PO, the Lower-byte and the upper-byte are input in the order.
“L” ; When 2 bytes of data are input to C2PO, the Upper-byte and the lower-byte are input in the order.
Table 2.1.1 indicates the setting value of bits 0 to 7 when Sony-made CIRC LSI is connected. Fig. 2.1.1 (1)
to (4) indicates the input timing chart.
Here, the upper byte means the upper 8 bits including MSB from CIRC LSI, Lower byte indicates the lower 8
bits including LSB from CIRC LSI.
Changes in value for the respective bits in this register have to be executed in the decoder disable condition.
—15—


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LRCK
BCLK
DATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
L0 RV
Rch Validity FLAG
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 LV
Rch LSB
Rch • MSB
Fig. 2.1.1 (1) Digital In Timing Chart (C2PO don’t care, no need for connection)
LRCK
BCLK
DATA
C2PO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
R0
Rch LSB
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Lch MSB
Lch • LSB
C2 Pointer for Upper byte
C2 Pointer for Lower byte
Fig. 2.1.1 (2) CDL30, 35 Series, Timing Chart


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LRCK
BCLK
DATA
C2PO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
R1 R0
Rch LSB
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Lch MSB
Lch LSB
C2 Pointer for Upper byte
C2 Pointer for Lower byte
Fig. 2.1.1 (3) CXD2500Q, 48 bit Slot Mode Timing Chart
LRCK
BCLK
DATA
C2PO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
L14 L15
Lch MSB
C2 Pointer for Upper byte
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Rch LSB
Rch MSB
C2 Pointer for Lower byte
Fig. 2.1.1 (4) CXD2500Q, 64 bit Slot Mode Timing Chart


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CXD1186CQ/CR
Sony-made CIRC LSI
CDL30 series
CDL35 series
CDL40 series
(48 bit slot mode)
CDL40 series
(64 bit slot mode)
Table 2.1.1 DRVIF Register setting value
DRV IF Register
bit7 bit6 bit5 bit4 bit3 bit2 bit1
L LLLHL
bit0
L
L LHLHLL
L HLHXHL
Timing chart
Fig. 2.1.1 (2)
Fig. 2.1.1 (3)
Fig. 2.1.1 (4)
(Note 1) at normal speed PB set to “L”, at double speed PB set to “H”.
(Note 2)
CDL30 series
CDL35 series
CDL40 series
CXD1125Q/QZ, CXD1130Q/QZ, CXD1135Q/QZ,
CXD1241Q/QZ, CXD1245Q, CXD1246Q/QZ,
CXD1247Q/QZ/R and others.
CXD1165Q, CXD1167Q/QZ/R and others.
CXD2500Q/QZ and others.
2.1.2 Decoder Control (DECCTL) register
bits0 to 2 : DECMDSL2, 1, 0
(Decoder Mode Select 2, 1, 0)
DECMDSL2
1
0
“L”
“L” “X”
Decoder disable
“L”
“H” “X”
Monitor only mode
“H”
“L” “L”
Write only mode
“H”
“L” “H”
Real time correction mode
“H”
“H” “L”
Repeat correction mode
“H”
“H” “H”
CD-DA mode
bit3 : AUTODIST (Auto Distinction)
“H” ; Error Correction performed according to the Mode byte and FORM bit read from Drive.
“L” ; Error Correction is performed according to the following MODESEL and FORMSEL bits.
bit4 : FORMSEL (Form Select)
bit5 : MODESEL (Mode Select)
When AUTODIST is at “L” the sector is corrected as the following MODE or FORM.
MODESEL FORMSEL
“L” “L” MODE1
“H” “L” MODE2, FORM1
“H” “H” MODE2, FORM2
bit6 : ECCSTR (ECC Strategy)
“H” ; Error Correction is performed with consideration to respective data error flag.
“L” ; Error Correction is performed without consideration to respective data error flag. When an 8
bit/Word RAM is connected, turn this bit to “L”.
bit7 : ENDLADR (Enable DLADR)
“H” ; When this bit is set to “H”, DLADR is enabled.
When, either write only mode, real time correction, or CD-DA mode is being executed, the decoder
stops the buffer write as DADRC and DLADR turn equal.
“L” ; When this bit is set to “L”, DLADR is disabled.
During the execution of write only mode or real time correction, even if DADRC and DLADR turn
equal, the decoder does not stop buffer write.
(See paragraph 4 for details)
—18—


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CXD1186CQ/CR
2.1.3 DMA Control (DMACTL) register
bit0 : HSRC (Host Source)
“H” ; Data is transferred from the host to the buffer memory.
“L” ; Data is transferred from the buffer memory to the host.
bit1 : HDMAEN (HOST DMA Enable)
“H” ; DMA of the host port is enabled.
“L” ; DMA of the host port is prohibited.
bit2 : ENXTC (Enable XTC)
“H” ; DMA completion of the host port through XTC pin input is enabled.
“L” ; DMA completion of the host port through XTC pin input is disabled.
bit3 : ENHXFRC (Enable XHFRC)
“H” ; DMA completion of the host port through HXFRC is enabled.
“L” ; DMA completion of the host port through HXFRC is disabled.
bit4 : ADMAEN (ADP DMA Enable)
“H” ; DMA of the audio processor port is enabled.
“L” ; DMA of the audio processor port is prohibited.
Also, prohibits turning HDMAEN and ADMAEN simultaneously to “H”.
bit5 : CSRC (CPU Source)
“H” ; Data is transferred from the CPU to the buffer memory.
“L” ; Data is transferred from the buffer memory to the CPU.
bit6 : CDMAEN (CPU DMA Enable)
“H” ; DMA of the CPU port is enable.
“L” ; DMA of the CPU port is prohibited.
bit7 : RESERVED
Unused, Keep set to “L”.
2.1.4 Configuration (CONFIG) register
bit0 : RESERVED
Unused, Keep set to “L”.
bits1 and 2 : SDMACYC1, 0 (SCSI DMA CYCLE)
DMA transfer between this IC, SCSI control IC and ADPCM processor is executed in the
following cycle.
SDMACYC1
0
“L” “L” 3 cycle.
“L” “H” 4 cycle.
“H” “X” 5 cycle.
bit3 : SBSCTL (SCSI Bus Control)
Setting this bit to “H” forces XHWR, XHRD, HDB0 to 7 and HDBP into high impedance condition.
bit4 : CINTPOSI (CPU Interrupt Positive)
“H” ; INT pin turns to High active.
“L” ; INT pin turns to Low active.
bit5 : 9 BITRAM
“H” ; When a 9 bit/word RAM is connected, this bit is turned to “H”.
“L” ; When a 8 bit/word RAM is connected, this bit is turned to “L”.
bits6 and 7 : RESERVED
Unused, Keep set to “L”.
—19—


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CXD1186CQ/CR
2.1.5 Interrupt Mask (INTMSK) register
Turning the respective bits of the register to “H” enables interrupt request from this IC to the CPU by means
of the corresponding interrupt status. (That is, when interrupt status is turned on, INT pin is activated) The
value of the respective bits in this register does not affect the corresponding interrupt status.
bit0 : DECINT (Decoder interrupt)
When the Decoder is executing one of the respective modes, write only, monitor, or real time
correction, if Sync mark is detected or introduced, DECINT status is turned on. However, When
Sync detection window is open, if sync interval is less than 2352 bytes, Decint status is not
turned on.
Also, when Decoder repeat correction mode is being executed, everytime one correction is
completed DECINT status is turned on.
bit1 : HDMACMP (Host DMA Complete)
When DMA of the host port is completed through HXFRC or XTC pins, HDMACMP status is
turned on.
bit2 : DRVOVRN (Drive Over Run)
When ENDLADR bit (bit7) of DECCTL register is set to “H”, and the DECODER has executed
write only, real time correction mode or CD-DA mode, as DADRC and DLADR become equal,
DRVOVRN status is turned on.
However, in CD-DA mode, even when ENDLADR bit is turned to “L”, DRVOVRN status is turned
on.
bit3 : HSTCMND (Host Command)
As the host writes a command in the Command register, HSTCMND status is turned on.
bit4 : HCRISD (Host Chip Reset Issued)
By having the host write “H” in CHPRST bit (bit7) of the Control register, this IC is reset and
HCRISD status is turned on.
bit5 : RSLTEMPT (Result Empty)
When the host reads the Result register, and the Result register becomes empty, RSLTEMPT
status turns on.
bit6 : DECTOUT (Decoder Timeout)
After setting the Decoder to either, monitor only, write only or real time correction modes, if, even
after the time of three sectors (normal speed PB 40.6 ms) passes, sync is not detected, then
DECTOUT status is turned on.
2.1.6 Clear Interrupt Status (INTCLR) register
When any of the respective bits of this register is set to “H”, the corresponding interrupt status is cleared.
After the interrupt status clearance, the bit automatically turns to “L”. Accordingly there is no need for the
CPU to set to “L” again.
bit0 : DECINT (Decoder Interrupt)
bit1 : HDMACMP (Host DMA Complete)
bit2 : DRVOVRN (Drive Over Run)
bit3 : HSTCMND (Host Command)
bit4 : HCRISD (Host Chip Reset Issued)
bit5 : RSLTEMPT (Result Empty)
bit6 : DECTOUT (Decoder Timeout)
2.1.7 Drive • Last • Address • Low (DLADR-L) register
—20—


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CXD1186CQ/CR
2.1.8 Drive • Last • Address • High (DLADR-H) register
When the Decoder is executing either of write only, real time correction mode or CD-DA mode, CPU sets the
last address that writes into the buffer, data from the drive. When ENDLADR bit of DECCTL register is set to
“H” and the Decoder is executing the above modes, if data from the drive is written into the buffer at the
address specified from DLADR, all writing into the buffer is prohibited after that.
2.1.9 Drive • Address • Low (DADRC-L) counter
2.1.10 Drive • Address • Counter High (DADRC-H)
This counter keeps the address that writes data from the drive into the buffer. When drive data is written into
the buffer, DADRC contents are output form BA0 to 15. For every byte written in the buffer, DADRC is
incremented. Before the Decoder executes either write only, real time correction mode or CD-DA mode,
CPU sets the buffer write head address to DADRC.
This counter can also be used as the DMA address of the CPU port. During DMA execution of the CPU port,
DADRC contents are output from BA0 to 15, DADRC is incremented at every byte of DMA execution.
CPU can read or set DADRC contents at any time. Do not alter DADRC contents during either write only,
real time correction or CD-DA mode and the DMA execution of CPU port.
2.1.11 Host • Address • Low (HADRC-L) counter
2.1.12 Host • Address • High (HADRC-H) counter
This counter keeps the address that writes data from the host into the buffer or reads from the buffer. During
execution of the host port DMA, HADRC contents are output from BA0 to 15. The counter is incremented at
every DMA of the host port.
Before execution of the host port DMA, CPU sets the DMA head address to HADRC.
CPU can read or set HADRC contents at any time, Do no alter HADRC contents during host port DMA
execution.
2.1.13 Host • Transfer • Low (HXFRC-1) counter
2.1.14 Host • Transfer • High (HXFRC-H) counter
This counter indicates the number of host port DMA transfers. It is decremented at every host port DMA.
When ENHXFRC bit (bit3) of DMACTL register is set to “H” and HXFRC value turns to 0, the host port DMA
is disabled. At that time it is possible to send an interrupt request from this IC to the CPU.
CPU can read and set HXFRC contents at any time. Do not alter HXFRC contents during Host port DMA
execution.
2.1.15 Chip Control (CHPCTL) register
bit0 : CPUBWPO (CPU Buffer Write Pointer)
Sets the pointer value for CPU port DMA (buffer write).
bit1 : CHPRST (Chip Reset)
Setting this bit to “H” initializes the interior of this IC. After the initialization of the interior of this IC is
completed, this bit automatically turns to “L”. Accordingly it is not necessary to set the CPU to “L”.
bit2 : SWOPN (Sync Window Open)
“H” ; Setting this bit to “H” opens the window to allow for SYNC Mark detection. Sync protection circuit
inside this IC is disabled.
“L” ; Setting this bit to “L” controls the window through the sync protection circuit inside the IC.
bit3 : RPSTART (Repeat Correction Start)
Setting the Decoder to repeat correction mode and this bit to “H” starts the sector error
correction. As correction starts, this bit automatically turns to “L”. Accordingly it is not necessary
to set the CPU to “L”.
bits4 to 7 : Do not fail to set to “L”. If set to “H” IC operation is not guaranteed.
—21—


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CXD1186CQ/CR
2.1.16 CPU Buffer Write Data (CPUBWDT) register
With the CPU port DMA (buffer write), data is written into this register.
When CDMAEN of DMACTL register=CSRC=“H”, write into this register is subject to the request of CPU port
DMA (buffer wire). See paragraph 6 for details.
2.1.17 Host Interface Control (HIFCTL) register
When HMDS is at “L”, this register controls the hardware of the host interface.
bit0 : HINT #1 (Host Interrupt #1)
This bit value becomes the value of HINTSTS #1 (bit0) from STATUS register on the host side.
bit1 : HINT #2 (Host Interrupt #2)
This bit value becomes the value of HINTSTS #2 (bit1) from STATUS register on the host side.
bit2 : HINT #3 (Host Interrupt #3)
This bit value becomes the value of HINTSTS #3 (bit2) from STATUS register on the host side.
(Note) Once “H” is written, until bits 0 to 2 are cleared from the host or the chip is reset, keep at “H”.
It is not possible to access the register from the CPU and turn bits 0 to 2 from “H” to “L”.
Accordingly, to set any of these bits, it is not necessary to take into consideration the value of other
bits.
When HINTSTS bit #1 to 3 from HIFSTS register that corresponds to the above bits are at “H”, it is
prohibited to write “H” in the above bits.
Therefore, before the CPU writes “H” in the above bits HIFSTS register should be read, and
confirmation made that corresponding HINTSTS bits #1 to 3 are at “L”.
bits3 to 5 : RESERVED
Unused. Keep set to “L”. If set to “H” the IC operation is not guaranteed.
bit6 : CLRRSLT (Clear Result)
When this bit is set to “H”, the result register is cleared. When these register’s clearance is
completed, this bit automatically turns to “L”. Therefore, there is no need for the CPU to set back
to “L”.
bit7 : CLRBUSY (Clear, Busy)
When this bit is set to “H”, BUSYSTS bit of HINTSTS register is cleared. When these register’s
clearance is complete, this bit turns automatically turns to “L”. Therefore, there is no need for the
CPU to reset to L.
2.1.18 Drive Result (DRVRSLT) register
This register is utilized to transfer the command execution result to the host, when HMDS=“L”. This register
is composed of a 10 bytes FIFO. For details see 4.2.1.
2.1.19 Register Address (REGADR) register
bits0 to 6 : Do not fail to set to “L”. If set to “H” the IC operation is not guaranteed.
bit7 : REGADR0 (Register Address0)
This bit is used for the register address expansion.
2.2 Read out register
2.2.1 Current Minute Address Low (CMADR-L) register
2.2.2 Current Minute Address High (CMADR-H) register
Indicates the buffer memory address where the current sector (after correction is completed) Minute bytes
are written.
—22—


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CXD1186CQ/CR
2.2.3 Header (HDR) register
A three bytes register that indicates the current sector Header byte.
By reading address 0H successively 4 times the CPU can know the Header byte value of the current sector,
starting from the Minute byte.
2.2.4 Sub Header (SHDR) register
A three bytes register that indicates the current sector Sub Header byte.
By reading address 1H successively 4 times, the CPU can know the Sub Header byte value of the current
sector, starting from the File byte.
2.2.5 Header Flag (HDRFLG) register
Indicates the Header and Sub Header error pointer value.
2.2.6 Interrupt Status (INTSTS) register
The value of the respective bits in this register indicates the condition of the corresponding interrupt status.
The bit value of INTMSK register does not affect the above mentioned bits.
bit0 : DECINT (DECODER Interrupt)
bit1 : HDMACMP (Host DMA Complete)
bit2 : DRVOVRN (Drive Over Run)
bit3 : HSTCMND (Host Command)
bit4 : HCRISD (Host Chip Reset Issued)
bit5 : RSLTEMPT (Result Empty)
bit6 : DECTOUT (Decoder Timeout)
2.2.7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
DECODER Status (DECSTS) register
: NOSYNC
Indicates that Sync Mark could not be detected and that SYNC was inserted.
: SHRTSCT (Short Sector)
Indicates the Sync Mark interval was within 2352 bytes. This sector does not execute ECC and
EDC.
: ECCOK (ECC OK)
Indicates there are no more errors from the header of the sector where error correction was
completed up to P Parity byte. (In FORM2, this bit turns to don’t care.)
: EDCOK
Indicates EDC check showed there were no errors.
: CORDONE (Correction Done)
Indicates that sector contains bytes that were error corrected.
: CORINH (Correction Inhibit)
Indicates there was an error flag at MODE (and FROM) bytes when AUTODIST bit of DECODER
register was turned to “H”. This sector does not execute ECC and EDC.
: ERINBLK (Erasure in Block)
Turns to “H” when C2 pointer from CIRC LSI stood in 1 byte or more of all the bytes, with the
exception of current sector Sync byte.
: EDCALL0 (EDC ALL ZERO)
This bit turns to “H” when there are no error flags in any of EDC parity bytes of current sector,
and the value is at 00H.
—23—


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CXD1186CQ/CR
2.2.8 MODE FORM (MDFM) register
This register is effective only during the execution of Real time correction mode or Repeated correction
mode.
bit0 : CFORM (Correction FORM)
bit1 : CMODE (Correction MODE)
These bits indicate whether this IC identified MODE and FORM in that sector and executed error
correction.
CMODE CFORM
“L” “L” MODE1
“H” “L” MODE2, FORM1
“H” “H” MODE2, FORM2
bits2 to 4 : RMODE0, 1, 2 (Raw MODE)
RMODE1, 0 : Indicates the lower 2 bits value of raw MODE byte.
RMODE2 : Indicate the logical sum of the upper 6 bits and pointer in raw MODE byte.
2.2.9
bit0
bit1
bit2
bit7
DMA Status (DMASTS) register
: CBFWRDY (CPU Buffer Write Ready)
This bit turns to “H” when data written from CPU into CPUBWDT register is written in the buffer
memory. As CPU writes the next data into CPUBWDT register, it turns to “L” until that data is
written into the buffer memory. Also, when CSRS is set to “H” and CDMAEN to “H” (DMACTL
register), this bit turns to “H”.
CPU confirms this bit is at “H” and writes in the data into CPUBWDT register.
: CBFRRDY (CPU Buffer Read Ready)
When data read from buffer memory is kept ready in CPUBRDT register, this bit turns to “H”.
When CPU reads CPUBRDT register out it turns to “L”.
CPU confirms this bit is at “H” and reads out data from CPUBRDT register.
: CBFRDPO (CPU Buffer Read Pointer)
Indicates the value of the pointer bit read from the buffer memory.
: REGADR (Register Address)
This bit indicates the value of bit7 from Register Address register.
2.2.10 DADRC-L counter
2.2.11 DADRC-H counter
2.2.12 HADRC-L counter
2.2.13 HADRC-H counter
2.2.14 HXFRC-L counter
2.2.15 HXFRC-H counter
2.2.16 CPU Buffer Read Data (CPUBRDT) register
CPU port DMA (buffer read) data is read out from this register.
When CDMAEN of DMACTL register is at “H” and CSRC at “L”, the read out of this register is set for the
DMA (buffer read) request of the next CPU port.
2.2.17 Host Parameter (HSTPRM) register
When HMDS is at “L”, this register is used to know the command parameter from the host. This register is
composed of a 10 bytes FIFO.
—24—


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CXD1186CQ/CR
2.2.18 Host Command (HSTCMD) register
When HMDS is at “L”, this register is used to know the command from the host.
2.2.19 Host Interface Status (HIFSFS) register
When HMDS is at “L”, this register is used to know the host interface condition.
bit0 : HINTSTS #1 (HOST Interrupt Status #1)
This bit turns to “H” as CPU writes “H” into HINT #1 (HIFCTL register bit0). It turns to “L” when
the host writes “H” into CLRINT #1 (Control register bit0). This bit is used as interrupt status
monitor to the host.
bit1 : HINTSTS #2 (HOST Interrupt Status #2)
This bit turns to “H” as CPU writes “H” into HINT #2 (HIFCTL register bit1). It turns to “L” when
the host writes “H” into CLRINT #2 (Control register bit1). This bit is used as interrupt status
monitor to the host.
bit2 : HINTSTS #3 (Host Interrupt Status #3)
This bit turns to “H” as CPU writes “H” into HINT #3 (HIFCTL register bit2). It turns to “L” when
the host writes “H” into CLRINT #3 (Control register bit2). This bit is used as interrupt status
monitor to the host.
bit3 : PRMRRDY (Parameter, Read Ready)
This bit at “H” indicates that HSTPRM register is not empty, so that Parameter data can be read
out from the CPU. When this bit is at “L”, HSTPRM register is empty and Parameter data cannot
be read out from the CPU.
bit4 : PRMFULL (Parameter Full)
This bit at “H” indicates HSTPRAM register is full.
bit5 : RSLWRDY (Result Write Ready)
This bit at “H” indicates that DRVRSLT register is not full, so that the CPU can write Result data.
When this bit is at “L” DRVRSLT register is full and the CPU can not write Result data.
bit6 : RSLEMPT (Result Empty)
This bit at “H” indicates DRVRSLT register is empty.
bit7 : BUSYSTS (Busy Status)
This bit has the same value as that of BUSYSTS (bit7) of the status register on the host side.
This bit turns to “H” as the host writes a command in the Command register. It turns to “L”, as the
CPU sets CLRBUSY bit of HIFCTL register.
—25—


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CXD1186CQ/CR
∗∗∗∗∗ Write register ∗∗∗∗∗
Drive Interface (DRVIF)
76543210
DIGIN
LSB1ST
BCKMD0
BCKMD1
BCKED
LCHLOW
DBLSPD
C2PL1ST
DMA Control (DMACTL)
76543210
HSRC
HDMAEN
ENXTC
ENHXFRC
ADMAEN
CSRC
CDMAEN
CORWRIDS
Interrupt Mask (INTMSK)
76543210
DECINT
HDMACMP
DRVOVRN
HSTCMD
HCRISD
RSLTEMPT
DECTOUT
DECODER Control (DECCTL)
76543210
DECMDSL0
DECMDSL1
DECMDSL2
AUTODIST
FORMSEL
MODESEL
ECCSTR
ENDLADR
Configuration (CONFIG)
76543210
RESERVED “L”
SDMACYC0
SDMACYC1
SBSCTL
CINTPOSI
9BITRAM
RESERVED “L”
RESERVED “L”
Clear Interrupt Status (INTCLR)
76543210
DETINT
HDMACMP
DRVOVRN
HSTCMD
HCRISD
RSLTEMPT
DECTOUT
Chip Control (CHPCTL)
76543210
CPUBWPO
CHPRST
SWOPN
RPSTART
“L”
“L”
“L”
“L”
Host Interface Control (HIFCTL)
76543210
HINT#1
HINT#2
HINT#2
“L”
“L”
“L”
CLRFIFO
CLRBUSY
—26—


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CXD1186CQ/CR
Register Address (REGADR)
76543210
“L”
“L”
“L”
“L”
“L”
“L”
“L”
REGADR
Drive • Last • Address • Low
Drive • Last • Address • High
Drive • Address • Counter • Low
Drive • Address • Counter • High
Host • Transfer • Counter • Low
Host • Transfer • Counter • High
Host • Address • Counter • Low
Host • Address • Counter • High
CPU Buffer Write register
Drive Status register
Register Address register
∗∗∗∗∗ Read register ∗∗∗∗∗
Header Flag
76543210
DTTYPE
SUBMODE
CHANNEL
FILE
MODE
BLOCK
SECOND
MINUTE
DECODER Status
76543210
NOSYNC
SHRTSCT
ECCOK
EDCOK
CORDONE
CORINH
ERINBLK
EDCALLO
Interrupt Status
76543210
DECINT
HDMACMP
DRVOVRN
HSTCMD
HCRISD
RSLTEMPT
DECTOUT
MODEFORM
76543210
CFORM
CMODE
RMODE0
RMODE1
RMODE2
—27—


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CXD1186CQ/CR
DMA Status
76543210
Host Interface Status
76543210
REGADR
CBFWRRDY
CBFRDRDY
CBFRDPO
HINT#1
HINT#2
HINT#3
PRMRRDY
PRMFULL
RSLWRDY
RSLEMPT
BUSYSTS
Header register
Sub Header register
Current • Minute • Address • Low
Current • Minute • Address • High
Drive • Last • Address • Low
Drive • Last • Address • High
Drive • Address • Counter • Low
Drive • Address • Counter • High
Host • Transfer • Counter • Low
Host • Transfer • Counter • High
Host • Address • Counter • Low
Host • Address • Counter • High
CPU • Address • Counter • Low
CPU • Address • Counter • High
CPU Buffer Read register
Host Command register
Host Parameter register
—28—


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CXD1186CQ/CR
CXD1186Q register
ADDRESS
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Write
REGISTER-ADDRESS
LH
DRVIF
CONFIG
DECCTL
DMACTL
INTMSK
INTCLR
DLADR-L
DLADR-H
CPUBWDT
HIFCTL
CHPCTL
DRVRSLT
REGADR
DADRC-L
DADRC-H
HXFRC-L
HXFRC-H
HADRC-L
HADRC-H
Read
REGISTER-ADDRESS
LH
HDR
SHDR
HDRFLG
MODEFORM
DECSTS
INTSTS
DMASTS
CPUBRDT
CMADR-L
CMADR-H
TEST2
TEST1
TEST0
HSTCMD
HSTPRM
HIFSTS
3. DECODER Operation
Here after, the block containing functions 1 and 2 is called DECODER.
1 Interface with CIRC LSI
The data stream from CIRC LSI is taken in, while sync detection, descramble and data write to the
buffer are executed.
2 Error correction
Executes error correction of the sector written in the buffer.
3.1 DECODER operation mode
The Decoder features 4 operation modes set by means of DECMDSEL0 to 2 bits of DECCTL register.
DECMDSL2
10
“L”
“L” “X”
Decoder disable
“L”
“H” “X”
Monitor only mode
“H”
“L” “L”
Write only mode
“H”
“L” “H”
Real time correction mode
“H”
“H” “L”
Repeat correction mode
“H”
“H” “H”
CD-DA mode
(1) Decoder disable
DECODER operation is disabled.
(2) Monitor only mode
Data from the drive is not written in the buffer. Raw data from the drive is written in the Header, Sub
Header and HDRFLG registers.
(3) Write only mode
Set to this mode, first Sync pattern detection is performed. As sync pattern is detected, write from that
sector into the buffer starts from Minute byte. The buffer memory address of this Minute byte, is the
value set to DADRC though the CPU before setting the DECODER mode. Sectors after that, and the
Sync pattern too, are written into the buffer.
This buffer write continues until either Decoder is disabled or when ENDLADR is at “H”, DLADR value
becomes equal to that of DADRC.
—29—


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CXD1186CQ/CR
(4) Real time correction mode
Buffer write works the same as write only mode.
At the same time, error correction of the sectors already written in the buffer is executed in real time.
(When this mode is set and while the first sector is being written in the buffer, as long as a whole sector
is not yet stored in the buffer, correction is not executed.)
(5) Repeat correction mode
Data from the drive is not written in the buffer. Error Correction of sectors already written in the buffer
can be executed repeatedly. This way, errors that could not be corrected during real time correction
mode, can now be corrected.
(6) CD-DA mode
To write CD-DA (Digital audio) Disc data into the buffer, this mode is set. As this mode is set, write into
the buffer is executed from the lower byte of LCH.
This buffer write continues until either Decoder is disabled, or when ENDLADR is at “H”, DLADR value
becomes equal to that of DADRC.
3.2 DADRC (Drive Address Counter)
DADRC is the counter that holds the address when data from the drive is written into the buffer. When data
from the drive is written into the buffer, the contents are output from BA0 to 15 as buffer memory address.
CPU can set or read DADRC contents. CPU sets the buffer write head address in DADRC before the setting
of Decoder write only mode, real time correction mode and CD-DA mode.
3.3 DLADR (Drive Last Address)
DLADR is the register that indicates in bytes the value of DADRC that stops the drive data buffer write during
the execution of write only mode, real time correction mode and CD-DA mode. When ENDLADR bit of
DECCTL register is at “H” and the above modes are being executed, if DADRC value becomes equal to
DLADR, it stops the buffer write data from the drive. Then, DRVOVRN status is on. When sync interrupt
applies and DRVOVRN bit is at “H”, have CPU disable the DECODER. When ENDLADR bit is at “L”, even if
DADRC value becomes equal to DLADR, buffer write of the data from the drive is not stopped and
DRVOVRN status does not turn on.
Through the usage of DLADR, buffer overran of the drive can be prevented.
When a value is set to DLADR, make sure to set the upper byte first and the lower byte next in the order.
(Even in case only the value of one of bytes is to be changed, set both bytes in the mentioned order. If this is
not performed, IC operation can not be guaranteed.) The DLADR upper byte is first set then the lower byte is
set and until data from the drive is written in the buffer, the above function is disabled. DLADR setting should
be made carefully.
3.4 Error correction
(1) MODE and FORM discrimination
Mode and Form discrimination in the sector that performs error correction is executed in bits
AUTODIST, FORMSEL and MODESEL of DECCTL register, as indicated in Fig. 3.1.
—30—




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