CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
S2-Compatible 5-Input 2-Output Audio/Video Switch
Description
The CXA2089Q/S is a 5-input, 2-output audio/video
switch featuring I2C bus compatibility for TVs. This IC
has input pins that are compatible with S2 protocol.
CXA2089Q
48 pin QFP (Plastic)
CXA2089S
48 pin SDIP (Plastic)
Features
3 inputs that are compatible with S2 protocol
Serial control with I2C bus
5 inputs, 2 outputs
The desired inputs can be selected independently
for each of the 2 outputs
Wide band video amplifier (20MHz, –3dB)
Y/C MIX circuit
Slave address can be changed (90H/92H)
Audio muting from external pin
High impedance maintained by I2C bus lines (SDA,
SCL) even when power is OFF
Wide audio dynamic range (3Vrms typ.)
Applications
Audio/video switch featuring I2C bus compatibility
for TVs
Absolute Maximum Ratings
Supply voltage
VCC
Operating temperature Topr
Storage temperature Tstg
Allowable power dissipation
PD
12
–20 to +75
–65 to +150
1500
V
°C
°C
mW
Operating Conditions
Supply voltage
9 ± 0.5
V
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97431B7Z-PS


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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Block Diagram
CXA2089Q
TV 47
V1 1
V2 8
V3 15
V4 23
Y1 3
Y2 10
Y3 17
C1 5
C2 12
C3 19
S2-1 6
S2-2 13
S2-3 20
S-1 7
S-2 14
S-3 21
LTV 46
LV1 2
LV2 9
LV3 16
LV4 22
RTV 48
RV1 4
RV2 11
RV3 18
RV4 24
CXA2089Q/S
6dB
6dB
6dB
6dB
6dB
6dB
BIAS
Logic
6dB
0dB
6dB
0dB
6dB
6dB
40 VOUT1
36 YIN1
43 YOUT1
42 TRAP1
45 COUT1
38 CIN1
33 VOUT2
31 YOUT2
29 COUT2
44 GND
37 BIAS
34 VCC
28 DC OUT
26 SCL
27 SDA
25 ADR
35 MUTE
39 LOUT1
41 ROUT1
30 LOUT2
32 ROUT2
Audio system is attenuated by 6dB for 6kresistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB).
–2–


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089S
TV 5
V1 7
V2 14
V3 21
V4 29
Y1 9
Y2 16
Y3 23
C1 11
C2 18
C3 25
S2-1 12
S2-2 19
S2-3 26
S-1 13
S-2 20
S-3 27
LTV 4
LV1 8
LV2 15
LV3 22
LV4 28
RTV 6
RV1 10
RV2 17
RV3 24
RV4 30
CXA2089Q/S
6dB
6dB
6dB
6dB
6dB
6dB
BIAS
Logic
6dB
0dB
6dB
0dB
6dB
6dB
46 VOUT1
42 YIN1
1 YOUT1
48 TRAP1
3 COUT1
44 CIN1
39 VOUT2
37 YOUT2
35 COUT2
2 GND
43 BIAS
40 VCC
34 DC OUT
32 SCL
33 SDA
31 ADR
41 MUTE
45 LOUT1
47 ROUT1
36 LOUT2
38 ROUT2
Audio system is attenuated by 6dB for 6kresistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB).
–3–


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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Pin Configuration
CXA2089Q
36 35 34 33 32 31 30 29 28 27 26 25
BIAS 37
CIN1 38
LOUT1 39
VOUT1 40
ROUT1 41
TRAP1 42
YOUT1 43
GND 44
COUT1 45
LTV 46
TV 47
RTV 48
24 RV4
23 V4
22 LV4
21 S-3
20 S2-3
19 C3
18 RV3
17 Y3
16 LV3
15 V3
14 S-2
13 S2-2
1 2 3 4 5 6 7 8 9 10 11 12
CXA2089S
CXA2089Q/S
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
–4–


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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Pin Description
Pin
No.
Symbol
Pin
voltage
47 (5) TV
1 (7) V1
8 (14) V2
15 (21) V3
23 (29) V4
4.0V
CXA2089Q/S
Pin numbers in brackets are for the CXA2089S.
Equivalent circuit
Description
VCC
47 15
1 23
8
150
3µA
Video signal inputs.
Input composite video signals.
3 (9) Y1
10 (16) Y2
17 (23) Y3
36 (42) YIN1
4.0V
VCC
3 150
10
17 3µA
36
Y/C separation signal inputs.
Input luminance signals.
The YIN1 pin inputs the signal
obtained by Y/C separating the
VOUT1 pin output.
5 (11) C1
12 (18) C2
19 (25) C3
38 (44) CIN1
4.5V
VCC
20k
5
150
12
19 27k
38
Y/C separation signal inputs.
Input chrominance signals.
The CIN1 pin inputs the signal
obtained by Y/C separating the
VOUT1 pin output.
46 (4) LTV
2 (8) LV1
9 (15) LV2
16 (22) LV3
22 (28) LV4
48 (6) RTV
4 (10) RV1
11 (17) RV2
18 (24) RV3
24 (30) RV4
4.5V
40 (46) VOUT1
33 (39) VOUT2
3.9V
46 48
24
9 11
VCC
27k
33k
16 18
15k
22 24
VCC
250
VCC
30k
40
33 27k 23.5k
Audio signal inputs.
Video signal outputs.
Output composite video signals.
–5–


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
Pin
No.
Symbol
Pin
voltage
43 (1) YOUT1
3.3V
31 (37) YOUT2
3.5V
45 (3) COUT1
29 (35) COUT2
4.5V
Equivalent circuit
VCC VCC VCC
VCC
43
31
VCC VCC VCC
VCC
45
29
Description
Video signal outputs.
Output luminance signals.
Video signal outputs.
Output chrominance signals.
39 (45) LOUT1
30 (36) LOUT2
41 (47) ROUT1
32 (38) ROUT2
4.5V
VCC
39
30
41
32
VCC
56
20k
20k
Audio signal outputs.
Zo = 50(within DC ± 2mA)
6 (12) S2-1
13 (19) S2-2
20 (26) S2-3
7 (13) S-1
14 (20) S-2
21 (27) S-3
25 (31) ADR
Detects the S2-compatible DC
VCC
VCC
superimposed onto the C signal.
VCC 4:3 video signal at 1.3V or less
4:3 letter-box signal at 1.3V or more
6
147
13
20 100k
to 2.5V or less
16:9 picture squeezed signal at 2.5V
or more
These pins are pulled down to GND
by a 100kresistor, so the 4:3 video
signals are selected when open.
Composite video/S selector.
5V VCC VCC
The detection results are written to
the status register.
VCC 50k
S signal at 3.5V or less
100k
7
50k
Composite video signal at 3.5V or
more
14 These pins are pulled up to 5V by a
21
10k
100kresistor, so the composite
video signals are selected when
open.
VCC
147 72k
25
28k
Selects the slave address for the I2C
bus.
90H at 1.5V or less
92H at 2.5V or more
90H when open
–6–


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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Pin
No.
Symbol
Pin
voltage
26 (32) SCL
27 (33) SDA
28 (34) DC OUT
42 (48) TRAP1
3.8V
Equivalent circuit
VCC
4k
26
10k
VCC
4k
27
VCC
4k 1k
28 Q1
28k
VCC
100
42
1k
CXA2089Q/S
Description
I2C bus signal input
VILmax = 1.5V
VIHmin = 3.0V
I2C bus signal input
VILmax = 1.5V
VIHmin = 3.0V
VOLmax = 0.4V
Outputs the S2-compatible DC
superimposed onto the COUT2
output. The DC is superimposed by
connecting this pin to the COUT2
output via a capacitor.
Control is performed by the I2C bus.
When 0V is output, Q1 is ON and
the impedance is 5k.
S2 protocol output DC impedance of
10 ± 3kis realized by attaching
external resistance of 4.7k.
DC OUT (bus) Output DC
0 4.5V
1 0V
2 1.9V
3 4.5V
Connects trap circuit for subcarrier.
35 (41) MUTE
37 (43) BIAS
4.5V
VCC
147 72k
35
28k
VCC VCC
20k 147
37
20k
VCC
–7–
Audio signal output mute.
Mute OFF at 1.5V or less
Mute ON at 2.5V or more
Mute OFF when open
Internal reference bias (Vcc/2).
Connects to GND via a capacitor.


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
Electrical Characteristics
Item Symbol
Conditions
Current consumption ICC
No signal, no load
(Ta = 25°C, VCC = 9V)
Min. Typ. Max. Unit
30 45 62 mA
Video system (Measurement circuit; Fig. 1)
Gain
GVv f = 100kHz, 0.3Vp-p input
Frequency response
characteristics
Frequency response
characteristics
(Y/C mix)
FBWv1
f = 100kHz, input frequency where
output amplitude is –3dB with 0.3Vp-p
FBWv2 output serving as 0dB
Input dynamic range
Ddv
f = 100kHz,
maximum with distortion < 1.0%
Cross talk
Vctv f = 4.43MHz, 1Vp-p input
5.9
15
10
1.4
6.4 6.9 dB
20 — MHz
15 — MHz
— — Vp-p
— –50 dB
Audio system (Measurement circuits; Fig. 2 to Fig. 5)
Gain
Frequency response
characteristics
Total harmonic
distortion
Input dynamic range
Cross talk
Ripple rejection ratio
Output DC offset
Residual noise
S/N ratio
GVA
FBWA
THD
DdA
VctA
VctA
Voff
VNA
S/N
f = 1kHz, 1Vp-p input,
5.7kresistor inserted to input
f = 1kHz, input frequency where
output amplitude is –3dB with 1Vp-p
output serving as 0dB
f=1kHz, 2.2Vp-p input, where 400Hz
HPF + 80kHz LPF are inserted
f=1kHz, maximum with distortion < 0.3%
f=1kHz, 1Vp-p input
f=100Hz, 0.3Vp-p applied to Vcc
Offset voltage between input and
output
When 400Hz HPF+ 30kHz LPF are
inserted
f=1kHz, 1Vrms input
When 400Hz HPF + 30kHz LPF are
inserted
–1
50
2.8
–30
0
0
0.03
3.0
–90
–55
20
–100
1 dB
— kHz
0.05 %
— Vrms
–80 dB
–40 dB
30 mV
30 µVrms
–90 dB
–8–


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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Logic system
Item Symbol
Conditions
High level input voltage VIH
Low level input voltage VIL
Low level output voltage VOL With SDA 3mA current supplied
High level input current IIH
VIH = 4.5V
Low level input current IIL
VIL = 0.4V
Maximum clock
frequency
fSCL
Minimum waiting time
for data change
tBUF
Minimum waiting time
for data transfer start
tHD;STA
Low level clock pulse
width
tLOW
High level clock pulse
width
tHIGH
Minimum waiting time
for start preparation
tSU;STA
Minimum data hold time tHD;DAT
Minimum data
preparation time
tSU;DAT
Rise time
Fall time
tR
tF
Minimum waiting time
for stop preparation
tSU;STO
CXA2089Q/S
Min. Typ. Max. Unit
3.0 — 5.0 V
0
— 1.5
V
0
— 0.4
V
0 — 10 µA
0 — 10 µA
0 — 100 kHz
4.7 — — µs
4.0 — — µs
4.7 — — µs
4.0 — — µs
4.7 — — µs
150 — — ns
0 — — ns
— — 1 µs
— — 300 ns
4.7 — — µs
–9–


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 10 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 11 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 12 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 13 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 14 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 15 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 16 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 17 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 18 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 19 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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I2C BUS Control Signal
CXA2089Q/S
34 SDA
33 SCL
tBUF
tLOW
tHD;STA
tR
tHD;DAT
tHIGH tF
tSU;DAT
tSU;STA
PS
S
Fig. 6. I2C BUS Control Signal Timing Chart
tSU;STO
P
Description of Operation
The CXA2089Q/S is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system
both have 5 inputs and 2 outputs each. 3 of the 5 video system inputs support S2 and S protocols.
The desired inputs can be independently assigned to each output (in the audio system, the left and right
channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the video
and audio system output 2.
I2C BUS Registers
1) I2C BUS
The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA – serial data, SCL –
serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC
outputs are either open collector or open drain, forming a bus line in the wired OR format.
SDA
AA
MSB
LSB MSB
LSB
SCL
S
1 234 567 891 2
S: Start condition; SDA is set "Low" when SCL is "High"
P: Stop condition; SDA is set "High" when SCL is "High"
A: Acknowledge; signal sent from the slave
P
9
Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which
indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave1 IC
receives data at the rising edge of SCL and the master2 IC changes data at the falling edge of SCL.
1 Slave: An IC that is placed under the control of the master. In a normal system, all devices excluding the
central microcomputer are slaves.
2 Master: A central microcomputer or other controlling IC.
– 20 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
2) Control Registers
The CXA2089Q/S control is exercised by writing 2-byte data into the two 8-bit control registers which control
the output selector circuits for the 2 outputs.
S Slave address A
DATA1
A DATA2
AP
S: Start condition
A: Acknowledge
P: Stop condition
Control register structure (DATA1 and DATA2)
All registers are set to "0" during IC power on.
"" indicates undefined.
b7 b6 b5 b4
Slave add.
1
0
0
1
DATA1 A-GAIN S/COMP1
V-IN1
DATA2
S/COMP2
AV-IN2
R/W (1): Read/write mode
0: Control data write
1: Status register read
b3
0
b2 b1
0 ADR
A-IN1
DC OUT
b0
R/W
ADR (1): This bit sets the slave address set by the address pin.
0: 90H
1: 92H
A-GAIN (1): LOUT1/ROUT1 output gain selector
0: 0dB output
1: –6dB output
S/COMP1 and S/COMP2 (1 each): S terminal input/composite signal input selectors
By setting S/COMP1 to "0", when composite signal input is selected, YOUT1/COUT1 output the
inputs from YIN1/CIN1.
0: Composite signal inputs (TV, V1 to V4 inputs)
1: S terminal inputs (Y1/C1 to Y3/C3 inputs)
V-IN1 (3 each): This bit selects the input signals output to each video output.
0: Mute
1: Selects the TV input
2: Selects the V1 and Y1/C1 inputs
3: Selects the V2 and Y2/C2 inputs
4: Selects the V3 and Y3/C3 inputs
5: Selects the V4 inputs
6: Mute
7: Mute
– 21 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
A-IN1 (3 each): This bit selects the input signals output to each audio output.
0: Mute
1: Selects the LTV/RTV inputs
2: Selects the LV1/RV1 inputs
3: Selects the LV2/RV2 inputs
4: Selects the LV3/RV3 inputs
5: Selects the LV4/RV4 inputs
6: Mute
7: Mute
AV-IN2 (3): This bit selects the input signals output to output 2 (VOUT2, YOUT2/COUT2, LOUT2/ROUT2).
Note) Both the video output and the audio output are selected at the same time only for AV-IN2.
0: Mute
1: Selects the TV and LTV/RTV inputs
2: Selects the V1, Y1/C1 and LV1/RV1 inputs
3: Selects the V2, Y2/C2 and LV2/RV2 inputs
4: Selects the V3, Y3/C3 and LV3/RV3 inputs
5: Selects the V4 and LV4/RV4 inputs
6: Mute
7: Mute
DC OUT (2): This bit sets the DC voltage output from DC OUT.
0: 4.5V
1: 0V
2: 1.9V
3: 4.5V
3) Status Registers
When reading two bytes
S Slave address A
DATA1
A
DATA2
NA P
When reading one byte
S Slave address A
DATA1
NA P
S: Start condition
A: Acknowledge
NA: No acknowledge
P: Stop condition
When communication is to be terminated in the status register reading mode, the no-acknowledge signal is
needed to assure that the master does not issue the acknowledge signal to the slave.
It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA1.
– 22 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
Status register structure (DATA1 and DATA2)
"" indicates undefined.
b7 b6 b5
Slave add.
1
0
0
DATA1
DATA2
S1SEL
S1SEL
S2SEL
S2SEL
S3SEL
S3SEL
b4
1
b3 b2
00
S-C1
S-C3
b1
ADR
b0
1
S-C2
S1SEL to S3SEL (1 each): S-1 to S-3 pin status
0: S-1 to S-3 pins are not grounded.
1: S-1 to S-3 pins are grounded.
S1SEL to S3SEL are actually determined by comparing the S-1 to S-3 pin DC voltages with 3.5V.
S-1 to S-3 pin DC voltage
3.5V or more
3.5V or less
S1SEL to S3SEL
0
1
S-C1, S-C2, S-C3 (2 each): S2-1, S2-2 and S2-3 pin status
0: 4:3 video signal
1: 4:3 letter-box signal
2: 16:9 video squeezed signal
3: No signal
S-C1 to S-C3 are actually determined by comparing the S2-1 to S2-3 pin DC voltages with two
threshold. However, when the S-1 to S-3 pins are open, the outputs are fixed to "3".
S2-1 to S2-3 pin DC voltage
1.3V or less
1.3V or more to 2.5V or less
2.5V or more
S-1 to S-3 OPEN
S-C1 to S-C3
0
1
2
3
4) Power-on Reset
The CXA2089Q/S has an internal power-on reset function that sets each control register to "0" during IC power
ON.
The power-on reset VTH has hysteresis.
Power-on reset
released
Power-on reset
4.5V
5.6V
– 23 –
VCC


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 24 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
– 25 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089Q/S
Example of Representative Characteristics
Video system frequency response characteristics
8
TV, V1 to V4 VOUT1, VOUT2
Y1 to Y3 YOUT1, YOUT2
C1 to C3 COUT1, COUT2
6
Audio system frequency response characteristics
2
L/RTV, L/R1 to L/R4 LOUT1 (0dB)
L/RTV, L/R1 to L/R4 LOUT2
0
Y1/C1 to Y3/C3
4 VOUT1, VOUT2
–2
2 –4
L/RTV, L/R1 to L/R4 LOUT1 (–6dB)
0 –6
–2
100k
1M 10M
Frequency [Hz]
100M
–8
1k
10k 100k
Frequency [Hz]
1M
Audio system distortion vs. Input amplitude
10
f = 1kHz
400Hz HPF, 80kHz LPF
1
0.1
LOUT1 output (0dB gain)
LOUT2 output
0.01
0.002
0
123
Input amplitude [Vrms]
– 26 –
4


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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Package Outline
Unit: mm
CXA2089Q
15.3 ± 0.4
+ 0.4
12.0 – 0.1
48PIN QFP (PLASTIC)
36 25
37 24
CXA2089Q/S
+ 0.1
0.15 – 0.05
0.15
48 13
1
0.8
12
+ 0.15
0.3 – 0.1
± 0.12 M
+ 0.35
2.2 – 0.15
+ 0.2
0.1 – 0.1
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-48P-L04
QFP048-P-1212-B
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 27 –


CXA2089Q (Sony Corporation)
S2-Compatible 5-Input 2-Output Audio/Video Switch

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CXA2089S
48PIN SDIP (PLASTIC)
+ 0.4
43.2 – 0.1
48 25
1 24
1.778
CXA2089Q/S
0° to 15°
0.5 ± 0.1
0.9 ± 0.15
Two kinds of package surface:
1.All mat surface type.
2.Center part is mirror surface.
SONY CODE
EIAJ CODE
JEDEC CODE
SDIP-48P-02
SDIP048-P-0600
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER/PALLADIUM
PLATING
42/COPPER ALLOY
5.1g
– 28 –




CXA2089Q.pdf
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