AD402M48VBA-5 (ETC)
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ASCEND
Semiconductor
4Mx4 EDO
Data sheet
Rev.1
Page 1


AD402M48VBA-5 (ETC)
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AD 40 4M 4 2 V S A – 5
Ascend
Semiconductor
EDO/FPM
D-RAMBUS
DDRSDRAM
DDRSGRAM
SGRAM
SDRAM
: 40
: 41
: 42
: 43
: 46
: 48
Density
16M : 16 Mega Bits
8M : 8 Mega Bits
4M : 4 Mega Bits
2M : 2 Mega Bits
1M : 1 Mega Bit
Organization
4: x4
8 : x8
9 : x9
16 : x16
18 : x18
32 : x32 Refresh
1 : 1K 8 : 8K
2 : 2K 6 :16K
4 : 4K
Interface
V: 3.3V
R: 2.5V
Min Cycle Time ( Max Freq.)
-5 : 5ns ( 200MHz )
-6 : 6ns ( 167MHz )
-7 : 7ns ( 143MHz )
-75 : 7.5ns ( 133MHz )
-8 : 8ns ( 125MHz )
-10 : 10ns ( 100MHz )
EDO : -5 (50 ns)
-6 (60 ns)
Revision
A : 1st B : 2nd
C : 3rd D :4th
Package
C: CSP B: uBGA
T: TSOP Q: TQFP
P: PQFP ( QFP )
L: LQFP S: SOJ
Rev.1
Page 2


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Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access
mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single
3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-
tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).
Features
• Single 3.3V(±10 %) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
- Active mode : 432/396 mW (Mas)
- Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)
• 4 refresh modesh:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh(S-version)
Rev.1
Page 3


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Pin Configuration
26/24-PIN 300mil Plastic SOJ
VCC
DQ1
DQ2
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
26/24-PIN 300mil Plastic TSOP (ll)
VCC
DQ1
DQ2
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
Pin Description
Pin Name
Function
A0-A10
Address inputs
- Row address
- Column address
- Refresh address
A0-A10
A0-A10
A0-A10
DQ1~DQ4
Data-in / data-out
RAS
Row address strobe
CAS
Column address strobe
WE Write enable
OE Output enable
Vcc Power (+ 3.3V)
Vss Ground
Rev.1
Page 4


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Block Diagram
WE
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS
NO. 2 CLOCK
GENERATOR
COLUMN
ADDRESS
BUFFERS (11)
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFERS (11)
NO. 1 CLOCK
GENERATOR
CONTROL
LOGIC
DATA-IN BUFFER
COLUMN
DECODER
2048
SENSE AMPLIFIERS
I/O GATING
2048x4
DATA-OUT
BUFFER
2048x2048x4
MEMORY
ARRAY
DQ. 1
.
DQ4
OE
Vcc
Vss
Rev.1
Page 5


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TRUTH TABLE
FUNCTION
STANDBY
RAS
H
READ
WRITE: (EARLY WRITE )
READ WRITE
L
L
L
EDO-PAGE-
MODE READ
1st Cycle
2nd Cycle
L
L
EDO-PAGE 1st Cycle
MODE WRITE
2nd Cycle
L
L
EDO-
1st Cycle
PAGE-MODE
READ-WRITE 2nd Cycle
L
L
HIDDEN
REFRESH
READ
WRITE
LHL
LHL
RAS-ONLY REFRESH
L
CBR REFRESH
HL
Notes: 1. EARLY WRITE only.
CAS
HX
L
L
L
HL
HL
HL
HL
HL
HL
L
L
H
L
ADDRESSES
WE OE ROW COL
DQS
X X X X High-Z
H
L
HL
H
L
X
LH
L
ROW
ROW
ROW
ROW
COL Data-Out
COL Data-ln
COL Data-Out,Data-ln
COL Data-Out
H L n/a COL Data-Out
L X ROW COL Data-In
L X n/a COL Data-In
H L L H ROW COL Data-Out, Data-In
H L L H n/a
H L ROW
COL Data-Out, Data-In
COL Data-Out
L X ROW COL Data-In
X X ROW n/a High-Z
H X X X High-Z
Notes
1
Rev.1
Page 6


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Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Supply voltage relative to Vss
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Symbol
VT
VCC
IOUT
PD
TOPT
TSTG
Value
-0.5 to + 4.6
-0.5 to + 4.6
50
1.0
0 to + 70
-55 to + 125
Recommended DC Operating Conditions
Parameter/Condition
Symbol
Supply Voltage
Input High Voltage, all inputs
Input Low Voltage, all inputs
VCC
VIH
VIL
3.3 Volt Version
Min Typ
3.0 3.3
Max
3.6
2.0 - VCC + 0.3
-0.3 -
0.8
Unit
V
V
V
Unit
V
V
mA
W
°C
°C
Capacitance
Ta = 25°C, VCC = 3.3V ±10 %, f = 1MHz
Parameter
Symbol
Typ Max Unit Note
Input capacitance (Address)
CI1 - 5 pF 1
Input capacitance (RAS, CAS, OE, WE)
CI2
- 7 pF 1
Output capacitance
(Data-in, Data-out)
CI/O
-
Note: 1. Capacitance measured with effective capacitance measuring method.
2. RAS, CAS = VIH to disable Dout.
7
pF 1, 2
Rev.1
Page 7


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DC Characteristics :
(Ta = 0 to 70°C, VCC = + 3.3V ±10 %, VSS = 0V)
Parameter
Symbol
Test Conditions
Operating current
Low
power
S-version
Standby
Current
Standard
power
version
RAS- only refresh current
EDO page mode current
CAS- before- RAS refresh
current
Self- refresh current
(S-Version)
ICC1
RAS cycling
CAS, cycling
tRC = min
ICC2
LVTTL interface
RAS, CAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS VCC -0.2V
Dout = High-Z
LVTTL interface
RAS, CAS = VIH
Dout = High-Z
CMOS interface
RAS, CAS VCC -0.2V
Dout = High-Z
ICC3
RAS cycling, CAS = VIH
tRC = min
ICC4 tPC = min
ICC5
ICC8
tRC = min
RAS, CAS cycling
tRASS 100µs
AD404M42V
Unit Notes
-5 -6
Min Max Min Max
- 120
- 110 mA 1, 2
- 0.5
- 0.5 mA
- 0.15
- 0.15 mA
- 2 - 2 mA
- 0.5
- 0.5 mA
- 120
- 90
- 120
- 550
- 110 mA 1, 2
- 80 mA 1, 3
- 110 mA 1, 2
- 550 µA
Rev.1
Page 8


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DC Characteristics :
(Ta = 0 to 70°C, VCC= +3.3V ±10 %, VSS= 0V)
Parameter
Input leakage current
Output leakage current
Output high Voltage
Output low voltage
Symbol
ILI
ILO
VOH
VOL
Test Conditions
0V Vin VCC + 0.3V
0V Vout VCC + 0.3V
Dout = Disable
IOH = -2mA
IOL = +2mA
AD404M42V
Unit Notes
-5 -6
Min Max Min Max
-5 5 -5 5 µA
-5 5 -5 5 µA
2.4 - 2.4 - V
- 0.4
- 0.4 V
Notes:
1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the
device is selected. ICC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
Rev.1
Page 9


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AC Characteristics
(Ta = 0 to + 70°C, Vcc = 3.3V ±10 %, Vss = 0V) *1, *2, *3, *4
Test conditions
• Output load: one TTL Load and 100pF (VCC = 3.3V ±10 %)
• Input timing reference levels:
VIH = 2.0V, VIL = 0.8V (VCC = 3.3V ±10 %)
• Output timing reference levels:
VOH = 2.0V, VOL = 0.8V
Read, Write, Read- Modify- Write and Refresh Cycles
(Common Parameters)
Parameter
Random read or write cycle time
RAS precharge time
CAS precharge time in normal mode
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
Column address to RAS lead time
RAS hold time
CAS hold time
CAS to RAS precharge time
OE to Din delay time
Transition time (rise and fall)
Refresh period
Refresh period (S- Version)
CAS to output in Low- Z
CAS delay time from Din
OE delay time from Din
Symbol
tRC
tRP
tCPN
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRAL
tRSH
tCSH
tCRP
tOED
tT
tREF
tREF
tCLZ
tDZC
tDZO
AD404M42V
-5 -6
Min Max Min Max
84 - 104 -
30 - 40 -
10 - 10 -
50 10000
60 10000
8 10000
10 10000
0 -0 -
8 - 10 -
0 -0 -
8 - 10 -
12 37 14 45
10 25 12 30
25 - 30 -
8 - 10 -
38 - 40 -
5 -5 -
12 - 15 -
1 50 1 50
- 32
- 32
- 128
- 128
0 -0 -
0 -0 -
0 -0 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
Notes
5
6
7
8
9
10
11
Rev.1
Page 10


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Read Cycle
Parameter
Access time from RAS
Access time from CAS
Access time from column address
Access time from OE
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Output buffer turn-off time
Output buffer turn-off time from OE
Write Cycle
Parameter
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
Data-in hold time
WE to Data-in delay
Symbol
tRAC
tCAC
tAA
tOEA
tRCS
tRCH
tRRH
tOFF
tOEZ
AD404M42V
-5 -6
Min Max Min Max
- 50
- 60
- 14
- 15
- 25
- 30
- 12
- 15
0 -0 -
0 -0 -
0 -0 -
0 12
0 15
0 12
0 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
13, 14
14, 15
7
10, 16
16
17
17
Symbol
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tDH
tWED
AD404M42V
-5 -6
Min Max Min Max
0 -0 -
8 - 10 -
8 - 10 -
13 - 15 -
8 - 10 -
0 -0 -
8 - 10 -
10 - 10 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
7, 18
19
19
Rev.1
Page 11


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Read- Modify- Write Cycle
Parameter
Read-modify- write cycle time
RAS to WE delay time
CAS to WE dealy time
Column address to WE delay time
OE hold time from WE
Symbol
tRWC
tRWD
tCWD
tAWD
tOEH
AD404M42V
-5 -6
Min Max Min Max
108 - 133 -
64 - 77 -
26 - 32 -
39 - 47 -
8 - 10 -
Unit
ns
ns
ns
ns
ns
Notes
18
18
18
Refresh Cycle
Parameter
CAS setup time (CBR refresh)
CAS hold time (CBR refresh)
RAS precharge to CAS hold time
RAS pulse width (self refresh)
RAS precharge time (self refresh)
CAS hold time (CBR self refresh)
WE setup time
WE hold time
Symbol
tCSR
tCHR
tRPC
tRASS
tRPS
tCHS
tWSR
tWHR
AD404M42V
-5 -6
Min Max Min Max Unit
5 - 5 - ns
8 - 10 - ns
5 - 5 - ns
100 - 100 - µs
90 - 110 - ns
-50 - -50 - ns
0 - 0 - ns
10 - 10 - ns
Notes
10
7
Rev.1
Page 12


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EDO Page Mode Cycle
Parameter
EDO page mode cycle time
EDO page mode CAS precharge time
EDO page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
OE high hold time from CAS high
OE high pulse width
Data output hold time after CAS low
Output disable delay from WE
WE pulse width for output disable when
CAS high
Symbol
tPC
tCP
tRASP
tCPA
tCPRH
tOEHC
tOEP
tCOH
tWHZ
tWPZ
AD404M42V
-5 -6
Min Max Min Max Unit Notes
20 - 25 - ns
10 - 10 - ns
50 105
60 105 ns
20
- 30
- 35 ns 10, 14
30 - 35 - ns
5 - 5 - ns
10 - 10 - ns
5 - 5 - ns
3 10
3 10 ns
7 - 7 - ns
EDO Page Mode Read Modify Write Cycle
Parameter
EDO page mode read- modify- write cycle
CAS precharge to WE delay time
EDO page mode read- modify- write cycle
time
Symbol
tCPW
AD404M42V
-5 -6
Min Max Min Max
45 - 55 -
Unit
ns
Notes
10
tPRWC
56
- 68
- ns
Rev.1
Page 13


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Notes :
1. AC measurements assume tT = 2ns.
2. An initial pause of 100 µs is required after power up, and it followed by a minimum of eight
initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal
refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
4. All the VCC and VSS pins shall be supplied with the same voltages.
5. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle.
6. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle.
7. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS .
8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.
Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit.
9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.
Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit.
10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS .
11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition
time is measured between VIH and VIL.
12. Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
13. Assumes that tRCD tRCD(max) and tRAD tRAD (max).
14. Access time is determined by the maximum of tAA, tCAC, tCPA.
15. Assumes that tRCD tRCD (max) and tRAD tRAD (max).
16. Either tRCH or tRRH must be satisfied for a read cycle.
17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high
impedance). tOFF is determined by the later rising edge of RAS or CAS.
18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS tWCS (min), the cycle is an early write cycle and the
data out will remain open circuit (high impedance) throughout the entire cycle. If tRWD tRWD (min),
tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell. If neither of the above sets of conditions
is satisfied, the condition of the data output (at access time) is indeterminate.
19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a
delayed write or a read-modify-write cycle.
20. tRASP defines RAS pulse width in EDO page mode cycles.
Rev.1
Page 14


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Timing Waveforms
• Read Cycle
RAS
CAS
ADDRESS
tRC
t RAS
tCSH
tRCD
tT
tRSH
tCAS
tRAD
tRAL
tASR
tRAH
Row
tASC
tCAH
Column
tRCS
WE
tRP
tCRP
tCPN
tRRH
tRCH
OE
DQ1~DQ4
Note :
= don’t care
= Invalid Dout
tAA
tRAC
tOEA
tCAC
tCLZ
tOEZ
tOFF
tOFF
D OUT
Rev.1
Page 15


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•Early Write Cycle
RAS
CAS
ADDRESS
tRC
t RAS
tCSH
tRCD
tT
tRSH
tCAS
tASR
tRAD
tRAH
Row
tRAL
tASC
tCAH
tRAL
Column
WE
DQ1~DQ4
tWCS
t WCH
tDS tDH
DIN
tRP
tCRP
tCPN
Rev.1
Page 16


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• Delayed Write Cycle
RAS
CAS
tT
tRC
t RAS
tRCD
tCSH
tRSH
tCAS
tRP
tCRP
tCPN
ADDRESS
WE
OE
DQ1~DQ4
tASR
tRAH
Row
tASC
tCAH
Column
t RCS
tCWL
t RWL
t WP
t OED
t DS
t OEH
OPEN
tDS
tDH
DIN
Rev.1
Page 17


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• Read - Modify - Write Cycle
RAS
CAS
ADDRESS
WE
DQ1~DQ4
OE
DQ1~DQ4
tT
tRCD
tRWC
t RAS
tCAS
tRP
tCRP
tCPN
tASR
tRAD
tRAH
Row
tASC
tCAH
Column
tRCS
tCWD
tAWD
tRWD
tCWL
tRWL
tWP
tDZC
tDZO
OPEN
tDS
tDH
DIN
tOED
tOEH
tRAC
tOEA
tCAC
tAA
tOEZ
DOUT
Rev.1
Page 18


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• EDO Page Mode Read Cycle
RAS
tCRP
tCSH
tRCD
tCAS
tRASP
tPC
tCP
tCAS
tCPRH
tRSH
t CP tCAS
tRP
tCRP
tCPN
CAS
ADDRESS
tASR
tRAD
tRAH
tASC tCAH
Row
Column 1
WE WE
OE OE
DQ1~DQ4
tRCS
tOEA
tRAC
tAA
tCAC
tASC tCAH
Column 2
tASC
tRAL
tCAH
Column N
tOEHC
tOEP
tOEA
Row
tRRH
tRCH
tCPA
tAA
DOUT 1
tCAC
tCOH
tCPA
tAA
tOEZ
tCAC
DOUT 2
tOEZ
tOFF
tOFF
DOUT N
OPEN
Rev.1
Page 19


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• EDO Page Mode Early Write Cycle
RAS
CAS
t RASP
tRP
tT
tCSH
tPC
tRSH
tCRP
tRCD
tCAS
tCP tCAS t CP tCAS
tCPN
ADDRESS
tASR tRAH
Row
tASC
tCAH
Column 1
tASC tCAH
Column 2
tASC tCAH
Column N
WE WE
tWCS
tWCH
tWCS tWCH
tWCS tWCH
DQ1~DQ4
tDS tDH
DIN 1
tDS tDH
DIN 2
tDS tDH
DIN N
Rev.1
Page 20


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• EDO Page Mode Read-Early-Write Cycle
RAS
CAS
ADDRESS
tCRP
tCSH
tRCD
tCAS
tASR
tCSH
tRAD
tRAH
tASC
tRAH
Row
Column 1
WE WE
tRCS
t RASP
tCPRH
tPC tRSH
tCP tCAS t CP tCAS
tASC tCAH
Column 2
tASC
tCAL
tRAL
tCAH
Column N
tRCH
tWCS
tWCH
OE
DQ1~DQ4
tOEA
tWED
OE
tRAC
OPEN
tAA
tCAC
tCPA
tAA
tCAC
tCOH
tWHZ
tDS
tDH
Data
Doutput 1
Data
Doutput 2
Data
Input N
tRP
tCRP
tCPN
Row
Rev.1
Page 21


AD402M48VBA-5 (ETC)
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• EDO Page Mode Read-Modify-Write Cycle
RAS
tT
CAS
tRCD
tRASP
tCAS
tCP
tPRWC
tCAS
tCP
tCPRH
tCAS
tRP
tCRP
tASR
tRAD
tRAH
tASC
tCAH
ADDRESS
Row
ColumCnol1umn 1
tRWD
tAWD
tCWD
tCWL
tRCS
WE WE
tRCS
tDZC
tWP
tDS
tDH
DQ1~DQ4
OPEN
DIN 1
tDZO
tOED
tOEH
tASC
tCAH
Column 2
tCPW
tAWD
tCWD
tCWL
tRCS
tDZC
tWP
tDS
tDH
OPEN
tDZO
DIN 2
tOED
tOEH
tRAL
tASC
tCAH
Column N
tCPW tCWL
tAWD
tCWD
tRWL
tDZC
tWP
tDS
tDH
OPEN
DIN N
tDZO
tOED
tOEH
OE
DQ1~DQ4
tOEA
tCAC
tAA
tRAC
tOEZ
tCAC
tAA
tCPA
tOEA
tOEZ
DOUT 1
DOUT 2
tCAC
tAA
tCPA
tOEA
tOEZ
DOUT N
Rev.1
Page 22


AD402M48VBA-5 (ETC)
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• Read Cycle with WE Controlled Disable
RAS
CAS
ADDRESS
tCSH
tRCD
tT
tCAS
tASR
tRAD
tRAH
tASC
tCAH
Row
Column
t RCS
WE
OE
DQ1~DQ4
t DS
tRAC
tAA
tOEA
tCAC
tCLZ
t RCH
t WPZ
tWHZ
tOEZ
DOUT
Rev.1
Page 23


AD402M48VBA-5 (ETC)
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RAS-Only Refresh Cycle
RAS
CAS
ADDRESS
tT
tCRP
tASR
tRAH
ROW
tRC
tRAS
DQ1~DQ4
tOFF
OPEN
tRP
tRPC
tCRP
CAS-Before-RAS Refresh Cycle
tRC
tRP
tRAS
tRP
tRC
tRAS
tRP
RAS
CAS
WE
DQ1~DQ4
tRPC
tT
tCSR
tCHR
tWSR tWHR
tOFF
tRPC
tCSR
tCHR
tWSR
tWHR
OPEN
tCRP
Rev.1
Page 24


AD402M48VBA-5 (ETC)
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CBR Self-Refesh Cycle
RAS
tRPC
tCSR
CAS
DQ1~DQ4
WE
tOFF
tWSR tWHR
tRASS
OPEN
tRPS
tCHS
High lmpedance
Rev.1
Page 25


AD402M48VBA-5 (ETC)
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• Hidden Refresh Cycle
RAS
tT
tRC
tRAS
(READ)
CAS
ADDRESS
tRCD
tRSH
tASR
t RAD
t RAH
ROW
tASC
tRAL
tCAH
COlumn
tRC tRC
tRP tRAS tRP tRAS
(REFRESH)
(REFRESH)
tRP
tCAS
tCHR
tCRP
t RCS
WE
tRRH
tRCH
OE
DQ1~DQ4
tAA
t RAC
t OEA
tCAC
D OUT
tOEZ
tOFF
t OFF
Rev.1
Page 26


AD402M48VBA-5 (ETC)
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Ordering information
Part Number
AD404M42VSA-5
AD404M42VSA-6
AD404M42VTA-5
AD404M42VTA-6
Access time
50 ns
60 ns
50 ns
60 ns
Package
300mil 26/24-Pin
Plastic SOJ
TSOP II
AD404M42VSA-5
• AD
40
• 4M4
•2
•V
•S
•A
•5
• Ascend Memory Product
• Device Type
• Density and Organization
• Refresh Rate, 2: 2K Refresh
• T: 5V, V: 3.3V
• Package Type (S : SOJ, T : TSOP II)
• Version
• Speed (5: 50 ns, 6: 60 ns)
Packaging information
300 mil, 26/24-Pin Plastic SOJ
DIM MILLIMETERS
INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 3.25 3.51 3.76 0.128 0.138 0.148
A1 2.08 ---
--- 0.082 ---
---
A2 2.54 REF.
0.100 REF.
b 0.41 ---
0.51 0.016 --- 0.020
b1 0.41 0.46 0.48 0.016 0.018 0.019
b2 0.66 ---
0.81 0.026 --- 0.032
c 0.18 ---
0.30
c1 0.18 ---
0.28
D 17.02 17.15 17.27
E 8.51 BASIC
E1 7.49 7.62 7.75
E2 6.78 BASIC
e 1.27 BASIC
R1 0.76 ---
1.02
0.007 --- 0.012
0.007 --- 0.011
0.670 0.675 0.680
0.335 BASIC
0.295 0.300 0.305
0.267 BASIC
0.050 BASIC
0.030 --- 0.040
26
1
A2
D
21 19
68
CL
NOTE:
1. CONTROLLING DIMENSION : INCHES
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE.
3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR
INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE
SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm)
DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH
TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN.
b2
b 0.007"M
e
4-e
14
E1 E
13
b
b1
c1 c
BASE METAL
WITH PLATING
SECTION B-B
0.025" MIN.
A
A1
RAD R1
0.004" SEATING PLANE
E2
B
B
Rev.1
Page 27


AD402M48VBA-5 (ETC)
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300 mil, 26/24-Pin TSOP II
DIM
A
A1
A2
b
b1
c
c1
D
ZD
e
E
E1
L
R
R1
MILLIMETERS
MIN. NOM. MAX.
--- --- 1.20
0.05 ---
0.15
0.95 1.00 1.05
0.30 ---
0.52
0.30 0.40 0.45
0.12 ---
0.21
0.12 0.15 0.16
17.01 17.14 17.27
0.95 REF.
1.27 BASIC
9.02 9.22 9.42
7.49 7.62 7.75
0.40 0.50 0.60
0.12 ---
0.25
0.12 ---
---
INCHES
MIN. NOM. MAX.
--- --- 0.047
0.002 ---
0.006
0.037 0.039 0.041
0.012
---
0.020
0.012 0.016 0.018
0.005
---
0.008
0.005 0.006 (0.006)
0.670 0.675 0.680
0.0374 BASIC
0.050 BASIC
0.355 0.363 0.371
0.295 0.300 0.305
0.016 0.020 0.024
0.005 ---
0.010
0.005 ---
---
NOTE:
1. CONTROLLING DIMENSION : MILLIMETERS
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
26 21 19
1 68
D
(ZD)
4-1.27
REF.
b
0.200(0.008") M
14
A2
E1 E A1
DETAIL A
RAD R1
RAD R
B
c
B
L 0 ~5
b
13 b1 SECTION B-B
c1 c
BASE METAL
WITH PLATING
DETAIL A
A
e
0.100(0.004")
SEATING PLANE
Rev.1
Page 28




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