CD4052B (etcTI)
CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
CD405xB CMOS Single 8-Channel Analog Multiplexer/Demultiplexer
With Logic-Level Conversion
1 Features
1 Wide Range of Digital and Analog Signal Levels
– Digital: 3 V to 20 V
– Analog: 20 VP-P
• Low ON Resistance,125 (Typical) Over 15 VP-P
Signal Input Range for VDD – VEE = 18 V
• High OFF Resistance, Channel Leakage of ±100
pA (Typical) at VDD – VEE = 18 V
• Logic-Level Conversion for Digital Addressing
Signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V)
to Switch Analog Signals to 20 VP-P (VDD – VEE =
20 V) Matched Switch Characteristics, rON = 5
(Typical) for VDD – VEE = 15 V Very Low Quiescent
Power Dissipation Under All Digital-Control Input
and Supply Conditions, 0.2 µW (Typical) at VDD
VSS = VDD – VEE = 10 V
• Binary Address Decoding on Chip
• 5 V, 10 V, and 15 V Parametric Ratings
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full
Package Temperature Range, 100 nA at 18 V and
25°C
• Break-Before-Make Switching Eliminates Channel
Overlap
2 Applications
• Analog and Digital Multiplexing and
Demultiplexing
• A/D and D/A Conversion
• Signal Gating
• Factory Automation
• Televisions
• Appliances
• Consumer Audio
• Programmable Logic Circuits
• Sensors
3 Description
The CD405xB analog multiplexers and demuliplexers
are digitally-controlled analog switches having low
ON impedance and very low OFF leakage current.
These multiplexer circuits dissipate extremely low
quiescent power over the full VDD – VSS and VDD
VEE supply-voltage ranges, independent of the logic
state of the control signals.
Device Information(1)
PART NUMBER PACKAGE
BODY SIZE (NOM)
CDIP (16)
19.50 mm × 6.92 mm
PDIP (16)
19.30 mm × 6.35 mm
CD405xB
SOIC (16)
9.90 mm × 3.91 mm
SOP (16)
10.30 mm × 5.30 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Diagrams of CD405xB
INH
COM
CBA
CD4051B
CBA
000
001
010
011
Ch 0
Ch 1
Ch 2
Ch 3
1 0 0 Ch 4
101
Ch 5
110
1 1 1 Ch 6
Ch 7
INH
BA
Ch X0
X COM
Y COM
Ch Y0
BA
0 0 Ch X1
0 1 Ch Y1
1 0 Ch X2
1 1 Ch Y2
Ch X3
CD4052B
Ch Y3
INH
ax OR ay
bx OR by
cx OR cy
CD4053B
A ax
A ay
B bx
B by
C cx
C cy
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


CD4052B (etcTI)
CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
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Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 AC Performance Characteristics............................... 8
6.7 Typical Characteristics .............................................. 9
7 Parameter Measurement Information ................ 11
8 Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagrams ..................................... 15
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 17
9 Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1 Documentation Support ........................................ 21
12.2 Related Links ........................................................ 21
12.3 Trademarks ........................................................... 21
12.4 Electrostatic Discharge Caution ............................ 21
12.5 Glossary ................................................................ 21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Revision H (April 2015) to Revision I
Page
• Added: ON Channel Leakage Current to the Electrical Characteristics table ....................................................................... 6
• Added Note 3 to the Electrical Characteristics table .............................................................................................................. 6
• Added Figure 13 ................................................................................................................................................................... 12
Changes from Revision G (October 2003) to Revision H
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Added Device Information table. ............................................................................................................................................ 1
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5 Pin Configuration and Functions
CD4051B E, M, NS, and PW Package
16-Pin PDIP, CDIP, SOIC, SOP, and TSSOP
(Top View)
CHANNELS
IN/OUT
41
62
COM OUT/IN 3
CHANNELS
IN/OUT
74
55
INH 6
VEE 7
VSS 8
16 VDD
15 2
14 1
13 0
CHANNELS IN/OUT
12 3
11 A
10 B
9C
CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
CD4052B E, M, NS, and PW Package
16-Pin PDIP, CDIP, SOP, and TSSOP
(Top View)
Y CHANNELS 0 1
IN/OUT 2 2
COMMON “Y” OUT/IN 3
Y CHANNELS 3 4
IN/OUT 1 5
INH 6
VEE 7
VSS 8
16 VDD
15 2
14 1
X CHANNELS
IN/OUT
13 COMMON “X” OUT/IN
12 0
11 3
X CHANNELS
IN/OUT
10 A
9B
PIN
NO. NAME
1 CH 4 IN/OUT
2 CH 6 IN/OUT
3 COM OUT/IN
4 CH 7 IN/OUT
5 CH 5 IN/OUT
6 INH
7 VEE
8 VSS
9C
10 B
11 A
12 CH 3 IN/OUT
13 CH 0 IN/OUT
14 CH 1 IN/OUT
15 CH 2 IN/OUT
16 VDD
CD4053B E, M, NS, and PW Package
16-Pin PDIP, CDIP, SOP, and TSSOP
(Top View)
by 1
bx 2
cy 3
OUT/IN CX OR CY 4
IN/OUT CX 5
INH 6
VEE 7
VSS 8
16 VDD
15 OUT/IN bx OR by
14 OUT/IN ax OR ay
13 ay
IN/OUT
12 ax
11 A
10 B
9C
Pin Functions CD4051B
I/O DESCRIPTION
I/O Channel 4 in/out
I/O Channel 6 in/out
I/O Common out/in
I/O Channel 7 in/out
I/O Channel 5 in/out
I Disables all channels. See Table 1.
— Negative power input
— Ground
I Channel select C. See Table 1.
I Channel select B. See Table 1.
I Channel select A. See Table 1.
I/O Channel 3 in/out
I/O Channel 0 in/out
I/O Channel 1 in/out
I/O Channel 2 in/out
— Positive power input
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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
PIN
NO. NAME
1 Y CH 0 IN/OUT
2 Y CH 2 IN/OUT
3 Y COM OUT/IN
4 Y CH 3 IN/OUT
5 Y CH 1 IN/OUT
6 INH
7 VEE
8 VSS
9B
10 A
11 X CH 3 IN/OUT
12 X CH 0 IN/OUT
13 X COM IN/OUT
14 X CH 1 IN/OUT
15 X CH 2 IN/OUT
16 VDD
Pin Functions CD4052B
I/O DESCRIPTION
I/O Channel Y0 in/out
I/O Channel Y2 in/out
I/O Y common out/in
I/O Channel Y3 in/out
I/O Channel Y1 in/out
I Disables all channels. See Table 1.
— Negative power input
— Ground
I Channel select B. See Table 1.
I Channel select A. See Table 1.
I/O Channel X3 in/out
I/O Channel X0 in/out
I/O X common out/in
I/O Channel in/out
I/O Channel in/out
— Positive power input
PIN
NO. NAME
1 BY IN/OUT
2 BX IN/OUT
3 CY IN/OUT
4
CX OR CY
OUT/IN
5 CX IN/OUT
6 INH
7 VEE
8 VSS
9C
10 B
11 A
12 AX IN/OUT
13 AY IN/OUT
14
AX OR AY
OUT/IN
15
BX OR BY
OUT/IN
16 VDD
Pin Functions CD4053B
I/O DESCRIPTION
I/O B channel Y in/out
I/O B channel X in/out
I/O C channel Y in/out
I/O C common out/in
I/O C channel X in/out
I Disables all channels. See Table 1.
— Negative power input
— Ground
I Channel select C. See Table 1.
I Channel select B. See Table 1.
I Channel select A. See Table 1.
I/O A channel X in/out
I/O A channel Y in/out
I/O A common out/in
I/O B common out/in
— Positive power input
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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
TJMAX1
TJMAX2
TLMAX
Tstg
Supply Voltage
DC Input Voltage
V+ to V-, Voltages Referenced to VSS Terminal
DC Input Current
Any One Input
Maximum junction temperature, ceramic package
Maximum junction temperature, plastic package
Maximum lead temperature, SOIC - Lead Tips Only, Soldering 10s
Storage temperature
MIN
–0.5
–0.5
–10
–65
MAX
20
VDD + 0.5
10
175
150
265
150
UNIT
V
V
mA
°C
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
CD4051B in PDIP, CDIP, SOIC, SOP, TSSOP Packages
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101 (2)
CD4053B in PDIP, CDIP, SOP and TSSOP Packages
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101 (2)
VALUE
+3000
+2000
+2500
+1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Temperature Range
MIN
MAX
UNIT
–55 125 °C
6.4 Thermal Information
CD405xB
THERMAL METRIC(1)
E (PDIP) M (SOIC)
NS (SOP)
PW
(TSSOP)
UNIT
16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance
67 73
64 108 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
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6.5 Electrical Characteristics
over operating free-air temperature range, VSUPPLY = ±5 V, and RL = 100 Ω, (unless otherwise noted)(1)
PARAMETER
VIS (V)
TEST CONDITIONS
VEE (V)
VSS (V)
VDD (V)
TEMP
MIN TYP
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
–55°C
–40°C
5 25°C
0.04
85°C
125°C
–55°C
–40°C
10 25°C
0.04
85°C
Quiescent Device Current, IDD Max
125°C
–55°C
–40°C
15 25°C
0.04
85°C
125°C
–55°C
–40°C
20 25°C
0.08
85°C
125°C
–55°C
–40°C
0 0 5 25°C
470
85°C
125°C
–55°C
Drain to Source ON Resistance rON Max
0 VIS VDD
–40°C
0 0 10 25°C
85°C
180
125°C
–55°C
–40°C
0 0 15 25°C
125
85°C
125°C
Change in ON Resistance
(Between Any Two Channels),
rON
0 05
0 0 10 25°C
0 0 15
15
10
5
–55°C
OFF Channel Leakage Current: Any Channel OFF (Max)
or ALL Channels OFF (Common OUT/IN) (Max)
–40°C
0 0 18 25°C
85°C
± 0.01
125°C
ON Channel Leakage Current: Any Channel ON (Max) or
ALL Channels ON (Common OUT/IN) (Max)
5 or 0
5
-5
0
0
10.5
85°C
0 18 85°C
Input, CIS
CD4051
–5 –5 –5
25°C
5
30
Capacitance
Output, COS
CD4052
CD4053
25°C
18
9
Feed through, CIOS
0.2
MAX
UNIT
5
5
5
150
150
10
10
10
300
300
20
20
20
600
600
100
100
100
3000
3000
800
850
1050
1200
1300
310
300
400
520
550
200
210
240
300
300
± 100
± 100(2)
± 1000(2)
± 300(3)
± 300(3)
µA
nA
nA
pF
(1) Peak-to-Peak voltage symmetrical about (VDD – VEE) / 2.
(2) Determined by minimum feasible leakage measurement for automatic testing.
(3) Does not apply to Hi-Rel CD4051BF and CD4051BFA3 devices.
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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
Electrical Characteristics (continued)
over operating free-air temperature range, VSUPPLY = ±5 V, and RL = 100 Ω, (unless otherwise noted)(1)
PARAMETER
VIS (V)
TEST CONDITIONS
VEE (V)
VSS (V)
VDD (V)
TEMP
MIN TYP
VDD RL = 200 k,
5
30
Propagation Delay Time (Signal Input to Output)
CL = 50 pF,
10 25°C
15
tr , tf = 20 ns
15
10
CONTROL (ADDRESS OR INHIBIT), VC
–55°C
1.5
–40°C
1.5
5 25°C
85°C
1.5
125°C
1.5
–55°C
3
–40°C
3
Input Low Voltage, VIL , Max
10 25°C
85°C
3
125°C
3
–55°C
4
–40°C
4
VIL = VDD
through 1
k;
VIH = VDD
through 1
k
VEE = VSS,
RL = 1 kto VSS,
IIS < 2 µA on All OFF
Channels
15 25°C
85°C
125°C
–55°C
–40°C
5 25°C
4
4
3.5
3.5
3.5
85°C
3.5
125°C
3.5
–55°C
7
–40°C
7
Input High Voltage, VIH , Min
10 25°C
85°C
7
7
125°C
7
–55°C
11
–40°C
11
15 25°C
11
85°C
11
125°C
11
–55°C
± 0.1
–40°C
± 0.1
Input Current, IIN (Max)
VIN = 0, 18
18 25°C
85°C
± 10–5
±1
125°C
±1
Propagation
Delay Time
Address-to-Signal OUT (Channels ON
or OFF) (See Figure 10, Figure 11,
and Figure 15)
tr , tf = 20
ns,
CL = 50 pF,
RL = 10 k
0
0
0
–5
05
0 10
0 15
05
450
160
120
225
0 05
Propagation
Inhibit-to-Signal OUT (Channel
tr , tf = 20
ns,
0
0 10
Delay Time
Turning ON) (See Figure 11)
CL = 50 pF,
0
0 15
RL = 1 k
–10 0 5
400
160
120
200
0 05
Propagation
Inhibit-to-Signal OUT (Channel
tr , tf = 20
ns,
0
0 10
Delay Time
Turning OFF) (See Figure 17)
CL = 50 pF,
0
0 15
RL = 10 k
–10 0 5
200
90
70
130
Input Capacitance, CIN (Any Address or Inhibit Input)
5
MAX
UNIT
60
30 ns
20
1.5
3V
4
V
± 0.1
µA
720
320
ns
240
450
720
320
ns
240
400
450
210
ns
160
300
7.5 pF
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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
6.6 AC Performance Characteristics
PARAMETER
Cutoff (–3dB)
Frequency Channel
ON (Sine Wave
Input)
Total Harmonic
Distortion, THD
VIS (V)
VDD (V)
TEST CONDITIONS
RL (k)
5(1) 10 1 VOS at Common OUT/IN
VEE = VSS ,
20Log
VOS
VIS
=
3
dB
2(1) 5
3(1) 10
5(1) 15
10
VOS at Any Channel
CD4053
CD4052
CD4051
VEE = VSS, fIS = 1 kHz Sine Wave
5(1) 10
1
CD4053
–40dB Feedthrough
Frequency
(All Channels OFF)
VEE = VSS ,
20Log VOS
VIS
= 40dB
5(1) 10
1
VOS at Common OUT/IN CD4052
CD4051
VOS at Any Channel
Between Any two Channels
–40dB Signal
Crosstalk
Frequency
Address-or-Inhibit-to-
Signal
Crosstalk
VEE = VSS,
20Log VOS
VIS
= 40dB
10 10(2)
VEE = 0, VSS = 0, tr , tf = 20 ns,
VCC = VDD – VSS (Square Wave)
Between Sections,
CD4052 Only
Between Any Two
Sections, CD4053 Only
Measured on Common
Measured on Any Channel
In Pin 2, Out Pin 14
In Pin 15, Out Pin 14
(1) Peak-to-Peak voltage symmetrical about (VDD - VEE) / 2.
(2) Both ends of channel.
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TYP
30
25
20
60
UNIT
MHz
0.3%
0.2%
0.12%
8
10
12
8
3
6
10
2.5
6
65
65
MHz
MHz
mVPEAK
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6.7 Typical Characteristics
600
VDD - VEE = 5V
500
400
300 TA = 125oC
TA = 25oC
200
TA = -55oC
100
0
-4 -3 -2 -1
0
1
2
3
4
5
CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
300
250
200 TA = 125oC
150
TA = 25oC
100
TA = -55oC
50
0
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10
VIS, INPUT SIGNAL VOLTAGE (V)
Figure 1. Channel ON Resistance vs Input Signal Voltage
(All Types)
600
TA = 25oC
500
VDD - VEE = 5V
400
300
200
10V
100 15V
0
-10 -7.5 -5 -2.5 0 2.5 5 7.5
VIS, INPUT SIGNAL VOLTAGE (V)
10
Figure 2. Channel ON Resistance vs Input Signal Voltage
(All Types)
250
VDD - VEE = 15V
200 TA = 125oC
150
100 TA = 25oC
TA = -55oC
50
0
-10 -7.5
-5 -2.5 0 2.5 5 7.5
VIS, INPUT SIGNAL VOLTAGE (V)
10
Figure 3. Channel ON Resistance vs Input Signal Voltage
(All Types)
6
VDD = 5V
VSS = 0V
4
VEE = -5V
TA = 25oC
RL = 100k, RL = 10k
1k
500
100
2
0
-2
-4
-6
-6
-4 -2 0 2 4
VIS, INPUT SIGNAL VOLTAGE (V)
6
Figure 4. Channel ON Resistance vs Input Signal Voltage
(All Types)
105 TA = 25oC
ALTERNATING “O”
AND “I” PATTERN
104 CL = 50pF
VDD = 15V
TEST CIRCUIT
VDD
f
B/D
CD4029
VDD A B C
10011 10 9
13
103
14
15
12 CD4051
1
102
VDD = 10V
VDD = 5V
5
23
4 8 7 6 CL
100Ι
10
1
CL = 15pF
10 102
103 104 105
SWITCHING FREQUENCY (kHz)
Figure 5. ON Characteristics for 1 of 8 Channels (CD4051B)
Figure 6. Dynamic Power Dissipation vs Switching
Frequency (CD4051B)
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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
Typical Characteristics (continued)
105 TA = 25oC
ALTERNATING “O”
AND “I” PATTERN
CL = 50pF
104
VDD = 15V
103
VDD = 10V
102 VDD = 5V
CL = 15pF
TEST CIRCUIT
f VDD
CD4029
VDD
B/D
AB
100
1 10 9
5
3 CL
13
2 12
4
CD4052
14
15
6 11
7
8
Ι
10
1
10 102 103 104 105
SWITCHING FREQUENCY (kHz)
Figure 7. Dynamic Power Dissipation vs Switching
Frequency (CD4052B)
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105 TA = 25oC
ALTERNATING “O”
AND “I” PATTERN
CL = 50pF
104
103
102 VDD = 5V
CL = 15pF
VDD = 15V
VDD = 10V
TEST CIRCUIT
VDD f
100
9
3
4
12
100
5 13
CD4053 2
10 1
11 15
6 14
7
Ι8
CL
10
1
10 102 103 104
SWITCHING FREQUENCY (kHz)
105
Figure 8. Dynamic Power Dissipation vs Switching
Frequency (CD4053B)
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7 Parameter Measurement Information
VDD = 15V
VDD = 7.5V
VDD = 5V
CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
VDD = 5V
16
VEE = 0V
VSS = 0V
7
8
(A)
7.5V
VSS = 0V
5V
16
VSS = 0V
16
VEE = -7.5V
7
8
VEE = -10V
7
8
(B) (C)
Figure 9. Typical Bias Voltages
5V
VSS = 0V
VEE = -5V
16
7
8
(D)
NOTE
The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = VSS
and 1 = VDD. The analog signal (through the TG) may swing from VEE to VDD.
10%
tr = 20ns
90%
50%
90%
50%
90%
50%
TURN-ON TIME
10%
TURN-OFF TIME
tf = 20ns
10%
10%
Figure 10. Waveforms, Channel Being Turned ON
(RL = 1 kΩ)
10%
tr = 20ns
90%
50%
90%
50%
tf = 20ns
10%
90%
10%
tPHZ
TURN-OFF TIME
TURN-ON
TIME
Figure 11. Waveforms, Channel Being Turned OFF
(RL = 1 kΩ)
VDD
VDD
VDD
1 16
2 15
3 14 IDD
4 13
5 12
6 11
7 10
89
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
CD4052
IDD
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
CD4053
IDD
Figure 12. OFF Channel Leakage Current - Any Channel OFF
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SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
VDD
VDD
VDD
1
2
IDD 3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4051
1
2
IDD 3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
IDD 4
5
6
7
8
16
15
14
13
12
11
10
9
CD4052
CD4053
Copyright © 2017, Texas Instruments Incorporated
Figure 13. On Channel Leakage Current - Any Channel On
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Figure 14. OFF Channel Leakage Current - All Channels OFF
VDD
VEE
VSS
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
CD4051
VDD
OUTPUT
OUTPUT
RL CL CL RL
VEE
VDD
VDD
VSS CLOCK
IN
VEE VEE
VSS
VSS
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
CD4052
VDD
VDD
VEE
VSS CLOCK
IN VSS
VSS
VDD
1 16
OUTPUT
2 15
3 14
RL CL
4 13
5 12 VDD
VEE
6 11
7 10 VSS CLOCK
89
IN
CD4053 VSS
Figure 15. Propagation Delay - Address Input to Signal Output
OUTPUT
VDD
RL 50pF
VEE
VDD
VDD
VSS CLOCK VEE
IN VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
tPHL AND tPLH VSS
CD4051
OUTPUT
VDD
RL 50pF
VEE
VDD
VDD
VSS CLOCK VEE
IN VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
tPHL AND tPLHVSS
CD4052
OUTPUT
RL 50pF
VEE
VDD
VDD
VSS CLOCK VEE
IN VSS
1
2
3
4
5
6
7
8
16 VDD
15
14
13
12
11
10
9
tPHL AND tPLHVSS
CD4053
Figure 16. Propagation Delay - Inhibit Input to Signal Output
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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
VDD
µA
1K
1K
VIH
VIL
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
CD4051B
VIH
VIL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6)
VDD
1
2 15
1K
µA
3 14
VIH
4 13
5 12
1K
6 11
VIL 7 10
89
VIH
CD4052B
VIL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 2x)
VDD
1K
VIH
VIL
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
CD4053B
µA
1K
VIH
VIL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL by)
Figure 17. Input Voltage Test Circuits (Noise Immunity)
VDD
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
Ι
CD4053
VDD
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
Ι CD4052
VDD
10kΩ
VSS
TG
“ON”
KEITHLEY
160 DIGITAL
MULTIMETER
1k
RANGE
H.P.
MOSELEY
7030A
Y
X-Y
PLOTTER
X
Figure 18. Quiescent Device Current
Figure 19. Channel ON Resistance Measurement
Circuit
VDD
VDD
1 16
2 15
3 14
4 13
5 12
6 11
VDD
7 10
Ι
89
VSS
VSS CD4051
CD4053
NOTE: Measure inputs sequentially,
to both VDD and VSS connect all
unused inputs to either VDD or VSS.
1 16
2 15
3 14
4 13
5 12
6 11
VDD
7 10
Ι
89
VSS CD4052
VSS
NOTE: Measure inputs sequentially,
to both VDD and VSS connect all
unused inputs to either VDD or VSS.
Figure 20. Input Current
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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
5VP-P
OFF
CHANNEL
VDD
6
7
8
1K
RF
VM
Figure 21. Feedthrough (All Types)
5VP-P
CHANNEL IN X
ON OR OFF
www.ti.com
COMMON
CHANNEL
ON
RL
5VP-P
CHANNEL
OFF
RF
VM
CHANNEL
OFF
RF
VM
CHANNEL
ON
RL RL
RL
Figure 22. Crosstalk Between Any Two Channels
(All Types)
CHANNEL IN Y
ON OR OFF
RF
VM
RL RL
Figure 23. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)
DIFFERENTIAL
SIGNALS
CD4052
CD4052
LINK
DIFF.
AMPLIFIER/
LINE DRIVER
DIFF.
RECEIVER
DIFF.
MULTIPLEXING
DEMULTIPLEXING
Special Considerations: In applications where separate power sources are used to drive VDD and the signal inputs,
the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent
current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B or
CD4053B.
Figure 24. Typical Time-Division Application of the CD4052B
A
B
C
DA
Q0
1/2 Q1
E B CD4556 Q2
E
A
B
CD4051B
C
INH
A
B
CD4051B
C
INH
COMMON
A
B
CD4051B
C
INH
Figure 25. 24-to-1 MUX Addressing
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8 Detailed Description
CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
8.1 Overview
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low
ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achieved by
digital signal amplitudes of 4.5 V to 20 V (if VDD – VSS = 3 V, a VDD – VEE of up to 13 V can be controlled; for
VDD – VEE level differences above 13 V, a VDD – VSS of at least 4.5 V is required). For example, if VDD = +4.5 V,
VSS = 0 V, and VEE = –13.5 V, analog signals from –13.5 V to +4.5 V can be controlled by digital inputs of 0 V to
5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD – VSS and VDD – VEE
supply-voltage ranges, independent of the logic state of the control signals. When a logic 1 is present at the
inhibit input terminal, all channels are off.
The CD4051B device is a single 8-channel multiplexer having three binary control inputs, A, B, and C, and an
inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to
the output.
The CD4052B device is a differential 4-channel multiplexer having two binary control inputs, A and B, and an
inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog
inputs to the outputs.
The CD4053B device is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C,
and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole,
double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the
COMMON OUT/IN terminals are the inputs.
8.2 Functional Block Diagrams
16 VDD
CHANNEL IN/OUT
76543210
4 2 5 1 12 15 14 13
TG
A 11
B 10
C9
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
TG
TG
COMMON
TG OUT/IN
3
TG
TG
INH 6
TG
TG
8 VSS
7 VEE
All inputs are protected by standard CMOS protection network.
Figure 26. Functional Block Diagram, CD4051B
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SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
Functional Block Diagrams (continued)
X CHANNELS IN/OUT
3210
11 15 14 12
16 VDD
A 10
B9
INH 6
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
8 VSS
7 VEE
1524
0123
Y CHANNELS IN/OUT
All inputs are protected by standard CMOS protection network.
Figure 27. Functional Block Diagram, CD4052B
TG
TG
TG
TG
TG
TG
TG
TG
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COMMON X
OUT/IN
13
3
COMMON Y
OUT/IN
LOGIC
LEVEL
CONVERSION
16 VDD
BINARY TO
1 OF 2
DECODERS
IN/OUT
WITH
INHIBIT cy cx by bx ay ax
A 11
B 10
C9
3 5 1 2 13 12
COMMON
OUT/IN
TG ax OR ay
14
TG
COMMON
OUT/IN
TG bx OR by
15
TG
COMMON
OUT/IN
TG cx OR cy
4
TG
INH 6
VDD
8 VSS
7 VEE
All inputs are protected by standard CMOS protection network.
Figure 28. Functional Block Diagram, CD4053B
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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
8.3 Feature Description
The CD405xB line of multiplexers and demultiplexers can accept a wide range of digital and analog signal levels.
Digital signals range from 3 V to 20 V, and analog signals are accepted at levels 20 V. They have low ON
resistance, typically 125 over 15 VP-P signal input range for VDD – VEE = 18 V. This allows for very little signal
loss through the switch. Matched switch characteristics are typically rON = 5 for VDD – VEE = 15 V.
The CD405xB devices also have high OFF resistance, which keeps from wasting power when the switch is in the
OFF position, with typical channel leakage of ±100 pA at VDD – VEE = 18 V. Very low quiescent power dissipation
under all digital-control input and supply conditions, typically 0.2 µW at VDD – VSS = VDD – VEE = 10 V keeps
power consumption total very low. All devices have been 100% tested for quiescent current at 20 V with
maximum input current of 1 µA at 18 V over the full package temperature range, and only 100 nA at 18 V and
25°C.
Logic-level conversion for digital addressing signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to switch analog
signals to 20 VP-P (VDD – VEE = 20 V). Binary address decoding on chip makes channel selection easy. When
channels are changed, a break-before-make system eliminates channel overlap.
8.4 Device Functional Modes
INHIBIT
CD4051B
0
0
0
0
0
0
0
0
1
CD4052B
0
0
0
0
1
CD4053B
0
0
0
0
0
0
1
(1) X = Don't Care
Table 1. Truth Table(1)
INPUT STATES
CB
A
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
X XX
00
01
10
11
XX
X X0
X X1
X 0X
X 1X
0 XX
1 XX
X XX
ON CHANNEL(S)
0
1
2
3
4
5
6
7
None
0x, 0y
1x, 1y
2x, 2y
3x, 3y
None
ax
ay
bx
by
cx
cy
None
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SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
9 Application and Implementation
www.ti.com
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CD405xB multiplexers and demuliplexers can be used for a wide variety of applications.
9.2 Typical Application
One application of the CD4051B is to use it in conjunction with a microcontroller to poll a keypad. Figure 29
shows the basic schematic for such a polling system. The microcontroller uses the channel select pins to cycle
through the different channels while reading the input to see if a user is pressing any of the keys. This is a very
robust setup, allowing for multiple simultaneous key-presses with very little power consumption. It also utilizes
very few pins on the microcontroller. The down side of polling is that the microcontroller must continually scan
the keys for a press and can do little else during this process.
Input
Microcontroller
Channel Select
INH
3.3 V
COM
VDD
VEE
VSS
CBA
CD4051B
CBA
000
001
010
011
Ch 0
Ch 1
Ch 2
Ch 3
100
101
110
111
Ch 4
Ch 5
Ch 6
Ch 7
3.3 V
k0
k1
k2
k3
k4
k5
k6
k7
Pull-down resistors (10)
Figure 29. The CD4051B Being Used to Help Read Button Presses on a Keypad.
9.2.1 Design Requirements
These devices use CMOS technology and have balanced output drive. Take care to avoid bus contention
because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into
light loads, so routing and load conditions should be considered to prevent ringing.
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CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For switch time specifications, see propagation delay times in Electrical Characteristics.
– Inputs should not be pushed more than 0.5 V above VDD or below VEE.
– For input voltage level specifications for control inputs, see VIH and VIL in Electrical Characteristics.
2. Recommended Output Conditions
– Outputs should not be pulled above VDD or below VEE.
3. Input/output current consideration: The CD405xB series of parts do not have internal current drive circuitry
and thus cannot sink or source current. Any current will be passed through the device.
9.2.3 Application Curve
6
VDD = 5V
VSS = 0V
4
VEE = -5V
TA = 25oC
2
RL = 100k, RL = 10k
1k
500
100
0
-2
-4
-6
-6 -4 -2 0 2 4 6
VIS, INPUT SIGNAL VOLTAGE (V)
Figure 30. ON Characteristics for 1 of 8 Channels
(CD4051B)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Electrical Characteristics.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
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SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
11 Layout
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11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Figure 31 shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.
11.2 Layout Example
WORST
BETTER
BEST
1W min.
W
Figure 31. Trace Example
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12 Device and Documentation Support
CD4051B, CD4052B, CD4053B
SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017
12.1 Documentation Support
12.1.1 Related Documentation
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
PARTS
CD4051B
CD4052B
CD4053B
PRODUCT FOLDER
Click here
Click here
Click here
Table 2. Related Links
SAMPLE & BUY
Click here
Click here
Click here
TECHNICAL
DOCUMENTS
Click here
Click here
Click here
TOOLS &
SOFTWARE
Click here
Click here
Click here
SUPPORT &
COMMUNITY
Click here
Click here
Click here
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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27-Nov-2019
PACKAGING INFORMATION
Orderable Device
7901502EA
Status Package Type Package Pins Package
(1)
Drawing
Qty
ACTIVE
CDIP
J 16 1
Eco Plan
(2)
TBD
Lead/Ball Finish
(6)
A42
MSL Peak Temp
(3)
N / A for Pkg Type
Op Temp (°C)
-55 to 125
8101801EA
ACTIVE
CDIP
J 16 1
TBD
A42 N / A for Pkg Type -55 to 125
CD4051BE
CD4051BEE4
CD4051BF
CD4051BF3A
CD4051BM
CD4051BM96
CD4051BM96G3
CD4051BM96G4
CD4051BMG4
CD4051BMT
CD4051BNSR
CD4051BNSRE4
CD4051BPW
CD4051BPWE4
CD4051BPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
CDIP
CDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
SO
TSSOP
TSSOP
TSSOP
N 16 25 Green (RoHS CU NIPDAU | CU SN N / A for Pkg Type -55 to 125
& no Sb/Br)
N 16 25 Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type -55 to 125
J 16 1
TBD
A42 N / A for Pkg Type -55 to 125
J 16 1
TBD
A42 N / A for Pkg Type -55 to 125
D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125
& no Sb/Br)
D 16 2500 Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM -55 to 125
D 16 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 250 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
NS 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
NS 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
PW 16
90 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
PW 16
90 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125
& no Sb/Br)
Device Marking
(4/5)
7901502EA
CD4052BF3A
8101801EA
CD4053BF3A
CD4051BE
CD4051BE
CD4051BF
CD4051BF3A
CD4051BM
CD4051BM
CD4051BM
CD4051BM
CD4051BM
CD4051BM
CD4051B
CD4051B
CM051B
CM051B
CM051B
Samples
Addendum-Page 1


CD4052B (etcTI)
CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
CD4051BPWRG4
CD4052BE
CD4052BEE4
CD4052BF
CD4052BF3A
CD4052BM
CD4052BM96
CD4052BM96E4
CD4052BM96G3
CD4052BM96G4
CD4052BMG4
CD4052BMT
CD4052BNSR
CD4052BPW
CD4052BPWR
CD4052BPWRG3
CD4052BPWRG4
CD4053BE
27-Nov-2019
Status Package Type Package Pins Package Eco Plan
(1) Drawing Qty (2)
ACTIVE TSSOP
PW 16 2000 Green (RoHS
& no Sb/Br)
ACTIVE
PDIP
N 16 25 Green (RoHS
& no Sb/Br)
ACTIVE
PDIP
N 16 25
Pb-Free
(RoHS)
ACTIVE
CDIP
J 16 1
TBD
Lead/Ball Finish
(6)
CU NIPDAU
CU NIPDAU | CU SN
CU NIPDAU
A42
MSL Peak Temp Op Temp (°C)
(3)
Level-1-260C-UNLIM -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
N / A for Pkg Type -55 to 125
ACTIVE
CDIP
J 16 1
TBD
A42 N / A for Pkg Type -55 to 125
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
TSSOP
TSSOP
TSSOP
TSSOP
PDIP
D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125
& no Sb/Br)
D 16 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 2500 Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM -55 to 125
D 16 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 250 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
NS 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
PW 16
90 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125
& no Sb/Br)
PW 16 2000 Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM -55 to 125
PW 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
N 16 25 Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type -55 to 125
Device Marking
(4/5)
CM051B
CD4052BE
CD4052BE
CD4052BF
7901502EA
CD4052BF3A
CD4052BM
CD4052BM
CD4052BM
CD4052BM
CD4052BM
CD4052BM
CD4052BM
CD4052B
CM052B
CM052B
CM052B
CM052B
CD4053BE
Addendum-Page 2
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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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PACKAGE OPTION ADDENDUM
www.ti.com
27-Nov-2019
Orderable Device
CD4053BEE4
CD4053BF
CD4053BF3A
Status Package Type Package Pins Package Eco Plan
(1) Drawing Qty (2)
ACTIVE
PDIP
N 16 25 Green (RoHS
& no Sb/Br)
ACTIVE
CDIP
J 16 1
TBD
ACTIVE
CDIP
J 16 1
TBD
Lead/Ball Finish
(6)
CU NIPDAU
A42
A42
MSL Peak Temp
(3)
N / A for Pkg Type
Op Temp (°C)
-55 to 125
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
CD4053BM
CD4053BM96
CD4053BM96E4
CD4053BM96G3
CD4053BM96G4
CD4053BMG4
CD4053BMT
CD4053BNSR
CD4053BPW
CD4053BPWR
CD4053BPWRG3
CD4053BPWRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
TSSOP
TSSOP
TSSOP
TSSOP
D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125
& no Sb/Br)
D 16 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 2500 Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM -55 to 125
D 16 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
D 16 250 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
NS 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
PW 16
90 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125
& no Sb/Br)
PW 16 2000 Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM -55 to 125
PW 16 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM -55 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Device Marking
(4/5)
CD4053BE
CD4053BF
8101801EA
CD4053BF3A
CD4053M
CD4053M
CD4053M
CD4053M
CD4053M
CD4053M
CD4053M
CD4053B
CM053B
CM053B
CM053B
CM053B
Addendum-Page 3
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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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PACKAGE OPTION ADDENDUM
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27-Nov-2019
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4051B, CD4051B-MIL, CD4052B, CD4052B-MIL, CD4053B, CD4053B-MIL :
Catalog: CD4051B, CD4052B, CD4053B
Automotive: CD4051B-Q1, CD4051B-Q1, CD4053B-Q1, CD4053B-Q1
Military: CD4051B-MIL, CD4052B-MIL, CD4053B-MIL
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 4


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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
27-Nov-2019
Addendum-Page 5


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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
3-Dec-2019
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CD4051BM96
CD4051BM96
CD4051BM96
CD4051BM96G3
CD4051BM96G4
CD4051BM96G4
CD4051BPWR
CD4051BPWR
CD4051BPWRG4
CD4052BM96
CD4052BM96
CD4052BM96G3
CD4052BM96G4
CD4052BNSR
CD4052BPWR
CD4052BPWR
CD4052BPWRG3
CD4052BPWRG4
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
SO
TSSOP
TSSOP
TSSOP
TSSOP
D
D
D
D
D
D
PW
PW
PW
D
D
D
D
NS
PW
PW
PW
PW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SPQ
2500
2500
2500
2500
2500
2500
2000
2000
2000
2500
2500
2500
2500
2000
2000
2000
2000
2000
Reel Reel A0 B0 K0 P1 W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
330.0 16.4 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.4 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.8 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.8 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.4 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.4 6.5 10.3 2.1 8.0 16.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
330.0 16.8 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.4 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.8 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.4 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.4 8.2 10.5 2.5 12.0 16.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
Pack Materials-Page 1


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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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PACKAGE MATERIALS INFORMATION
3-Dec-2019
Device
CD4053BM96
CD4053BM96
CD4053BM96G3
CD4053BM96G4
CD4053BPWR
CD4053BPWR
CD4053BPWRG3
CD4053BPWRG4
Package Package Pins
Type Drawing
SOIC
SOIC
SOIC
SOIC
TSSOP
TSSOP
TSSOP
TSSOP
D
D
D
D
PW
PW
PW
PW
16
16
16
16
16
16
16
16
SPQ
2500
2500
2500
2500
2000
2000
2000
2000
Reel Reel A0 B0 K0 P1 W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
330.0 16.8 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.4 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.8 6.5 10.3 2.1 8.0 16.0
Q1
330.0 16.4 6.5 10.3 2.1 8.0 16.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
330.0 12.4 6.9 5.6 1.6 8.0 12.0
Q1
*All dimensions are nominal
Device
CD4051BM96
CD4051BM96
CD4051BM96
CD4051BM96G3
CD4051BM96G4
CD4051BM96G4
CD4051BPWR
CD4051BPWR
CD4051BPWRG4
Package Type
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
TSSOP
TSSOP
Package Drawing Pins
D 16
D 16
D 16
D 16
D 16
D 16
PW 16
PW 16
PW 16
SPQ
2500
2500
2500
2500
2500
2500
2000
2000
2000
Length (mm)
333.2
367.0
364.0
364.0
333.2
367.0
364.0
367.0
367.0
Width (mm)
345.9
367.0
364.0
364.0
345.9
367.0
364.0
367.0
367.0
Height (mm)
28.6
38.0
27.0
27.0
28.6
38.0
27.0
35.0
35.0
Pack Materials-Page 2


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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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PACKAGE MATERIALS INFORMATION
3-Dec-2019
Device
CD4052BM96
CD4052BM96
CD4052BM96G3
CD4052BM96G4
CD4052BNSR
CD4052BPWR
CD4052BPWR
CD4052BPWRG3
CD4052BPWRG4
CD4053BM96
CD4053BM96
CD4053BM96G3
CD4053BM96G4
CD4053BPWR
CD4053BPWR
CD4053BPWRG3
CD4053BPWRG4
Package Type
SOIC
SOIC
SOIC
SOIC
SO
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
TSSOP
TSSOP
TSSOP
TSSOP
Package Drawing Pins
D 16
D 16
D 16
D 16
NS 16
PW 16
PW 16
PW 16
PW 16
D 16
D 16
D 16
D 16
PW 16
PW 16
PW 16
PW 16
SPQ
2500
2500
2500
2500
2000
2000
2000
2000
2000
2500
2500
2500
2500
2000
2000
2000
2000
Length (mm)
364.0
333.2
364.0
333.2
367.0
364.0
367.0
364.0
367.0
364.0
333.2
364.0
333.2
364.0
367.0
364.0
367.0
Width (mm)
364.0
345.9
364.0
345.9
367.0
364.0
367.0
364.0
367.0
364.0
345.9
364.0
345.9
364.0
367.0
364.0
367.0
Height (mm)
27.0
28.6
27.0
28.6
38.0
27.0
35.0
27.0
35.0
27.0
28.6
27.0
28.6
27.0
35.0
27.0
35.0
Pack Materials-Page 3


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CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

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