ISO7821F (etcTI)
Dual Channel Digital Isolator

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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
ISO7821x High-Performance, 8000 VPK Reinforced Dual Channel Digital Isolator
1 Features
1 Signaling Rate: Up to 100 Mbps
• Wide Supply Range: 2.25 V to 5.5 V
• 2.25 V to 5.5 V Level Translation
• Wide Temperature Range: –55°C to 125°C
• Low Power Consumption, Typical 1.8 mA per
Channel at 1 Mbps
• Low Propagation Delay: 11 ns Typical
(5 V Supplies)
• Industry leading CMTI(Min): ±100 kV/μs
• Robust Electromagnetic Compatibility (EMC)
• System-Level ESD, EFT, and Surge Immunity
• Low Emissions
• Isolation Barrier Life: > 25 Years
• SOIC-16 Wide Body (DW) and Extra-Wide Body
(DWW) Package Options
• Safety and Regulatory Approvals:
– 8000 VPK Reinforced Isolation per DIN V VDE
V 0884-10 (VDE V 0884-10):2006-12
– 5.7 kVRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 60601-1 End Equipment
Standards
– CQC Certification per GB4943.1-2011
– TUV Certification per EN 61010-1 and EN
60950-1
– All DW Package Certifications Complete;
DWW Package Certifications Complete per
UL, TUV and Planned for VDE, CSA, and
CQC
3 Description
The ISO7821 is a high-performance, dual-channel
digital isolator with 8000 VPK isolation voltage. This
device has reinforced isolation certifications
according to VDE, CSA, CQC, and TUV. The isolator
provides high electromagnetic immunity and low
emissions at low power consumption, while isolating
CMOS or LVCMOS digital I/O’s. Each isolation
channel has a logic input and output buffer separated
by silicon dioxide (SiO2) insulation barrier. ISO7821
has one forward and one reverse-direction channel. If
the input power or signal is lost, default output is
'high' for the ISO7821 and 'low' for the ISO7821F
device. Used in conjunction with isolated power
supplies, this device prevents noise currents on a
data bus or other circuits from entering the local
ground and interfering with or damaging sensitive
circuitry. Through innovative chip design and layout
techniques, electromagnetic compatibility of ISO7821
has been significantly enhanced to ease system-level
ESD, EFT, Surge and Emissions compliance.
ISO7821 is available in 16-pin SOIC wide-body (DW)
and extra-wide body (DWW) packages. The DWW
package option comes with enable pins which can be
used to put the respective outputs in high impedance
for multi-master driving applications and to reduce
power consumption.
Device Information(1)
PART NUMBER PACKAGE
BODY SIZE (NOM)
ISO7821,
ISO7821F
SOIC, DW (16) 10.30 mm x 7.50 mm
Extra wide SOIC,
DWW (16)
10.30 mm × 14.0 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
spacer
2 Applications
• Industrial Automation
• Motor Control
• Power Supplies
• Solar Inverters
• Medical Equipment
• Hybrid Electric Vehicles
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx OUTx
ENx (DWW package only)
GNDI
GNDO
(1) VCCI and GNDI are supply and ground
connections respectively for the input
channels.
(2) VCCO and GNDO are supply and ground
connections respectively for the output
channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


ISO7821F (etcTI)
Dual Channel Digital Isolator

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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 5
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ..................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information .................................................. 7
6.5 Power Dissipation Characteristics ............................ 7
6.6 Electrical Characteristics, 5 V ................................... 8
6.7 Electrical Characteristics, 3.3 V ................................ 9
6.8 Electrical Characteristics, 2.5 V .............................. 10
6.9 Switching Characteristics, 5 V ................................ 11
6.10 Switching Characteristics, 3.3 V ........................... 11
6.11 Switching Characteristics, 2.5 V ........................... 12
6.12 Typical Characteristics .......................................... 13
7 Parameter Measurement Information ................ 14
8 Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 21
9 Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Application .................................................. 23
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 PCB Material ......................................................... 26
11.2 Layout Guidelines ................................................. 26
11.3 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1 Documentation Support ........................................ 27
12.2 Related Links ........................................................ 27
12.3 Community Resources.......................................... 27
12.4 Trademarks ........................................................... 27
12.5 Electrostatic Discharge Caution ............................ 27
12.6 Glossary ................................................................ 27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (December 2015) to Revision F
Page
• Changed the Safety and Regulatory Approvals list of Features ........................................................................................... 1
• Added Features "TUV Certification per EN 61010-1 and EN 60950-1" ................................................................................ 1
• Changed text in the first paragraph of the Description From: "certifications according to VDE, CSA, and CQC". To:
"certifications according to VDE, CSA, CQC, and TUV." ...................................................................................................... 1
• Added Note 1 to Table 2 ..................................................................................................................................................... 18
• Added TUV to the Regulatory Information section and Table 4. Deleted Note 1 in Table 4 .............................................. 19
• Changed Figure 15 .............................................................................................................................................................. 22
Changes from Revision D (July 2015) to Revision E
Page
• Changed Features From: 8000 VPK VIOTM and 2121 VPK VIORM Reinforced..To: 8000 VPK Reinforced.................................. 1
• Added Features: DW Package Certifications Complete; DWW Certifications Planned ........................................................ 1
• Added text to the Description: and extra-wide body (DWW) packages... .............................................................................. 1
• Added package: Extra wide SOIC, DWW (16) to the Device Information table .................................................................... 1
• Added the DWW pinout image .............................................................................................................................................. 5
• Added the DWW package to the Thermal Information .......................................................................................................... 7
• Changed the MIN value of CMTI in Electrical Characteristics, 5 V table From: 70 To: 100 kV/µs, deleted the TYP
value of 100 kV/µs ................................................................................................................................................................. 8
• Added the DW package value to the Supply Current section of the Electrical Characteristics, 5 V ...................................... 8
• Added the DWW package value to the Supply Current section of the Electrical Characteristics, 5 V .................................. 8
• Changed the MIN value of CMTI in Electrical Characteristics, 3.3 V table From: 70 To: 100 kV/µs, deleted the TYP
value of 100 kV/µs ................................................................................................................................................................. 9
• Added the DW package value to the Supply Current section of the Electrical Characteristics, 3.3 V ................................... 9
• Added the DWW package value to the Supply Current section of the Electrical Characteristics, 3.3 V .............................. 9
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ISO7821F (etcTI)
Dual Channel Digital Isolator

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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
• Changed the MIN value of CMTI in Electrical Characteristics, 2.5 V table From: 70 To: 100 kV/µs, deleted the TYP
value of 100 kV/µs ............................................................................................................................................................... 10
• Added the DW package value to the Supply Current section of the Electrical Characteristics, 2.5 V ................................. 10
• Added the DWW package value to the Supply Current section of the Electrical Characteristics, 2.5 V ............................ 10
• Added tPHZ, tPLZ, tPZH, and tPZL to Switching Characteristics, 3.3 V....................................................................................... 11
• Added tPHZ, tPLZ, tPZH, and tPZL to Switching Characteristics, 2.5 V....................................................................................... 12
• Added Figure 8 .................................................................................................................................................................... 14
• Added the DWW package to Table 1 ................................................................................................................................... 17
• Changed CIO typ value From: 2 To 1 pF in Table 1 ............................................................................................................ 17
• Added the DWW package to Table 2 ................................................................................................................................... 18
• Changed Parameter information and added the DWW package information in Table 3 .................................................... 18
• Added the DWW package information to Table 4 ................................................................................................................ 19
• added DWW-16 package options to Table 5 ...................................................................................................................... 20
• Changed Table 6 ................................................................................................................................................................. 21
• Added text to the Application Information section: "isolation voltage per UL 1577." ........................................................... 23
Changes from Revision C (May 2015) to Revision D
Page
• Added device ISO7821F to the datasheet ............................................................................................................................ 1
• Changed the Description to include: "default output is 'high' for the ISO7821 device and 'low' for the ISO7821F
device. ................................................................................................................................................................................... 1
• Changed the Simplified Schematic ........................................................................................................................................ 1
• Changed tPLH and tPHL From: 5.5 V to 5 V in Figure 6 ......................................................................................................... 13
• Changed Figure 9 ................................................................................................................................................................ 15
• Changed the Functional Block Diagram .............................................................................................................................. 16
• Changed Table 1 title From: IEC Insulation and Safety-Related Specifications for DW-16 Package To: Package
Insulation and Safety-Related Specifications ...................................................................................................................... 17
• Changed Figure 13 , Added Figure 14 ................................................................................................................................. 20
Changes from Revision B (April 2015) to Revision C
Page
• Changed From: VCC1 and VCC2 To: VCCI and VCCO, GND1 and GND2 To: GNDI and GNDO and added Notes 1 and
2 in the Simplified Schematic ................................................................................................................................................ 1
• Changed the MIN value of CMTI in Electrical Characteristics, 5 V table From: 50 To: 70 kV/µs ......................................... 8
• Changed the MIN value of CMTI in Electrical Characteristics, 3.3 V table From: 50 To: 70 kV/µs ...................................... 9
• Changed the MIN value of CMTI in Electrical Characteristics, 2.5 V table From: 50 To: 70 kV/µs .................................... 10
• Added sentence "If the EN pin is available and low then the output goes to high impedance." to the Overview
section ................................................................................................................................................................................. 16
• Changed the Functional Block Diagram to include the EN pin on the Receiver side .......................................................... 16
• Changed the Installation classification of the Table 3 to include DW package information ................................................. 18
• Changed "ISO782W functional modes" To: "ISO7821DW functional modes" in Device Functional Modes........................ 21
• Changed Table 6 title From: "Functional Table" To: "ISO7821DW Function Table"............................................................ 21
• Added the Device I/O Schematics section .......................................................................................................................... 22
• Changed device number ISO7821 To: ISO7821DW in Figure 17 ....................................................................................... 24
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ISO7821F (etcTI)
Dual Channel Digital Isolator

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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
www.ti.com
Changes from Revision A (December 2014) to Revision B
Page
• Changed the document title From: "Channel Digital Isolator" To: "Channel 1/1 Digital Isolator" .......................................... 1
• Added Features: 2.25 V to 5.5 V Level Translation ............................................................................................................... 1
• Changed the Safety and Regulatory Approvals list of Features ........................................................................................... 1
• Changed text in the Description From: "This device is being reviewed for reinforced isolation certification by VDE
and CSA. To: "This device has reinforced isolation certifications according to VDE, CSA, and CQC." ................................ 1
• Added Note (3) to the Absolute Maximum Ratings(1) table .................................................................................................... 6
• Changed From: VCCX To: VCCO In IOH and IOL of the Recommended Operating Conditions table ........................................ 6
• Changed From: VCCX To: VCCI In VIH and VIL of the Recommended Operating Conditions table ......................................... 6
• Changed Note (1) of the Recommended Operating Conditions table ................................................................................... 6
• Added the Power Dissipation Characteristics table ............................................................................................................... 7
• Changed From: VCCX To: VCCO In VOH of the Electrical Characteristics, 5 V table ................................................................ 8
• Changed From: VCCX To: VCCO In VI(HYS) of the Electrical Characteristics, 5 V table ............................................................ 8
• Changed From: VCCX To: VCCI In IIH of the Electrical Characteristics, 5 V table .................................................................... 8
• Changed From: VCCX To: VCCI In CMTI of the Electrical Characteristics, 5 V table .............................................................. 8
• Changed From: VCCX To: VCCI In Supply Current, DC Signal of the Electrical Characteristics, 5 V table.............................. 8
• Changed Note (1) of the Electrical Characteristics, 5 V table ............................................................................................... 9
• Changed From: VCCX To: VCCO In VOH of the Electrical Characteristics, 3.3 V table ............................................................. 9
• Changed From: VCCX To: VCCO In VI(HYS) of the Electrical Characteristics, 3.3 V table ......................................................... 9
• Changed From: VCCX To: VCCI In IIH of the Electrical Characteristics, 3.3 V table.................................................................. 9
• Changed From: VCCX To: VCCI In CMTI of the Electrical Characteristics, 3.3 V table ........................................................... 9
• Changed From: VCCX To: VCCI In Supply Current, DC Signal of the Electrical Characteristics, 3.3 V table .......................... 9
• Changed Note (1) of the Electrical Characteristics, 3.3 V table .......................................................................................... 10
• Changed From: VCCX To: VCCO In VOH of the Electrical Characteristics, 2.5 V table ........................................................... 10
• Changed From: VCCX To: VCCI In IIH of the Electrical Characteristics, 2.5 V table ............................................................... 10
• Changed From: VCCX To: VCCI In Supply Current, DC Signal of the Electrical Characteristics, 2.5 V table ........................ 10
• Changed Note (1) of the Electrical Characteristics, 2.5 V table .......................................................................................... 11
• Changed Figure 7 ................................................................................................................................................................ 14
• Changed From: VCC1 To: VCCI in Figure 9 ........................................................................................................................... 15
• Changed Figure 10 .............................................................................................................................................................. 15
• Changed the Test Condition of CTI in Table 1 .................................................................................................................... 17
• Changed the MIN value of CTI From" > 600 V To: 600 V.................................................................................................... 17
• Changed Table 2 title From: DIN V VDE 0884-10 (VDE V 0884-10) and UL 1577 Insulation Characteristics To:
Added the DWW package to ................................................................................................................................................ 18
• Changed Table 2 ................................................................................................................................................................. 18
• Changed columns VDE and CSA to Table 4 ....................................................................................................................... 19
• Changed title From: IEC Safety Limiting Values To: Safety Limiting Values ....................................................................... 20
• Changed the table in Safety Limiting Values, added IS DW-16 package options ................................................................ 20
• Changed Figure 13 .............................................................................................................................................................. 20
• Deleted INPUT-SIDE and OUTPUT-SIDE from columns 1 and 2 of Table 6 ..................................................................... 21
• Changed Note (1) of Table 6 ............................................................................................................................................... 21
• Changed the Application Information section ....................................................................................................................... 23
• Changed the Typical Application section and Figure 16 ...................................................................................................... 23
• Added text and Figure 17 to the Detailed Design Procedure section ................................................................................. 24
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ISO7821F (etcTI)
Dual Channel Digital Isolator

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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
Changes from Original (November 2014) to Revision A
Page
• Changed From: A product preview that included only page 1 and the pinout section To: A complete data sheet .............. 1
• Added Note: "This coupler..." to the High Voltage Feature Description section ................................................................. 17
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ISO7821F (etcTI)
Dual Channel Digital Isolator

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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
5 Pin Configuration and Functions
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DW Package
16-Pin (SOIC)
Top View
GND1 1
NC 2
VCC1 3
OUTA 4
INB 5
NC 6
GND1 7
NC 8
16 GND2
15 NC
14 VCC2
13 INA
12 OUTB
11 NC
10 NC
9 GND2
DWW Package
16-Pin (SOIC)
Top View
VCC1 1
GND1 2
NC 3
EN1 4
OUTA 5
INB 6
NC 7
GND1 8
16 VCC2
15 GND2
14 NC
13 EN2
12 INA
11 OUTB
10 NC
9 GND2
NAME
GND1
GND2
INA
INB
NC
OUTA
OUTB
VCC1
VCC2
EN1
EN2
PIN
NO.
DW
1, 7
9, 16
13
5
2, 6, 8, 10 ,11,
15
4
12
3
14
NO.
DWW
2,8
9,15
12
6
3,7,10,14
5
11
1
16
4
13
Pin Functions
I/O DESCRIPTION
– Ground connection for VCC1
– Ground connection for VCC2
I Input, channel A
I Input, channel B
– Not connected
O Output, channel A
O Output, channel B
– Power supply, VCC1
– Power supply, VCC2
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and
in high-impedance state when EN1 is low.
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and
in high-impedance state when EN2 is low.
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Dual Channel Digital Isolator

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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
6 Specifications
6.1 Absolute Maximum Ratings(1)
Supply voltage(2)
Voltage
Output Current
Surge Immunity
VCC1, VCC2
INx, OUTx
IO
MIN
–0.5
–0.5
-15
MAX
6
VCC + 0.5(3)
15
12.8
UNIT
V
V
mA
kV
Storage temperature, Tstg
–65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VESD
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
VALUE
±6000
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
V
6.3 Recommended Operating Conditions
MIN
VCC1, VCC2
IOH
Supply voltage
High-level output current
IOL Low-level output current
VIH High-level input voltage
VIL Low-level input voltage
DR Signaling rate
TJ Junction temperature(2)
TA Ambient temperature
VCCO (1) = 5 V
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 5 V
VCCO = 3.3 V
VCCO = 2.5 V
2.25
-4
-2
-1
0.7 x VCCI (1)
0
0
-55
-55
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
(2) To maintain the recommended operating conditions for TJ, see the Thermal Information table.
TYP
25
MAX
5.5
UNIT
V
mA
4
2
1
VCCI
0.3 x VCCI
100
150
125
mA
V
V
Mbps
°C
°C
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Dual Channel Digital Isolator

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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
www.ti.com
6.4 Thermal Information
THERMAL METRIC(1)
ISO7821
DW (SOIC)
DWW (SOIC)
UNIT
16 PINS
16-PINS
RθJA
RθJC(top)
RθJB
ψJT
ψJB
RθJC(bottom)
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
84.7 84.7 °C/W
47.3 46.0 °C/W
49.4 54.5 °C/W
19.1 18.5 °C/W
48.8 53.8 °C/W
n/a n/a °C/W
(1) For more information about trdational and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Dissipation Characteristics
PD Maximum power dissipation by ISO7821x
PD1
Maximum power dissipation by side-1 of
ISO7821x
PD2
Maximum power dissipation by side-2 of
ISO7821x
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, input a 50 MHz 50% duty cycle
square wave
VALUE
100
50
50
UNIT
mW
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ISO7821F (etcTI)
Dual Channel Digital Isolator

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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
6.6 Electrical Characteristics, 5 V
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOH
VOL
VI(HYS)
IIH
IIL
CMTI
High-level output voltage
Low-level output voltage
Input threshold voltage hysteresis
High-level input current
Low-level input current
Common-mode transient immunity
Supply Current - ISO7821DW and ISO7821FDW
IOH = –4 mA; see Figure 7
IOL = 4 mA; see Figure 7
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
VI = VCCI or 0 V; see Figure 10
VCCO (1) – 0.4
0.1 x VCCO (1)
-10
100
ICC1, ICC2 DC Signal
ICC1, ICC2 DC Signal
VI = 0 V (ISO7821F) , VI =
VCCI (1)(ISO7821)
VI = VCCI(1) (ISO7821F) , VI = 0 V
(ISO7821)
ICC1, ICC2 1 Mbps
ICC1, ICC2 10 Mbps
ICC1, ICC2 100 Mbps
Supply Current - ISO7821DWW and ISO7821FDWW
All channels switching with square wave
clock input;
CL = 15 pF
ICC1, ICC2 Disable
ICC1, ICC2 Disable
ICC1, ICC2 DC Signal
ICC1, ICC2 DC Signal
EN1 = EN2 = 0V, VI = 0 V (ISO7821F) ,
VI = VCCI(1)(ISO7821)
EN1 = EN2 = 0V, VI = VCCI(1)
(ISO7821F) , VI = 0 V (ISO7821)
VI = 0 V (ISO7821F) , VI =
VCCI (1)(ISO7821)
VI = VCCI(1) (ISO7821F) , VI = 0 V
(ISO7821)
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1 Mbps
10 Mbps
100 Mbps
All channels switching with square wave
clock input; CL = 15 pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
TYP
VCCO – 0.2
0.2
MAX
0.4
10
UNIT
V
V
V
μA
kV/μs
1.2 1.7 mA
2.4 3.4 mA
1.8 2.6 mA
2.4 3.2 mA
7.5 9.3 mA
0.7 1.1 mA
1.8 2.9 mA
1.2 1.7 mA
2.4 3.5 mA
1.9 2.7 mA
2.5 3.2 mA
7.7 9.3 mA
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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
6.7 Electrical Characteristics, 3.3 V
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOH
VOL
VI(HYS)
IIH
IIL
CMTI
High-level output voltage
Low-level output voltage
Input threshold voltage hysteresis
High-level input current
Low-level input current
Common-mode transient immunity
Supply Current - ISO7821DW and ISO7821FDW
IOH = –2 mA; see Figure 7
IOL = 2 mA; see Figure 7
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
VI = VCCI or 0 V; see Figure 10
VCCO (1) – 0.4
0.1 x VCCO
-10
100
ICC1, ICC2 DC Signal
ICC1, ICC2 DC Signal
VI = 0 V (ISO7821F) , VI =
VCCI (1)(ISO7821)
VI = VCCI(1) (ISO7821F) , VI = 0 V
(ISO7821)
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1 Mbps
10 Mbps
100 Mbps
All channels switching with square wave
clock input; CL = 15 pF
Supply Current - ISO7821DWW and ISO7821FDWW
ICC1, ICC2 Disable
ICC1, ICC2 Disable
ICC1, ICC2 DC Signal
ICC1, ICC2 DC Signal
EN1 = EN2 = 0V, VI = 0 V (ISO7821F) ,
VI = VCCI(1)(ISO7821)
EN1 = EN2 = 0V, VI = VCCI(1)
(ISO7821F) , VI = 0 V (ISO7821)
VI = 0 V (ISO7821F) , VI =
VCCI (1)(ISO7821)
VI = VCCI(1) (ISO7821F) , VI = 0 V
(ISO7821)
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1 Mbps
10 Mbps
100 Mbps
All channels switching with square wave
clock input; CL = 15 pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
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TYP
VCCO – 0.2
0.2
MAX
0.4
10
UNIT
V
V
V
μA
kV/μs
1.2 1.7 mA
2.4 3.4 mA
1.8 2.6 mA
2.2 3 mA
5.8 7.1 mA
0.7 1.1 mA
1.8 2.9 mA
1.2 1.7 mA
2.4 3.5 mA
1.9 2.6 mA
2.3 3 mA
5.9 7.1 mA
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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
6.8 Electrical Characteristics, 2.5 V
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOH
VOL
VI(HYS)
IIH
IIL
CMTI
High-level output voltage
Low-level output voltage
Input threshold voltage hysteresis
High-level input current
Low-level input current
Common-mode transient immunity
Supply Current - ISO7821DW and ISO7821FDW
IOH = –1 mA; see Figure 7
IOL = 1 mA; see Figure 7
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
VI = VCCI or 0 V; see Figure 10
VCCO (1) – 0.4
0.1 x VCCO
-10
100
ICC1, ICC2 DC Signal
ICC1, ICC2 DC Signal
VI = 0 V (ISO7821F) , VI =
VCCI (1)(ISO7821)
VI = VCCI(1) (ISO7821F) , VI = 0 V
(ISO7821)
ICC1, ICC2 1 Mbps
ICC1, ICC2 10 Mbps
ICC1, ICC2 100 Mbps
Supply Current - ISO7821DWW and ISO7821FDWW
All channels switching with square wave
clock input; CL = 15 pF
ICC1, ICC2 Disable
ICC1, ICC2 Disable
ICC1, ICC2 DC Signal
ICC1, ICC2 DC Signal
EN1 = EN2 = 0V, VI = 0 V (ISO7821F) ,
VI = VCCI(1)(ISO7821)
EN1 = EN2 = 0V, VI = VCCI(1)
(ISO7821F) , VI = 0 V (ISO7821)
VI = 0 V (ISO7821F) , VI =
VCCI (1)(ISO7821)
VI = VCCI(1) (ISO7821F) , VI = 0 V
(ISO7821)
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
1 Mbps
10 Mbps
100 Mbps
All channels switching with square wave
clock input; CL = 15 pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
TYP
VCCO – 0.2
0.2
MAX
0.4
10
UNIT
V
V
V
μA
kV/μs
1.2 1.7 mA
2.4 3.4 mA
1.8 2.6 mA
2.1 2.8 mA
4.9 5.9 mA
0.7 1.1 mA
1.8 2.9 mA
1.2 1.7 mA
2.4 3.5 mA
1.9 2.6 mA
2.2 2.9 mA
5 6 mA
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6.9 Switching Characteristics, 5 V
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
PWD (1)
tsk(pp) (2)
tr
tf
tPHZ
Propagation delay time
Pulse width distortion |tPHL – tPLH|
Part-to-part skew time
Output signal rise time
Output signal fall time
Disable propagation delay, high-to-high impedance output for
ISO7821DWW and ISO7821FDWW
See Figure 7
See Figure 7
tPLZ
Disable propagation delay, low-to-high impedance output for
ISO7821DWW and ISO7821FDWW
Enable propagation delay, high impedance-to-high output for
ISO7821DWW
tPZH Enable propagation delay, high impedance-to-high output for
ISO7821FDWW
See Figure 8
Enable propagation delay, high impedance-to-low output for
ISO7821DWW
tPZL Enable propagation delay, high impedance-to-low output for
ISO7821FDWW
tfs Default output delay time from input power loss
Measured from the time VCC
goes below 1.7 V. See Figure 9
tie Time interval error
216 - 1 PRBS data at 100 Mbps
MIN
6
TYP
10.7
0.6
2.4
2.4
12
12
10
2
2
10
0.2
1
MAX
16
4.6
4.5
3.9
3.9
UNIT
ns
ns
ns
20 ns
20 ns
20 ns
2.5 μs
2.5 μs
20 ns
9 μs
ns
(1) Also known as Pulse Skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.10 Switching Characteristics, 3.3 V
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
PWD (1)
tsk(pp) (2)
tr
tf
tPHZ
Propagation delay time
Pulse width distortion |tPHL – tPLH|
Part-to-part skew time
Output signal rise time
Output signal fall time
Disable propagation delay, high-to-high impedance output for
ISO7821DWW and ISO7821FDWW
See Figure 7
See Figure 7
tPLZ
Disable propagation delay, low-to-high impedance output for
ISO7821DWW and ISO7821FDWW
Enable propagation delay, high impedance-to-high output for
ISO7821DWW
tPZH
See Figure 8
Enable propagation delay, high impedance-to-high output for
ISO7821FDWW
Enable propagation delay, high impedance-to-low output for
ISO7821DWW
tPZL Enable propagation delay, high impedance-to-low output for
ISO7821FDWW
tfs Default output delay time from input power loss
Measured from the time VCC goes
below 1.7 V. See Figure 9
tie Time interval error
216 - 1 PRBS data at 100 Mbps
MIN
6
TYP
10.8
0.7
1.3
1.3
17
17
17
2
2
17
0.2
1
MAX
16
4.7
4.5
3
3
32
UNIT
ns
ns
ns
32 ns
32 ns
2.5 μs
2.5 μs
32 ns
9 μs
ns
(1) Also known as Pulse Skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
6.11 Switching Characteristics, 2.5 V
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
PWD (1)
tsk(pp) (2)
tr
tf
tPHZ
Propagation delay time
Pulse width distortion |tPHL – tPLH|
Part-to-part skew time
Output signal rise time
Output signal fall time
Disable propagation delay, high-to-high impedance output for
ISO7821DWW and ISO7821FDWW
See Figure 7
See Figure 7
tPLZ
Disable propagation delay, low-to-high impedance output for
ISO7821DWW and ISO7821FDWW
Enable propagation delay, high impedance-to-high output for
ISO7821DWW
tPZH
Enable propagation delay, high impedance-to-high output for
See Figure 8
ISO7821FDWW
Enable propagation delay, high impedance-to-low output for
ISO7821DWW
tPZL Enable propagation delay, high impedance-to-low output for
ISO7821FDWW
tfs Default output delay time from input power loss
Measured from the time VCC goes
below 1.7 V. See Figure 9
tie Time interval error
216 - 1 PRBS data at 100 Mbps
MIN TYP
7.5 11.7
0.7
1.8
1.8
22
MAX
17.5
4.7
4.5
3.5
3.5
45
UNIT
ns
ns
ns
22 45 ns
18 45 ns
2 2.5 μs
2 2.5 μs
18 45 ns
0.2 9 μs
1 ns
(1) Also known as Pulse Skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
6.12 Typical Characteristics
24
ICC1 at 2.5 V
ICC2 at 2.5 V
20 ICC1 at 3.3 V
ICC2 at 3.3 V
16
ICC1 at 5.0 V
ICC2 at 5.0 V
12
8
4
0
0 25 50 75 100 125 150
Data Rate (Mbps)
D001
TA = 25°C
CL = 15 pF
Figure 1. Supply Current vs Data Rate (with 15 pF Load)
6
5
4
3
2
1
0
-15 -10
-5
High-Level Output Current (mA)
TA = 25°C
VCC at 2.5V
VCC at 3.3V
VCC at 5.0V
0
D001
Figure 3. High-Level Output Voltage vs High-level Output
Current
2.25
2.20
2.15
2.10
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
2.05
2.00
1.95
1.90
1.85
1.80
1.75
1.70
-50
0 50 100
Free-Air Temperature (oC )
150
D001
Figure 5. Power Supply Undervoltage Threshold vs Free-Air
Temperature
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10
ICC1 at 2.5 V
ICC2 at 2.5 V
8 ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5.0 V
6 ICC2 at 5.0 V
4
2
0
0 25 50 75 100 125 150
Data Rate (Mbps)
D002
TA = 25°C
CL = No Load
Figure 2. Supply Current vs Data Rate (with No Load)
1.0
0.9
VCC at 2.5V
VCC at 3.3V
0.8 VCC at 5.0V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
5 10
Low-Level Output Current (mA)
TA = 25°C
15
D001
Figure 4. Low-Level Output Voltage vs Low-Level Output
Current
15
14
13
12
11
10
9
tPLH at 2.5 V
8 tPHL at 2.5 V
7
tPHL at 3.3 V
tPLH at 3.3 V
6 tPLH at 5 V
tPHL at 5 V
5
-60 -30
0
30 60 90 120
Free-Air Temperature (oC )
D006
Figure 6. Propagation Delay Time vs Free-Air Temperature
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7 Parameter Measurement Information
ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
VCCI
IN
OUT
VI 50%
50%
0V
Input
Generator
(See Note A)
VI 50
tPLH
CL
VO See Note B
VO 50%
90%
10%
tPHL
50%
VOH
VOL
tr tf
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A. The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr 3
ns, tf 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7. Switching Characteristics Test Circuit and Voltage Waveforms
IN
0V
Input
Generator
(See Note A)
VI
VCCO
RL = 1 k ±1%
OUT
EN
CL
See Note B
50
VO
VI VCC / 2
tPZL
VO 50%
VCC / 2
tPLZ
VCC
0V
VOH
0.5 V
VOL
3 V IN
Input
Generator
(See Note A)
VI
OUT
VO
EN
CL
See Note B
50
VI
RL = 1 k ±1%
VO
tPZH
VCC / 2
50%
tPHZ
VCC / 2
VCC
0V
VOH
0.5 V
0V
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A. The input pulse is supplied by a generator having the following characteristics: PRR 10 kHz, 50% duty cycle,
tr 3 ns, tf 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
Parameter Measurement Information (continued)
VI
VCC
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
IN
OUT
VO
CL
See Note A
VI
VO
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VCC
2.7 V
t fs
50%
0V
fs high VOH
fs low VOL
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A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
C = 0.1 µF ±1%
VCCO
C = 0.1 µF ±1%
IN
S1
Pass-fail criteria:
The output must
remain stable.
OUT
+
EN
CL
See Note A
VOH or VOL
±
GNDI
+ VCM ±
GNDO
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A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
8.1 Overview
ISO7821 employs an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a silicon
dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one
digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after
advanced signal conditioning and produces the output through a buffer stage. These devices also incorporates
advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the
high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator,
Figure 11, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
TX IN
OOK
Modulation
Receiver
EN
TX Signal
Conditioning
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Oscillator
Emissions
Reduction
Techniques
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Figure 11. Conceptual Block Diagram of a Digital Capacitive Isolator
Also a conceptual detail of how the ON/OFF Keying scheme works is shown in Figure 12.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 12. On-Off Keying (OOK) Based Modulation Scheme
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SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
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8.3 Feature Description
ISO7821 is available in two channel configurations and default output state options to enable a variety of
application uses.
PRODUCT
ISO7821
ISO7821F
CHANNEL DIRECTION
1 Forward, 1 Reverse
1 Forward, 1 Reverse
RATED ISOLATION
5700 VRMS / 8000 VPK (1)
5700 VRMS / 8000 VPK (1)
(1) See the Regulatory Information section for detailed isolation ratings.
MAX DATA RATE
100 Mbps
100 Mbps
DEFAULT OUTPUT
High
Low
8.3.1 High Voltage Feature Description
NOTE
This coupler is suitable for 'safe electrical insulation' only within the safety ratings.
Compliance with the safety ratings shall be ensured by means of suitable protective
circuits.
Table 1. Package Insulation and Safety-Related Specifications
(over recommended operating conditions (unless otherwise noted)
CLR
CPG
CTI
RIO
CIO
CI
PARAMETER
TEST CONDITIONS
External clearance
Shortest terminal-to-terminal distance DW-16
through air
DWW-16
External creepage
Shortest terminal-to-terminal distance DW-16
across the package surface
DWW-16
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
Isolation resistance, input to output(1)
Barrier capacitance, input to output(1)
Input capacitance(2)
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C TA max
VIO = 0.4 x sin (2πft), f = 1 MHz
VI = VCC/2 + 0.4 x sin (2πft), f = 1 MHz, VCC = 5 V
MIN
8
14.5
8
14.5
600
1012
1011
TYP MAX
1
2
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.
UNIT
mm
mm
V
pF
pF
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
PARAMETER
Table 2. Insulation Characteristics
TEST CONDITIONS
DTI Distance through the insulation
Minimum internal gap (internal clearance)
VIOWM Maximum working isolation voltage Time dependent dielectric breakdown (TDDB) test
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
VIOSM
VIORM
Maximum surge isolation voltage
Maximum repetitive peak isolation
voltage
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 x VIOSM = 12800 VPK(1) (qualification)
Method a, After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
VPR Input-to-output test voltage
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
Method b1,After environmental tests subgroup 1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
RS Isolation resistance
Pollution degree
VIO = 500 V at TS
Climatic category
UL 1577
VISO Withstanding isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 sec (qualification);
VTEST = 1.2 x VISO = 6840 VRMS , t = 1 sec (100%
production)
(1) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
SPECIFICATION
DW DWW
21 21
1500
2000
2121
2828
UNIT
μm
VRMS
VDC
8000
8000
2121
2545
8000
8000
2828
3394
VPK
VPK
VPK
3394
4525
VPK
3977
5303
>109
2
55/125/21
>109
2
55/125/21
5700
5700
VRMS
Material group
PARAMETER
Overvoltage category /
Installation classification
DW package
DWW package
Table 3. IEC 60664-1 Ratings Table
TEST CONDITIONS
Rated mains voltage 600 VRMS
Rated mains voltage 1000 VRMS
Rated mains voltage 1000 VRMS
SPECIFICATION
I
I–IV
I–III
I–IV
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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
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8.3.1.1 Regulatory Information
DW package certifications are complete; DWW package certifications completed for UL and TUV and planned for
VDE, CSA, and CQC.
Table 4. Regulatory Information
VDE
CSA
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-
12 and DIN EN 60950-1
(VDE 0805 Teil 1):2011-
01
Approved under CSA
Component Acceptance
Notice 5A, IEC 60950-1
and IEC 60601-1
Reinforced insulation
Maximum transient
isolation voltage, 8000
VPK;
Maximum repetitive peak
isolation voltage, 2121
VPK (DW), 2828 VPK
(DWW);
Maximum surge isolation
voltage, 8000 VPK
Reinforced insulation per
CSA 60950-1-07+A1+A2
and IEC 60950-1 2nd Ed.,
800 VRMS (DW package)
and 1450 VRMS (DWW
package) max working
voltage (pollution degree
2, material group I);
2 MOPP (Means of
Patient Protection) per
CSA 60601-1:14 and IEC
60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
working voltage (DW
package)
Certificate number:
40040142
Master contract number:
220991
UL
Recognized under UL
1577 Component
Recognition Program
Single protection, 5700
VRMS
File number: E181974
CQC
Certified according to
GB 4943.1-2011
Reinforced Insulation,
Altitude 5000 m,
Tropical Climate, 250
VRMS maximum
working voltage
Certificate number:
CQC15001121716
TUV
Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/
A1:2010/A12:2011/A2:2013
5700 VRMS Reinforced insulation
per EN 61010-1:2010 (3rd Ed)
up to working voltage of 600
VRMS (DW package) and 1000
VRMS (DWW package)
5700 VRMS Reinforced insulation
per EN 60950-1:2006/A11:2009/
A1:2010/A12:2011/A2:2013 up
to working voltage of 800 VRMS
(DW package) and 1450 VRMS
(DWW package)
Client ID number: 77311
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ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
8.3.1.2 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
Table 5. Safety Limiting
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Safety input, output, or supply RθJA = 84.7°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
IS current for DW-16 package RθJA = 84.7°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
and DWW-16 Packages
RθJA = 84.7°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C
PS Safety input, output, or total RθJA = 84.7°C/W, TJ = 150°C, TA = 25°C
power
268
410
537
1476
mA
mW
TS Maximum safety temperature
150 °C
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a High-K test board for Leaded Surface Mount Packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
600
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
500 VCC1 = VCC2 = 5.5 V
400
300
200
100
0
0 50 100 150 200
Ambient Temperature (qC)
D014
Figure 13. Thermal Derating Curve for Safety Limiting
Current per VDE
1600
1400
Power
1200
1000
800
600
400
200
0
0 50 100 150 200
Ambient Temperature (qC)
D015
Figure 14. Thermal Derating Curve for Safety Limiting
Power per VDE
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8.4 Device Functional Modes
ISO7821 functional modes are shown in Table 6.
Table 6. ISO7821 Function Table(1)
VCCI
VCCO
PU PU
X PU
PD PU
X PD
INPUT
(INx) (2)
H
L
Open
X
X
X
OUTPUT ENABLE
(ENx)
(DWW Package Only)
H or open
H or open
H or open
L
H or open
X
OUTPUT
(OUTx)
COMMENTS
H
L
Default
Z
Default
Undetermined
Normal Operation:
A channel output assumes the logic state of its input.
Default mode: When INx is open, the corresponding channel output
goes to its default high logic state. Default= High for ISO7821 and Low
for ISO7821F.
A low value of Output Enable causes the outputs to be high-
impedance.
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option.Default= High for
ISO7821 and Low for ISO7821F.
When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of its input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC 2.25 V); PD = Powered down (VCC 1.7 V); X = Irrelevant; H
= High level; L = Low level; Z = High impedance
(2) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
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8.4.1 Device I/O Schematics
Input (Device Without Suffix F)
VCCI
VCCI VCCI
VCCI
985 W
INx
1.5 MW
Output
VCCO
~20 W
OUTx
ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
Input (Device With Suffix F)
VCCI
VCCI
VCCI
985 W
INx
1.5 MW
VCCO
Enable
VCCO VCCO
VCCO
1970 W
Enx
2 MW
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Figure 15. Device I/O Schematics
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9 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7821 is a high-performance, dual-channel digital isolator with 5.7 kVRMS isolation voltage per UL 1577. It
utilizes single-ended CMOS-logic switching technology. Its supply voltage range is from 2.25 V to 5.5 V for both
supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type
or standard.
9.2 Typical Application
ISO7821 can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter,
transformer driver, and voltage regulator to create an isolated 4-20 mA current loop.
VS
3.3 V
0.1 F
2
1:1.33 MBR0520L
VCC
3
D2
SN6501
1
GND D1 10 F
4, 5
MBR0520L
Isolation Barrier
10 F 0.1 F
1
IN
5 3.3VISO
OUT
TPS76333
10 F
3
EN
2
GND
0.1 F
20 0.1 F
0.1 F
0.1 F
0.1 F
2
5
XOUT
DVCC
6 MSP430G2132
XIN
P3.0 11
P3.1 12
DVSS
4
3 14
VCC1
VCC2
4 INA 13
OUTA ISO7821
12
5 OUTB
INB
GND1
GND2
1, 7 9, 16
15 3
10
LOW
8 ERRLVL
5 DBACK
4
DIN
C1
VA VD
DAC161P997
C2 C3 COMA
16
BASE
OUT 9
COMD
22
14 13 12 1
3 × 2.2 nF
2
LOOP+
0.1 F 1 F
LOOP±
Figure 16. Isolated 4-20 mA Current Loop
9.2.1 Design Requirements
For the ISO7821, use the parameters shown in Table 7.
Table 7. Design Parameters
PARAMETER
Supply voltage
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
VALUE
2.25 V to 5.5 V
0.1 µF
0.1 µF
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9.2.2 Detailed Design Procedure
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,
ISO7821 only needs two external bypass capacitors to operate.
VCC1
0.1 µF
GND1
OUTA
INB
GND1
GND1
GND1 1
NC 2
VCC1 3
OUTA 4
INB 5
NC 6
GND1 7
NC 8
ISO7821DW
16 GND2
15 NC
14 VCC2
13 INA
12 OUTB
11 NC
10 NC
9 GND2
GND2
GND2
VCC2
0.1 µF
GND2
INA
OUTB
Figure 17. Typical ISO7821 Circuit Hook-up
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7821
incorporate many chip-level design improvements for overall system robustness. Some of these improvements
include:
• Robust ESD protection for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.2.3 Application Performance Curve
Typical eye diagram of ISO7821 indicate low jitter and wide open eye at the maximum data rate of 100 Mbps.
Figure 18. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 datasheet (SLLSEA0) .
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11 Layout
ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
11.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-
extinguishing flammability-characteristics.
11.2 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 19). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
11.3 Layout Example
High-speed traces
Ground plane
Power plane
Low-speed traces
10 mils
40 mils
10 mils
Keep this
space free
from planes,
traces, pads,
and vias
Figure 19. Layout Example
FR-4
0r ~ 4.5
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12 Device and Documentation Support
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12.1 Documentation Support
12.1.1 Related Documentation
See the Isolation Glossary (SLLA353)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
PARTS
ISO7821
ISO7821F
PRODUCT FOLDER
Click here
Click here
Table 8. Related Links
SAMPLE & BUY
Click here
Click here
TECHNICAL
DOCUMENTS
Click here
Click here
TOOLS &
SOFTWARE
Click here
Click here
SUPPORT &
COMMUNITY
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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DW0016B
10.63
9.97
TYP
A
PIN 1 ID
AREA
1
10.5
10.1
NOTE 3
ISO7821, ISO7821F
SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016
PACKAGE OUTLINE
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
14X 1.27
16
C
SEATING PLANE
0.1 C
2X
8.89
8
B
7.6
7.4
NOTE 4
9
16X
0.51
0.31
0.25 C A B
2.65 MAX
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0 -8
1.27
0.40
(1.4)
0.3
0.1
DETAIL A
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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DW0016B
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EXAMPLE BOARD LAYOUT
SOIC - 2.65 mm max height
SOIC
16X (2)
1
16X (0.6)
SYMM
SEE
DETAILS
16
16X (1.65)
1
16X (0.6)
SYMM
SYMM
SEE
DETAILS
16
SYMM
14X (1.27)
8
R0.05 TYP
(9.3)
9
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
14X (1.27)
R0.05 TYP
8
(9.75)
9
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
4221009/B 07/2016
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