71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
71321SA/LA
71421SA/LA
Features
High-speed access
– Commercial: 20/35/55ns (max.)
– Industrial: 25/55ns (max.)
Low-power operation
– IDT71321/IDT71421SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT71321/421LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
Two INT flags for port-to-port communications
MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
On-chip port arbitration logic (IDT71321 only)
BUSY output flag on IDT71321; BUSY input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and
64-Pin STQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A10L
A0L
I/O
Control
I/O
Control
Address
Decoder
11
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
11
CER
OER
R/WR
I/O0R-I/O7R
BUSYR(1,2)
A10R
A0R
INTL(2)
NOTES:
1. IDT71321(MASTER): BUSYisopendrainoutputandrequirespullupresistorof270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
©2019 Integrated Device Technology, Inc.
1
INTR(2)
2691 drw 01
SEPTEMBER 2019
DSC-2691/17


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor communications.
The IDT71321 is designed to be used as a stand-alone 8-bit Dual-
Port Static RAM or as a "MASTER" Dual-Port Static RAM together
with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap-
proach in 16-or-more-bit memory system applications results in full
speed, error-free operation without the need for additional discrete
logic.
Both devices provide two independent ports with separate control,
Industrial and Commercial Temperature Ranges
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in 52-pin PLCC,
52-pin STQFP, 64-pin TQFP, and 64-pin STQFP.
Pin Configurations(1,2,3)
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
I/O 0R
I/O 1R
I/O 2R
I/O 3R
I/O 4R
I/O 5R
I/O 6R
20 19 18 17 16 15 14 13 12 11 10 9 8
21 7
22 6
23 5
24 4
25 3
26 2
27
71321/421
1
28 PLG52(4) 52
29 PLCC
Top View
30
51
50
31 49
32 48
33 47
34 35 36 37 38 39 40 41 42 43 44 45 46
A0L
OEL
A10L
INTL
BUSYL
R/WL
CEL
VCC
CER
R/WR
BUSYR
INTR
A10R
2691 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PLG52 package body is approximately .75 in x .75 in x .17 in.
PNG64 package body is approximately 14mm x 14mm x 1.4mm.
PPG64 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
N/C
N/C
A10R
INTR
BUSYR
R/WR
CER
VCC
VCC
CEL
R/WL
BUSYL
INTL
A10L
N/C
N/C
48 4746 45444342 41 40 39 38 3736 3534 33
49 32
50 31
51 30
52 29
53 28
54 27
55
71321/421
26
56
PNG64/PPG64(4)
25
57 24
58
59
64-Pin TQFP
64-Pin STQFP
Top View
23
22
60 21
61 20
62 19
63 18
64 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I/O5R
I/O4R
N/C
I/O3R
I/O2R
I/O1R
I/O0R
GND
GND
N/C
I/O7L
I/O6L
I/O5L
I/O4L
N/C
I/O3L
2691 drw 03
6.242


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Pin Configurations (continued)(1,2,3)
Industrial and Commercial Temperature Ranges
A10R
INTR
BUSYR
R/WR
CER
VCC
CEL
R/WL
BUSYL
INTL
A10L
OEL
A0L
39 38 37 36 35 34 33 32 31 30 29 28 27
40 26
41 25
42 24
43 23
44 22
45
71321
PPG52(4)
21
46 20
47
52-Pin STQFP
19
48
Top View
18
49 17
50 16
51 15
52 14
1 2 3 4 5 6 7 8 9 10 11 12 13
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
GND
N/C
I/O7L
I/O6L
I/O5L
I/O4L
2691 drw 03a
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PPG52 package body is approximately 10mm x 10mm x 1.4mm.
4. Thispackagecodeisusedtoreferencethepackagediagram.
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
Symbol
Parameter
Conditions(2)
Max. Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT Output Capacitance
VOUT = 3dV
10 pF
NOTES:
2691 tbl 00
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
TBIAS Temperature
Under Bias
-55 to +125
oC
TSTG Storage
Temperature
-65 to +150
oC
IOUT DC Output
Current
50 mA
Recommended Operating
Temperature and Supply Voltage(1,2)
Grade
Ambient
Temperature
GND
Vcc
Commercial
0OC to +70OC
0V
5.0V + 10%
Industrial
-40OC to +85OC
0V
5.0V + 10%
NOTES:
2691 tbl 02
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Recommended DC Operating
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VCC Supply Voltage
4.5 5.0 5.5 V
GND Ground
0 0 0V
VIH Input High Voltage
2.2 ____ 6.0(2) V
VIL Input Low Voltage
-0.5(1)
____
0.8
V
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
2691 tbl 03
NOTES:
2691 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
6.342


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4) (VCC = 5.0V ± 10%)
71321X20
71421X20
Com'l Only
Symbol
Parameter
ICC Dynamic Operating
Current
(Both Ports Active)
CEL and CER = VIL,
Outputs Disabled
f = fMAX(2)
Test Condition
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(2)
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(2)
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
ISB4 Full Standby Current
(One Port -
CMOS Level Inputs)
CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX(2)
Version
COM'L
SA
LA
IND SA
LA
COM'L
SA
LA
IND SA
LA
COM'L
SA
LA
IND SA
LA
COM'L
SA
LA
IND SA
LA
COM'L
SA
LA
IND SA
LA
Typ.
110
110
____
____
30
30
____
____
65
65
____
____
1.0
0.2
____
____
60
60
____
____
Max.
250
200
____
____
65
45
____
____
165
125
____
____
15
5
____
____
155
115
____
____
71321X25
71421X25
Com'l
& Ind
Typ. Max.
110 220
110 170
110 270
110 220
30 65
30 45
30 75
30 55
65 150
65 115
65 170
65 140
1.0 15
0.2 5
1.0 30
0.2 10
60 145
60 105
60 165
60 130
Unit
mA
mA
mA
mA
mA
Symbol
Parameter
ICC Dynamic Operating
Current
(Both Ports Active)
CEL and CER = VIL,
Outputs Disabled
f = fMAX(2)
Test Condition
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(2)
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(2)
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
ISB4 Full Standby Current
(One Port -
CMOS Level Inputs)
CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX(2)
71321X35
71421X35
Com'l Only
Version
COM'L
SA
LA
IND SA
LA
COM'L
SA
LA
IND SA
LA
COM'L
SA
LA
IND SA
LA
COM'L
SA
LA
IND SA
LA
COM'L
SA
LA
IND SA
LA
Typ.
80
80
____
____
25
25
____
____
50
50
____
____
1.0
0.2
____
____
45
45
____
____
Max.
165
120
____
____
65
45
____
____
125
90
____
____
15
4
____
____
110
85
____
____
71321X55
71421X55
Com'l
& Ind
2691 tbl 04a
Typ. Max. Unit
65 155 mA
65 110
65 190
65 140
20 65 mA
20 35
20 70
20 50
40 110 mA
40 75
40 125
40 90
1.0 15 mA
0.2 4
1.0 30
0.2 10
40 100 mA
40 70
40 110
40 85
NOTES:
2691 tbl 04b
1. 'X' in part numbers indicates power rating (SA or LA).
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
6.442


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
71321SA
71421SA
71321LA
71421LA
Symbol
Parameter
Test Conditions
Min. Max. Min. Max. Unit
|ILI| Input Leakage Current(1)
|ILO| Output Leakage Current(1)
VCC = 5.5V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC,
VCC - 5.5V
___ 10 ___
___ 10 ___
5 µA
5 µA
VOL Output Low Voltage (I/O0-I/O7)
IOL = 4mA
___ 0.4 ___ 0.4 V
VOL Open Drain Output
Low Voltage (BUSY/INT)
IOL = 16mA
___ 0.5 ___ 0.5 V
VOH Output High Voltage
IOH = -4mA
2.4 ___ 2.4 ___ V
NOTE:
1. At Vcc < 2.0V leakages are undefined.
2691 tbl 05
Data Retention Characteristics (LA Version Only)
Symbol
Parameter
Test Condition
VDR VCC for Data Retention
ICCDR
Data Retention Current
VCC = 2.0V, CE > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
tCDR(3)
Chip Deselect to Data Retention Time
tR(3) Operation Recovery Time
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
COM'L
IND
Min.
2.0
____
____
0
tRC(2)
Typ.(1)
____
100
100
____
____
Max. Unit
V____
1500 µA
4000 µA
____ ns
____ ns
2691 tbl 06
Data Retention Waveform
DATA RETENTION MODE
VCC
CE
4.5V
tCDR
VIH
VDR 2.0V
VDR
4.5V
tR
VIH
,
2691 drw 04
6.542


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1,2 and 3
2691 tbl 07
Industrial and Commercial Temperature Ranges
DATA OUT
775Ω
5V
1250Ω
30pF*
*100pF for 55ns versions
DATA OUT
775Ω
5V
1250Ω
5pF*
Figure 1. AC Output Test Load
5V
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
270Ω
BUSY or INT
30pF*
*100pF for 55ns versions
Figure 3. BUSY and INT
AC Output Test Load
2691 drw 05
6.642


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(2)
71321X20
71421X20
Com'l Only
Symbol
Parameter
Min. Max.
71321X25
71421X25
Com'l
& Ind
Min. Max.
Unit
READ CYCLE
tRC Read Cycle Time
tAA Address Access Time
tACE Chip Enable Access Time
tAOE Output Enable Access Time
tOH Output Hold from Address Change
tLZ Output Low-Z Time(1,3)
tHZ Output High-Z Time(1,3)
tPU Chip Enable to Power Up Time (3)
tPD Chip Disable to Power Down Time(3)
20 ____
____ 20
____ 20
____ 11
3 ____
0 ____
____ 10
0 ____
____ 20
71321X35
71421X35
Com'l Only
25 ____
____ 25
____ 25
____ 12
3 ____
0 ____
____ 10
0 ____
____ 25
71321X55
71421X55
Com'l
& Ind
ns
ns
ns
ns
ns
ns
ns
ns
ns
2691 tbl 08a
Symbol
Parameter
Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time
35 ____ 55 ____ ns
tAA Address Access Time
____ 35 ____ 55 ns
tACE Chip Enable Access Time
____ 35 ____ 55 ns
tAOE Output Enable Access Time
____ 20 ____ 25 ns
tOH Output Hold from Address Change
tLZ Output Low-Z Time(1,3)
tHZ Output High-Z Time(1,3)
tPU Chip Enable to Power Up Time (3)
tPD Chip Disable to Power Down Time(3)
3 ____ 3 ____ ns
0 ____ 5 ____ ns
____ 15 ____ 25 ns
0 ____ 0 ____ ns
____ 35 ____ 50 ns
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. 'X' in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
2691 tbl 08b
6.742


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
ADDRESS
DATAOUT
BUSYOUT
tAA
tOH
PREVIOUS DATA VALID
tRC
DATA VALID
tOH
tBDDH (2,3)
2691 drw 06
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side (3)
CE
OE
DATAOUT
ICC
CURRENT
ISS
tACE
tAOE(4)
tLZ(1)
tLZ (1)
tPU
50%
tHZ (2)
tHZ (2)
VALID DATA
tPD(4)
50%
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
2691 drw 07
6.842


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol
Parameter
Min. Max. Min. Max. Unit
WRITE CYCLE
tWC Write Cycle Time(2)
20 ____ 25 ____ ns
tEW Chip Enable to End-of-Write
15 ____ 20 ____ ns
tAW Address Valid to End-of-Write
tAS Address Set-up Time
tWP Write Pulse Width(3)
15 ____ 20 ____ ns
0 ____ 0 ____ ns
15 ____ 15 ____ ns
tWR Write Recovery Time
0 ____ 0 ____ ns
tDW Data Valid to End-of-Write
tHZ Output High-Z Time(1)
10 ____ 12 ____ ns
____ 10 ____ 10 ns
tDH Data Hold Time
tWZ Write Enable to Output in High-Z(1)
tOW Output Active from End-of-Write(1)
0 ____ 0 ____ ns
____ 10 ____ 10 ns
0 ____ 0 ____ ns
2691 tbl 09a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Parameter
Min. Max. Min. Max. Unit
WRITE CYCLE
tWC Write Cycle Time(2)
35 ____ 55 ____ ns
tEW Chip Enable to End-of-Write
tAW Address Valid to End-of-Write
30 ____ 40 ____ ns
30 ____ 40 ____ ns
tAS Address Set-up Time
tWP Write Pulse Width(3)
tWR Write Recovery Time
0 ____ 0 ____ ns
25 ____ 30 ____ ns
0 ____ 0 ____ ns
tDW Data Valid to End-of-Write
tHZ Output High-Z Time(1)
tDH Data Hold Time
tWZ Write Enable to Output in High-Z(1)
tOW Output Active from End-of-Write(1)
15 ____ 20 ____ ns
____ 15 ____ 25 ns
0 ____ 0 ____ ns
____ 15 ____ 30 ns
0 ____ 0 ____ ns
NOTES:
2691 tbl 09b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
4. 'X' in part numbers indicates power rating (SA or LA).
6.942


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
ADDRESS
OE
CE
R/W
DATA OUT
DATA IN
tWC
tAS(6)
(4)
tAW
tWP(2)
tWZ(7)
tDW
tHZ(7)
tWR(3)
tOW
tDH
tHZ(7)
(4)
2691 drw 08
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
ADDRESS
CE
R/W
DATAIN
tAS(6)
tWC
tAW
tEW(2)
tDW
tWR(3)
tDH
2691 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
61.402


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol
BUSY TIMING (For MASTER 71321)
Parameter
Min. Max. Min. Max. Unit
tBAA BUSY Access Time from Address
____ 20 ____ 20 ns
tBDA BUSY Disable Time from Address
____ 20 ____ 20 ns
tBAC BUSY Access Time from Chip Enable
tBDC BUSY Disable Time from Chip Enable
tWH Write Hold After BUSY(5)
tWDD Write Pulse to Data Delay(1)
tDDD Write Data Valid to Read Data Delay(1)
tAPS Arbitration Priority Set-up Time(2)
tBDD BUSY Disable to Valid Data(3)
BUSY INPUT TIMING (For SLAVE 71421)
tWB Write to BUSY Input(4)
tWH Write Hold After BUSY(5)
tWDD Write Pulse to Data Delay(1)
tDDD Write Data Valid to Read Data Delay(1)
____ 20 ____ 20 ns
____ 20 ____ 20 ns
12 ____ 15 ____ ns
____ 50 ____ 50 ns
____ 35 ____ 35 ns
5 ____ 5 ____ ns
____ 25 ____ 35 ns
0 ____ 0 ____ ns
12 ____ 15 ____ ns
____ 40 ____ 50 ns
____ 30 ____ 35 ns
2691 tbl 10a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
BUSY TIMING (For MASTER 71321)
Parameter
Min. Max. Min. Max. Unit
tBAA BUSY Access Time from Address
____ 20 ____ 30 ns
tBDA BUSY Disable Time from Address
____ 20 ____ 30 ns
tBAC BUSY Access Time from Chip Enable
____ 20 ____ 30 ns
tBDC BUSY Disable Time from Chip Enable
tWH Write Hold After BUSY(5)
tWDD Write Pulse to Data Delay(1)
tDDD Write Data Valid to Read Data Delay(1)
tAPS Arbitration Priority Set-up Time(2)
____ 20 ____ 30 ns
20 ____ 20 ____ ns
____ 60 ____ 80 ns
____ 35 ____ 55 ns
5 ____ 5 ____ ns
tBDD BUSY Disable to Valid Data(3)
BUSY INPUT TIMING (For SLAVE 71421)
tWB Write to BUSY Input(4)
tWH Write Hold After BUSY(5)
tWDD Write Pulse to Data Delay(1)
tDDD Write Data Valid to Read Data Delay(1)
____ 35 ____ 50 ns
0 ____ 0 ____ ns
20 ____ 20 ____ ns
____ 60 ____ 80 ns
____ 35 ____ 55 ns
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (SA or LA)..
2691 tbl 10b
61.412


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
ADDR"A"
R/W "A"
DATAIN "A"
tAPS(1)
tWC
MATCH
tWP
tDW
VALID
tDH
ADDR"B"
BUSY"B"
tBAA
MATCH
tBDA
tWDD
tBDD
DATAOUT"B"
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT71421).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
VALID
2691 drw 10
Timing Waveform of Write with BUSY(4)
tWP
R/W"A"
BUSY"B"
tWB(3)
R/W"B"
(2)
tWH (1)
,
NOTES:
2691 drw 11
1. tWH must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version (IDT71421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
61.422


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR "A"
AND "B"
ADDRESSES MATCH
CE"B"
CE"A"
BUSY"A"
tAPS(2)
tBAC
tBDC
2691 drw 12
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing(1)
tRC or tWC
ADDR"A"
tAPS(2)
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDR"B"
BUSY"B"
tBAA
tBDA
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. IftAPSisnotsatisfied,the BUSYwillbeassertedononesideortheother,butthereisnoguaranteeonwhichsideBUSY willbeasserted(IDT71321only).
2691 drw 13
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
71321X20
71421X20
Com'l Only
Symbol
INTERRUPT TIMING
tAS Address Set-up Time
tWR Write Recovery Time
tINS Interrupt Set Time
tINR Interrupt Reset Time
Parameter
NOTE:
1. 'X' in part numbers indicates power rating (SA or LA).
Min. Max.
0 ____
0 ____
____ 20
____ 20
71321X25
71421X25
Com'l
& Ind
Min. Max.
Unit
0 ____ ns
0 ____ ns
____ 25 ns
____ 25 ns
2691 tbl 11a
61.432


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(1)
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Parameter
Min. Max. Min. Max. Unit
INTERRUPT TIMING
tAS Address Set-up Time
0 ____ 0 ____ ns
tWR Write Recovery Time
0 ____ 0 ____ ns
tINS Interrupt Set Time
____ 25 ____ 45 ns
tINR Interrupt Reset Time
____ 25 ____ 45 ns
NOTE:
1. 'X' in part numbers indicates power rating (SA or LA).
2691 tbl 11b
Timing Waveform of Interrupt Mode(1)
Set INT
ADDR"A"
R/W"A"
INT"B"
tWC
INTERRUPT ADDRESS (2)
tAS (3)
tWR (4)
tINS (3)
Clear INT
ADDR"B"
tRC
INTERRUPT CLEAR ADDRESS(2)
tAS(3)
OE"B"
INT"B"
tINR(3)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
2691 drw 14
2691 drw 15
,
61.442


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Truth Tables
Truth Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1)
R/W CE OE
D0-7
Function
X HX
Z Port Disabled and in Power-Down Mode, ISB2 or ISB4
X HX
Z CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
L L X DATAIN Data on Port Written Into Memory(2)
H L L DATAOUT Data in Memory Output on Port(3)
HLH
Z High Impedance Outputs
NOTES:
1. A0L – A10L A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
2691 tbl 12
Truth Table II. Interrupt Flag(1,4)
Left Port
R/WL
CEL
OEL A10L-A0L INTL R/WR
L L X 7FF X X
XXX X XX
X X X X L(3) L
X L L 7FE H(2) X
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Right Port
CER OER A10R-A0R
XX
X
LL
7FF
LX
7FE
XX
X
INTR Function
L(2) Set Right INTR Flag
H(3) Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
2691 tbl 13
Truth Table III — Address BUSY Arbitration
Inputs
Outputs
CEL CER
A0L-A10L
A0R-A10R
BUSYL(1) BUSYR(1)
Function
X X NO MATCH
H
H
Normal
HX
MATCH
H
H
Normal
XH
MATCH
H
H
Normal
LL
MATCH
(2)
(2) Write Inhibit(3)
NOTES:
2691 tbl 14
1. Pins BUSYL and BUSYR are both outputs for IDT71321 (Master). Both are inputs for IDT71421 (Slave). BUSYX outputs on the IDT71321 are open drain, not push-
pull outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
61.452


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Functional Description
The IDT71321/IDT71421 provides two ports with separate control,
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT71321/IDT71421 has an automatic
power down feature controlled by CE. The CE controls on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CER = R/WR = VIL,per Truth Table
II. The left port clears the interrupt by accessing address location 7FE when
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag (INTR) is asserted when the left port writes to memory location 7FF
(HEX) and to clear the interrupt flag (INTR), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,
sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a busy indication, the write signal is gated internally
to prevent the write from proceeding.
Theuseof BUSYLogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORthe BUSYoutputstogether
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. In slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT71321 (Master) are open drain type
outputs and require open drain resistors to operate. If these SRAMs are
being expanded in depth, then the BUSY indication for the resulting array
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
WhenexpandinganSRAMarrayinwidthwhileusingBUSY logic,one
master part is used to decide which side of the SRAM array will receive
a BUSY indication, and to output that indication. Any number of slaves to
be addressed in the same address range as the master, use the BUSY
signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs
the BUSY pin is an output if the part is Master (IDT71321), and theBUSY
pin is an input if the part is a Slave (IDT71421) as shown in Figure 3.
5V
270Ω
MASTER
Dual Port
SRAM
BUSYL
CE
BUSYR
SLAVE
Dual Port
SRAM
BUSYL
CE
BUSYR
5V
270Ω
BUSYL
MASTER
Dual Port
SRAM
BUSYL
CE
BUSYR
SLAVE
Dual Port
SRAM
BUSYL
CE
BUSYR
BUSYR
2691 drw 16
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
arrayandanothermasterindicatingBUSY ononeothersideofthearray.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
61.462


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Ordering Information
XXXX
A 999
A
A
Device Type Power Speed Package
A
Process/
Temperature
Range
A
Industrial and Commercial Temperature Ranges
Blank Tube or Tray
8 Tape and Reel
Blank Commercial (0°C to +70°C)
I(1) Industrial (-40°C to +85°C)
G Green
J 52-pin PLCC (PLG52)
PF 64-pin TQFP (PNG64)
PP 52-pin STQFP (PPG52)
TF 64-pin STQFP (PPG64)
20 Commercial Only
25 Industrial Only
35 Commercial Only
Speed in nanoseconds
55 Commercial & Industrial
LA Low Power
SA Standard Power
71321 16K (2K x 8-Bit) MASTER Dual-Port SRAM w/ Interrupt
71421 16K (2K x 8-Bit) SLAVE Dual-Port SRAM w/ Interrupt
NOTES:
1. Contact your sales office for industrial temperature range availability in other speeds, packages and powers.
LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02
Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience.
2691 drw 18
Orderable Part Information
Speed
(ns)
Orderable Part ID
Pkg.
Code
Pkg.
Type
20 71321LA20JG
PLG52
PLCC
71321LA20JG8
PLG52
PLCC
71321LA20PFG
PNG64
TQFP
71321LA20PFG8
PNG64
TQFP
71321LA20TFG
PPG64
TQFP
71321LA20TFG8
PPG64
TQFP
25 71321LA25JGI
PLG52
PLCC
71321LA25JGI8
PLG52
PLCC
71321LA25PFGI
PNG64
TQFP
71321LA25PFGI8
PNG64
TQFP
71321LA25TFGI
PPG64
TQFP
71321LA25TFGI8
PPG64
TQFP
55 71321LA55PPGI
PPG52
TQFP
71321LA55PPGI8
PPG52
TQFP
71321LA55TFG
PPG64
TQFP
71321LA55TFG8
PPG64
TQFP
Temp.
Grade
C
C
C
C
C
C
I
I
I
I
I
I
I
I
C
C
Speed
(ns)
Orderable Part ID
35 71321SA35TFG
71321SA35TFG8
55 71321SA55JG
71321SA55JG8
Speed
(ns)
Orderable Part ID
20 71421LA20JG
71421LA20JG8
71421LA20PFG
71421LA20PFG8
25 71421LA25PFGI
71421LA25PFGI8
Pkg.
Code
PPG64
PPG64
PLG52
PLG52
Pkg.
Type
TQFP
TQFP
PLCC
PLCC
Temp.
Grade
C
C
C
C
Pkg.
Code
PLG52
PLG52
PNG64
PNG64
PNG64
PNG64
Pkg.
Type
PLCC
PLCC
TQFP
TQFP
TQFP
TQFP
Temp.
Grade
C
C
C
C
I
I
61.472


71421LA (IDT)
HIGH SPEED 2K x 8 DUAL-PORT STATIC RAM

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71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Datasheet Document History
03/24/99:
06/07/99:
11/10/99:
08/23/01:
Pages 2 & 3
Page 3
Page 4
Page 16
Page 4
01/17/06:
08/25/06:
10/29/08:
09/10/12:
06/10/16:
Page 7 & 9
Page 17
Page 1
Page 17
Page 1 & 17
Page 14
Page 17
Page 1 & 2
Page 3
Page 9
Page 17
Page 2
Page 3
Pages 2 & 17
02/20/18:
09/24/19:
Pages 1 & 17
Pages 2 & 3
Page 3
Page 5
Page 17
Initiated datasheet document history
Converted to new format
Cosmetic typographical corrections
Added additional notes to pin configurations
Changed drawing format
Replaced IDT logo
Increased storage temperature parameters
Clarified TA parameter
DC Electrical parameters–changed wording from "open" to "disabled"
Fixed part numbers in "Width Expansion" paragraph
Changed ±500mV to 0mV in notes
Industrial temperature range offering added to DC Electrical Characteristics for 25ns and removed
for 35ns
Industrial temperature range added to AC Electrical Characteristics for 25ns
Industrial offering removed for 35ns ordering information
Added green availability to features
Added green indicator to ordering information
Replaced old IDTTM with new IDTTM logo
Changed INT"A" to INT"B" in the CLEAR INT drawing in the Timing Waveform of Interrupt Mode
Removed "IDT" from orderable part number
52-pin STQFP added to the features and description
PP52-1 pin configuration added
Typo corrected
Added T&R indicator and PP52-1 package information to the ordering information
Changed diagram for the J52 pin configuration by rotating package pin labels and pin
numbers 90 degrees clockwise to reflect pin1 orientation and added pin 1 dot at pin 1
Removed J52 chamfers and aligned the top and bottom pin labels in the standard direction
Changed diagram for the PN64/PP64 pin configuration by rotating package pin labels and pin
numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1
PP52 pin configuration. Added the IDT logo, changed the text to be in alignment with new diagram
marking specs
Removed footnote 5 and its references
In pin configuration footnotes and in the Ordering Information: The package codes J52-1, PN64-1,
PP64-1 and PP52-1 changed to J52, PN64, PP64 & PP52 respectively to match standard package codes
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Deleted obsolete Commercial 25ns speed grade
Updated package codes
Rotated PPG52 STQFP pin configuration to accurately reflect pin 1 orientation
Typo corrected in the Data Retention Characteristics table 06
Added Orderable Part Information
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
61.482
for Tech Support:
408-284-2794
DualPortHelp@idt.com




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