MSP430FR5968 (etcTI)
Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
MSP430FR596x, MSP430FR594x Mixed-Signal Microcontrollers
1 Device Overview
1.1 Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16MHz Clock
– Wide Supply Voltage Range From 3.6 V Down
to 1.8 V (Minimum Supply Voltage is Restricted
by SVS Levels, See the SVS Specifications)
• Optimized Ultra-Low-Power Modes
– Active Mode: Approximately 100 µA/MHz
– Standby (LPM3 With VLO): 0.4 µA (Typical)
– Real-Time Clock (LPM3.5): 0.25 µA (Typical) (1)
– Shutdown (LPM4.5): 0.02 µA (Typical)
• Ultra-Low-Power Ferroelectric RAM (FRAM)
– Up to 64KB of Nonvolatile Memory
– Ultra-Low-Power Writes
– Fast Write at 125 ns Per Word (64KB in 4 ms)
– Unified Memory = Program + Data + Storage in
One Single Space
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– 32-Bit Hardware Multiplier (MPY)
– 3-Channel Internal DMA
– Real-Time Clock (RTC) With Calendar and
Alarm Functions
– Five 16-Bit Timers With up to Seven
Capture/Compare Registers Each
– 16-Bit Cyclic Redundancy Checker (CRC)
• High-Performance Analog
– 16-Channel Analog Comparator
– 12-Bit Analog-to-Digital Converter (ADC)
With Internal Reference and Sample-and-Hold
and up to 16 External Input Channels
• Multifunction Input/Output Ports
– All Pins Support Capacitive Touch Capability
With No Need for External Components
(1) RTC is clocked by a 3.7-pF crystal.
– Accessible Bit-, Byte-, and Word-Wise (in Pairs)
– Edge-Selectable Wake From LPM on All Ports
– Programmable Pullup and Pulldown on All Ports
• Code Security and Encryption
– 128-Bit or 256-Bit AES Security Encryption and
Decryption Coprocessor
– Random Number Seed for Random Number
Generation Algorithms
• Enhanced Serial Communication
– eUSCI_A0 and eUSCI_A1 Support
– UART With Automatic Baud-Rate Detection
– IrDA Encode and Decode
– SPI
– eUSCI_B0 Supports
– I2C With Multiple Slave Addressing
– SPI
– Hardware UART and I2C Bootloader (BSL)
• Flexible Clock System
– Fixed-Frequency DCO With 10 Selectable
Factory-Trimmed Frequencies
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– 32-kHz Crystals (LFXT)
– High-Frequency Crystals (HFXT)
• Development Tools and Software
– Free Professional Development Environments
With EnergyTrace++™ Technology
– Development Kit (MSP-TS430RGZ48C)
• Family Members
Device Comparison Summarizes the Available
Device Variants and Package Types
• For Complete Module Descriptions, See the
MSP430FR58xx, MSP430FR59xx, and
MSP430FR6xx Family User's Guide
1.2 Applications
• Metering
• Energy Harvested Sensor Nodes
• Wearable Electronics
• Sensor Management
• Data Logging
1.3 Description
The MSP430™ ultra-low-power (ULP) FRAM platform combines uniquely embedded FRAM and a holistic
ultra-low-power system architecture, allowing innovators to increase performance at lowered energy
budgets. FRAM technology combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash at much lower power.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


MSP430FR5968 (etcTI)
Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
www.ti.com
The MSP430 ULP FRAM portfolio consists of a diverse set of devices featuring FRAM, the ULP 16-bit
MSP430 CPU, and intelligent peripherals targeted for various applications. The ULP architecture
showcases seven low-power modes, optimized to achieve extended battery life in energy-challenged
applications.
PART NUMBER
MSP430FR5969IRGZ
MSP430FR5959IRHA
MSP430FR5959IDA
Device Information(1)
PACKAGE
VQFN (48)
VQFN (40)
TSSOP (38)
BODY SIZE(2)
7 mm × 7 mm
6 mm × 6 mm
12.5 mm × 6.2 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the devices.
DMA
Controller
3 Channel
CPUXV2
incl. 16
Registers
EEM
(S: 3 + 1)
EnergyTrace++
JTAG
Interface
LFXIN, LFXOUT,
HFXIN HFXOUT
MCLK
Clock
System
ACLK
SMCLK
Comp_E
(up to 16
inputs)
ADC12_B
(up to 16
standard
inputs,
up to 8
differential
inputs)
Bus
Control
Logic
MAB
MDB
P1.x, P2.x P3.x, P4.x
2x8 2x8
PJ.x
1x8
REF_A
Voltage
Reference
Capacitive Touch I/O 0,
Capacitive Touch I/O 1
I/O Ports
P1, P2
2x8 I/Os
PA
1x16 I/Os
I/O Ports
P3, P4
2x8 I/Os
PB
1x16 I/Os
I/O Port
PJ
1x8 I/Os
MPU
IP Encap
FRAM
64KB
48KB
32KB
MDB
MAB
RAM
2KB
1KB
Power
Mgmt
LDO
SVS
Brownout
CRC16
MPY32
AES256
Security
Encryption,
Decryption
(128, 256)
Watchdog
TA2
TA3
Timer_A
2 CC
Registers
(int. only)
Spy-Bi-Wire
TB0 TA0 TA1
Timer_B
7 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
eUSCI_A0
eUSCI_A1
(UART,
IrDA,
SPI)
eUSCI_B0
(I2C,
SPI)
RTC_B
LPM3.5 Domain
A. The low-frequency (LF) crystal oscillator and the corresponding LFXIN and LFXOUT pins are available in the
MSP430FR5x6x and MSP430FR5x4x devices only.
RTC_B is available only in conjunction with the LF crystal oscillator in MSP430FR5x6x and MSP430FR5x4x devices.
B. The high-frequency (HF) crystal oscillator and the corresponding HFXIN and HFXOUT pins are available in the
MSP430FR5x6x and MSP430FR5x5x devices only.
MSP430FR5x5x devices with the HF crystal oscillator only do not include the RTC_B module.
Figure 1-1. Functional Block Diagram
2 Device Overview
Copyright © 2012–2018, Texas Instruments Incorporated
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MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471


MSP430FR5968 (etcTI)
Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Table of Contents
1 Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 1
1.3 Description............................................ 1
1.4 Functional Block Diagram ............................ 2
2 Revision History ......................................... 4
3 Device Comparison ..................................... 5
3.1 Related Products ..................................... 6
4 Terminal Configuration and Functions.............. 7
4.1 Pin Diagrams ......................................... 7
4.2 Signal Descriptions.................................. 12
4.3 Pin Multiplexing ..................................... 16
4.4 Connection of Unused Pins ......................... 16
5 Specifications ........................................... 17
5.1 Absolute Maximum Ratings ......................... 17
5.2 ESD Ratings ........................................ 17
5.3 Recommended Operating Conditions............... 17
5.4 Active Mode Supply Current Into VCC Excluding
External Current .................................... 18
5.5 Typical Characteristics – Active Mode Supply
Currents ............................................. 19
5.6 Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................ 19
5.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply
Currents (Into VCC) Excluding External Current .... 20
5.8 Low-Power Mode (LPM3.5, LPM4.5) Supply
Currents (Into VCC) Excluding External Current .... 21
5.9 Typical Characteristics, Low-Power Mode Supply
Currents ............................................. 22
5.10 Typical Characteristics, Current Consumption per
Module .............................................. 23
5.11 Thermal Resistance Characteristics ................ 23
5.12 Timing and Switching Characteristics ............... 24
5.13 Emulation and Debug ............................... 52
6 Detailed Description ................................... 53
6.1 Overview ............................................ 53
6.2 CPU ................................................. 53
6.3 Operating Modes .................................... 54
6.4 Interrupt Vector Table and Signatures .............. 57
6.5 Memory Organization ............................... 60
6.6 Bootloader (BSL).................................... 60
6.7 JTAG Operation ..................................... 61
6.8 FRAM................................................ 62
6.9 Memory Protection Unit Including IP Encapsulation 62
6.10 Peripherals .......................................... 63
6.11 Input/Output Diagrams ............................. 84
6.12 Device Descriptor (TLV) ........................... 112
6.13 Identification........................................ 114
7 Applications, Implementation, and Layout ...... 115
7.1 Device Connection and Layout Fundamentals .... 115
7.2 Peripheral- and Interface-Specific Design
Information ......................................... 119
8 Device and Documentation Support .............. 121
8.1 Getting Started and Next Steps ................... 121
8.2 Device Nomenclature .............................. 121
8.3 Tools and Software ................................ 122
8.4 Documentation Support............................ 124
8.5 Related Links ...................................... 125
8.6 Community Resources............................. 126
8.7 Trademarks ........................................ 126
8.8 Electrostatic Discharge Caution ................... 126
8.9 Export Control Notice .............................. 126
8.10 Glossary............................................ 126
9 Mechanical, Packaging, and Orderable
Information ............................................. 127
Copyright © 2012–2018, Texas Instruments Incorporated
Table of Contents
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
3


MSP430FR5968 (etcTI)
Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from March 10, 2017 to August 29, 2018
Page
• Updated Section 3.1, Related Products ........................................................................................... 6
• Added note (1) to Table 5-2, SVS................................................................................................. 25
• Changed capacitor value from 4.7 µF to 470 nF in Figure 7-5, ADC12_B Grounding and Noise Considerations ... 119
• Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 7.2.1.2, Design Requirements ... 120
• Updated text and figure in Section 8.2, Device Nomenclature .............................................................. 121
4 Revision History
Copyright © 2012–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471


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Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison(1)(2)
DEVICE
MSP430FR5969
MSP430FR59691
MSP430FR5968
MSP430FR5967
FRAM
(KB)
64
64
48
32
SRAM
(KB)
2
2
2
1
CLOCK
SYSTEM
DCO
HFXT
LFXT
DCO
HFXT
LFXT
DCO
HFXT
LFXT
DCO
HFXT
LFXT
ADC12_B
16 ext, 2 int
ch.
16 ext, 2 int
ch.
16 ext, 2 int
ch.
16 ext, 2 int
ch.
Comp_E Timer_A(3) Timer_B(4)
16 ch.
16 ch.
16 ch.
16 ch.
3, 3(7)
2, 2(8)
3, 3(7)
2, 2(8)
3, 3(7)
2, 2(8)
3, 3(7)
2, 2(8)
7
7
7
7
eUSCI
A (5)
B (6)
21
21
21
21
AES
yes
yes
yes
yes
BSL
UART
I2C
UART
UART
I/O PACKAGE
40 48 RGZ
40 48 RGZ
40 48 RGZ
40 48 RGZ
MSP430FR5949
14 ext, 2 int
64
2
DCO
LFXT
ch.
12 ext,
16 ch.
3, 3(7)
2, 2(8)
7
2 int ch.
33 40 RHA
2 1 yes UART
31 38 DA
MSP430FR5948
14 ext,
48
2
DCO
LFXT
2 int ch.
12 ext,
16 ch.
3, 3(7)
2, 2(8)
7
2 int ch.
33 40 RHA
2 1 yes UART
31 38 DA
MSP430FR5947
14 ext,
32
1
DCO
LFXT
2 int ch.
12 ext,
16 ch.
3, 3(7)
2, 2(8)
7
2 int ch.
33 40 RHA
2 1 yes UART
31 38 DA
MSP430FR59471
32
1
DCO
LFXT
14 ext,
2 int ch.
16 ch.
3, 3(7)
2, 2(8)
7
2 1 yes I2C
33 40 RHA
MSP430FR5959
MSP430FR5958
MSP430FR5957
14 ext,
64
2
DCO
HFXT
2 int ch.
12 ext,
16 ch.
3, 3(7)
2, 2(8)
7
2 int ch.
14 ext,
48
2
DCO
HFXT
2 int ch.
12 ext,
16 ch.
3, 3(7)
2, 2(8)
7
2 int ch.
14 ext,
32
1
DCO
HFXT
2 int ch.
12 ext,
16 ch.
3, 3(7)
2, 2(8)
7
2 int ch.
33 40 RHA
2 1 yes UART
31 38 DA
33 40 RHA
2 1 yes UART
31 38 DA
33 40 RHA
2 1 yes UART
31 38 DA
(1) For the most current device, package, and ordering information for all available devices, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
(5) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(6) eUSCI_B supports I2C with multiple slave addresses, and SPI.
(7) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(8) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).
Copyright © 2012–2018, Texas Instruments Incorporated
Device Comparison
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MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
5


MSP430FR5968 (etcTI)
Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
www.ti.com
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous
future
Products for MSP430 ultra-low-power sensing and measurement microcontrollers One platform.
One ecosystem. Endless possibilities.
Products for MSP430 ultrasonic and performance sensing microcontrollers Ultra-low-power single-
chip MCUs with integrated sensing peripherals
Companion Products for MSP430FR5969 Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430FR5969 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
6 Device Comparison
Copyright © 2012–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471


MSP430FR5968 (etcTI)
Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the 48-pin RGZ package for the MSP430FR596x and MSP430FR596x1 MCUs.
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
P3.3/A15/C15
P4.7
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
DVSS
P4.6
P4.5
P4.4/TB0.5
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB0.6
P3.6/TB0.5
P3.5/TB0.4/COUT
P3.4/TB0.3/SMCLK
P2.2/TB0.2/UCB0CLK
P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
NOTE: TI recommends connecting the QFN package pad to VSS.
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
NOTE: On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-1. 48-Pin RGZ Package (Top View) – MSP430FR596x and MSP430FR596x1
Copyright © 2012–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
Submit Documentation Feedback
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MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
www.ti.com
Figure 4-2 shows the 40-pin RHA package for the MSP430FR594x and MSP430FR594x1 MCUs (LFXT
only).
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
P3.3/A15/C15
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
40 39 38 37 36 35 34 33 32 31
1 30
2 29
3 28
4 27
5 26
6 25
7 24
8 23
9 22
10 21
11 12 13 14 15 16 17 18 19 20
P4.4/TB0.5
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB0.6
P3.6/TB0.5
P3.5/TB0.4/COUT
P3.4/TB0.3/SMCLK
P2.2/TB0.2/UCB0CLK
P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
NOTE: TI recommends connecting the QFN package pad to VSS.
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
NOTE: On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-2. 40-Pin RHA Package (Top View) – MSP430FR594x and MSP430FR594x1
8 Terminal Configuration and Functions
Copyright © 2012–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
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Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Figure 4-3 shows the 38-pin DA package for the MSP430FR594x MCUs (LFXT only).
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS
AVCC
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
P3.3/A15/C15
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
PJ.2/TMS/ACLK/SROSCOFF/C8
PJ.3/TCK/SRCPUOFF/C9
P2.5/TB0.0/UCA1TXD/UCA1SIMO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38 AVSS
37 P2.4/TA1.0/UCA1CLK/A7/C11
36 P2.3/TA0.0/UCA1STE/A6/C10
35 P2.7
34 DVCC
33 DVSS
32 P4.4/TB0.5
31 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
30 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
29 P3.7/TB0.6
28 P3.6/TB0.5
27 P3.5/TB0.4/COUT
26 P3.4/TB0.3/SMCLK
25 P2.2/TB0.2/UCB0CLK
24 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
23 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
22 RST/NMI/SBWTDIO
21 TEST/SBWTCK
20 P2.6/TB0.1/UCA1RXD/UCA1SOMI
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
Figure 4-3. 38-Pin DA Package (Top View) – MSP430FR594x
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MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Figure 4-4 shows the 40-pin RHA package for the MSP430FR595x MCUs (HFXT only).
www.ti.com
P1.0/TA0.1/DMAE0/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
P3.3/A15/C15
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
40 39 38 37 36 35 34 33 32 31
1 30
2 29
3 28
4 27
5 26
6 25
7 24
8 23
9 22
10 21
11 12 13 14 15 16 17 18 19 20
P4.4/TB0.5
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB0.6
P3.6/TB0.5
P3.5/TB0.4/COUT
P3.4/TB0.3/SMCLK
P2.2/TB0.2/UCB0CLK
P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
NOTE: TI recommends connecting the QFN package pad to VSS.
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
Figure 4-4. 40-Pin RHA Package (Top View) – MSP430FR595x
10 Terminal Configuration and Functions
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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Figure 4-5 shows the 38-pin DA package for the MSP430FR595x MCUs (HFXT only).
PJ.6/HFXIN
PJ.7/HFXOUT
AVSS
AVCC
P1.0/TA0.1/DMAE0/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
P3.3/A15/C15
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
PJ.2/TMS/ACLK/SROSCOFF/C8
PJ.3/TCK/SRCPUOFF/C9
P2.5/TB0.0/UCA1TXD/UCA1SIMO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38 AVSS
37 P2.4/TA1.0/UCA1CLK/A7/C11
36 P2.3/TA0.0/UCA1STE/A6/C10
35 P2.7
34 DVCC
33 DVSS
32 P4.4/TB0.5
31 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
30 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
29 P3.7/TB0.6
28 P3.6/TB0.5
27 P3.5/TB0.4/COUT
26 P3.4/TB0.3/SMCLK
25 P2.2/TB0.2/UCB0CLK
24 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
23 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
22 RST/NMI/SBWTDIO
21 TEST/SBWTCK
20 P2.6/TB0.1/UCA1RXD/UCA1SOMI
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
Figure 4-5. 38-Pin DA Package (Top View) – MSP430FR595x
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MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
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4.2 Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
TERMINAL
NAME
NO. (2)
I/O (1)
RGZ RHA DA
DESCRIPTION
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR1 capture: CCI1A input, compare: Out1
P1.0/TA0.1/DMAE0/
RTCCLK/A0/C0/VREF-/
VeREF-
External DMA trigger
RTC clock calibration output (not available on MSP430FR5x5x devices)
1 1 5 I/O
Analog input A0 for ADC
Comparator input C0
Output of negative reference voltage
Input for an external negative reference voltage to the ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR2 capture: CCI2A input, compare: Out2
P1.1/TA0.2/TA1CLK/
COUT/A1/C1/VREF+/
VeREF+
TA1 input clock
Comparator output
2 2 6 I/O
Analog input A1 for ADC
Comparator input C1
Output of positive reference voltage
Input for an external positive reference voltage to the ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR1 capture: CCI1A input, compare: Out1
P1.2/TA1.1/TA0CLK/
COUT/A2/C2
TA0 input clock
3 3 7 I/O
Comparator output
Analog input A2 for ADC
Comparator input C2
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.0/A12/C12
4 4 8 I/O Analog input A12 for ADC
Comparator input C12
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.1/A13/C13
5 5 9 I/O Analog input A13 for ADC
Comparator input C13
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.2/A14/C14
6 6 10 I/O Analog input A14 for ADC
Comparator input C14
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.3/A15/C15
7 7 11 I/O Analog input A15 for ADC
Comparator input C15
P4.7
8 N/A N/A I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.3/TA1.2/UCB0STE/
A3/C3
TA1 CCR2 capture: CCI2A input, compare: Out2
9 8 12 I/O Slave transmit enable – eUSCI_B0 SPI mode
Analog input A3 for ADC
Comparator input C3
(1) I = input, O = output
(2) N/A = not available
12 Terminal Configuration and Functions
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MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO. (2)
I/O (1)
RGZ RHA DA
DESCRIPTION
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.4/TB0.1/UCA0STE/
A4/C4
TB0 CCR1 capture: CCI1A input, compare: Out1
10 9 13 I/O Slave transmit enable – eUSCI_A0 SPI mode
Analog input A4 for ADC
Comparator input C4
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
P1.5/TB0.2/UCA0CLK/
A5/C5
11
10
14
I/O
Clock signal input – eUSCI_A0 SPI slave mode,
Clock signal output – eUSCI_A0 SPI master mode
Analog input A5 for ADC
Comparator input C5
General-purpose digital I/O
Test data output port
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1/C6
Switch all PWM outputs high impedance input – TB0
12 11 15 I/O
SMCLK output
Low-Power Debug: CPU Status Register Bit SCG1
Comparator input C6
General-purpose digital I/O
PJ.1/TDI/TCLK/MCLK/
SRSCG0/C7
Test data input or test clock input
13 12 16 I/O MCLK output
Low-Power Debug: CPU Status Register Bit SCG0
Comparator input C7
General-purpose digital I/O
PJ.2/TMS/ACLK/
SROSCOFF/C8
Test mode select
14 13 17 I/O ACLK output
Low-Power Debug: CPU Status Register Bit OSCOFF
Comparator input C8
General-purpose digital I/O
PJ.3/TCK/
SRCPUOFF/C9
Test clock
15 14 18 I/O
Low-Power Debug: CPU Status Register Bit CPUOFF
Comparator input C9
P4.0/A8
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
16 15 N/A I/O
Analog input A8 for ADC
P4.1/A9
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
17 16 N/A I/O
Analog input A9 for ADC
P4.2/A10
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
18 N/A N/A I/O
Analog input A10 for ADC
P4.3/A11
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
19 N/A N/A I/O
Analog input A11 for ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.5/TB0.0/UCA1TXD/
UCA1SIMO
TB0 CCR0 capture: CCI0B input, compare: Out0
20 17 19 I/O
Transmit data – eUSCI_A1 UART mode
Slave in, master out – eUSCI_A1 SPI mode
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MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO. (2)
I/O (1)
RGZ RHA DA
DESCRIPTION
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.6/TB0.1/UCA1RXD/
UCA1SOMI
TB0 CCR1 compare: Out1
21 18 20 I/O
Receive data – eUSCI_A1 UART mode
Slave out, master in – eUSCI_A1 SPI mode
TEST/SBWTCK
22 19 21
Test mode pin – select digital I/O on JTAG pins
I
Spy-Bi-Wire input clock
Reset input active low
RST/NMI/SBWTDIO
23 20 22 I/O Nonmaskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR6 capture: CCI6B input, compare: Out6
P2.0/TB0.6/UCA0TXD/
UCA0SIMO/TB0CLK/
ACLK
Transmit data – eUSCI_A0 UART mode
24 21 23 I/O BSL Transmit (UART BSL)
Slave in, master out – eUSCI_A0 SPI mode
TB0 clock input
ACLK output
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR0 capture: CCI0A input, compare: Out0
P2.1/TB0.0/UCA0RXD/
UCA0SOMI/TB0.0
Receive data – eUSCI_A0 UART mode
25 22 24 I/O
BSL receive (UART BSL)
Slave out, master in – eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.2/TB0.2/UCB0CLK
26 23 25 I/O TB0 CCR2 compare: Out2
Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.4/TB0.3/SMCLK
27 24 26 I/O TB0 CCR3 capture: CCI3A input, compare: Out3
SMCLK output
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.5/TB0.4/COUT
28 25 27 I/O TB0 CCR4 capture: CCI4A input, compare: Out4
Comparator output
P3.6/TB0.5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
29 26 28 I/O
TB0 CCR5 capture: CCI5A input, compare: Out5
P3.7/TB0.6
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
30 27 29 I/O
TB0 CCR6 capture: CCI6A input, compare: Out6
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR3 capture: CCI3B input, compare: Out3
P1.6/TB0.3/UCB0SIMO/
UCB0SDA/TA0.0
Slave in, master out – eUSCI_B0 SPI mode
31 28 30 I/O I2C data – eUSCI_B0 I2C mode
BSL Data (I2C BSL)
TA0 CCR0 capture: CCI0A input, compare: Out0
14 Terminal Configuration and Functions
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MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO. (2)
I/O (1)
RGZ RHA DA
DESCRIPTION
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR4 capture: CCI4B input, compare: Out4
P1.7/TB0.4/UCB0SOMI/
UCB0SCL/TA1.0
Slave out, master in – eUSCI_B0 SPI mode
32 29 31 I/O I2C clock – eUSCI_B0 I2C mode
BSL clock (I2C BSL)
TA1 CCR0 capture: CCI0A input, compare: Out0
P4.4/TB0.5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
33 30 32 I/O
TB0CCR5 capture: CCI5B input, compare: Out5
P4.5
34 N/A N/A I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.6
35 N/A N/A I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
DVSS
36 31 33
Digital ground supply
DVCC
37 32 34
Digital power supply
P2.7
38 33 35 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.3/TA0.0/UCA1STE/
A6/C10
TA0 CCR0 capture: CCI0B input, compare: Out0
39 34 36 I/O Slave transmit enable – eUSCI_A1 SPI mode
Analog input A6 for ADC
Comparator input C10
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR0 capture: CCI0B input, compare: Out0
P2.4/TA1.0/UCA1CLK/
A7/C11
Clock signal input – eUSCI_A1 SPI slave mode
40 35 37 I/O
Clock signal output – eUSCI_A1 SPI master mode
Analog input A7 for ADC
Comparator input C11
AVSS
41 36 38
Analog ground supply
PJ.6/HFXIN
General-purpose digital I/O
42 37 1 I/O Input for high-frequency crystal oscillator HFXT (in RHA and DA packages:
MSP430FR595x devices only)
PJ.7/HFXOUT
General-purpose digital I/O
43 38 2 I/O Output for high-frequency crystal oscillator HFXT (in RHA and DA packages:
MSP430FR595x devices only)
AVSS
44 N/A N/A
Analog ground supply
PJ.4/LFXIN
General-purpose digital I/O
45 37 1 I/O Input for low-frequency crystal oscillator LFXT (in RHA and DA packages:
MSP430FR594x devices only)
PJ.5/LFXOUT
General-purpose digital I/O
46 38 2 I/O Output of low-frequency crystal oscillator LFXT (in RHA and DA packages:
MSP430FR594x devices only)
AVSS
47 39 3
Analog ground supply
AVCC
48 40 4
Analog power supply
QFN Pad
Pad Pad N/A
QFN package exposed thermal pad. TI recommends connection to VSS.
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MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
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4.3 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and diagrams of the
multiplexed ports, see Section 6.11.
4.4 Connection of Unused Pins
Table 4-2 lists the correct termination of all unused pins.
Table 4-2. Connection of Unused Pins(1)
PIN
AVCC
AVSS
Px.0 to Px.7
RST/NMI
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
TEST
POTENTIAL
COMMENT
DVCC
DVSS
Open
DVCC or VCC
Set to port function, output direction (PxDIR.n = 1)
47-kpullup or internal pullup selected with 2.2-nF (10-nF(2)) pulldown
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not
used as JTAG pins, these pins should be switched to port function, output
direction. When used as JTAG pins, these pins should remain open.
Open
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the
Px.0 to Px.7 unused pin connection guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices in Spy-Bi-Wire mode or in 4-
wire JTAG mode with TI tools like FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire
access is not needed, up to a 10-nF pulldown capacitor may be used.
16 Terminal Configuration and Functions
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MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
5 Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins(2)
–0.3 4.1 V
±0.3 V
Voltage applied to any pin (3)
–0.3
VCC + 0.3 V
(4.1 Max)
V
Diode current at any device pin
Storage temperature, Tstg(4)
±2 mA
–40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
(3) All voltages referenced to VSS.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
VALUE
±1000
±250
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
Typical data are based on VCC = 3.0 V, TA = 25°C (unless otherwise noted)
MIN NOM MAX UNIT
VCC
Supply voltage range applied at all DVCC and AVCC
pins (1) (2) (3)
1.8 (4)
3.6 V
VSS
TA
TJ
CDVCC
fSYSTEM
Supply voltage applied at all DVSS and AVSS pins
Operating free-air temperature
Operating junction temperature
Capacitor value at DVCC(5)
Processor frequency (maximum MCLK frequency)(6)
No FRAM wait states
(NWAITSx = 0)
With FRAM wait states
(NWAITSx = 1)(8)
–40
–40
1–20%
0
0
0V
85 °C
85 °C
µF
8 (7)
16 (9)
MHz
fACLK
fSMCLK
Maximum ACLK frequency
Maximum SMCLK frequency
50 kHz
16(9) MHz
(1) TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device
operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) See Table 5-1 for additional important information.
(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(4) The minimum supply voltage is defined by the supervisor SVS levels. See Table 5-2 for the values.
(5) Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC pin.
(6) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(7) DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted.
(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed
without wait states.
(9) DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted. If a clock sources with a larger
typical value is used, the clock must be divided in the clock system.
Copyright © 2012–2018, Texas Instruments Incorporated
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MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
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5.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
EXECUTION
MEMORY
FREQUENCY (fMCLK = fSMCLK)
1 MHz
4 MHz
8 MHz
12 MHz
16 MHz
VCC 0 wait states 0 wait states 0 wait states 1 wait states 1 wait states UNIT
(NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 1) (NWAITSx = 1)
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
IAM, FRAM_UNI
(Unified memory)(3)
FRAM
3.0 V
210
640 1220 1475 1845 µA
IAM,
FRAM
(4)
(0%)
(5)
FRAM
0% cache hit
ratio
3.0 V
370
1280
2510
2080
2650
µA
IAM,
FRAM
(4)
(50%)
(5)
FRAM
50% cache hit
ratio
3.0 V
240
745 1440 1575 1990 µA
IAM,
FRAM
(4)
(66%)
(5)
FRAM
66% cache hit
ratio
3.0 V
200
560 1070 1300 1620 µA
IAM,
FRAM
(4)
(75%)
(5)
FRAM
75% cache hit
ratio
3.0 V
170 255 480
890 1085 1155 1310 1420 1620 µA
FRAM
IAM,
FRAM
(4)
(100%)
(5)
100% cache hit 3.0 V
110
235
420
640
730 µA
ratio
IAM, RAM (6)
IAM, RAM only (7) (5)
RAM
3.0 V
130
320
585
890 1070 µA
RAM
3.0 V
100 180 290
555
860 1040 1300 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and
fMCLK = fSMCLK = fDCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio, fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
(5) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data from Section 5.4.
(6) Program and data reside entirely in RAM. All execution is from RAM.
(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
18 Specifications
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MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
5.5 Typical Characteristics – Active Mode Supply Currents
3000
2500
2000
1500
I(AM,0%)
I(AM,50%)
I(AM,66%)
I(AM,75%)
I(AM,100%)
I(AM,RAMonly)
I(AM,75%) [µA] = 103 × f [MHz] + 68
1000
500
0
012345678
MCLK Frequency (MHz)
NOTE: I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with
cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are
FRAM accesses.
NOTE: I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 5-1. Typical Active Mode Supply Currents vs MCLK frequency, No Wait States
9
C001
5.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
VCC
1 MHz
TYP MAX
4 MHz
FREQUENCY (fSMCLK)
8 MHz
TYP MAX TYP MAX
12 MHz
TYP MAX
16 MHz
UNIT
TYP MAX
ILPM0
2.2 V
70
95 150 250 215
µA
3.0 V
80 115 105
160
260
225 260
ILPM1
2.2 V
35
60 115 215 180
µA
3.0 V
35 60 60
115
215
180 205
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and fSMCLK =
fDCO / 2.
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MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
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5.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
–40°C
25°C
60°C
85°C
VCC
UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
ILPM2,XT12
Low-power mode 2, 12-pF
crystal (2) (3) (4)
2.2 V
3.0 V
0.5
0.5
0.9 2.2
0.9 1.8 2.2
6.1
μA
6.1 17
ILPM2,XT3.7
Low-power mode 2, 3.7-pF
cyrstal (2) (5) (4)
2.2 V
3.0 V
0.5
0.5
0.9
0.9
2.2
2.2
6.0
μA
6.0
ILPM2,VLO
Low-power mode 2, VLO,
includes SVS(6)
2.2 V
3.0 V
0.3
0.3
0.7 1.9
0.7 1.6 1.9
5.8
μA
5.8 16.7
ILPM3,XT12
Low-power mode 3, 12-pF
crystal, excludes SVS(2) (3)
(7)
2.2 V
3.0 V
0.5
0.5
0.6 0.9
0.6 0.9 0.9
1.85
μA
1.85 4.9
ILPM3,XT3.7
ILPM3,VLO
ILPM4,SVS
ILPM4
Low-power mode 3, 3.7-pF
cyrstal, excludes SVS(2) (5)
(8)
(also see Figure 5-2)
Low-power mode 3,
VLO, excludes SVS(9)
Low-power mode 4, includes
SVS (10)
(also see Figure 5-3)
Low-power mode 4,
excludes SVS(11)
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
2.2 V
3.0 V
0.4
0.4
0.3
0.3
0.4
0.4
0.2
0.2
0.5 0.8
0.5 0.8
0.4 0.7
0.4 0.7 0.7
0.5 0.8
0.5 0.8 0.8
0.3 0.6
0.3 0.6 0.6
1.7
μA
1.7
1.6
μA
1.6 4.7
1.7
μA
1.7 4.8
1.5
μA
1.5 4.6
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout and SVS are included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen
to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS are included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(9) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout is included. SVS is
disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(10) Low-power mode 4, includes SVS test conditions:
Current for brownout and SVS are included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
(11) Low-power mode 4, excludes SVS test conditions:
Current for brownout is included. SVS is disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
20 Specifications
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MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
–40°C
25°C
60°C
85°C
VCC TYP MAX TYP MAX TYP MAX TYP MAX
IIDLE,GroupA
Additional idle current if one
or more modules from Group
A (see Table 6-3) are
activated in LPM3 or LPM4.
3.0V
0.02
0.33 1.3
IIDLE,GroupB
Additional idle current if one
or more modules from Group
B (see Table 6-3) are
activated in LPM3 or LPM4
3.0V
0.015
0.25 1.0
UNIT
μA
μA
5.8 Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
–40°C
25°C
60°C
85°C
VCC
TYP MAX
TYP MAX
TYP MAX
UNIT
TYP MAX
ILPM3.5,XT12
Low-power mode 3.5, 12-pF
crystal, includes SVS(2)(3)(4)
2.2 V
3.0 V
0.4
0.4
0.45 0.5
0.45 0.7 0.5
0.7
μA
0.7 1.2
ILPM3.5,XT3.7
Low-power mode 3.5, 3.7-pF
cyrstal, excludes SVS(2)(5)(6)
(also see Figure 5-4)
2.2 V
3.0 V
0.2
0.2
0.25
0.25
0.3 0.45
μA
0.3 0.5
ILPM4.5,SVS
Low-power mode 4.5,
includes SVS(7)
(also see Figure 5-5)
2.2 V
3.0 V
0.2
0.2
0.2 0.2
0.2 0.4 0.2
0.3
μA
0.3 0.55
ILPM4.5
Low-power mode 4.5,
excludes SVS(8)
(also see Figure 5-5)
2.2 V
3.0 V
0.02
0.02
0.02
0.02
0.02
0.02
0.08
μA
0.08 0.35
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(4) Low-power mode 3.5, 12-pF crystal, includes SVS test conditions:
Current for RTC clocked by XT1 is included. Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen
to closely match the required 3.7-pF load.
(6) Low-power mode 3.5, 3.7-pF crystal, excludes SVS test conditions:
Current for RTC clocked by XT1 is included. Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator isdisabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 4.5, excludes SVS test conditions:
Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
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MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
www.ti.com
5.9 Typical Characteristics, Low-Power Mode Supply Currents
2
3.0 V, SVS on
1.8 2.2 V, SVS on
3.0 V, SVS off
1.6 2.2 V, SVS off
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50.00
0.00
50.00
Temperature (°C)
100.00
C003
Figure 5-2. LPM3,XT3.7 Supply Current vs Temperature
0.5
3.0 V, SVS off
2.2 V, SVS off
0.4
2
3.0 V, SVS on
1.8 2.2 V, SVS on
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50.00
0.00 50.00
Temperature (°C)
100.00
C001
Figure 5-3. LPM4,SVS Supply Current vs Temperature
0.5
3.0 V, SVS on
2.2 V, SVS on
3.0 V, SVS off
0.4 2.2 V, SVS off
0.3 0.3
0.2 0.2
0.1 0.1
0
-50.00
0.00
50.00
Temperature (°C)
100.00
C003
Figure 5-4. LPM3.5,XT3.7 Supply Current vs Temperature
0
-50.00
0.00 50.00
Temperature (°C)
100.00
C004
Figure 5-5. LPM4.5 Supply Current vs Temperature
22 Specifications
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MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
5.10 Typical Characteristics, Current Consumption per Module(1)
MODULE
Timer_A
Timer_B
eUSCI_A
eUSCI_A
eUSCI_B
eUSCI_B
RTC_B
MPY
AES
CRC
TEST CONDITIONS
UART mode
SPI mode
SPI mode
I2C mode, 100 kbaud
Only from start to end of operation
Only from start to end of operation
Only from start to end of operation
REFERENCE CLOCK
Module input clock
Module input clock
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
MCLK
MCLK
MCLK
(1) For other module currents not listed here, see the module specific parameter sections.
MIN TYP MAX UNIT
3 μA/MHz
5 μA/MHz
5.5 μA/MHz
3.5 μA/MHz
3.5 μA/MHz
3.5 μA/MHz
100 nA
25 μA/MHz
21 μA/MHz
2.5 μA/MHz
5.11 Thermal Resistance Characteristics
THERMAL METRIC
PACKAGE
VALUE
UNIT
θJA
θJC(TOP)
θJB
ΨJB
Junction-to-ambient thermal resistance, still air(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
Junction-to-board thermal characterization parameter
QFN-48 (RGZ)
30.6 °C/W
17.2 °C/W
7.2 °C/W
7.2 °C/W
ΨJT
θJC(BOTTOM)
θJA
θJC(TOP)
θJB
ΨJB
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance(4)
Junction-to-ambient thermal resistance, still air(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
Junction-to-board thermal characterization parameter
QFN-40 (RHA)
0.2 °C/W
1.2 °C/W
30.1 °C/W
18.7 °C/W
6.4 °C/W
6.3 °C/W
ΨJT
θJC(BOTTOM)
θJA
θJC(TOP)
θJB
ΨJB
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance(4)
Junction-to-ambient thermal resistance, still air(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
Junction-to-board thermal characterization parameter
TSSOP-38 (DA)
0.3 °C/W
1.5 °C/W
65.5 °C/W
12.5 °C/W
32.3 °C/W
31.8 °C/W
ΨJT
θJC(BOTTOM)
Junction-to-top thermal characterization parameter
Junction-to-case (bottom) thermal resistance(4)
0.3 °C/W
N/A °C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and FRAM.
At power up, the device does not start executing code before the supply voltage reaches VSVSH+ if the
supply rises monotonically to this level.
Table 5-1 lists the reset power ramp requirements.
Table 5-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VVCC_BOR–
VVCC_BOR+
PARAMETER
Brownout power-down level(1)(2)
Brownout power-up level(2)
TEST CONDITIONS
| dDVCC/dt | < 3 V/s(3)
| dDVCC/dt | > 300 V/s(3)
| dDVCC/dt | < 3 V/s(4)
MIN TYP MAX UNIT
0.7 1.66 V
0V
0.79 1.68 V
(1) In case of a supply voltage brownout, the device supply voltages need to ramp down to the specified brownout power-down level
VVCC_BOR- before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data sheet
including the correct operation of the on-chip SVS module.
(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
(3) The brownout levels are measured with a slowly changing supply. With faster slopes the MIN level required to reset the device properly
can decrease to 0 V. Use the graph in Figure 5-6 to estimate the VVCC_BOR- level based on the down slope of the supply voltage. After
removing VCC the down slope can be estimated based on the current consumption and the capacitance on DVCC: dV/dt = I/C with
dV/dt: slope, I: current, C: capacitance.
(4) The brownout levels are measured with a slowly changing supply.
2
Process-Temperature Corner Case 1
1.5
Typical
1
Process-Temperature Corner Case 2
MIN Limit
0.5
VVCC_BOR- for reliable
device start-up
0
1
10
100
1000
10000
100000
Supply Voltage Power-Down Slope (V/s)
Figure 5-6. Brownout Power-Down Level vs Supply Voltage Down Slope
24 Specifications
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MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Table 5-2 lists the characteristics of the SVS.
Table 5-2. SVS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
ISVSH,LPM
VSVSH-
VSVSH+
VSVSH_hys
tPD,SVSH, AM
SVSH current consumption, low power modes
SVSH power-down level(1)
SVSH power-up level(1)
SVSH hysteresis
SVSH propagation delay, active mode
dVVcc/dt = –10 mV/µs
170 300 nA
1.75 1.80 1.85 V
1.77 1.88 1.99 V
40 120 mV
10 µs
(1) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
5.12.2 Reset Timing
Table 5-11 lists the required reset input timing.
Table 5-3. Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
t(RST) External reset pulse duration on RST(1)
VCC
2.2 V, 3.0 V
MIN
2
(1) Not applicable if RST/NMI pin configured as NMI.
MAX UNIT
µs
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5.12.3 Clock Specifications
Table 5-4 lists the characteristics of the LFXT.
Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
IVCC.LFXT
fLFXT
DCLFXT
fLFXT,SW
PARAMETER
Current consumption
LFXT oscillator crystal frequency
LFXT oscillator duty cycle
LFXT oscillator logic-level
square-wave input frequency
TEST CONDITIONS
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF, ESR 44 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR 40 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR 40 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR 40 kΩ
LFXTBYPASS = 0
Measured at ACLK,
fLFXT = 32768 Hz
LFXTBYPASS = 1(2) (3)
VCC
3.0 V
MIN TYP
180
185
225
330
32768
30%
10.5 32.768
DCLFXT, SW
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
30%
OALFXT
CLFXIN
Oscillation allowance for
LF crystals(4)
Integrated load capacitance at
LFXIN terminal(5) (6)
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
210
300
2
CLFXOUT
Integrated load capacitance at
LFXOUT terminal(5) (6)
2
MAX UNIT
nA
70%
Hz
50 kHz
70%
k
pF
pF
(1) To improve EMI on the LFXT oscillator, observe the following guidelines.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, CL,eff = 6 pF
• For LFXTDRIVE = {2}, 6 pF CL,eff 9 pF
• For LFXTDRIVE = {3}, 9 pF CL,eff 12.5 pF
(5) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
(6) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
26 Specifications
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MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTART,LFXT Start-up time(7)
fFault,LFXT
Oscillator fault frequency(8) (9)
TEST CONDITIONS
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
VCC
3.0 V
3.0 V
MIN TYP MAX UNIT
800
1000
ms
0 3500 Hz
(7) Includes start-up counter of 1024 clock cycles.
(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition sets the flag.
(9) Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5 lists the characteristics of the HFXT.
Table 5-5. High-Frequency Crystal Oscillator, HFXT(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IDVCC.HFXT
fHFXT
HFXT oscillator
crystal current HF
mode at typical
ESR
HFXT oscillator
crystal frequency,
crystal mode
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1(2)
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
HFXTBYPASS = 0, HFFREQ = 1 (2)(3)
HFXTBYPASS = 0, HFFREQ = 2(3)
HFXTBYPASS = 0, HFFREQ = 3(3)
VCC MIN TYP
75
3.0 V
120
190
250
4
8.01
16.01
DCHFXT
fHFXT,SW
HFXT oscillator
duty cycle
Measured at SMCLK, fHFXT = 16 MHz
HFXT oscillator HFXTBYPASS = 1, HFFREQ = 0(4)(3)
logic-level square- HFXTBYPASS = 1, HFFREQ = 1(4)(3)
wave input
frequency, bypass
HFXTBYPASS = 1, HFFREQ = 2 (4)(3)
mode
HFXTBYPASS = 1, HFFREQ = 3 (4)(3)
40%
0.9
4.01
8.01
16.01
50%
DCHFXT, SW
HFXT oscillator
logic-level square-
wave input duty
HFXTBYPASS = 1
cycle
40%
MAX
8
16
24
60%
4
8
16
24
60%
UNIT
μA
MHz
MHz
(1) To improve EMI on the HFXT oscillator, observe the following guidelines.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) HFFREQ = {0} is not supported for HFXT crystal mode of operation.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
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Table 5-5. High-Frequency Crystal Oscillator, HFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tSTART,HFXT
CHFXIN
Start-up time(5)
Integrated load
capacitance at
HFXIN terminaI(6)
(7)
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1,
TA = 25°C, CL,eff = 16 pF
fOSC = 24 MHz ,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C, CL,eff = 16 pF
VCC
3.0 V
MIN TYP
1.6
3.0 V
0.6
2
MAX
UNIT
ms
pF
CHFXOUT
Integrated load
capacitance at
HFXOUT
terminaI(6) (7)
2 pF
fFault,HFXT
Oscillator fault
frequency(8) (9)
0 800 kHz
(5) Includes start-up counter of 1024 clock cycles.
(6) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition set the flag.
(9) Measured with logic-level input frequency but also applies to operation with crystals.
28 Specifications
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SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
Table 5-6 lists the characteristics of the DCO.
Table 5-6. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
fDCO1
PARAMETER
DCO frequency range
1 MHz, trimmed
TEST CONDITIONS
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0,
DCORSEL = 1, DCOFSEL = 0
VCC MIN TYP MAX UNIT
1 ±3.5% MHz
fDCO2.7
DCO frequency range
2.7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
2.667
±3.5% MHz
fDCO3.5
DCO frequency range
3.5 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
3.5 ±3.5% MHz
fDCO4
DCO frequency range
4 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3
4 ±3.5% MHz
fDCO5.3
DCO frequency range
5.3 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4,
DCORSEL = 1, DCOFSEL = 1
5.333
±3.5% MHz
fDCO7
DCO frequency range
7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5,
DCORSEL = 1, DCOFSEL = 2
7 ±3.5% MHz
fDCO8
DCO frequency range
8 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6,
DCORSEL = 1, DCOFSEL = 3
8 ±3.5% MHz
fDCO16
DCO frequency range
16 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
16 ±3.5%(1) MHz
fDCO21
DCO frequency range
21 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
21 ±3.5%(1) MHz
fDCO24
DCO frequency range
24 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
24 ±3.5%(1) MHz
fDCO,DC
Duty cycle
Measured at SMCLK, divide by 1,
no external divide, all
DCORSEL/DCOFSEL settings except
DCORSEL = 1, DCOFSEL = 5 and
DCORSEL = 1, DCOFSEL = 6
48% 50%
52%
tDCO, JITTER DCO jitter
dfDCO/dT
DCO temperature drift(2)
Based on fsignal = 10 kHz and DCO used
for 12-bit SAR ADC sampling source.
This achieves >74 dB SNR due to jitter
(that is, it is limited by ADC
performance).
3.0 V
2 3 ns
0.01 %/ºC
(1) After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few clock
cycles by up to 5% before settling into the specified steady-state frequency range.
(2) Calculated using the box method: (MAX(–40ºC to 85ºC) – MIN(–40ºC to 85ºC)) / MIN(–40ºC to 85ºC) / (85ºC – (–40ºC))
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SLAS704G – OCTOBER 2012 – REVISED AUGUST 2018
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Table 5-7 lists the characteristics of the VLO.
Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
IVLO
fVLO
dfVLO/dT
dfVLO/dVCC
fVLO,DC
Current consumption
VLO frequency
VLO frequency temperature drift
VLO frequency supply voltage drift
Duty cycle
Measured at ACLK
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
6
40%
100
9.4
0.2
0.7
50%
14
60%
(1) Calculated using the box method: (MAX(–40ºC to 85°C) – MIN(–40ºC to 85°C)) / MIN(–40ºC to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
UNIT
nA
kHz
%/°C
%/V
Table 5-8 lists the characteristics of the MODOSC.
Table 5-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
IMODOSC
fMODOSC
fMODOSC/dT
fMODOSC/dVCC
Current consumption
MODOSC frequency
MODOSC frequency temperature drift(1)
MODOSC frequency supply voltage
drift (2)
Enabled
25
4.0 4.8
0.08
1.4
5.4
DCMODOSC
Duty cycle
Measured at SMCLK, divide by 1
40% 50% 60%
(1) Calculated using the box method: (MAX(–40ºC to 85°C) – MIN(–40ºC to 85°C)) / MIN(–40ºC to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
UNIT
μA
MHz
%/
%/V
30 Specifications
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