S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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S29NS-P MirrorBit® Flash Family
S29NS512P, S29NS256P, S29NS128P
512/256/128 Mb (32/16/8 M x 16 bit), 1.8V Burst Simultaneous
Read/Write, Multiplexed MirrorBit Flash Memory
Data Sheet
S29NS-P MirrorBit® Flash Family Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S29NS-P_00
Revision A Amendment 8
Issue Date September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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S29NS-P MirrorBit® Flash Family
S29NS512P, S29NS256P, S29NS128P
512/256/128 Mb (32/16/8 M x 16 bit), 1.8V Burst Simultaneous
Read/Write, Multiplexed MirrorBit Flash Memory
Data Sheet
Features
Single 1.8V read/program/erase (1.70–1.95V)
90 nm MirrorBit Technology
Multiplexed Data and Address for reduced I/O count
Simultaneous Read/Write operation
Full/Half drive output slew rate control
32-word Write Buffer
Sixteen-bank architecture consisting of
64/32/16 MB for NS512/256/128P, respectively
Four 32 kB sectors at the top of memory array (NS256/128P)
512 128 kB sectors (NS512P), 255/127 128 kB sectors
(NS256/128P)
Programmable linear (8/16/32) with or without wrap around
and continuous burst read modes
Secured Silicon Sector region consisting of 128 words each
for factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector (typical)
RDY output indicates data available to system
Command set compatible with JEDEC (42.4) standard
Hardware (WP#) protection of highest two sectors
Top Boot sector configuration (NS256/128P)
Handshaking by monitoring RDY
Offered Packages
– NS512P: 64-ball FBGA (8 mm x 9.2 mm)
– NS256P/NS128P: 44-ball FBGA (6.2 mm x 7.7 mm)
Low VCC write inhibit
Persistent and Password methods of Advanced Sector
Protection
Write operation status bits indicate program and erase
operation completion
Suspend and Resume commands for Program and Erase
operations
Unlock Bypass program command to reduce programming
time
Synchronous or Asynchronous program operation,
independent of burst control register settings
VPP input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch. Burst Access, ns (tBACC)
Max. Asynch. Access Time, ns (tACC)
Max OE# Access Time, ns (tOE)
83 MHz
9.0 ns
80 ns
7.0 ns
Current Consumption (typical values)
Continuous Burst Read @ 83 MHz
Simultaneous Operation 83 MHz
Program
Standby Mode
42 mA
60 mA
30 mA
20 µA
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (VCC) Per Word
Effective Write Buffer Programming (VPP) Per Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
40 µs
9.4 µs
6 µs
450 ms
900 ms
General Description
The Spansion S29NS512/256/128P are MirrorBit Flash products fabricated on 90 nm process technology. These burst mode
Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using
multiplexed data and address pins. These products can operate up to 83 MHz and use a single VCC of 1.7 V to 1.95 V that
makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered
power consumption.
Publication Number S29NS-P_00
Revision A Amendment 8
Issue Date September 8, 2011
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. Input/Output Descriptions and Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3 Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.9 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.10 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.11 Programmable Output Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7. Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2 Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.3 Dynamic Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.4 Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.5 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.7 Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8. Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.2 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.3 Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9. Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.1 Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.2 Customer Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.3 Secured Silicon Sector Entry and Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . . . . 64
10. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.4 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.5 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.6 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.7 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.8 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.10 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
12. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Figures
Figure 3.1 Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4.1 64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down . . 10
Figure 4.2 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down . . 11
Figure 4.3 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down . . 11
Figure 4.4 VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P . . . . . . . . . . . . . . . . . . 12
Figure 4.5 VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P . . . . . . . . . . . . . . 13
Figure 6.1 Synchronous Read Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 6.2 Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6.3 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 6.4 Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 6.5 Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 7.1 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 7.2 PPB Program/Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 7.3 Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 10.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 10.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 10.3 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 10.4 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 10.5 VCC Power-Up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 10.6 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 10.7 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around . . . . . . . . . . . . . . . . 71
Figure 10.8 8-Word Linear Single Data Read Synchronous Burst without Wrap Around . . . . . . . . . . . . . 71
Figure 10.9 Asynchronous Mode Read with Latched Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 10.10 Asynchronous Mode Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 10.11 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 10.12 Asynchronous Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 10.13 Chip/Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 10.14 Accelerated Unlock Bypass Programming Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 10.15 Data# Polling Timings (During Embedded Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 10.16 Toggle Bit Timings (During Embedded Algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 10.17 Synchronous Data Polling Timings/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 10.18 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 10.19 Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 10.20 Wait State Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 10.21 Back-to-Back Read/Write Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
5


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Tables
6
Table 2.1
Table 5.1
Table 5.2
Table 5.3
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 6.8
Table 6.9
Table 6.10
Table 6.11
Table 6.12
Table 6.13
Table 6.14
Table 6.15
Table 6.16
Table 6.17
Table 6.18
Table 6.19
Table 6.20
Table 6.21
Table 6.22
Table 6.23
Table 6.24
Table 6.25
Table 6.26
Table 6.27
Table 6.28
Table 6.29
Table 7.1
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10
Table 10.11
Table 10.12
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
S29NS512P Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
S29NS256P Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
S29NS128P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Address Latency for 2 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Programmable Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Secured Silicon SectorSecure Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Secured Silicon Sector Entry (LLD Function = lld_SecSiSectorEntryCmd) . . . . . . . . . . . . . .64
Secured Silicon Sector Program (LLD Function = lld_ProgramCmd) . . . . . . . . . . . . . . . . . . .64
Secured Silicon Sector Exit (LLD Function = lld_SecSiSectorExitCmd) . . . . . . . . . . . . . . . . .65
DC Characteristics—CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
VCC Power-Up with No Ramp Rate Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Synchronous Wait State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Asynchronous Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Example of Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
1. Ordering Information
The ordering part number is formed by a valid combination of the following:
S29NS 512 P xx BJ W 00 0
Packing Type
0 = Tray (standard; (Note 1))
3 = 13-inch Tape and Reel
Model Number
00 = Standard
Temperature Range
W = Wireless (–25°C to +85°C)
Package Type & Material Set
BJ = Very Thin Fine-Pitch BGA,Lead (Pb)-free LF35 Package
Speed Option (Burst Frequency)
0P = 66 MHz
0S = 83 MHz
Process Technology
P = 90 nm MirrorBit Technology
Flash Density
512 =512 Mb
256 =256 Mb
128 =128 Mb
Product Family
S29NS = 1.8 Volt-Only Simultaneous Read/Write, Burst Mode Multiplexed Flash
Memory
Valid Combinations
Base Ordering
Part Number
Speed
Option
Package Type, Material,
& Temperature Range
Packing
Type
Model
Number
S29NS512P
S29NS256P
0P, 0S
BJW (Lead (Pb)-free, LF35) 0, 3 (1)
00
S29NS128P
Notes
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading S29 and packing type designator from ordering part number.
Package Type
8.0 mm x 9.2 mm, 64-ball
6.2 mm x 7.7 mm, 44-ball
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
7


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
2. Input/Output Descriptions and Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
A24 – A16
A23 – A16
A22 – A16
A/DQ15 – A/DQ0
CE#
OE#
WE#
VCC
VCCQ
VSS
VSSQ
NC
RDY
CLK
AVD#
RESET#
WP#
VPP
RFU
DNU
Type
Description
Input
Address inputs, S29NS512P.
Input
Address inputs, S29NS256P.
Input
Address inputs, S29NS128P.
I/O Multiplexed Address/Data input/output.
Input
Chip Enable. Asynchronous relative to CLK for the Burst mode.
Input
Output Enable. Asynchronous relative to CLK for the Burst mode.
Input
Write Enable.
Supply Device Power Supply.
Supply
I/O
Input/Output Power Supply (must be ramped simultaneously with VCC).
Ground.
I/O Input/Output Ground.
Not
Connected
No device internal signal is connected to the package connector nor is there any future plan to use
the connector for a signal. The connection may safely be used for routing space for a signal on a
Printed Circuit Board (PCB).
Output Ready. Indicates when valid burst data is ready to be read.
Input
The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst
mode operation. After the initial word is output, subsequent rising edges of CLK increment the
internal address counter. CLK should remain low during asynchronous access.
Input
Input
Address Valid input. Indicates to device that the valid address is present on the address inputs
(address bits A15 – A0 are multiplexed, address bits Amax – A16 are address only).
VIL = for asynchronous mode, indicates valid address; for burst mode, cause staring address to be
latched on rising edge of CLK.
VIH = device ignores address inputs.
Hardware Reset. Low = device resets and returns to reading array data.
Input
Write Protect. At VIL, disables program and erase functions in the four top sectors. Should be at VIH
for all other conditions.
Input
Reserved
Accelerated input.
At VHH, accelerates programming; automatically places device in unlock bypass mode.
At VIL,disables all program and erase functions.
Should be at VIH for all other conditions.
Reserved for Future Use. No device internal signal is currently connected to the package connector
but there is potential future use for the connector for a signal. It is recommended to not use RFU
connectors for PCB routing channels so that the PCB may take advantage of future enhanced
features in compatible footprint devices.
Do Not Use
A device internal signal may be connected to the package connector. The connection may be used by
Spansion for test or other purposes and is not intended for connection to any host system signal. Any
DNU signal related function will be inactive when the signal is at VIL. The signal has an internal pull-
down resistor and may be left unconnected in the host system or may be tied to VSS. Do not use
these connections for PCB signal routing channels. Do not connect any host system signal to these
connections.
8
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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3. Block Diagrams
VCC
VSS
VCCQ
VSSQ
WP#
VPP
RESET#
WE#
CE#
AVD#
RDY
A/DQ15–A/DQ0
Amax–A16
Data Sheet
Figure 3.1 Simultaneous Operation Circuit
Bank Address
Amax–A0
Bank 0
X-Decoder
DQ15–DQ0
OE#
Bank Address
Bank 1
DQ15–DQ0
Amax–A0
STATE
CONTROL
&
COMMAND
REGISTER
Amax–A16
X-Decoder
Status
Control
X-Decoder
Bank Address
Bank (n-1)
DQ15–DQ0
DQ15–DQ0
Bank Address
Notes
1. Amax = A24 for NS512P, A23 for NS256P, A22 for NS128P.
2. Bank (n) = 15 for NS512P/ NS256P/ NS128P.
X-Decoder
Bank (n)
DQ15–DQ0
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
9


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
4. Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications for the OPN.
4.1 Related Documents
The following documents contain information relating to the S29NS-P devices. Click on the title or go to
www.spansion.com, or request a copy from your sales office.
Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
4.2 Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
4.2.1 64-Ball Fine-Pitch Grid Array, S29NS512P
Figure 4.1 64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down
1
A
nc
B
C
D
E
F
G
H
nc
2 3 4 5 6 7 8 9 10 11 12 13 14
DNU DNU VSS A24 VCC VSS VCC RFU DNU DNU
RDY A21 VSS CLK VCC WE# VPP A19 A17 A22
VCCQ A16 A20 ADV# A23 RESET# WP# A18 CE# VSSQ
VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0
DNU DNU DNU VCCQ VSSQ RFU VCCQ DNU DNU DNU
nc
nc
Legend
Flash Only
No Connect
Reserved for
Future Use
Do Not Use
10
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
4.2.2
44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P
Figure 4.2 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down
NC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
RDY A21 VSS CLK VCC WE# VPP A19 A17 A22
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
VCCQ
A16
A20 AVD# A23 RESET# WP#
A18
CE#
VSSQ
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0
NC
NC NC
4.2.3
44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P
Figure 4.3 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down
NC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
RDY A21 VSS CLK VCC WE# VPP A19 A17 A22
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
VCCQ
A16
A20 AVD# NC RESET# WP#
A18
CE#
VSSQ
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE#
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0
NC
NC NC
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
11


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
4.2.4
VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array
Figure 4.4 VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P
10
A1 CORNER
INDEX MARK
DA
D1
e
A1 CORNER
e
E
0.50
10 9 8 7 6 5 4 3 2 1
NF2 NF1
A
B
C
D
E
F
NF4 NF3
7
SE E1
A
A1
TOP VIEW
SEATING PLANE
SIDE VIEW
B
A2 0.10 C
C 0.08 C
1.00
Øb 6
SD 7
Ø 0.05 M C
Ø 0.15 M C A B
BOTTOM VIEW
PACKAGE
JEDEC
SYMBOL
A
A1
A2
D
E
D1
E1
MD
ME
N
Øb
e
SD / SE
VDD 064
N/A
8.00 mm x 9.20 mm NOM
PACKAGE
MIN NOM MAX
0.86 --- 1.00
0.20
---
---
0.66
0.71
0.76
7.90
8.00
8.10
9.10
9.20
9.30
4.50
2.50
10
6
64
0.25
0.30
0.35
0.50
0.25
NOTE
OVERALL THICKNESS
BALL HEIGHT
BODY THICKNESS
BODY SIZE
BODY SIZE
BALL FOOTPRINT
BALL FOOTPRINT
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
BALL DIAMETER
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3533 \ 16-038.27 \ 12.13.05
12
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
4.2.5
VDE44-44-Ball Very Thin Fine-Pitch Ball Grid Array, 7.7 mm x 6.2 mm
Figure 4.5 VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P
A1 CORNER
INDEX MARK
10
DA
D1
10 9 8 7 6 5 4 3 2 1
A1 CORNER
e
E
1.00
NF2
NF4
NF1
A
B
C
D
NF3
SE
7
E1
A
A1
TOP VIEW
B
A2
SIDE VIEW
SEATING PLANE C
1.00
0.10 C
0.08 C
φb 6
SD 7
φ 0.05 M C
φ 0.15 M C A B
BOTTOM VIEW
PACKAGE
JEDEC
SYMBOL
A
A1
A2
D
E
D1
E1
MD
ME
N
φb
e
SD / SE
?
VDE 044
N/A
7.70 mm x 6.20 mm NOM
PACKAGE
MIN NOM MAX
0.86 --- 1.00
0.20 ---
---
0.66 0.71 0.76
7.6 7.7 7.8
6.1 6.2 6.3
4.50
1.50
10
4
44
0.25 0.30 0.35
0.50 BSC.
0.25 BSC.
NOTE
OVERALL THICKNESS
BALL HEIGHT
BODY THICKNESS
BODY SIZE
BODY SIZE
BALL FOOTPRINT
BALL FOOTPRINT
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
BALL DIAMETER
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN ?
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3308.2 \ 16-038.9L
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
13


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
5. Product Overview
The S29NS-P family consists of 512, 256, and 128 Mb, 1.8 volts-only, simultaneous read/write burst mode,
multiplexed Flash device optimized for today’s wireless designs that demand a large storage array, rich
functionality, and low power consumption.
These devices are organized in 32, 16, or 8 Mwords of 16 bits each and are capable of continuous,
synchronous (burst) read or linear read (8-word, 16-word, or 32-word aligned group) with or without wrap
around. These flash devices multiplex the data and addresses for reduced I/O count. These products also
offer single word programming or a 32-word buffer for programming with program/erase and suspend
functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required
256 words of Secured Silicon area for storing customer and factory secured information. The Secured
Silicon Sector is One Time Programmable.
5.1
Bank
Memory Map
The S29NS512/256/128P devices consist of 16 banks organized as shown in Tables 5.1 5.3.
Table 5.1 S29NS512P Sector and Memory Address Map (Sheet 1 of 8)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
Bank
Sector
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
14
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Bank
Sector
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
Table 5.1 S29NS512P Sector and Memory Address Map (Sheet 2 of 8)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
Bank
Sector
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
Sector Size
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
Address Range
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7FFFFFh
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
15


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Bank
Sector
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
Table 5.1 S29NS512P Sector and Memory Address Map (Sheet 3 of 8)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
800000h–80FFFFh
810000h–81FFFFh
820000h–82FFFFh
830000h–83FFFFh
840000h–84FFFFh
850000h–85FFFFh
860000h–86FFFFh
870000h–87FFFFh
880000h–88FFFFh
890000h–89FFFFh
8A0000h–8AFFFFh
8B0000h–8BFFFFh
8C0000h–8CFFFFh
8D0000h–8DFFFFh
8E0000h–8EFFFFh
8F0000h–8FFFFFh
900000h–90FFFFh
910000h–91FFFFh
920000h–92FFFFh
930000h–93FFFFh
940000h–94FFFFh
950000h–95FFFFh
960000h–96FFFFh
970000h–97FFFFh
980000h–98FFFFh
990000h–99FFFFh
9A0000h–9AFFFFh
9B0000h–9BFFFFh
9C0000h–9CFFFFh
9D0000h–9DFFFFh
9E0000h–9EFFFFh
9F0000h–9FFFFFh
Bank
Sector
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
A00000h–A0FFFFh
A10000h–A1FFFFh
A20000h–A2FFFFh
A30000h–A3FFFFh
A40000h–A4FFFFh
A50000h–A5FFFFh
A60000h–A6FFFFh
A70000h–A7FFFFh
A80000h–A8FFFFh
A90000h–A9FFFFh
AA0000h–AAFFFFh
AB0000h–ABFFFFh
AC0000h–ACFFFFh
AD0000h–ADFFFFh
AE0000h–AEFFFFh
AF0000h–AFFFFFh
B00000h–B0FFFFh
B10000h–B1FFFFh
B20000h–B2FFFFh
B30000h–B3FFFFh
B40000h–B4FFFFh
B50000h–B5FFFFh
B60000h–B6FFFFh
B70000h–B7FFFFh
B80000h–B8FFFFh
B90000h–B9FFFFh
BA0000h–BAFFFFh
BB0000h–BBFFFFh
BC0000h–BCFFFFh
BD0000h–BDFFFFh
BE0000h–BEFFFFh
BF0000h–BFFFFFh
16
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Bank
Sector
SA192
SA193
SA194
SA195
SA196
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
Table 5.1 S29NS512P Sector and Memory Address Map (Sheet 4 of 8)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
C00000h–C0FFFFh
C10000h–C1FFFFh
C20000h–C2FFFFh
C30000h–C3FFFFh
C40000h–C4FFFFh
C50000h–C5FFFFh
C60000h–C6FFFFh
C70000h–C7FFFFh
C80000h–C8FFFFh
C90000h–C9FFFFh
CA0000h–CAFFFFh
CB0000h–CBFFFFh
CC0000h–CCFFFFh
CD0000h–CDFFFFh
CE0000h–CEFFFFh
CF0000h–CFFFFFh
D00000h–D0FFFFh
D10000h–D1FFFFh
D20000h–D2FFFFh
D30000h–D3FFFFh
D40000h–D4FFFFh
D50000h–D5FFFFh
D60000h–D6FFFFh
D70000h–D7FFFFh
D80000h–D8FFFFh
D90000h–D9FFFFh
DA0000h–DAFFFFh
DB0000h–DBFFFFh
DC0000h–DCFFFFh
DD0000h–DDFFFFh
DE0000h–DEFFFFh
DF0000h–DFFFFFh
Bank
Sector
SA224
SA225
SA226
SA227
SA228
SA229
SA230
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
Sector Size
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
Address Range
E00000h–E0FFFFh
E10000h–E1FFFFh
E20000h–E2FFFFh
E30000h–E3FFFFh
E40000h–E4FFFFh
E50000h–E5FFFFh
E60000h–E6FFFFh
E70000h–E7FFFFh
E80000h–E8FFFFh
E90000h–E9FFFFh
EA0000h–EAFFFFh
EB0000h–EBFFFFh
EC0000h–ECFFFFh
ED0000h–EDFFFFh
EE0000h–EEFFFFh
EF0000h–EFFFFFh
F00000h–F0FFFFh
F10000h–F1FFFFh
F20000h–F2FFFFh
F30000h–F3FFFFh
F40000h–F4FFFFh
F50000h–F5FFFFh
F60000h–F6FFFFh
F70000h–F7FFFFh
F80000h–F8FFFFh
F90000h–F9FFFFh
FA0000h–FAFFFFh
FB0000h–FBFFFFh
FC0000h–FCFFFFh
FD0000h–FDFFFFh
FE0000h–FEFFFFh
FF0000h–FFFFFFh
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
17


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Bank
Sector
SA256
SA257
SA258
SA259
SA260
SA261
SA262
SA263
SA264
SA265
SA266
SA267
SA268
SA269
SA270
SA271
SA272
SA273
SA274
SA275
SA276
SA277
SA278
SA279
SA280
SA281
SA282
SA283
SA284
SA285
SA286
SA287
Table 5.1 S29NS512P Sector and Memory Address Map (Sheet 5 of 8)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
1000000h-100FFFFh
1010000h-101FFFFh
1020000h-102FFFFh
1030000h-103FFFFh
1040000h-104FFFFh
1050000h-105FFFFh
1060000h-106FFFFh
1070000h-107FFFFh
1030000h-108FFFFh
1090000h-109FFFFh
10A0000h-10AFFFFh
10B0000h-10BFFFFh
10C0000h-10CFFFFh
10D0000h-10DFFFFh
10E0000h-10EFFFFh
10F0000h-10FFFFFh
1100000h-110FFFFh
1110000h-111FFFFh
1120000h-112FFFFh
1130000h-113FFFFh
1140000h-114FFFFh
1150000h-115FFFFh
1160000h-116FFFFh
1170000h-117FFFFh
1180000h-118FFFFh
1190000h-119FFFFh
11A0000h-11AFFFFh
11B0000h-11BFFFFh
11C0000h-11CFFFFh
11D0000h-11DFFFFh
11E0000h-11EFFFFh
11F0000h-11FFFFFh
Bank
Sector
SA288
SA289
SA290
SA291
SA292
SA293
SA294
SA295
SA296
SA297
SA298
SA299
SA300
SA301
SA302
SA303
SA304
SA305
SA306
SA307
SA308
SA309
SA310
SA311
SA312
SA313
SA314
SA315
SA316
SA317
SA318
SA319
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
1200000h-120FFFFh
1210000h-121FFFFh
1220000h-122FFFFh
1230000h-123FFFFh
1240000h-124FFFFh
1250000h-125FFFFh
1260000h-126FFFFh
1270000h-127FFFFh
1230000h-128FFFFh
1290000h-129FFFFh
12A0000h-12AFFFFh
12B0000h-12BFFFFh
12C0000h-12CFFFFh
12D0000h-12DFFFFh
12E0000h-12EFFFFh
12F0000h-12FFFFFh
1300000h-130FFFFh
1310000h-131FFFFh
1320000h-132FFFFh
1330000h-133FFFFh
1340000h-134FFFFh
1350000h-135FFFFh
1360000h-136FFFFh
1370000h-137FFFFh
1380000h-138FFFFh
1390000h-139FFFFh
13A0000h-13AFFFFh
13B0000h-13BFFFFh
13C0000h-13CFFFFh
13D0000h-13DFFFFh
13E0000h-13EFFFFh
13F0000h-13FFFFFh
18
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Bank
Sector
SA320
SA321
SA322
SA323
SA324
SA325
SA326
SA327
SA328
SA329
SA330
SA331
SA332
SA333
SA334
SA335
SA336
SA337
SA338
SA339
SA340
SA341
SA342
SA343
SA344
SA345
SA346
SA347
SA348
SA349
SA350
SA351
Table 5.1 S29NS512P Sector and Memory Address Map (Sheet 6 of 8)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
1400000h-140FFFFh
1410000h-141FFFFh
1420000h-142FFFFh
1430000h-143FFFFh
1440000h-144FFFFh
1450000h-145FFFFh
1460000h-146FFFFh
1470000h-147FFFFh
1430000h-148FFFFh
1490000h-149FFFFh
14A0000h-14AFFFFh
14B0000h-14BFFFFh
14C0000h-14CFFFFh
14D0000h-14DFFFFh
14E0000h-14EFFFFh
14F0000h-14FFFFFh
1500000h-150FFFFh
1510000h-151FFFFh
1520000h-152FFFFh
1530000h-153FFFFh
1540000h-154FFFFh
1550000h-155FFFFh
1560000h-156FFFFh
1570000h-157FFFFh
1580000h-158FFFFh
1590000h-159FFFFh
15A0000h-15AFFFFh
15B0000h-15BFFFFh
15C0000h-15CFFFFh
15D0000h-15DFFFFh
15E0000h-15EFFFFh
15F0000h-15FFFFFh
Bank
Sector
SA352
SA353
SA354
SA355
SA356
SA357
SA358
SA359
SA360
SA361
SA362
SA363
SA364
SA365
SA366
SA367
SA368
SA369
SA370
SA371
SA372
SA373
SA374
SA375
SA376
SA377
SA378
SA379
SA380
SA381
SA382
SA383
Sector Size
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
Address Range
1600000h-160FFFFh
1610000h-161FFFFh
1620000h-162FFFFh
1630000h-163FFFFh
1640000h-164FFFFh
1650000h-165FFFFh
1660000h-166FFFFh
1670000h-167FFFFh
1630000h-168FFFFh
1690000h-169FFFFh
16A0000h-16AFFFFh
16B0000h-16BFFFFh
16C0000h-16CFFFFh
16D0000h-16DFFFFh
16E0000h-16EFFFFh
16F0000h-16FFFFFh
1700000h-170FFFFh
1710000h-171FFFFh
1720000h-172FFFFh
1730000h-173FFFFh
1740000h-174FFFFh
1750000h-175FFFFh
1760000h-176FFFFh
1770000h-177FFFFh
1780000h-178FFFFh
1790000h-179FFFFh
17A0000h-17AFFFFh
17B0000h-17BFFFFh
15C0000h-17CFFFFh
17D0000h-17DFFFFh
17E0000h-17EFFFFh
17F0000h-17FFFFFh
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
19


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

No Preview Available !

Click to Download PDF File for PC

Data Sheet
Bank
Sector
SA384
SA385
SA386
SA387
SA388
SA389
SA390
SA391
SA392
SA393
SA394
SA395
SA396
SA397
SA398
SA399
SA400
SA401
SA402
SA403
SA404
SA405
SA406
SA407
SA408
SA409
SA410
SA411
SA412
SA413
SA414
SA415
Table 5.1 S29NS512P Sector and Memory Address Map (Sheet 7 of 8)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
1800000h-180FFFFh
1810000h-181FFFFh
1820000h-182FFFFh
1830000h-183FFFFh
1840000h-184FFFFh
1850000h-185FFFFh
1860000h-186FFFFh
1870000h-187FFFFh
1830000h-188FFFFh
1890000h-189FFFFh
18A0000h-18AFFFFh
18B0000h-18BFFFFh
18C0000h-18CFFFFh
18D0000h-18DFFFFh
18E0000h-18EFFFFh
18F0000h-18FFFFFh
1900000h-190FFFFh
1910000h-191FFFFh
1920000h-192FFFFh
1930000h-193FFFFh
1940000h-194FFFFh
1950000h-195FFFFh
1960000h-196FFFFh
1970000h-197FFFFh
1980000h-198FFFFh
1990000h-199FFFFh
19A0000h-19AFFFFh
19B0000h-19BFFFFh
19C0000h-19CFFFFh
19D0000h-19DFFFFh
19E0000h-19EFFFFh
19F0000h-19FFFFFh
Bank
Sector
SA416
SA417
SA418
SA419
SA420
SA421
SA422
SA423
SA424
SA425
SA426
SA427
SA428
SA429
SA430
SA431
SA432
SA433
SA434
SA435
SA436
SA437
SA438
SA439
SA440
SA441
SA442
SA443
SA444
SA445
SA446
SA447
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
1A00000h-1A0FFFFh
1A10000h-1A1FFFFh
1A20000h-1A2FFFFh
1A30000h-1A3FFFFh
1A40000h-1A4FFFFh
1A50000h-1A5FFFFh
1A60000h-1A6FFFFh
1A70000h-1A7FFFFh
1A30000h-1A8FFFFh
1A90000h-1A9FFFFh
1AA0000h-1AAFFFFh
1AB0000h-1ABFFFFh
1AC0000h-1ACFFFFh
1AD0000h-1ADFFFFh
1AE0000h-1AEFFFFh
1AF0000h-1AFFFFFh
1B00000h-1B0FFFFh
1B10000h-1B1FFFFh
1B20000h-1B2FFFFh
1B30000h-1B3FFFFh
1B40000h-1B4FFFFh
1B50000h-1B5FFFFh
1B60000h-1B6FFFFh
1B70000h-1B7FFFFh
1B80000h-1B8FFFFh
1B90000h-1B9FFFFh
1BA0000h-1BAFFFFh
1BB0000h-1BBFFFFh
1BC0000h-1BCFFFFh
1BD0000h-1BDFFFFh
1BE0000h-1BEFFFFh
1BF0000h-1BFFFFFh
20
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

No Preview Available !

Click to Download PDF File for PC

Data Sheet
Bank
Sector
SA448
SA449
SA450
SA451
SA452
SA453
SA454
SA455
SA456
SA457
SA458
SA459
SA460
SA461
SA462
SA463
SA464
SA465
SA466
SA467
SA468
SA469
SA470
SA471
SA472
SA473
SA474
SA475
SA476
SA477
SA478
SA479
Table 5.1 S29NS512P Sector and Memory Address Map (Sheet 8 of 8)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
1C00000h-1C0FFFFh
1C10000h-1C1FFFFh
1C20000h-1C2FFFFh
1C30000h-1C3FFFFh
1C40000h-1C4FFFFh
1C50000h-1C5FFFFh
1C60000h-1C6FFFFh
1C70000h-1C7FFFFh
1C30000h-1C8FFFFh
1C90000h-1C9FFFFh
1CA0000h-1CAFFFFh
1CB0000h-1CBFFFFh
1CC0000h-1CCFFFFh
1CD0000h-1CDFFFFh
1CE0000h-1CEFFFFh
1CF0000h-1CFFFFFh
1D00000h-1D0FFFFh
1D10000h-1D1FFFFh
1D20000h-1D2FFFFh
1D30000h-1D3FFFFh
1D40000h-1D4FFFFh
1D50000h-1D5FFFFh
1D60000h-1D6FFFFh
1D70000h-1D7FFFFh
1D80000h-1D8FFFFh
1D90000h-1D9FFFFh
1DA0000h-1DAFFFFh
1DB0000h-1DBFFFFh
1DC0000h-1DCFFFFh
1DD0000h-1DDFFFFh
1DE0000h-1DEFFFFh
1DF0000h-1DFFFFFh
Bank
Sector
SA480
SA481
SA482
SA483
SA484
SA485
SA486
SA487
SA488
SA489
SA490
SA491
SA492
SA493
SA494
SA495
SA496
SA497
SA498
SA499
SA500
SA501
SA502
SA503
SA504
SA505
SA506
SA507
SA508
SA509
SA510
SA511
Sector Size
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
Address Range
1E00000h-1E0FFFFh
1E10000h-1E1FFFFh
1E20000h-1E2FFFFh
1E30000h-1E3FFFFh
1E40000h-1E4FFFFh
1E50000h-1E5FFFFh
1E60000h-1E6FFFFh
1E70000h-1E7FFFFh
1E30000h-1E8FFFFh
1E90000h-1E9FFFFh
1EA0000h-1EAFFFFh
1EB0000h-1EBFFFFh
1EC0000h-1ECFFFFh
1ED0000h-1EDFFFFh
1EE0000h-1EEFFFFh
1EF0000h-1EFFFFFh
1F00000h-1F0FFFFh
1F10000h-1F1FFFFh
1F20000h-1F2FFFFh
1F30000h-1F3FFFFh
1F40000h-1F4FFFFh
1F50000h-1F5FFFFh
1F60000h-1F6FFFFh
1F70000h-1F7FFFFh
1F80000h-1F8FFFFh
1F90000h-1F9FFFFh
1FA0000h-1FAFFFFh
1FB0000h-1FBFFFFh
1FC0000h-1FCFFFFh
1FD0000h-1FDFFFFh
1FE0000h-1FEFFFFh
1FF0000h-1FFFFFFh
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
21


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

No Preview Available !

Click to Download PDF File for PC

Data Sheet
Bank
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
Table 5.2 S29NS256P Sector and Memory Address Map (Sheet 1 of 3)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
Bank
Sector
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
Address Range
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
22
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

No Preview Available !

Click to Download PDF File for PC

Data Sheet
Bank
Sector
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
Table 5.2 S29NS256P Sector and Memory Address Map (Sheet 2 of 3)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
800000h–80FFFFh
810000h–81FFFFh
820000h–82FFFFh
830000h–83FFFFh
840000h–84FFFFh
850000h–85FFFFh
860000h–86FFFFh
870000h–87FFFFh
880000h–88FFFFh
890000h–89FFFFh
8A0000h–8AFFFFh
8B0000h–8BFFFFh
8C0000h–8CFFFFh
8D0000h–8DFFFFh
8E0000h–8EFFFFh
8F0000h–8FFFFFh
900000h–90FFFFh
910000h–91FFFFh
920000h–92FFFFh
930000h–93FFFFh
940000h–94FFFFh
950000h–95FFFFh
960000h–96FFFFh
970000h–97FFFFh
980000h–98FFFFh
990000h–99FFFFh
9A0000h–9AFFFFh
9B0000h–9BFFFFh
9C0000h–9CFFFFh
9D0000h–9DFFFFh
9E0000h–9EFFFFh
9F0000h–9FFFFFh
Bank
Sector
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
SA179
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
Sector Size
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7FFFFFh
A00000h–A0FFFFh
A10000h–A1FFFFh
A20000h–A2FFFFh
A30000h–A3FFFFh
A40000h–A4FFFFh
A50000h–A5FFFFh
A60000h–A6FFFFh
A70000h–A7FFFFh
A80000h–A8FFFFh
A90000h–A9FFFFh
AA0000h–AAFFFFh
AB0000h–ABFFFFh
AC0000h–ACFFFFh
AD0000h–ADFFFFh
AE0000h–AEFFFFh
AF0000h–AFFFFFh
B00000h–B0FFFFh
B10000h–B1FFFFh
B20000h–B2FFFFh
B30000h–B3FFFFh
B40000h–B4FFFFh
B50000h–B5FFFFh
B60000h–B6FFFFh
B70000h–B7FFFFh
B80000h–B8FFFFh
B90000h–B9FFFFh
BA0000h–BAFFFFh
BB0000h–BBFFFFh
BC0000h–BCFFFFh
BD0000h–BDFFFFh
BE0000h–BEFFFFh
BF0000h–BFFFFFh
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
23


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

No Preview Available !

Click to Download PDF File for PC

Data Sheet
Bank
Sector
SA192
SA193
SA194
SA195
SA196
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
Table 5.2 S29NS256P Sector and Memory Address Map (Sheet 3 of 3)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
C00000h–C0FFFFh
C10000h–C1FFFFh
C20000h–C2FFFFh
C30000h–C3FFFFh
C40000h–C4FFFFh
C50000h–C5FFFFh
C60000h–C6FFFFh
C70000h–C7FFFFh
C80000h–C8FFFFh
C90000h–C9FFFFh
CA0000h–CAFFFFh
CB0000h–CBFFFFh
CC0000h–CCFFFFh
CD0000h–CDFFFFh
CE0000h–CEFFFFh
CF0000h–CFFFFFh
D00000h–D0FFFFh
D10000h–D1FFFFh
D20000h–D2FFFFh
D30000h–D3FFFFh
D40000h–D4FFFFh
D50000h–D5FFFFh
D60000h–D6FFFFh
D70000h–D7FFFFh
D80000h–D8FFFFh
D90000h–D9FFFFh
DA0000h–DAFFFFh
DB0000h–DBFFFFh
DC0000h–DCFFFFh
DD0000h–DDFFFFh
DE0000h–DEFFFFh
DF0000h–DFFFFFh
Bank
Sector
SA224
SA225
SA226
SA227
SA228
SA229
SA230
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
SA256
SA257
SA258
Sector Size
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
16 K words
16 K words
16 K words
16 K words
Address Range
E00000h–E0FFFFh
E10000h–E1FFFFh
E20000h–E2FFFFh
E30000h–E3FFFFh
E40000h–E4FFFFh
E50000h–E5FFFFh
E60000h–E6FFFFh
E70000h–E7FFFFh
E80000h–E8FFFFh
E90000h–E9FFFFh
EA0000h–EAFFFFh
EB0000h–EBFFFFh
EC0000h–ECFFFFh
ED0000h–EDFFFFh
EE0000h–EEFFFFh
EF0000h–EFFFFFh
F00000h–F0FFFFh
F10000h–F1FFFFh
F20000h–F2FFFFh
F30000h–F3FFFFh
F40000h–F4FFFFh
F50000h–F5FFFFh
F60000h–F6FFFFh
F70000h–F7FFFFh
F80000h–F8FFFFh
F90000h–F9FFFFh
FA0000h–FAFFFFh
FB0000h–FBFFFFh
FC0000h–FCFFFFh
FD0000h–FDFFFFh
FE0000h–FEFFFFh
FF0000h–FF3FFFh
FF4000h–FF7FFFh
FF8000h–FFBFFFh
FFC000h–FFFFFFh
24
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Bank
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
Table 5.3 S29NS128P Sector & Memory Address Map (Sheet 1 of 2)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
Bank
Sector
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
Address Range
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
25


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Bank
Sector
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
Table 5.3 S29NS128P Sector & Memory Address Map (Sheet 2 of 2)
Sector Size
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
Address Range
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
Bank
Sector
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
Sector Size
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
64 K words
16 K words
16 K words
16 K words
16 K words
Address Range
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7F3FFFh
7F4000h–7F7FFFh
7F8000h–7FBFFFh
7FC000h–7FFFFFh
26
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
6. Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset
features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns
into the command registers (see Tables 11.1 and 11.2). The command register itself does not occupy any
addressable memory location; rather, it is composed of latches that store the commands, along with the
address and data information needed to execute the command. The contents of the register serve as input to
the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect
address and data values or writing them in an improper sequence may place the device in an unknown state,
in which case the system must write the reset command to return the device to the reading array data mode.
6.1
Device Operation Table
The device must be setup appropriately for each operation. Table 6.1 describes the required state of each
control pin for any particular operation.
Table 6.1 Device Operations
Operation
Asynchronous Read –
Addresses Latched
CE# OE# WE#
LL
H
CLK
X
AVD#
Amax–
A16
A/DQ15–
A/DQ0
Addr In
I/O
RDY RESET#
HH
Asynchronous Write
LH
X
Addr In
I/O
H
H
Standby (CE#)
HX
X
X
X
X
High-Z
High-Z
H
Hardware Reset
XX
X
X
X
X
High-Z
High-Z
Burst Read Operations
Latch Starting Burst Address by CLK
LH
H
L Addr In Addr In
X
H
Advance Burst read to next address
LL
H
HX
Terminate current Burst read cycle
Terminate current Burst read cycle
via RESET#
HX
H
X
X
X
XX
H
X
X
X
Terminate current Burst read cycle
and start new Burst read cycle
LX
H
Addr In
Legend
L = Logic 0, H = Logic 1, X = can be either VIL or VIH.,
= rising edge,
= high to low,
Notes
1. Address is latched on the rising edge of clock.
2. CLK must stay low or high after CE# goes low when device in Asynchronous Read mode.
I/O
High-Z
High-Z
H
High-Z
High-Z
Addr In
X
= toggle.
H
H
L
H
6.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from
one memory location at a time. Addresses are presented to the device in random order, and the propagation
delay through the device causes the data on its outputs to arrive asynchronously with the address on its
inputs.
To read data from the memory array, the system must first assert a valid address while driving AVD# and
CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches the address. The OE# signal must be
driven to VIL, once AVD# has been driven to VIH.
The data is output on A/DQ15 – A/DQ0 pins after the access time (tOE) has elapsed from the falling edge of
OE#.
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
27


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
6.3
Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a preset length.
When the device first powers up, it is enabled for Asynchronous read and can be automatically enabled for
burst mode and the address is latched on the first rising edge of CLK input, while AVD# is held low for one
clock cycle.
Prior to activating the clock signal, the system should determine how many wait states are desired for the
initial word (tIACC) of each burst access, what mode of burst operation is desired and how the RDY signal
transitions with valid data. The system would then write the configuration register command sequence.
At startup the system writes the Set Configuration Register command sequence to optimize the system
performance.
The data is output tIACC after the rising edge of the first CLK. Subsequent words are output tBACC after the
rising edge of each successive clock cycle, which automatically increments the internal address counter.
Note that data is output only at the rising edge of the clock. RDY indicates the initial latency.
Note that the device has a fixed internal address boundary that occurs every 128 words. No boundary
crossing latency is required when the device operates with wait states set from 2 to 9.
6.3.1
Latency Tables for Variable Wait State
Tables 6.2 6.9 show the latency for variable wait state in a normal Burst operation.
Table 6.2 Address Latency for 9 Wait States
Word
0
1
2
3
4
5
6
7
Initial Wait
9 ws
D0 D1
D1 D2
D2 D3
D3 D4
D4 D5
D5 D6
D6 D7
D7 1 ws
D2
D3
D4
D5
D6
D7
1 ws
1 ws
D3
D4
D5
D6
D7
1 ws
1 ws
1 ws
D4
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D7
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D8
D8
D8
D8
D8
D8
D8
D8
Word
0
1
2
3
4
5
6
7
Initial Wait
8 ws
Table 6.3 Address Latency for 8 Wait States
D0 D1
D1 D2
D2 D3
D3 D4
D4 D5
D5 D6
D6 D7
D7 1 ws
D2
D3
D4
D5
D6
D7
1 ws
1 ws
D3
D4
D5
D6
D7
1 ws
1 ws
1 ws
D4
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D7 D8
D8 D9
D8 D9
D8 D9
D8 D9
D8 D9
D8 D9
D8 D9
28
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Word
0
1
2
3
4
5
6
7
Word
0
1
2
3
4
5
6
7
Word
0
1
2
3
4
5
6
7
Word
0
1
2
3
4
5
6
7
Initial Wait
7 ws
Initial Wait
6 ws
Initial Wait
5 ws
Initial Wait
4 ws
Table 6.4 Address Latency for 7 Wait States
D0 D1
D1 D2
D2 D3
D3 D4
D4 D5
D5 D6
D6 D7
D7 1 ws
D2
D3
D4
D5
D6
D7
1 ws
1 ws
D3
D4
D5
D6
D7
1 ws
1 ws
1 ws
D4
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
Table 6.5 Address Latency for 6 Wait States
D6 D7
D7 D8
D8 D9
D8 D9
D8 D9
D8 D9
D8 D9
D8 D9
D8
D9
D10
D10
D10
D10
D10
D10
D0 D1
D1 D2
D2 D3
D3 D4
D4 D5
D5 D6
D6 D7
D7 1 ws
D2
D3
D4
D5
D6
D7
1 ws
1 ws
D3
D4
D5
D6
D7
1 ws
1 ws
1 ws
D4
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
D5 D6
D6 D7
D7 D8
D8 D9
D8 D9
D8 D9
D8 D9
D8 D9
Table 6.6 Address Latency for 5 Wait States
D7
D8
D9
D10
D10
D10
D10
D10
D8
D9
D10
D11
D11
D11
D11
D11
D0 D1
D1 D2
D2 D3
D3 D4
D4 D5
D5 D6
D6 D7
D7 1 ws
D2
D3
D4
D5
D6
D7
1 ws
1 ws
D3
D4 D5
D6
D7
D8
D4
D5 D6
D7
D8
D9
D5
D6 D7
D8
D9 D10
D6
D7 D8
D9
D10 D11
D7
D8 D9
D10
D11
D12
1 ws
D8 D9
D10
D11
D12
1 ws
D8 D9
D10
D11
D12
1 ws
D8 D9
D10
D11
D12
Table 6.7 Address Latency for 4 Wait States
D0 D1
D1 D2
D2 D3
D3 D4
D4 D5
D5 D6
D6 D7
D7 1 ws
D2
D3 D4
D5
D6
D7
D8
D3
D4 D5
D6
D7
D8
D9
D4
D5 D6
D7
D8
D9 D10
D5
D6 D7
D8
D9 D10 D11
D6
D7 D8
D9
D10 D11 D12
D7
D8 D9
D10
D11
D12
D13
1 ws
D8 D9
D10
D11
D12
D13
1 ws
D8 D9
D10
D11
D12
D13
September 8, 2011 S29NS-P_00_A8
S29NS-P MirrorBit® Flash Family
29


S29NS256P (SPANSION)
Multiplexed MirrorBit Flash Memory

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Data Sheet
Word
0
1
2
3
4
5
6
7
Word
0
1
2
3
4
5
6
7
Initial Wait
3 ws
Initial Wait
2 ws
Table 6.8 Address Latency for 3 Wait States
D0
D1
D2 D3
D4
D5
D6
D7
D8
D1
D2
D3 D4
D5
D6
D7
D8
D9
D2
D3
D4 D5
D6
D7
D8
D9 D10
D3
D4
D5 D6
D7
D8
D9 D10 D11
D4
D5
D6 D7
D8
D9 D10 D11 D12
D5
D6
D7 D8
D9
D10 D11 D12 D13
D6
D7
D8 D9
D10
D11
D12
D13
D14
D7
1 ws
D8 D9
D10
D11
D12
D13
D14
Table 6.9 Address Latency for 2 Wait States
D0 D1 D2
D3
D4
D5
D6
D7
D8
D1 D2 D3
D4
D5
D6
D7
D8
D9
D2 D3 D4
D5
D6
D7
D8
D9 D10
D3 D4 D5
D6
D7
D8
D9 D10 D11
D4 D5 D6
D7
D8
D9 D10 D11 D12
D5 D6 D7
D8
D9 D10 D11 D12 D13
D6 D7 D8
D9
D10 D11 D12 D13 D14
D7 D8 D9
D10
D11
D12
D13
D14
D15
30
S29NS-P MirrorBit® Flash Family
S29NS-P_00_A8 September 8, 2011




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