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Section I. Stratix II Device
Family Data Sheet
This section provides the data sheet specifications for Stratix® II devices.
This section contains feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing information, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix II devices.
This section contains the following chapters:
Chapter 1, Introduction
Chapter 2, Stratix II Architecture
Chapter 3, Configuration & Testing
Chapter 4, Hot Socketing & Power-On Reset
Chapter 5, DC & Switching Characteristics
Chapter 6, Reference & Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
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Stratix II Device Family Data Sheet
Stratix II Device Handbook, Volume 1
Section I–2
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1. Introduction
SII51001-4.2
Introduction
Features
Altera Corporation
May 2007
The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper
SRAM process and features a new logic structure that maximizes
performance, and enables device densities approaching 180,000
equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of
on-chip, TriMatrix™ memory for demanding, memory intensive
applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit)
multipliers for efficient implementation of high performance filters and
other DSP functions. Various high-speed external memory interfaces are
supported, including double data rate (DDR) SDRAM and DDR2
SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data
rate (SDR) SDRAM. Stratix II devices support various I/O standards
along with support for 1-gigabit per second (Gbps) source synchronous
signaling with DPA circuitry. Stratix II devices offer a complete clock
management solution with internal clock frequency of up to 550 MHz
and up to 12 phase-locked loops (PLLs). Stratix II devices are also the
industry’s first FPGAs with the ability to decrypt a configuration
bitstream using the Advanced Encryption Standard (AES) algorithm to
protect designs.
The Stratix II family offers the following features:
15,600 to 179,400 equivalent LEs; see Table 1–1
New and innovative adaptive logic module (ALM), the basic
building block of the Stratix II architecture, maximizes performance
and resource usage efficiency
Up to 9,383,040 RAM bits (1,172,880 bytes) available without
reducing logic resources
TriMatrix memory consisting of three RAM block sizes to implement
true dual-port memory and first-in first-out (FIFO) buffers
High-speed DSP blocks provide dedicated implementation of
multipliers (at up to 450 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
Up to 16 global clocks with 24 clocking resources per device region
Clock control blocks support dynamic clock network enable/disable,
which allows clock networks to power down to reduce power
consumption in user mode
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
provide spread spectrum, programmable bandwidth, clock switch-
over, real-time PLL reconfiguration, and advanced multiplication
and phase shifting
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Features
Support for numerous single-ended and differential I/O standards
High-speed differential I/O support with DPA circuitry for 1-Gbps
performance
Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
Support for high-speed external memory, including DDR and DDR2
SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
Support for multiple intellectual property megafunctions from
Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
Support for design security using configuration bitstream
encryption
Support for remote configuration updates
Table 1–1. Stratix II FPGA Family Features
Feature
ALMs
Adaptive look-up tables (ALUTs) (1)
Equivalent LEs (2)
M512 RAM blocks
M4K RAM blocks
M-RAM blocks
Total RAM bits
DSP blocks
18-bit × 18-bit multipliers (3)
Enhanced PLLs
Fast PLLs
Maximum user I/O pins
EP2S15
6,240
12,480
15,600
104
78
0
419,328
12
48
2
4
366
EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
13,552 24,176 36,384 53,016 71,760
27,104 48,352 72,768 106,032 143,520
33,880 60,440 90,960 132,540 179,400
202 329 488 699 930
144 255 408 609 768
12469
1,369,728 2,544,192 4,520,488 6,747,840 9,383,040
16 36 48 63 96
64 144 192 252 384
24444
48888
500
718
902
1,126
1,170
Notes to Table 1–1:
(1) One ALM contains two ALUTs. The ALUT is the cell used in the Quartus® II software for logic synthesis.
(2) This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture).
(3) These multipliers are implemented using the DSP blocks.
1–2
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Introduction
Stratix II devices are available in space-saving FineLine BGA® packages
(see Tables 1–2 and 1–3).
Table 1–2. Stratix II Package Options & I/O Pin Counts Notes (1), (2)
Device
484-Pin
FineLine BGA
EP2S15
EP2S30
EP2S60 (3)
EP2S90 (3)
EP2S130 (3)
EP2S180 (3)
342
342
334
484-Pin
Hybrid
FineLine
BGA
308
672-Pin
FineLine
BGA
366
500
492
780-Pin
FineLine
BGA
1,020-Pin
1,508-Pin
FineLine BGA FineLine BGA
718
534 758
902
534 742 1,126
742 1,170
Notes to Table 1–2:
(1) All I/O pin counts include eight dedicated clock input pins (clk1p, clk1n, clk3p, clk3n, clk9p, clk9n,
clk11p, and clk11n) that can be used for data inputs.
(2) The Quartus II software I/O pin counts include one additional pin, PLL_ENA, which is not available as general-
purpose I/O pins. The PLL_ENA pin can only be used to enable the PLLs within the device.
(3) The I/O pin counts for the EP2S60, EP2S90, EP2S130, and EP2S180 devices in the 1020-pin and 1508-pin packages
include eight dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n, FPLL9CLKp/n, and
FPLL10CLKp/n) that can be used for data inputs.
Table 1–3. Stratix II FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm2)
Length × width
(mm × mm)
484 Pin
1.00
529
23 × 23
484-Pin
Hybrid
1.00
729
27 × 27
672 Pin
1.00
729
27 × 27
780 Pin
1.00
841
29 × 29
1,020 Pin
1.00
1,089
33 × 33
1,508 Pin
1.00
1,600
40 × 40
All Stratix II devices support vertical migration within the same package
(for example, you can migrate between the EP2S15, EP2S30, and EP2S60
devices in the 672-pin FineLine BGA package). Vertical migration means
that you can migrate to devices whose dedicated pins, configuration pins,
and power pins are the same for a given package across device densities.
To ensure that a board layout supports migratable densities within one
package offering, enable the applicable vertical migration path within the
Quartus II software (Assignments menu > Device > Migration Devices).
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Features
After compilation, check the information messages for a full list of I/O,
DQ, LVDS, and other pins that are not available because of the selected
migration path.
Table 1–4 lists the Stratix II device package offerings and shows the total
number of non-migratable user I/O pins when migrating from one
density device to a larger density device. Additional I/O pins may not be
migratable if migrating from the larger device to the smaller density
device.
1 When moving from one density to a larger density, the larger
density device may have fewer user I/O pins. The larger device
requires more power and ground pins to support the additional
logic within the device. Use the Quartus II Pin Planner to
determine which user I/O pins are migratable between the two
devices.
Table 1–4. Total Number of Non-Migratable I/O Pins for Stratix II Vertical Migration Paths
Vertical Migration
Path
EP2S15 to EP2S30
EP2S15 to EP2S60
EP2S30 to EP2S60
EP2S60 to EP2S90
EP2S60 to EP2S130
EP2S60 to EP2S180
EP2S90 to EP2S130
EP2S90 to EP2S180
EP2S130 to EP2S180
484-Pin
FineLine BGA
0 (1)
8 (1)
8 (1)
672-Pin
FineLine BGA
0
0
8
780-Pin
FineLine BGA
0 (1)
1020-Pin
FineLine BGA
0
0
0
16
16
0
1508-Pin
FineLine BGA
17
0
0
Note to Table 1–4:
(1) Some of the DQ/DQS pins are not migratable. Refer to the Quartus II software information messages for more
detailed information.
f
1 To determine if your user I/O assignments are correct, run the
I/O Assignment Analysis command in the Quartus II software
(Processing > Start > Start I/O Assignment Analysis).
Refer to the I/O Management chapter in volume 2 of the Quartus II
Handbook for more information on pin migration.
1–4
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Introduction
Stratix II devices are available in up to three speed grades, -3, -4, and -5,
with -3 being the fastest. Table 1–5 shows Stratix II device speed-grade
offerings.
Table 1–5. Stratix II Device Speed Grades
Device
Temperature
Grade
484-Pin
FineLine
BGA
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
-3, -4, -5
-4
-3, -4, -5
-4
-3, -4, -5
-4
484-Pin
Hybrid
FineLine
BGA
-4, -5
672-Pin
FineLine
BGA
-3, -4, -5
-4
-3, -4, -5
-4
-3, -4, -5
-4
780-Pin
FineLine
BGA
1,020-Pin
FineLine
BGA
1,508-Pin
FineLine
BGA
-4, -5
-4, -5
-3, -4, -5
-4
-3, -4, -5
-4
-3, -4, -5
-4
-3, -4, -5
-4
-3, -4, -5
-4
-3, -4, -5
-4
-3, -4, -5
-4
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Document Revision History
Document
Table 1–6 shows the revision history for this chapter.
Revision History
Table 1–6. Document Revision History
Date and
Document
Version
Changes Made
May 2007, v4.2 Moved Document Revision History to the end of the
chapter.
April 2006, v4.1 Updated “Features” section.
Removed Note 4 from Table 1–2.
Updated Table 1–4.
December 2005, Updated Tables 1–2, 1–4, and 1–5.
v4.0 Updated Figure 2–43.
July 2005, v3.1
Added vertical migration information, including
Table 1–4.
Updated Table 1–5.
May 2005, v3.0 Updated “Features” section.
Updated Table 1–2.
March 2005,
v2.1
Updated “Introduction” and “Features” sections.
January 2005, Added note to Table 1–2.
v2.0
October 2004, Updated Tables 1–2, 1–3, and 1–5.
v1.2
July 2004, v1.1 Updated Tables 1–1 and 1–2.
Updated “Features” section.
February 2004, Added document to the Stratix II Device Handbook.
v1.0
Summary of Changes
1–6
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2. Stratix II Architecture
SII51002-4.3
Functional
Description
Stratix® II devices contain a two-dimensional row- and column-based
architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provides signal interconnects
between logic array blocks (LABs), memory block structures (M512 RAM,
M4K RAM, and M-RAM blocks), and digital signal processing (DSP)
blocks.
Each LAB consists of eight adaptive logic modules (ALMs). An ALM is
the Stratix II device family’s basic building block of logic providing
efficient implementation of user logic functions. LABs are grouped into
rows and columns across the device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus
parity (576 bits). These blocks provide dedicated simple dual-port or
single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks are
grouped into columns across the device in between certain LABs.
M4K RAM blocks are true dual-port memory blocks with 4K bits plus
parity (4,608 bits). These blocks provide dedicated true dual-port, simple
dual-port, or single-port memory up to 36-bits wide at up to 550 MHz.
These blocks are grouped into columns across the device in between
certain LABs.
M-RAM blocks are true dual-port memory blocks with 512K bits plus
parity (589,824 bits). These blocks provide dedicated true dual-port,
simple dual-port, or single-port memory up to 144-bits wide at up to
420 MHz. Several M-RAM blocks are located individually in the device's
logic array.
DSP blocks can implement up to either eight full-precision 9 × 9-bit
multipliers, four full-precision 18 × 18-bit multipliers, or one
full-precision 36 × 36-bit multiplier with add or subtract features. The
DSP blocks support Q1.15 format rounding and saturation in the
multiplier and accumulator stages. These blocks also contain shift
registers for digital signal processing applications, including finite
impulse response (FIR) and infinite impulse response (IIR) filters. DSP
blocks are grouped into columns across the device and operate at up to
450 MHz.
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Functional Description
Each Stratix II device I/O pin is fed by an I/O element (IOE) located at
the end of LAB rows and columns around the periphery of the device.
I/O pins support numerous single-ended and differential I/O standards.
Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with
dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR and DDR2
SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial
interface channels with dynamic phase alignment (DPA) support data
transfer at up to 1 Gbps using LVDS or HyperTransportTM technology I/O
standards.
Figure 2–1 shows an overview of the Stratix II device.
Figure 2–1. Stratix II Block Diagram
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
IOEs Support DDR, PCI, PCI-X,
SSTL-3, SSTL-2, HSTL-1, HSTL-2,
LVDS, HyperTransport & other
I/O Standards
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
M-RAM Block
LABs
LABs
LABs
LABs
LABs
LABs
DSP
Block
2–2
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Stratix II Architecture
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks. Table 2–1 lists
the resources available in Stratix II devices.
Table 2–1. Stratix II Device Resources
Device
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
M512 RAM
Columns/Blocks
4 / 104
6 / 202
7 / 329
8 / 488
9 / 699
11 / 930
M4K RAM
Columns/Blocks
3 / 78
4 / 144
5 / 255
6 / 408
7 / 609
8 / 768
M-RAM
Blocks
0
1
2
4
6
9
DSP Block
Columns/Blocks
2 / 12
2 / 16
3 / 36
3 / 48
3 / 63
4 / 96
LAB
Columns
LAB Rows
30 26
49 36
62 51
71 68
81 87
100 96
Logic Array
Blocks
Each LAB consists of eight ALMs, carry chains, shared arithmetic chains,
LAB control signals, local interconnect, and register chain connection
lines. The local interconnect transfers signals between ALMs in the same
LAB. Register chain connections transfer the output of an ALM register to
the adjacent ALM register in an LAB. The Quartus® II Compiler places
associated logic in an LAB or adjacent LABs, allowing the use of local,
shared arithmetic chain, and register chain connections for performance
and area efficiency. Figure 2–2 shows the Stratix II LAB structure.
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Logic Array Blocks
Figure 2–2. Stratix II LAB Structure
Row Interconnects of
Variable Speed & Length
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
ALMs
Direct link
interconnect from
adjacent block
Local Interconnect LAB
Direct link
interconnect to
adjacent block
Local Interconnect is Driven
from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive ALMs in the same LAB. It is driven
by column and row interconnects and ALM outputs in the same LAB.
Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM
blocks, or DSP blocks from the left and right can also drive an LAB's local
interconnect through the direct link connection. The direct link
connection feature minimizes the use of row and column interconnects,
providing higher performance and flexibility. Each ALM can drive
24 ALMs through fast local and direct link interconnects. Figure 2–3
shows the direct link connection.
2–4
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Figure 2–3. Direct Link Connection
Direct link interconnect from
left LAB, TriMatrix memory
block, DSP block, or IOE output
Stratix II Architecture
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
ALMs
Direct link
interconnect
to left
Local
Interconnect
Direct link
interconnect
to right
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs.
The control signals include three clocks, three clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load, and
synchronous load control signals. This gives a maximum of 11 control
signals at a time. Although synchronous load and clear signals are
generally used when implementing counters, they can also be used with
other functions.
Each LAB can use three clocks and three clock enable signals. However,
there can only be up to two unique clocks per LAB, as shown in the LAB
control signal generation circuit in Figure 2–4. Each LAB's clock and clock
enable signals are linked. For example, any ALM in a particular LAB
using the labclk1 signal also uses labclkena1. If the LAB uses both
the rising and falling edges of a clock, it also uses two LAB-wide clock
signals. De-asserting the clock enable signal turns off the corresponding
LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. By default, the Quartus II software uses a NOT gate
push-back technique to achieve preset. If you disable the NOT gate
push-up option or assign a given register to power up high using the
Quartus II software, the preset is achieved using the asynchronous load
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Adaptive Logic Modules
signal with asynchronous load data input tied high. When the
asynchronous load/preset signal is used, the labclkena0 signal is no
longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrackTM interconnect's inherent low
skew allows clock and control signal distribution in addition to data.
Figure 2–4 shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
Dedicated Row LAB Clocks
There are two unique
clock signals per LAB.
6
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk1
labclk2
syncload
labclkena0
or asyncload
or labpreset
labclkena1
labclkena2
labclr0
labclr1
synclr
Adaptive Logic
Modules
The basic building block of logic in the Stratix II architecture, the adaptive
logic module (ALM), provides advanced features with efficient logic
utilization. Each ALM contains a variety of look-up table (LUT)-based
resources that can be divided between two adaptive LUTs (ALUTs). With
up to eight inputs to the two ALUTs, one ALM can implement various
combinations of two functions. This adaptability allows the ALM to be
2–6
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Stratix II Architecture
completely backward-compatible with four-input LUT architectures. One
ALM can also implement any function of up to six inputs and certain
seven-input functions.
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a
shared arithmetic chain, and a register chain. Through these dedicated
resources, the ALM can efficiently implement various arithmetic
functions and shift registers. Each ALM drives all types of interconnects:
local, row, column, carry chain, shared arithmetic chain, register chain,
and direct link interconnects. Figure 2–5 shows a high-level block
diagram of the Stratix II ALM while Figure 2–6 shows a detailed view of
all the connections in the ALM.
Figure 2–5. High-Level Block Diagram of the Stratix II ALM
carry_in
shared_arith_in
reg_chain_in
dataf0
datae0
dataa
datab
datac
datad
datae1
dataf1
Combinational
Logic
adder0
adder1
DQ
reg0
DQ
reg1
carry_out
shared_arith_out
reg_chain_out
To general or
local routing
To general or
local routing
To general or
local routing
To general or
local routing
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Adaptive Logic Modules
Figure 2–6. Stratix II ALM Details
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Stratix II Architecture
f
One ALM contains two programmable registers. Each register has data,
clock, clock enable, synchronous and asynchronous clear, asynchronous
load data, and synchronous and asynchronous load/preset inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive
the register's clock and clear control signals. Either general-purpose I/O
pins or internal logic can drive the clock enable, preset, asynchronous
load, and asynchronous load data. The asynchronous load data input
comes from the datae or dataf input of the ALM, which are the same
inputs that can be used for register packing. For combinational functions,
the register is bypassed and the output of the LUT drives directly to the
outputs of the ALM.
Each ALM has two sets of outputs that drive the local, row, and column
routing resources. The LUT, adder, or register output can drive these
output drivers independently (see Figure 2–6). For each set of output
drivers, two ALM outputs can drive column, row, or direct link routing
connections, and one of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output
while the register drives another output. This feature, called register
packing, improves device utilization because the device can use the
register and the combinational logic for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT
of the same ALM so that the register is packed with its own fan-out LUT.
This provides another mechanism for improved fitting. The ALM can also
drive out registered and unregistered versions of the LUT or adder
output.
See the Performance & Logic Efficiency Analysis of Stratix II Devices White
Paper for more information on the efficiencies of the Stratix II ALM and
comparisons with previous architectures.
ALM Operating Modes
The Stratix II ALM can operate in one of the following modes:
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Each mode uses ALM resources differently. In each mode, eleven
available inputs to the ALM--the eight data inputs from the LAB local
interconnect; carry-in from the previous ALM or LAB; the shared
arithmetic chain connection from the previous ALM or LAB; and the
register chain connection--are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset/load, synchronous clear,
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Adaptive Logic Modules
synchronous load, and clock enable control for the register. These LAB-
wide signals are available in all ALM modes. See the “LAB Control
Signals” section for more information on the LAB-wide control signals.
The Quartus II software and supported third-party synthesis tools, in
conjunction with parameterized functions such as library of
parameterized modules (LPM) functions, automatically choose the
appropriate mode for common functions such as counters, adders,
subtractors, and arithmetic functions. If required, you can also create
special-purpose functions that specify which ALM operating mode to use
for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinational functions. In this mode, up to eight data inputs from the
LAB local interconnect are inputs to the combinational logic. The normal
mode allows two functions to be implemented in one Stratix II ALM, or
an ALM to implement a single function of up to six inputs. The ALM can
support certain combinations of completely independent functions and
various combinations of functions which have common inputs.
Figure 2–7 shows the supported LUT combinations in normal mode.
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Figure 2–7. ALM in Normal Mode Note (1)
dataf0
datae0
datac
dataa
datab
datad
datae1
dataf1
4-Input
LUT
4-Input
LUT
combout0
dataf0
datae0
datac
dataa
datab
combout1
datad
datae1
dataf1
5-Input
LUT
combout0
5-Input
LUT
combout1
dataf0
datae0
datac
dataa
datab
datad
datae1
dataf1
dataf0
datae0
datac
dataa
datab
datad
datae1
dataf1
5-Input
LUT
3-Input
LUT
5-Input
LUT
combout0
combout1
dataf0
datae0
dataa
datab
datac
datad
combout0
dataf0
datae0
dataa
datab
datac
datad
4-Input
LUT
combout1
datae1
dataf1
6-Input
LUT
combout0
6-Input
LUT
combout0
6-Input
LUT
combout1
Note to Figure 2–7:
(1) Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of
functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc.
The normal mode provides complete backward compatibility with four-
input LUT architectures. Two independent functions of four inputs or less
can be implemented in one Stratix II ALM. In addition, a five-input
function and an independent three-input function can be implemented
without sharing inputs.
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For the packing of two five-input functions into one ALM, the functions
must have at least two common inputs. The common inputs are dataa
and datab. The combination of a four-input function with a five-input
function requires one common input (either dataa or datab).
In the case of implementing two six-input functions in one ALM, four
inputs must be shared and the combinational function must be the same.
For example, a 4 × 2 crossbar switch (two 4-to-1 multiplexers with
common inputs and unique select lines) can be implemented in one ALM,
as shown in Figure 2–8. The shared inputs are dataa, datab, datac, and
datad, while the unique select lines are datae0 and dataf0 for
function0, and datae1 and dataf1 for function1. This crossbar
switch consumes four LUTs in a four-input LUT-based architecture.
Figure 2–8. 4 × 2 Crossbar Switch Example
sel0[1..0]
inputa
inputb
inputc
inputd
4 × 2 Crossbar Switch
out0
out1
sel1[1..0]
Implementation in 1 ALM
dataf0
datae0
dataa
datab
datac
datad
Six-Input
LUT
(Function0)
datae1
dataf1
Six-Input
LUT
(Function1)
combout0
combout1
In a sparsely used device, functions that could be placed into one ALM
may be implemented in separate ALMs. The Quartus II Compiler spreads
a design out to achieve the best possible performance. As a device begins
to fill up, the Quartus II software automatically utilizes the full potential
of the Stratix II ALM. The Quartus II Compiler automatically searches for
functions of common inputs or completely independent functions to be
placed into one ALM and to make efficient use of the device resources. In
addition, you can manually control resource usage by setting location
assignments.
Any six-input function can be implemented utilizing inputs dataa,
datab, datac, datad, and either datae0 and dataf0 or datae1 and
dataf1. If datae0 and dataf0 are utilized, the output is driven to
register0, and/or register0 is bypassed and the data drives out to
the interconnect using the top set of output drivers (see Figure 2–9). If
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datae1 and dataf1 are utilized, the output drives to register1
and/or bypasses register1 and drives to the interconnect using the
bottom set of output drivers. The Quartus II Compiler automatically
selects the inputs to the LUT. Asynchronous load data for the register
comes from the datae or dataf input of the ALM. ALMs in normal
mode support register packing.
Figure 2–9. 6-Input Function in Normal Mode Notes (1), (2)
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
datae1
dataf1
(2)
These inputs are available for register packing.
DQ
reg0
DQ
reg1
To general or
local routing
To general or
local routing
To general or
local routing
Notes to Figure 2–9:
(1) If datae1 and dataf1 are used as inputs to the six-input function, then datae0
and dataf0 are available for register packing.
(2) The dataf1 input is available for register packing only if the six-input function is
un-registered.
Extended LUT Mode
The extended LUT mode is used to implement a specific set of
seven-input functions. The set must be a 2-to-1 multiplexer fed by two
arbitrary five-input functions sharing four inputs. Figure 2–10 shows the
template of supported seven-input functions utilizing extended LUT
mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in Figure 2–10 occur naturally
in designs. These functions often appear in designs as “if-else” statements
in Verilog HDL or VHDL code.
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Figure 2–10. Template for Supported Seven-Input Functions in Extended LUT Mode
datae0
datac
dataa
datab
datad
dataf0
datae1
5-Input
LUT
5-Input
LUT
combout0
DQ
reg0
To general or
local routing
To general or
local routing
dataf1
(1)
This input is available
for register packing.
Note to Figure 2–10:
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second
register, reg1, is not available.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An ALM in
arithmetic mode uses two sets of two four-input LUTs along with two
dedicated full adders. The dedicated adders allow the LUTs to be
available to perform pre-adder logic; therefore, each adder can add the
output of two four-input functions. The four LUTs share the dataa and
datab inputs. As shown in Figure 2–11, the carry-in signal feeds to
adder0, and the carry-out from adder0 feeds to carry-in of adder1. The
carry-out from adder1 drives to adder0 of the next ALM in the LAB.
ALMs in arithmetic mode can drive out registered and/or unregistered
versions of the adder outputs.
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Figure 2–11. ALM in Arithmetic Mode
carry_in
datae0
dataf0
datac
datab
dataa
datad
datae1
dataf1
4-Input
LUT
4-Input
LUT
4-Input
LUT
4-Input
LUT
adder0
DQ
reg0
adder1
DQ
reg1
carry_out
To general or
local routing
To general or
local routing
To general or
local routing
To general or
local routing
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder's carry output along with combinational logic outputs. In
this operation, the adder output is ignored. This usage of the adder with
the combinational logic output provides resource savings of up to 50% for
functions that can use this ability. An example of such functionality is a
conditional operation, such as the one shown in Figure 2–12. The
equation for this example is:
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If
‘X’ is less than ‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is
fed to an adder where it drives out to the LAB local interconnect. It then
feeds to the LAB-wide syncload signal. When asserted, syncload
selects the syncdata input. In this case, the data ‘Y’ drives the
syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the
syncload signal is de-asserted and ‘X’ drives the data port of the
registers.
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Adaptive Logic Modules
Figure 2–12. Conditional Operation Example
ALM 1
Adder output
is not used.
X[0]
Y[0]
syncdata
X[1]
Y[1]
Carry Chain
Comb &
Adder
Logic
X[0]
Comb &
Adder
Logic
syncload
X[1]
syncload
R[0]
DQ
reg0
R[1]
DQ
reg1
ALM 2
To general or
local routing
To general or
local routing
X[2] Comb &
Adder X[2]
Y[2] Logic
R[2]
DQ
To general or
local routing
syncload
reg0
Comb &
Adder
Logic
carry_out
To local routing &
then to LAB-wide
syncload
The arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, add/subtract control, synchronous clear,
synchronous load. The LAB local interconnect data inputs generate the
clock enable, counter enable, synchronous up/down and add/subtract
control signals. These control signals are good candidates for the inputs
that are shared between the four LUTs in the ALM. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. The Quartus II software automatically places any
registers that are not used by the counter into other LABs.
Carry Chain
The carry chain provides a fast carry function between the dedicated
adders in arithmetic or shared arithmetic mode. Carry chains can begin in
either the first ALM or the fifth ALM in an LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
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The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together
automatically. For enhanced fitting, a long carry chain runs vertically
allowing fast horizontal connections to TriMatrix memory and DSP
blocks. A carry chain can continue as far as a full column.
To avoid routing congestion in one small area of the device when a high
fan-in arithmetic function is implemented, the LAB can support carry
chains that only utilize either the top half or the bottom half of the LAB
before connecting to the next LAB. This leaves the other half of the ALMs
in the LAB available for implementing narrower fan-in functions in
normal mode. Carry chains that use the top four ALMs in the first LAB
carry into the top half of the ALMs in the next LAB within the column.
Carry chains that use the bottom four ALMs in the first LAB carry into the
bottom half of the ALMs in the next LAB within the column. Every other
column of LABs is top-half bypassable, while the other LAB columns are
bottom-half bypassable.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on carry chain interconnect.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In
this mode, the ALM is configured with four 4-input LUTs. Each LUT
either computes the sum of three inputs or the carry of three inputs. The
output of the carry computation is fed to the next adder (either to adder1
in the same ALM or to adder0 of the next ALM in the LAB) via a
dedicated connection called the shared arithmetic chain. This shared
arithmetic chain can significantly improve the performance of an adder
tree by reducing the number of summation stages required to implement
an adder tree. Figure 2–13 shows the ALM in shared arithmetic mode.
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Figure 2–13. ALM in Shared Arithmetic Mode
shared_arith_in
carry_in
datae0
datac
datab
dataa
datad
datae1
4-Input
LUT
4-Input
LUT
4-Input
LUT
4-Input
LUT
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
carry_out
shared_arith_out
Note to Figure 2–13:
(1) Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Adder trees can be found in many different applications. For example, the
summation of the partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology.
An example of a three-bit add operation utilizing the shared arithmetic
mode is shown in Figure 2–14. The partial sum (S[2..0]) and the
partial carry (C[2..0]) is obtained using the LUTs, while the result
(R[2..0]) is computed using the dedicated adders.
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Figure 2–14. Example of a 3-bit Add Utilizing Shared Arithmetic Mode
shared_arith_in = '0'
3-Bit Add Example
1st stage add is
implemented in LUTs.
2nd stage add is
implemented in adders.
X2 X1 X0
Y2 Y1 Y0
+ Z2 Z1 Z0
S2 S1 S0
+ C2 C1 C0
R3 R2 R1 R0
ALM Implementation
ALM 1
3-Input
LUT
S0
X0
Y0
3-Input C0
Z0 LUT
carry_in = '0'
R0
Binary Add
110
101
+010
001
+1 1 0
1101
Decimal
Equivalents
6
5
+2
1
+ 2x6
13
X1 3-Input S1
Y1 LUT
Z1
3-Input C1
LUT
ALM 2
3-Input S2
LUT
X2 3-Input C2
Y2
Z2 LUT
R1
R2
3-Input '0'
LUT
3-Input
LUT
R3
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Shared Arithmetic Chain
In addition to the dedicated carry chain routing, the shared arithmetic
chain available in shared arithmetic mode allows the ALM to implement
a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
The shared arithmetic chains can begin in either the first or fifth ALM in
an LAB. The Quartus II Compiler creates shared arithmetic chains longer
than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking
LABs together automatically. For enhanced fitting, a long shared
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arithmetic chain runs vertically allowing fast horizontal connections to
TriMatrix memory and DSP blocks. A shared arithmetic chain can
continue as far as a full column.
Similar to the carry chains, the shared arithmetic chains are also top- or
bottom-half bypassable. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in a LAB while leaving the
other half available for narrower fan-in functionality. Every other LAB
column is top-half bypassable, while the other LAB columns are bottom-
half bypassable.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on shared arithmetic chain interconnect.
Register Chain
In addition to the general routing outputs, the ALMs in an LAB have
register chain outputs. The register chain routing allows registers in the
same LAB to be cascaded together. The register chain interconnect allows
an LAB to use LUTs for a single combinational function and the registers
to be used for an unrelated shift register implementation. These resources
speed up connections between ALMs while saving local interconnect
resources (see Figure 2–15). The Quartus II Compiler automatically takes
advantage of these resources to improve utilization and performance.
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Figure 2–15. Register Chain within an LAB Note (1)
Combinational
Logic
adder0
adder1
reg_chain_in
From Previous ALM
Within The LAB
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
Combinational
Logic
adder0
adder1
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
reg_chain_out
To Next ALM
within the LAB
Note to Figure 2–15:
(1) The combinational or adder logic can be utilized to implement an unrelated, un-registered function.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on register chain interconnect.
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MultiTrack Interconnect
MultiTrack
Interconnect
Clear & Preset Logic Control
LAB-wide signals control the logic for the register's clear and load/preset
signals. The ALM directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a NOT-
gate push-back technique. Stratix II devices support simultaneous
asynchronous load/preset, and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each
LAB supports up to two clears and one load/preset signal.
In addition to the clear and load/preset ports, Stratix II devices provide a
device-wide reset pin (DEV_CLRn) that resets all registers in the device.
An option set before compilation in the Quartus II software controls this
pin. This device-wide reset overrides all other control signals.
In the Stratix II architecture, connections between ALMs, TriMatrix
memory, DSP blocks, and device I/O pins are provided by the MultiTrack
interconnect structure with DirectDriveTM technology. The MultiTrack
interconnect consists of continuous, performance-optimized routing lines
of different lengths and speeds used for inter- and intra-design block
connectivity. The Quartus II Compiler automatically places critical design
paths on faster interconnects to improve design performance.
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
in the device. The MultiTrack interconnect and DirectDrive technology
simplify the integration stage of block-based designing by eliminating the
re-optimization cycles that typically follow design changes and
additions.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and repeatable performance when
migrating through different device densities. Dedicated row
interconnects route signals to and from LABs, DSP blocks, and TriMatrix
memory in the same row. These row resources include:
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
R24 row interconnects for high-speed access across the length of the
device
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