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CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES

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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
D 80-mHigh-Side MOSFET Switch
D 500 mA Continuous Current Per Channel
D Independent Thermal and Short-Circuit
Protection With Overcurrent Logic Output
D Operating Range . . . 2.7 V to 5.5 V
D CMOS- and TTL-Compatible Enable Inputs
D 2.5-ms Typical Rise Time
D Undervoltage Lockout
D 10 µA Maximum Standby Supply Current
for Single and Dual (20 µA for Triple and
Quad)
D Bidirectional Switch
D Ambient Temperature Range, 0°C to 85°C
D ESD Protection
D UL Listed – File No. E169910
description
TPS2041A, TPS2051A
D PACKAGE
(TOP VIEW)
GND
IN
IN
EN
1
2
3
4
8 OUT
7 OUT
6 OUT
5 OC
TPS2042A, TPS2052A
D PACKAGE
(TOP VIEW)
GND
IN
EN1
EN2
1
2
3
4
8 OC1
7 OUT1
6 OUT2
5 OC2
TPS2043A, TPS2053A
D PACKAGE
(TOP VIEW)
TPS2044A, TPS2054A
D PACKAGE
(TOP VIEW)
GNDA
IN1
EN1
EN2
GNDB
IN2
EN3
NC
1
2
3
4
5
6
7
8
16 OC1
15 OUT1
14 OUT2
13 OC2
12 OC3
11 OUT3
10 NC
9 NC
GNDA
IN1
EN1
EN2
GNDB
IN2
EN3
EN4
1
2
3
4
5
6
7
8
16 OC1
15 OUT1
14 OUT2
13 OC2
12 OC3
11 OUT3
10 OUT4
9 OC4
The TPS2041A through TPS2044A and
TPS2051A through TPS2054A power-distribution
switches are intended for applications where
All enable inputs are active high for the TPS205xA series.
NC – No connect
heavy capacitive loads and short circuits are likely to be encountered. These devices incorporate 80-m
N-channel MOSFET high-side power switches for power-distribution systems that require multiple power
switches in a single package. Each switch is controlled by an independent logic enable input. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, these devices limit the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from
a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present. These power-distribution switches are designed to current limit
at 0.9 A.
33 m, single TPS201xA 0.2 A – 2 A
TPS202x 0.2 A – 2 A
TPS203x 0.2 A – 2 A
80 m, dual
GENERAL SWITCH CATALOG
TPS2042
TPS2052
TPS2046
TPS2056
500 mA
500 mA
250 mA
250 mA
80 m, dual
80 m, triple
80 m, quad
80 m, quad
80 m, single
TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055
600 mA
1A
500 mA
500 mA
250 mA
250 mA
260 m
TPS2100/1
TPS2080 500 mA
IN1 500 mA TPS2081 500 mA TPS2043 500 mA
IN1
IN2
1.3
IN2 10 mA
OUT
TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
TPS2082
TPS2090
TPS2091
TPS2092
500 mA
250 mA
250 mA
250 mA
TPS2053
TPS2047
TPS2057
500 mA
250 mA
250 mA
TPS2044
TPS2054
TPS2048
TPS2058
500 mA
500 mA
250 mA
250 mA
TPS2085
TPS2086
TPS2087
TPS2095
500 mA
500 mA
500 mA
250 mA
TPS2096 250 mA
TPS2097 250 mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2000, Texas Instruments Incorporated
1


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CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES

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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
AVAILABLE OPTIONS
TA
ENABLE
RECOMMENDED
MAXIMUM CONTINUOUS
LOAD CURRENT
(A)
TYPICAL SHORT-CIRCUIT
CURRENT LIMIT AT 25°C
(A)
NUMBER OF
SWITCHES
Active low
Active high
Single
0°C to 85°C
Active low
Active high
Active low
Active high
0.5
Dual
0.9
Triple
Active low
Active high
The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2041ADR)
Quad
PACKAGED DEVICES
SOIC
(D)†
TPS2041AD
TPS2051AD
TPS2042AD
TPS2052AD
TPS2043AD
TPS2053AD
TPS2044AD
TPS2054AD
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES

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functional block diagrams
TPS2041A
IN
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
Power Switch
CS
OUT
Charge
Pump
EN‡
UVLO
Driver
Current
Limit
OC
GND
Thermal
Sense
TPS2042A
Current sense
Active high for TPS205xA series
OC1
GND
EN1‡
Charge
Pump
UVLO
IN
Charge
Pump
EN2‡
Thermal
Sense
Driver
Current
Limit
CS
Power Switch
CS
Driver
Current
Limit
Thermal
Sense
OUT1
OUT2
OC2
Current sense
Active high for TPS205xA series
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
functional block diagrams
TPS2043A
GNDA
EN1‡
Charge
Pump
UVLO
IN1
Charge
Pump
EN2‡
Thermal
Sense
Driver
Current
Limit
CS
Power Switch
CS
Driver
Current
Limit
Thermal
Sense
IN2
EN3‡
Power Switch
Charge
Pump
Driver
UVLO
GNDB
Current sense
Active high for TPS205xA series
Thermal
Sense
CS
Current
Limit
OC1
OUT1
OUT2
OC2
OUT3
OC3
4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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functional block diagrams
TPS2044A
GNDA
EN1‡
Charge
Pump
UVLO
IN1
Charge
Pump
EN2‡
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
Thermal
Sense
Driver
Current
Limit
CS
Power Switch
CS
Driver
Current
Limit
Thermal
Sense
OC1
OUT
1
OUT
2
OC2
GNDB
EN3‡
Charge
Pump
UVLO
IN2
Charge
Pump
EN4‡
Current sense
Active high for TPS205xA series
Thermal
Sense
Driver
Current
Limit
CS
Power Switch
CS
Driver
Current
Limit
Thermal
Sense
OC3
OUT3
OUT4
OC4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
Terminal Functions
TPS2041A and TPS2051A
TERMINAL
NO. I/O
NAME
TPS2041A TPS2051A
DESCRIPTION
EN 4
– I Enable input. Logic low turns on power switch.
EN –
4 I Enable input. Logic high turns on power switch.
GND
1
1 I Ground
IN 2, 3 2, 3 I Input voltage
OC 5
5 O Overcurrent. Logic output active low
OUT
6, 7, 8
6, 7, 8
O Power-switch output
TPS2042A and TPS2052A
TERMINAL
NO. I/O
NAME
TPS2042A TPS2052A
DESCRIPTION
EN1 3
– I Enable input. Logic low turns on power switch, IN-OUT1.
EN2 4
– I Enable input. Logic low turns on power switch, IN-OUT2.
EN1 –
3 I Enable input. Logic high turns on power switch, IN-OUT1.
EN2 –
4 I Enable input. Logic high turns on power switch, IN-OUT2.
GND
1
1 I Ground
IN 2 2 I Input voltage
OC1
8
8 O Overcurrent. Logic output active low, for power switch, IN-OUT1
OC2
5
5 O Overcurrent. Logic output active low, for power switch, IN-OUT2
OUT1
7
7 O Power-switch output
OUT2
6
6 O Power-switch output
6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
Terminal Functions (Continued)
TPS2043A and TPS2053A
TERMINAL
NO. I/O
NAME
TPS2043A TPS2053A
DESCRIPTION
EN1 3
– I Enable input, logic low turns on power switch, IN1-OUT1.
EN2 4
– I Enable input, logic low turns on power switch, IN1-OUT2.
EN3 7
– I Enable input, logic low turns on power switch, IN2-OUT3.
EN1 –
3 I Enable input, logic high turns on power switch, IN1-OUT1.
EN2 –
4 I Enable input, logic high turns on power switch, IN1-OUT2.
EN3 –
7 I Enable input, logic high turns on power switch, IN2-OUT3.
GNDA
1
1
Ground for IN1 switch and circuitry.
GNDB
5
5
Ground for IN2 switch and circuitry.
IN1 2
2 I Input voltage
IN2 6
6 I Input voltage
NC
8, 9, 10
8, 9, 10
No connection
OC1
16
16 O Overcurrent, logic output active low, IN1-OUT1
OC2
13
13 O Overcurrent, logic output active low, IN1-OUT2
OC3
12
12 O Overcurrent, logic output active low, IN2-OUT3
OUT1
15
15 O Power-switch output, IN1-OUT1
OUT2
14
14 O Power-switch output, IN1-OUT2
OUT3
11
11 O Power-switch output, IN2-OUT3
TPS2044A and TPS2054A
TERMINAL
NO. I/O
NAME
TPS2044A TPS2054A
DESCRIPTION
EN1 3
– I Enable input. logic low turns on power switch, IN1-OUT1.
EN2 4
– I Enable input. Logic low turns on power switch, IN1-OUT2.
EN3 7
– I Enable input. Logic low turns on power switch, IN2-OUT3.
EN4 8
– I Enable input. Logic low turns on power switch, IN2-OUT4.
EN1 –
3 I Enable input. Logic high turns on power switch, IN1-OUT1.
EN2 –
4 I Enable input. Logic high turns on power switch, IN1-OUT2.
EN3 –
7 I Enable input. Logic high turns on power switch, IN2-OUT3.
EN4 –
8 I Enable input. Logic high turns on power switch, IN2-OUT4.
GNDA
1
1
Ground for IN1 switch and circuitry.
GNDB
5
5
Ground for IN2 switch and circuitry.
IN1 2
2 I Input voltage
IN2 6
6 I Input voltage
OC1
16
16 O Overcurrent. Logic output active low, IN1-OUT1
OC2
13
13 O Overcurrent. Logic output active low, IN1-OUT2
OC3
12
12 O Overcurrent. Logic output active low, IN2-OUT3
OC4
9
9 O Overcurrent. Logic output active low, IN2-OUT4
OUT1
15
15 O Power-switch output, IN1-OUT1
OUT2
14
14 O Power-switch output, IN1-OUT2
OUT3
11
11 O Power-switch output, IN2-OUT3
OUT4
10
10 O Power-switch output, IN2-OUT4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 m(VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled. The power switch supplies a minimum of 500 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (ENx, ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 10 µA on the single and dual devices (20 µA on
the triple and quad devices) when a logic high is present on ENx (TPS204xA) or a logic low is present on ENx
(TPS205xA). A logic zero input on ENx or a logic high on ENx restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant-current mode and holds the current constant
while varying the voltage on the load.
thermal sense
The TPS204xA and TPS205xA implement a dual-threshold thermal trip to allow fully independent operation of
the power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled
approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is
removed. The (OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
Product series designations TPS204x and TPS205x refer to devices presented in this data sheet and not necessarily to other TI devices
numbered in this sequence.
8 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range, VI(IN) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Output voltage range, VO(OUT) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VI(IN) + 0.3 V
Input voltage range, VI(ENx) or VI(ENx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Continuous output current, IO(OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C . . . . . . . . . . . . . . . . . . . . . 2 kV
Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 kV
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
PACKAGE
D–8
D–16
DISSIPATION RATING TABLE
TA 25°C
POWER RATING
725 mW
DERATING FACTOR
ABOVE TA = 25°C
5.9 mW/°C
TA = 70°C
TA = 85°C
POWER RATING POWER RATING
464 mW
377 mW
1123 mW
9 mW/°C
719 mW
584 mW
recommended operating conditions
Input voltage, VI(IN)
Input voltage, VI(EN) or VI(EN)
Continuous output current, IO(OUT) (per switch)
Operating virtual junction temperature, TJ
MIN MAX UNIT
2.7 5.5 V
0 5.5 V
0 500 mA
0 125 °C
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(EN) = 0 V, VI(EN) = VI(IN) (unless otherwise noted)
power switch
PARAMETER
TEST CONDITIONS†
TPS204xA
MIN TYP MAX
TPS205xA
UNIT
MIN TYP MAX
VI(IN) = 5 V,
IO = 0.5 A
TJ = 25°C,
80 100
80 100
Static drain-source on-state
resistance, 5-V operation
VI(IN) = 5 V,
IO = 0.5 A
TJ = 85°C,
90 120
90 120
rDS(on)
VI(IN) = 5 V,
IO = 0.5 A
VI(IN) = 3.3 V,
IO = 0.5 A
TJ = 125°C,
TJ = 25°C,
100 135
90 125
100 135 m
90 125
Static drain-source on-state
resistance, 3.3-V operation
VI(IN) = 3.3 V,
IO = 0.5 A
TJ = 85°C,
110 145
110 145
VI(IN) = 3.3 V,
IO = 0.5 A
TJ = 125°C,
120 160
120 160
tr Rise time, output
VI(IN) = 5.5 V,
CL = 1 µF,
VI(IN) = 2.7 V,
CL = 1 µF,
TJ = 25°C,
RL=10
TJ = 25°C,
RL=10
2.5
3
2.5
ms
3
tf Fall time, output
VI(IN) = 5.5 V,
CL = 1 µF,
VI(IN) = 2.7 V,
CL = 1 µF,
TJ = 25°C,
RL=10
TJ = 25°C,
RL=10
4.4
2.5
4.4
ms
2.5
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input ENx or ENx
PARAMETER
VIH High-level input voltage
VIL Low-level input voltage
II Input current
ton Turnon time
toff Turnoff time
TPS204xA
TPS205xA
TEST CONDITIONS
2.7 V VI(IN) 5.5 V
4.5 V VI(IN) 5.5 V
2.7 VVI(IN) 4.5 V
VI(ENx) = 0 V or VI(ENx) = VI(IN)
VI(ENx) = VI(IN) or VI(ENx) = 0 V
CL = 100 µF, RL=10
CL = 100 µF, RL=10
TPS204xA
MIN TYP MAX
2
0.8
0.4
–0.5 0.5
20
40
TPS205xA
MIN TYP MAX
2
0.8
0.4
–0.5 0.5
20
40
UNIT
V
V
µA
ms
current limit
PARAMETER
TEST CONDITIONS†
TPS204xA
MIN TYP MAX
TPS205xA
UNIT
MIN TYP MAX
IOS Short-circuit output current
VI(IN) = 5 V, OUT connected to GND,
Device enabled into short circuit
0.7
1 1.3 0.7
1 1.3 A
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(EN) = 0 V, VI(EN) = VI(IN) (unless otherwise noted) (continued)
supply current (TPS2041A, TPS2051A)
PARAMETER
TEST CONDITIONS
Supply current, low-level No Load
output
on OUT
VI(EN) = VI(IN)
VI(EN) = 0 V
Supply current,
high-level output
No Load
on OUT
VI(EN) = 0 V
VI(EN) = VI(IN)
Leakage current
OUT
connected
to ground
VI(EN) = VI(IN)
VI(EN)= 0 V
Reverse leakage current
IN = High
impedance
VI(EN) = 0 V
VI(EN) = VI(IN)
supply current (TPS2042A, TPS2052A)
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
–40°C TJ 125°C
–40°C TJ 125°C
TJ = 25°C
PARAMETER
TEST CONDITIONS
Supply current, low-level No Load
output
on OUT
VI(ENx) = VI(IN)
VI(ENx) = 0 V
Supply current,
high-level output
No Load
on OUT
VI(ENx) = 0 V
VI(ENx) = VI(IN)
Leakage current
Reverse leakage current
OUT
connected
to ground
IN = high
impedance
VI(ENx) = VI(IN)
VI(ENx) = 0 V
VI(EN) = 0 V
VI(EN) = VI(IN)
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
–40°C TJ 125°C
–40°C TJ 125°C
TJ = 25°C
TPS2041A
MIN TYP MAX
0.025
1
10
85 110
100
100
0.3
TPS2042A
MIN TYP MAX
0.025
1
10
85 110
100
100
0.3
TPS2051A
UNIT
MIN TYP MAX
0.025
µA
1
10
µA
85 110
100
µA
100
µA
0.3
TPS2052A
UNIT
MIN TYP MAX
0.025
µA
1
10
µA
85 110
100
µA
100
µA
0.3
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(EN) = 0 V, VI(EN) = VI(IN) (unless otherwise noted) (continued)
supply current (TPS2043A, TPS2053A)
PARAMETER
TEST CONDITIONS
Supply current,
low-level output
Supply current,
high-level output
Leakage current
Reverse leakage
current
No Load
on OUTx
No Load
on OUTx
OUTx connected
to ground
IN = high
impedance
VI(ENx) = VI(INx)
VI(ENx) = 0 V
VI(ENx) = 0 V
VI(ENx) = VI(INx)
VI(ENx) = VI(INx)
VI(ENx) = 0 V
VI(ENx) = 0 V
VI(ENx) = VI(IN)
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
–40°C TJ 125°C
–40°C TJ 125°C
TJ = 25°C
supply current (TPS2044A, TPS2054A)
PARA-
METER
Supply current,
low-level output
No Load
on OUTx
Supply current,
high-level output
No Load
on OUTx
Leakage current
Reverse leakage
current
OUTx connected
to ground
IN = high
impedance
undervoltage lockout
TEST CONDITIONS
VI(ENx) = VI(INx)
VI(ENx) = 0 V
VI(ENx) = 0 V
VI(ENx) = VI(INx)
VI(ENx) = VI(INx)
VI(ENx) = 0 V
VI(EN) = 0 V
VI(EN) = VI(IN)
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
TJ = 25°C
–40°C TJ 125°C
–40°C TJ 125°C
–40°C TJ 125°C
TJ = 25°C
PARAMETER
TEST CONDITIONS
Low-level input voltage
Hysteresis
overcurrent OC
TJ = 25°C
PARAMETER
Sink current†
Output low voltage
Off-state current†
Specified by design, not production tested.
TEST CONDITIONS
VO = 5 V
IO = 5 V,
VO = 5 V,
VOL(OC)
VO = 3.3 V
TPS2043A
MIN TYP MAX
0.05 2
20
160 200
200
200
0.3
TPS2044A
MIN TYP MAX
0.05 2
20
170 220
200
200
0.3
TPS204xA
MIN TYP MAX
2 2.5
100
TPS204xA
MIN TYP MAX
10
0.5
1
TPS2053A
UNIT
MIN TYP MAX
µA
0.05 2
20
µA
160 200
200
µA
200
µA
0.3
TPS2054A
UNIT
MIN TYP MAX
µA
0.05 2
20
µA
170 220
200
µA
200
µA
0.3
TPS205xA
MIN TYP MAX
2 2.5
100
UNIT
V
mV
TPS205xA
MIN TYP MAX
10
0.5
1
UNIT
mA
V
µA
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
PARAMETER MEASUREMENT INFORMATION
OUT
RL CL
TEST CIRCUIT
tr
VO(OUT)
90% 90%
10%
10%
tf
VI(EN)
50%
ton
VO(OUT)
50%
90%
10%
toff
VI(EN)
50%
ton
VO(OUT)
50%
90%
10%
toff
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
VI(EN)
(5 V/div)
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
RL = 10
0 1 2 3 4 5 6 7 8 9 10
t – Time – ms
Figure 2. Turnon Delay and Rise Time
with 0.1-µF Load
VO(OUT)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
RL = 10
0 2 4 6 8 10 12 14 16 18 20
t – Time – ms
Figure 3. Turnoff Delay and Fall Time
with 0.1-µF Load
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TPS2052A (etcTI)
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
PARAMETER MEASUREMENT INFORMATION
VI(EN)
(5 V/div)
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 10
VO(OUT)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 10
0 1 2 3 4 5 6 7 8 9 10
t – Time – ms
0 2 4 6 8 10 12 14 16 18 20
t – Time – ms
Figure 4. Turnon Delay and Rise Time
with 1-µF Load
Figure 5. Turnoff Delay and Fall Time
with 1-µF Load
VI(EN)
(5 V/div)
VI(IN) = 5 V
TA = 25°C
VO(OUT)
(2 V/div)
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
0 1 2 3 4 5 6 7 8 9 10
t – Time – ms
Figure 6. TPS2051A, Short-Circuit Current,
Device Enabled into Short
IO(OUT)
(0.5 A/div)
0 10 20 30 40 50 60 70 80 90 100
t – Time – ms
Figure 7. TPS2051A, Threshold Trip Current
with Ramped Load on Enabled Device
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
PARAMETER MEASUREMENT INFORMATION
VO(OC)
(5 V/div)
VI(EN)
(5 V/div)
470 µF
220 µF
100 µF
IO(OUT)
(0.5 A/div)
VI(IN) = 5 V
TA = 25°C
Ramp = 1 A/100 ms
IO(OUT)
(0.2 A/div)
VI(IN) = 5 V
TA = 25°C
RL = 10
0 20 40 60 80 100 120 140 160 180 200
t – Time – ms
Figure 8. OC Response With Ramped Load
on Enabled Device
0 2 4 6 8 10 12 14 16 18 20
t – Time – ms
Figure 9. Inrush Current with 100-µF, 220-µF
and 470-µF Load Capacitance
VO(OC)
(5 V/div)
VI(IN) = 5 V
TA = 25°C
VO(OC)
(5 V/div)
VI(IN) = 5 V
TA = 25°C
IO(OUT)
(0.5 A/div)
IO(OUT)
(1 A/div)
0
1000
2000
3000
4000 5000
t – Time – µs
Figure 10. 4-Load Connected to Enabled Device
0
200 400 600 800 1000
t – Time – µs
Figure 11. 1-Load Connected
to Enabled Device
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TPS2052A (etcTI)
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
TYPICAL CHARACTERISTICS
TURNON DELAY TIME
vs
INPUT VOLTAGE
3.5
CL = 1 µF
RL = 10
3.2 TA = 25°C
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
12
CL = 1 µF
RL = 10
TA = 25°C
10
2.9
8
2.6
6
2.3
2
2.5 3
3.5 4 4.5 5
VI – Input Voltage – V
Figure 12
5.5 6
RISE TIME
vs
INPUT VOLTAGE
3
CL = 1 µF
RL = 10
TA = 25°C
2.7
2.4
2.1
1.8
2.5 3 3.5 4 4.5 5 5.5 6
VI – Input Voltage – V
Figure 14
4
2.5 3 3.5 4 4.5 5 5.5 6
VI – Input Voltage – V
Figure 13
FALL TIME
vs
INPUT VOLTAGE
2.2
CL = 1 µF
RL = 10
2.1 TA = 25°C
2
1.9
1.8
1.7
1.6
1.5
2.5 3 3.5 4 4.5 5 5.5 6
VI – Input Voltage – V
Figure 15
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
100
90
80
70
60
50
40
–40
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4.5 V
VI(IN) = 2.7 V
VI(IN) = 3.3 V
0 25 85
TJ – Junction Temperature – °C
Figure 16
125
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
160
140
VI(IN) = 5.5 V
120
VI(IN) = 5 V
100
VI(IN) = 4.5 V
80
VI(IN) = 3.3 V
60
VI(IN) = 2.7 V
40
20
0
–40
0 25 85
TJ – Junction Temperature – °C
Figure 17
125
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
160
IO = 0.5 A
140
VI(IN) = 2.7 V
VI(IN) = 3.3 V
120
VI(IN) = 3 V
100
80
VI(IN) = 5 V
60
VI(IN) = 4.5 V
40
20
0
0 25 85 125
TJ – Junction Temperature – °C
Figure 18
INPUT-TO-OUTPUT VOLTAGE
vs
LOAD CURRENT
70
TA = 25°C
60 VI(IN) = 2.7 V
VI(IN) = 4.5 V
50
VI(IN) = 3.3 V
40
30 VI(IN) = 5 V
20
10
0
100
200 300 400
IL – Load Current – A
Figure 19
500
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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TPS2052A (etcTI)
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES

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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
1.2
1.1
VI(IN) = 5.5 V
VI(IN) = 5 V
VI(IN) = 4.5 V
1
0.9
VI(IN) = 2.7 V
0.8
VI(IN) = 3.3 V
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
1.2
TA = 25°C
Load Ramp = 1 A/10 ms
1.16
1.12
1.08
0.7 1.04
0.6
–40
2.35
0 25 85
TJ – Junction Temperature – °C
Figure 20
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
125
2.3 Start Threshold
1
2.5 3 3.5 4 4.5 5 5.5 6
VI – Input Voltage – V
Figure 21
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
250
VI(IN) = 5 V
TA = 25°C
200
2.25
Stop Threshold
2.2
150
100
2.15
2.1
–40
0 25 85
TJ – Junction Temperature – °C
Figure 22
125
50
0
0 2.5 5 7.5 10 12.5
Peak Current – A
Figure 23
18 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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Power Supply
2.7 V to 5.5 V
TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
2,3
0.1 µF
5
4
TPS2041A
IN 6,7,8
OUT
OC
EN
GND
1
0.1 µF
22 µF
Load
Figure 24. Typical Application (Example, TPS2041A)
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.
overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do
not increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs
only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS204xA and TPS205xA sense the
short and immediately switch into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, very high currents may flow for a short time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS204xA and TPS205xA are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. The TPS204xA and
TPS205xA family of devices are designed to reduce false overcurrent reporting. An internal overcurrent
transient filter eliminates the need for external components to remove unwanted pulses. Using low-ESR
electrolytic capacitors on the output lowers the inrush current flow through the device during hot-plug events
by providing a low-impedance energy source, also reducing erroneous overcurrent reporting.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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TPS2052A (etcTI)
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TPS2041A
GND
IN
IN
EN
OUT
OUT
OUT
OC
V+
Rpullup
Figure 25. Typical Circuit for OC Pin (Example, TPS2041A)
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on)
of the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use
the highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the
power dissipation per switch can be calcultaed by:
+PD rDS(on) I2
Depending on which device is being used, multiply this number by the number of switches being used. This step
will render the total power dissipation from the N-channel MOSFETs.
Finally, calculate the junction temperature:
+ )TJ PD RqJA TA
Where:
TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W (for 8 pin), 111°C/W (for 16 pin)
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS204xA and TPS205xA into constant-current mode, which
causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across
the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high
levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built
into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back
on. The switch continues to cycle in this manner until the load fault or input power is removed.
The TPS204xA and TPS205xA implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach
160°C, both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or
overcurrent occurs.
20 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce
EMI and voltage overshoots.
universal serial bus (USB) applications
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
D Hosts/self-powered hubs (SPH)
D Bus-powered hubs (BPH)
D Low-power, bus-powered functions
D High-power, bus-powered functions
D Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS204xA and
TPS205xA can provide power-distribution solutions for many of these classes of devices.
host/self-powered and bus-powered hubs
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figures 26 and 27). This power supply must provide from 5.25 V to 4.75 V to the board
side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have
current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop
PCs, monitors, printers, and stand-alone hubs.
Power Supply
3.3 V
USB
Control
5V
2, 3
0.1 µF
TPS2041A
IN
OUT
7
5
OC
4 EN
GND
0.1 µF
120 µF
Downstream
USB Ports
D+
D–
VBUS
GND
Figure 26. Typical One-Port Solution
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
Power Supply
3.3 V
USB
Controller
5V
TPS2044A
2
IN1
6 IN2
15
OUT1
0.1 µF
14
OUT2
11
OC1
3 EN1
13
OC2
4
EN2
12 OC3
7 EN3
9
OC4
8
EN4
11
OUT3
10
OUT4
GNDA GNDB
15
+
33 µF
Downstream
USB Ports
D+
D–
VBUS
GND
+
33 µF
+
33 µF
D+
D–
VBUS
GND
D+
D–
VBUS
GND
+
33 µF
D+
D–
VBUS
GND
Figure 27. Typical Four-Port USB Host/Self-Powered Hub
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs
are required to power up with less than one unit load. The BPH usually has one embedded function, and power
is always available to the controller of the hub. If the embedded function and hub require more than 100 mA
on powerup, the power to the embedded function may need to be kept off until enumeration is completed. This
can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching
the embedded function is not necessary if the aggregate power draw for the function and controller is less than
one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
22 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
low-power bus-powered functions and high-power bus-powered functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and
can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of
44 and 10 µF at power up, the device must implement inrush current limiting (see Figure 28).
D+
D–
VBUS
GND
Power Supply
3.3 V
TPS2041A
10 µF
2,3
0.1 µF
IN
6, 7, 8
OUT
0.1 µF
10 µF
Internal
Function
USB
Control
5
OC
4 EN
GND
1
Figure 28. High-Power Bus-Powered Function (Example, TPS2041A)
USB power-distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
D Hosts/self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
D Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 and 10 µF)
D Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS204xA and TPS205xA allows them to meet each of these requirements. The
integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level
enable and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as
the input ports for bus-power functions (see Figures 29 through 32).
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TUSB2040
Hub Controller
Upstream
Port
D+
D–
GND
SN75240
AC
BD
DP0
DM0
TPS2041A
OC EN
5 V IN OUT
5 V Power
Supply
1 µF
TPS76333
0.1 µF
4.7 µF
GND
IN
3.3 V
GND
4.7 µF VCC
BUSPWR
GANGED
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
PWRON1
OVRCUR1
48-MHz
Crystal
Tuning
Circuit
XTAL1
PWRON2
OVRCUR2
XTAL2
OCSOFF
PWRON3
OVRCUR3
GND
PWRON4
OVRCUR4
Tie to TPS2041A EN Input
AC
BD
SN75240
AC
BD
SN75240
TPS2041A
EN IN
OC
OUT
TPS2041A
EN IN
OC
OUT
TPS2041A
EN IN
OC
OUT
TPS2041A
EN IN
OC
OUT
0.1 µF
0.1 µF
0.1 µF
0.1 µF
Downstream
Ports
Ferrite Beads
D+
D–
GND
5V
33 µF†
Ferrite Beads
D+
D–
GND
5V
33 µF†
Ferrite Beads
D+
D–
GND
5V
33 µF†
Ferrite Beads
D+
D–
GND
5V
USB rev 1.1 requires 120 µF per hub.
Figure 29. Hybrid Self/Bus-Powered Hub Implementation, TPS2041A
33 µF†
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TUSB2040
Hub Controller
Upstream
Port
D+
D–
GND
SN75240
AC
BD
DP0
DM0
TPS2041A
OC EN
5 V IN OUT
5 V Power
Supply
1 µF
TPS76333
0.1 µF
4.7 µF
GND
IN
3.3 V
GND
4.7 µF VCC
48-MHz
Crystal
Tuning
Circuit
XTAL1
XTAL2
OCSOFF
GND
BUSPWR
GANGED
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
Tie to TPS2042A EN Input
AC
BD
SN75240
AC
BD
SN75240
TPS2042A
EN1 OUT1
OC1 OUT2
EN2
OC2 IN
TPS2042A
EN1 OUT1
OC1 OUT2
EN2
OC2 IN
0.1 µF
0.1 µF
Downstream
Ports
Ferrite Beads
D+
D–
GND
5V
33 µF†
Ferrite Beads
D+
D–
GND
5V
33 µF†
Ferrite Beads
D+
D–
GND
5V
33 µF†
Ferrite Beads
D+
D–
GND
USB rev 1.1 requires 120 µF per hub.
Figure 30. Hybrid Self/Bus-Powered Hub Implementation, TPS2042A
5V
33 µF†
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TUSB2040
Hub Controller
Upstream
Port
D+
D–
GND
1/2 SN75240
AC
BD
DP0
DM0
TPS2041A
OC EN
5 V IN OUT
5 V Power
Supply
1 µF
TPS76333
0.1 µF
4.7 µF
GND
IN
3.3 V
GND
4.7 µF VCC
48-MHz
Crystal
XTAL1
BUSPWR
GANGED
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
Tie to TPS2043A EN Input
AC
BD
SN75240
AC
BD
1/2 SN75240
TPS2043A
EN1 OUT1
OC1 OUT2
EN2
OC2 IN1
0.1 µF
Tuning
Circuit
XTAL2
OCSOFF
GND
PWRON3
OVRCUR3
EN3 OUT3
OC3
IN2
GNDA
GNDB
0.1 µF
Downstream
Ports
Ferrite Beads
D+
D–
GND
5V
47 µF†
Ferrite Beads
D+
D–
GND
5V
47 µF†
Ferrite Beads
D+
D–
GND
5V
47 µF†
USB rev 1.1 requires 120 µF per hub.
Figure 31. Hybrid Self/Bus-Powered Hub Implementation, TPS2043A
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
TUSB2040
Hub Controller
Upstream
Port
D+
D–
GND
SN75240
AC
BD
DP0
DM0
TPS2041A
OC EN
5 V IN OUT
5 V Power
Supply
1 µF
0.1 µF
4.7 µF
GND
TPS76333
IN
3.3 V
GND
4.7 µF VCC
48-MHz
Crystal
XTAL1
BUSPWR
GANGED
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
Tie to TPS2041 EN Input
AC
BD
SN75240
AC
BD
SN75240
TPS2044A
EN1 OUT1
OC1 OUT2
EN2
OC2 IN1
0.1 µF
Downstream
Ports
Ferrite Beads
D+
D–
GND
5V
33 µF†
Ferrite Beads
D+
D–
GND
5V
33 µF†
Ferrite Beads
D+
D–
GND
Tuning
Circuit
XTAL2
OCSOFF
GND
PWRON3
OVRCUR3
PWRON4
OVRCUR4
EN3 OUT3
OC3 OUT4
EN4
OC4 IN2
GNDA
GNDB
0.1 µF
5V
33 µF†
Ferrite Beads
D+
D–
GND
5V
USB rev 1.1 requires 120 µF per hub.
Figure 32. Hybrid Self/Bus-Powered Hub Implementation, TPS2044A
33 µF†
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TPS2041A, TPS2042A, TPS2043A, TPS2044A
TPS2051A, TPS2052A, TPS2053A, TPS2054A
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS247 – SEPTEMBER 2000
APPLICATION INFORMATION
generic hot-plug applications (see Figure 33)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS204xA and TPS205xA, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS204xA and TPS205xA also ensures the switch will be off after the card has been removed, and the
switch will be off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for
every insertion of the card or module.
Power
Supply
2.7 V to 5.5 V
1000 µF
Optimum
PC Board
0.1 µF
TPS2041A
GND OUT
IN OUT
IN OUT
EN OC
Block of
Circuitry
Overcurrent Response
Figure 33. Typical Hot-Plug Implementation (Example, TPS2041A)
By placing the TPS204xA and TPS205xA between the VCC input and the rest of the circuitry, the input power
will reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing
a slow voltage ramp at the output of the device. This implementation controls system surge currents and
provides a hot-plugging mechanism for any device.
28 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
TPS2041AD
TPS2041ADR
TPS2041ADRG4
TPS2042AD
TPS2042ADR
TPS2043AD
TPS2043ADG4
TPS2044AD
TPS2044ADG4
TPS2044ADR
TPS2051AD
TPS2051ADR
TPS2052AD
TPS2052ADR
TPS2054AD
Status
(1)
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
Package Type Package Pins Package Eco Plan
Drawing Qty (2)
SOIC
D 8 75 Green (RoHS
& no Sb/Br)
SOIC
D 8 2500 Green (RoHS
& no Sb/Br)
SOIC
D 8 2500 Green (RoHS
& no Sb/Br)
SOIC
D 8 75 Green (RoHS
& no Sb/Br)
SOIC
D 8 2500 Green (RoHS
& no Sb/Br)
SOIC
D 16 40 Green (RoHS
& no Sb/Br)
SOIC
D 16 40 Green (RoHS
& no Sb/Br)
SOIC
D 16 40 Green (RoHS
& no Sb/Br)
SOIC
D 16 40 Green (RoHS
& no Sb/Br)
SOIC
D 16 2500 Green (RoHS
& no Sb/Br)
SOIC
D 8 75 Green (RoHS
& no Sb/Br)
SOIC
D 8 2500 Green (RoHS
& no Sb/Br)
SOIC
D 8 75 Green (RoHS
& no Sb/Br)
SOIC
D 8 2500 Green (RoHS
& no Sb/Br)
SOIC
D 16 40 Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
MSL Peak Temp Op Temp (°C)
(3)
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
Level-1-260C-UNLIM
0 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Device Marking
(4/5)
2041A
2041A
2041A
2042A
2042A
2043A
2043A
2044A
2044A
2044A
2051A
2051A
2052A
2052A
2054A
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2




TPS2052A.pdf
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