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TDC7201
SNAS686 – MAY 2016
TDC7201 Time-to-Digital Converter for Time-of-Flight Applications in LIDAR,
Range Finders, and ADAS
1 Features
1 Resolution: 55 ps
• Standard Deviation: 35 ps
• Measurement Range:
– Individual Mode 1: 12 ns to 2000 ns
– Individual Mode 2: 250 ns to 8 ms
– Combined Operation: 0.25 ns to 8 ms
• Low Active Power Consumption: 2.7 mA
• Supports up to 10 STOP Signals
• Autonomous Multi-Cycle Averaging Mode for Low
Power Consumption
• Supply Voltage: 2 V to 3.6 V
• Operating Temperature –40°C to +85°C
• SPI Interface for Register Access
2 Applications
• Range Finders
• LIDAR
• Drones and Robotics
• Advanced Driver Assistance Systems (ADAS)
• Collision Detection Systems
• Flow Meters
3 Description
The TDC7201 is designed for use with ultrasonic,
laser and radar range finding equipment using time-
of-flight technique. The TDC7201 has two built-in
Time-to-Digital Converters (TDCs) that can be used
to measure distance down to 4 cm and up to several
kilometers using a simple architecture, which
eliminates the need to use expensive FPGAs or
processors.
Each TDC performs the function of a stopwatch and
measures the elapsed time (time-of-flight or TOF)
between a START pulse and up to five STOP pulses.
The ability to measure simultaneously and individually
on two pairs of START and STOP pins using two
built-in TDCs offers high flexibility in time
measurement design.
The device has an internal self-calibrated time base
which compensates for drift over time and
temperature. Self-calibration enables time-to-digital
conversion accuracy in the order of picoseconds. This
accuracy makes the TDC7201 ideal for range finder
applications.
When placed in the Autonomous Multi-Cycle
Averaging Mode, the TDC7201 device can be
optimized for low system power consumption, which
is ideal for battery-powered flow meters. In this mode,
the host can go to sleep to save power and wake up
when interrupted by the TDC upon completion of the
measurement sequence.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TDC7201
nFBGA (25)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified LIDAR Application Block Diagram
Microcontroller
(MSP430)
Pulsed
Laser Diode
Transmission lens
2
CSBx
3
DI, DO, CLK
START1
STOP1
TDC7201
START2
STOP2
Detector
Photo
Diode
Receiving lens
Object
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements ................................................ 6
6.7 Switching Characteristics .......................................... 7
6.8 Typical Characteristics .............................................. 8
7 Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
7.5 Programming........................................................... 21
7.6 Register Maps ......................................................... 24
8 Application and Implementation ........................ 35
8.1 Application Information............................................ 35
8.2 Typical Application ................................................. 35
8.3 CLOCK Recommendations..................................... 38
9 Power Supply Recommendations...................... 40
10 Layout................................................................... 40
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 41
11 Device and Documentation Support ................. 42
11.1 Documentation Support ....................................... 42
11.2 Community Resources.......................................... 42
11.3 Trademarks ........................................................... 42
11.4 Electrostatic Discharge Caution ............................ 42
11.5 Glossary ................................................................ 42
12 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
DATE
May 2016
REVISION
*
NOTES
Initial release.
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5 Pin Configuration and Functions
ZAX Package
25-Pin nFBGA
Bottom View
1234
5
E
STOP2
GND2
DOUT2
VREG2
CSB2
TDC7201
SNAS686 – MAY 2016
D
START2
TRIGG2
INTB2
DNC
DIN
C
CLOCK
DNC
DNC
VDD2
DOUT1
B
STOP1
GND1
INTB1
VDD1
CSB1
A
START1
TRIGG1
ENABLE
VREG1
SCLK
Not to scale
Pin Functions
PIN
NO. NAME
TYPE
DESCRIPTION
A1
START1
Input
START signal for TDC1
A2
TRIGG1
Output Trigger output signal for TDC1
A3
ENABLE
Input
Enable signal to TDC
A4
VREG1
Output LDO output terminal for external decoupling cap
A5
SCLK
Input
SPI clock
B1
STOP1
Input
STOP signal for TDC1
B2
GND1
Ground Ground
B3
INTB1
Output Interrupt to MCU for TDC1, active low (open drain)
B4
VDD1
Power Supply input
B5
CSB1
Input
SPI chip select for TDC1, active low
C1
CLOCK
Input
Clock input to TDC
C2
DNC
— Do not connect
C3
DNC
— Do not connect
C4
VDD2
Power Supply input
C5
DOUT1
Output SPI data output for TDC1
D1
START2
Input
START signal for TDC2
D2
TRIGG2
Output Trigger output signal for TDC2
D3
INTB2
Output Interrupt to MCU for TDC2, active low (open drain)
D4
DNC
— Do not connect
D5
DIN
Input
SPI data input
E1
STOP2
Input
STOP signal for TDC2
E2
GND2
Ground Ground
E3
DOUT2
Output SPI data output for TDC2
E4
VREG2
Output LDO output terminal for external decoupling cap
E5
CSB2
Input
SPI chip select for TDC2, active low
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6 Specifications
6.1 Absolute Maximum Ratings
at TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted).(1)(2)(3)(4)(5)
MIN
VDD Supply voltage
Voltage on VREG1, VREG2 pins
VI Terminal input voltage on any other pin
–0.3
–0.3
–0.3
VDIFF_IN
VIN_GND_VDD
II
TA
Tstg
|Voltage differential| between any two input terminals
|Voltage differential| between any input terminal and GND or VDD
Input current at any pin
Ambient temperature
Storage temperature
–5
–40
–55
MAX
3.9
1.65
VDD + 0.3
3.9
3.9
5
125
150
UNIT
V
V
V
V
mA
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) All voltages are with respect to ground, unless otherwise specified.
(4) Pins VDD1 and VDD2 must be tied together at the board level and supplied from the same source.
(5) When the terminal input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > VDD), the current at that pin must not exceed
5 mA (source or sink), and the voltage (VI) at the pin must not exceed 3.9 V.
6.2 ESD Ratings
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
VALUE
±1000
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
At TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted).
MIN
VDD Supply voltage
VI Terminal voltage
VIH Voltage input high
VIL Voltage input low
FCALIB_CLK
Frequency (reference or calibration clock)
tCLOCK
Time period (reference or calibration clock)
DUTYCLOCK
Input clock duty cycle
TIMING REQUIREMENTS: Measurement Mode 1 (1)(2)(3)
2
0
0.7 × VDD
0
1 (1)
62.5
T1Min_STARTSTOP
Minimum time between start and stop signal
T1Max_STARTSTOP
Maximum time between start and stop signal
T1Min_STOPSTOP
Minimum time between 2 stop signals
T1Max_LASTSTOP
Maximum time between start and last stop signal
TIMING REQUIREMENTS: Measurement Mode 2(1)(2)(3)
12
67
T2Min_STARTSTOP
T2Max_STARTSTOP
T2Min_STOPSTOP
T2Max_LASTSTOP
Minimum time between start and stop signal
Maximum time between start and stop signal
Minimum time between 2 stop signals
Maximum time between start and last stop signal
2 × tCLOCK
2 × tCLOCK
(1) Specified by design.
(2) Applies to both pairs of START1, STOP1 and START2, STOP2 pins.
(3) Minimum time between 2 stop signals applies to 2 stop signals on the same TDC.
NOM
8
125
50%
MAX
3.6
VDD
3.6
0.3 × VDD
16
1000
UNIT
V
V
V
V
MHz
ns
2000
2000
ns
ns
ns
ns
(216-2) × tCLOCK
(216-2) × tCLOCK
s
s
s
s
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TDC7201
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Recommended Operating Conditions (continued)
At TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted).
MIN
TIMING REQUIREMENTS: ENABLE INPUT
TREN
Rise time for enable signal (20% to 80%)
TFEN
Fall time for enable signal (20% to 80%)
TIMING REQUIREMENTS: START1, STOP1, CLOCK, START2, STOP2
TRST, TFST
Maximum rise, fall time for START, STOP signals
(20% to 80%)
TRXCLK, TFXCLK
Maximum rise, fall time for external CLOCK
(20% to 80%)
TIMING REQUIREMENTS: TRIGG1, TRIGG2
TTRIG1START1
Time from TRIG1 to START1
TTRIG2START2
Time from TRIG2 to START2
TIMING REQUIREMENTS: Measurement Mode 1 Combined Operation(4)
5
5
T1STARTSTOP_Comb_Min
Minimum time between START and STOP signal
combined
TEMPERATURE
TA Ambient temperature
TJ Junction temperature
–40
–40
NOM
1 to 100
1 to 100
1
1
0.25
MAX UNIT
ns
ns
ns
ns
ns
ns
ns
85 °C
85 °C
(4) TDC7201 device in combined measurement mode where START1 and START2 are connected together:
(a) A common REFERENCE_START signal is applied to START1 and START2 at least 12 ns before occurrence of actual START and
STOP signals in Mode 1 (and at least 2 × tCLOCK before occurrence of actual Start and Stop signals in Mode 2).
(b) Start signal is connected to STOP1
(c) Stop signal is connected to STOP2
(d) Two time periods T1 (REFERENCE_START to Start) and T2 (REFERENCE_START to Stop) are measured and their difference (T2-
T1) is the time between Start to Stop
6.4 Thermal Information
THERMAL METRIC(1)
TDC7201
ZAX (nFBGA)
UNIT
25 PINS
RθJA
RθJC(top)
RθJB
ψJT
ψJB
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
155.1
109.5
114.1
20.8
110.6
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SNAS686 – MAY 2016
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6.5 Electrical Characteristics
TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TDC CHARACTERISTICS
LSB Resolution
Single shot measurement
TACC-2 Accuracy (Mode 2)(1)
CLOCK = 8 MHz, Jitter (RMS) < 1 ps,
Stability < 5 ppm
TSTD-2 Standard Deviation (Mode 2)
Measured time = 100 µs
Measured time = 1 µs
OUTPUT CHARACTERISTICS: TRIGG1, TRIGG2, INTB1, INTB2, DOUT1, DOUT2
VOH Output voltage high
Isource = –2 mA
VOL Output voltage low
Isink = 2 mA
INPUT CHARACTERISTICS: START1, STOP1, START2, STOP2, CSB1, CSB2
Cin Input capacitance(2)
INPUT CHARACTERISTICS: ENABLE, CLOCK, DIN, SCLK
Cin Input capacitance(2)
POWER CONSUMPTION(3) (see Measurement Mode 1 and Measurement Mode 2)
Ish Shutdown current
IQA Quiescent Current A
IQB Quiescent Current B
EN = LOW
EN = HIGH; TDC running
EN = HIGH; TDC OFF, Clock Counter
running
IQC Quiescent Current C
EN = HIGH; measurement stopped, SPI
communication only
IQD Quiescent Current D
EN = HIGH, TDC OFF, counter stopped,
no communication
MIN
2.31
(1) Accuracy is defined as the systematic error in the output signal; the error of the device excluding noise.
(2) Specified by design.
(3) Sum of TDC1 and TDC2 values
TYP
55
28
50
35
2.95
0.35
4
8
0.6
2.7
140
175
100
MAX UNIT
ps
ps
ps
ps
V
0.99 V
pF
pF
µA
mA
µA
µA
µA
6.6 Timing Requirements
TIMING REQUIREMENTS: START1, STOP1, START2, STOP2, CLOCK
PWSTART
Pulse width for Start Signal
PWSTOP
Pulse width for Stop Signal
SERIAL INTERFACE TIMING CHARACTERISTICS (VDD = 3.3 V, fSCLK = 25 MHz) (See Figure 1)
fSCLK
SCLK frequency
t1 SCLK period
SERIAL INTERFACE TIMING CHARACTERISTICS (VDD = 3.3 V, fSCLK = 20 MHz) (See Figure 1)
t1 SCLK period
t2 SCLK High Time
t3 SCLK Low Time
t4 DIN setup time
t5 DIN hold time
t6 CSB1 or CSB2 fall to SCLK rise
t7 Last SCLK rising edge to CSB1 or CSB2 rising edge
t8 Minimum pause time (CSB high)
t9 Clk fall to DOUT1 or DOUT2 bus transition
MIN NOM
10
10
40
50
16
16
5
5
6
6
40
MAX UNIT
ns
ns
25 MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
12 ns
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6.7 Switching Characteristics
TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
WAKE UP TIME
TWAKEUP_PERIOD
Time to be ready for
measurement
LSB within 0.3% of settled value
TDC7201
SNAS686 – MAY 2016
MIN TYP MAX UNIT
300 µs
CSBx Start Sequence
End Sequence
t6
t2
SCLK
t1
Data Latched On Rising Edge of SCLK
t7
1
23
45
6
78
9 10 11
12 13 14 15
16
t3
DIN
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
t4
t5
DOUTx
D7 D6 D5 D4 D3 D2 D1 D0
t9
DIN: SCLK rising edge
DOUTx: SCLK falling edge
Figure 1. SPI Register Access: 8 Bit Register Example
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6.8 Typical Characteristics
At TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V, CLOCK = 8 MHz, CALIBRATION2_PERIODS = 10,
AVG_CYCLES = 1 Measurement, NUM_STOP = Single STOP, Measurement Mode 2 (unless otherwise noted).
20.0002
20.00015
20.0001
20.00005
20
19.99995
19.9999
19.99985
19.9998
TOF TDC1 (us)
TOF TDC2 (us)
2 3.3
VDD (V)
20.0002
20.00015
TOF TDC1 (us)
TOF TDC2 (us)
20.0001
20.00005
20
19.99995
19.9999
19.99985
19.9998
3.6 -40 25
D001 Temperature (qC)
85
D002
250.1
250.05
250
249.95
249.9
249.85
249.8
Figure 2. Time-of-Flight (TOF) vs VDD
(Measurement Mode 2)
TOF TDC1 (ns)
TOF TDC2 (ns)
2
3.3
VDD (V)
3.6
D004
250.1
250.05
250
249.95
249.9
249.85
249.8
Figure 3. TOF vs Temperature
(Measurement Mode 2)
TOF TDC1 (ns)
TOF TDC2 (ns)
-40 25
85
Temperature (qC)
D005
0.522
0.52
0.518
0.516
0.514
0.512
Figure 4. TOF vs VDD
(Measurement Mode 1)
2 3.3 3.6
VDD (V)
D022
0.53
0.525
0.52
0.515
0.51
0.505
0.5
0.495
Figure 5. TOF vs Temperature
(Measurement Mode 1)
-40 25 85
Temperature (qC)
D023
Figure 6. TOF vs. VDD (Mode 1 Combined Operation)
Figure 7. TOF vs. Temperature (Mode 1 Combined
Operation)
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TDC7201
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Typical Characteristics (continued)
At TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V, CLOCK = 8 MHz, CALIBRATION2_PERIODS = 10,
AVG_CYCLES = 1 Measurement, NUM_STOP = Single STOP, Measurement Mode 2 (unless otherwise noted).
70 61
LSB TDC1 (ps)
LSB TDC1 (ps)
65
LSB TDC2 (ps)
60 LSB TDC2 (ps)
59
60
58
55 57
50 56
45 55
54
40
53
35 52
30
2
3.3
VDD (V)
3.6
D006
51
-40
25
Temperature (qC)
85
D007
1360
1350
1340
1330
1320
1310
1300
Figure 8. Resolution (LSB) vs VDD
IQA TDC1 (uA)
IQA TDC2 (uA)
2 3.3 3.6
VDD (V)
D008
1400
1380
Figure 9. Resolution (LSB) vs Temperature
IQA TDC1 (uA)
IQA TDC2 (uA)
1360
1340
1320
1300
1280
1260
-40
25
Temperature (qC)
85
D011
Figure 10. Operating Current (IQA) vs VDD
55
IQB TDC1 (uA)
IQB TDC2 (uA)
53
Figure 11. Operating Current (IQA) vs Temperature
60
IQB TDC1 (uA)
IQB TDC2 (uA)
57
51 54
49 51
47 48
45 45
2 3.3 3.6
-40 25 85
VDD (V)
D003
Temperature (°C)
D004
Figure 12. Operating Current (IQB) vs VDD
Figure 13. Operating Current (IQB) vs Temperature
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Typical Characteristics (continued)
At TA = 25°C , VDD1 = VDD2 = 3.3 V, GND1 = GND2 = 0 V, CLOCK = 8 MHz, CALIBRATION2_PERIODS = 10,
AVG_CYCLES = 1 Measurement, NUM_STOP = Single STOP, Measurement Mode 2 (unless otherwise noted).
70 70
IQC TDC1 (uA)
IQC TDC2 (uA)
65 65
60 60
55 55
50 50
IQC TDC1 (uA)
IQC TDC2 (uA)
45 45
2 3.3 3.6
-40 25 85
VDD (V)
D005
Temperature (°C)
D006
Figure 14. Operating Current (IQC) vs VDD
55
IQD TDC1 (uA)
IQD TDC2 (uA)
53
Figure 15. Operating Current (IQC) vs Temperature
70
IQD TDC1 (uA)
IQD TDC2 (uA)
65
51 60
49 55
47 50
45 45
2 3.3 3.6
VDD (V)
D007
-40 25
Temperature (°C)
85
D008
Figure 16. Operating Current (IQD) vs VDD
0.32
0.3
0.28
0.26
0.24
0.22
0.2
2
3.3
VDD (V)
ISH TDC1 (uA)
ISH TDC2 (uA)
3.6
D010
Figure 17. Operating Current (IQD) vs Temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1 ISH TDC1 (uA)
ISH TDC2 (uA)
0
-40 25 85
Temperature (°C)
D013
Figure 18. Shutdown Current (ISH) vs VDD
Figure 19. Shutdown Current (ISH) vs Temperature
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7 Detailed Description
TDC7201
SNAS686 – MAY 2016
7.1 Overview
The TDC7201 has two built-in TDCs with the capability to simultaneously and individually measure time delay on
two pairs of START and STOP pins. Each TDC is a stopwatch that measures time between a single event (edge
on START pin) and multiple subsequent events (edge on STOP pin). An event from a START pulse to a STOP
pulse is also known as time-of-flight, or TOF for short. The TDC has an internal time base that is used to
measure time with accuracy in the order of picoseconds. This accuracy makes the TDC7201 ideal for
applications such as drones and range finders, which require high accuracy in the picoseconds range.
NOTE
In rest of the documentation, we use TDCx to refer each TDC of the TDC7201, where x =
1, 2. Also, the prefix TDCx is used in register names to identify the TDC the register
belongs to. Further the associated START, STOP, TRIGG, CSB, DOUT, and INTB pins of
TDCx are represented as STARTx, STOPx, TRIGGx, CSBx, DOUTx, and INTBx.
7.2 Functional Block Diagram
VDD1 VDD2
VREG2
VREG1
TRIGG1
TRIGG2
START1
START2
STOP1
STOP2
CLOCK
LDO & Reference Subsystem
Schmitt
Triggered
Comparators
TDC1 Core
Ring
Osc
Coarse
Counter
TDC7201
Digital Core
Configuration Registers
Clock Counter & Decode
SPI
SLAVE
TDC2 Core
Ring
Osc
Coarse
Counter
Measurement Sequencer
Clock Counter & Decode
ENABLE
SCLK
CSB1
CSB2
DIN
DOUT1
DOUT2
INTB1
INTB2
NOTE
Do not tie together VREG1 and VREG2.
GND1 GND2
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7.3 Feature Description
7.3.1 LDO
The LDO (low-dropout) is an internal supply voltage regulator for the TDC7201. Each of the two TDC cores of
the TDC7201 has its own dedicated LDO. No external circuitry needs to be connected to the output of this
regulator other than the mandatory external decoupling capacitor on VREG1 and VREG2.
Recommendations for the decoupling capacitor parameters:
• Type: ceramic
• Capacitance: 0.4 µF to 2.7 µF (1 µF typical). If using a capacitor value outside the recommended range, the
part may malfunction and can be damaged.
• ESR: 100 mΩ (maximum)
7.3.2 CLOCK
The TDC7201 needs an external reference clock connected to the CLOCK pin. This external clock input serves
as the reference clock for both TDCs of the TDC7201. The external CLOCK is used to calibrate the internal time
base accurately and therefore, the measurement accuracy is heavily dependent on the external CLOCK
accuracy. This reference clock is also used by all digital circuits inside the device; thus, CLOCK has to be
available and stable at all times when the device is enabled (ENABLE = HIGH).
Figure 20 shows the typical effect of the external CLOCK frequency on the measurement uncertainty. With a
reference clock of 1 MHz, the standard deviation of a set of measurement results is approximately 243 ps. As the
reference clock frequency is increased, the standard deviation (or measurement uncertainty) reduces. Therefore,
using a reference clock of 16 MHz is recommended for optimal performance.
400
300
200
100
80
70
60
50
40
0 2 4 6 8 10 12 14 16 18
Clock Frequency (MHz)
D001
Figure 20. Standard Deviation vs CLOCK
7.3.3 Counters
7.3.3.1 Coarse and Clock Counters Description
Time measurements by each TDCx of the TDC7201 rely on two counters: the Coarse Counter and the Clock
Counter. The Coarse Counter counts the number of times the ring oscillator (the TDCx’s core time measurement
mechanism) wraps, which is used to generate the results in the TDCx_TIME1 to TDCx_TIME6 registers.
The Clock Counter counts the number of integer clock cycles between START and STOP events and is used in
Measurement Mode 2 only. The results for the Clock Counter are displayed in the TDCx_CLOCK_COUNT1 to
TDCx_CLOCK_COUNT5 registers.
7.3.3.2 Coarse and Clock Counters Overflow
Once the coarse counter value has reached the corresponding value of the Coarse Counter Overflow registers,
then its interrupt bit will be set to 1. In other words, if (TDCx_TIMEn / 63) COARSE_CNTR_OVF, then
COARSE_CNTR_OVF_INT = 1 (this interrupt bit is located in the TDCx_INT_STATUS register).
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Feature Description (continued)
TDCx_COARSE_CNTR_OVF = (TDCx_COARSE_CNTR_OVF_H x 28 + TDCx_COARSE_CNTR_OVF_L),
where TDCx_TIMEn refers to the TDCx_TIME1 to TDCx_TIME6 registers.
Similarly, once the clock counter value has reached the corresponding value of the Clock Counter Overflow
registers, then its interrupt bit will be set to 1. In other words, if TDCx_CLOCK_COUNTn >
TDCx_CLOCK_CNTR_OVF, then CLOCK_CNTR_OVF_INT = 1 (this interrupt bit is located in the INT_STATUS
register).
TDCx_CLOCK_CNTR_OVF = (TDCx_CLOCK_CNTR_OVF_H × 28 + TDCx_CLOCK_CNTR_OVF_L), where
TDCx_CLOCK_COUNTn refers to the TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5 registers.
As soon as there is an overflow detected, the running measurement will be terminated immediately.
7.3.3.3 Clock Counter STOP Mask
The values in the Clock Counter STOP Mask registers define the end of the mask window. The Clock Counter
STOP Mask value will be referred to as TDCx_CLOCK_CNTR_STOP_MASK =
(TDCx_CLOCK_CNTR_STOP_MASK_H x 28 + TDCx_CLOCK_CNTR_STOP_MASK_L).
The Clock Counter is started by the first rising edge of the external CLOCK after the START signal (see
Figure 23). All STOP signals occurring before the value set by the TDCx_CLOCK_CNTR_STOP_MASK registers
will be ignored. This feature can be used to help suppress wrong or unwanted STOP trigger signals.
For example, assume the following values:
• The first time-of-flight (TOF1), which is defined as the time measurement from the START to the 1st STOP =
19 μs.
• The second time-of-flight (TOF2), which is defined as the time measurement from the START to the 2nd
STOP = 119 μs.
• CLOCK = 8 MHz
In this example, the TDC7201 will provide a TDCx_CLOCK_COUNT1 of approximately 152 (19 μs / tCLOCK), and
TDCx_CLOCK_COUNT2 of approximately 952 (119 μs / tCLOCK). If the user sets
TDCx_CLOCK_CNTR_STOP_MASK anywhere between 152 and 952, then the 1st STOP will be ignored and 2nd
STOP will be measured.
The Clock Counter Overflow value (TDCx_CLOCK_CNTR_OVF_H × 28 + TDCx_CLOCK_CNTR_OVF_L) should
always be higher than the Clock Counter STOP Mask value (TDCx_CLOCK_CNTR_STOP_MASK_H × 28 +
TDCx_CLOCK_CNTR_STOP_MASK_L). Otherwise, the Clock Counter Overflow Interrupt will be set before the
STOP mask time expires, and the measurement will be halted.
7.3.3.4 ENABLE
The ENABLE pin is used as a reset to all digital circuits in the TDC7201. Therefore, it is essential that the
ENABLE pin sees a positive edge after the device has powered up. It is also important to ensure that there are
no transients (such as glitches) on the ENABLE pin; such glitches could cause the device to reset
7.4 Device Functional Modes
7.4.1 Calibration
The time measurements performed by each TDCx of the TDC7201 are based on an internal time base which is
represented as the LSB value of the TDCx_TIME1 to TDCx_TIME6 results registers. The typical LSB value can
be seen in Electrical Characteristics. However, the actual value of the LSB can vary depending on environmental
variables (temperature, systematic noise, and so forth). This variation can introduce significant error into the
measurement result. There is also an offset error in the measurement due to certain internal delays in the device.
In order to compensate for these errors and to calculate the actual LSB value, calibration needs to be performed.
The TDCx calibration consists of two measurement cycles of the external CLOCK. The first is a measurement of
a single clock cycle period of the external clock; the second measurement is for the number of external CLOCK
periods set by the CALIBRATION2_PERIODS in the TDCx_CONFIG2 register. The results from the calibration
measurements are stored in the TDCx_CALIBRATION1 and TDCx_CALIBRATION2 registers.
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Device Functional Modes (continued)
The two-point calibration is used to determine the actual LSB in real time in order to convert the TDCx_TIME1 to
TDCx_TIME6 results from number of delays to a real TOF number. Calibration is automatic and performed every
time after a measurement and before measurement completion interrupt is sent to the MCU through INTBx pin.
Only if a measurement is interrupted (for example, due to counter overflow or missing STOP signal), calibration
is not performed. As discussed in the next sections, the calibrations will be used for calculating TOF in
measurement modes 1 and 2.
7.4.2 Measurement Modes
7.4.2.1 Measurement Mode 1
In measurement mode 1, as shown in Figure 21, each TDCx of the TDC7201 performs the entire counting from
START to the last STOP using its internal ring oscillator plus coarse counter. This method is recommended for
measuring shorter time durations of < 2000 ns. TI does not recommend using measurement mode 1 for
measuring time > 2000 ns because this decreases accuracy of the measurement (as shown in Figure 22).
Input Clock
1-16 MHz
STARTx
STOPx
1st STOP 2nd STOP
3rd STOP
Ring oscillator running
IQD IQA
TOF1
TOF2
TOF3
Figure 21. Measurement Mode 1
500
400
300
200
IQD
100
70
50
40
30
20
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Measured Time (ns)
D002
Figure 22. Measurement Mode 1 Standard Deviation vs Measured Time-of-Flight
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Device Functional Modes (continued)
7.4.2.1.1 Calculating Time-of-Flight (Measurement Mode 1)
For measurement mode 1, the TOF between the START to the nth STOP can be calculated using Equation 1:
TOFn TIMEn normLSB
CLOCKperiod
normLSB
calCount
calCount CALIBRATION2 CALIBRATION1
CALIBRATION2 _ PERIODS 1
where
TOFn [sec] = time-of-flight measurement from the START to the nth STOP
TIMEn = nth TIME measurement given by the TIME1 to TIME6 registers
normLSB [sec] = normalized LSB value from calibration
CLOCKperiod [sec] = external CLOCK period
CALIBRATION1 = TDCx_CALIBRATION1 register value = TDC count for first calibration cycle
CALIBRATION2 = TDCx_CALIBRATION2 register value = TDC count for second calibration cycle
CALIBRATION2_PERIODS = setting for the second calibration cycle; located in register TDCx_CONFIG2
(1)
For example, assume the time-of-flight between the START to the 1st STOP is desired, and the following
readouts were obtained:
• TDCx_CALIBRATION2 = 21121 (decimal)
• TDCx_CALIBRATION1 = 2110 (decimal)
• CALIBRATION2_PERIODS = 10
• CLOCK = 8 MHz
• TDCx_TIME1 = 4175 (decimal)
Therefore, the calculation for time-of-flight is:
• calCount = (21121 – 2110) / (10 – 1) = 2112.33
• normLSB = (1/8MHz) / (2112.33) = 59.17 ps
• TOF1 = (4175)(5.917 x 10-11) = 247.061 ns
7.4.2.2 Measurement Mode 2
In measurement mode 2, the internal ring oscillator of each TDCx of the TDC7201 is used only to count fractional
parts of the total measured time. As shown in Figure 23, the internal ring oscillator starts counting from when it
receives the START signal until the first rising edge of the CLOCK. Then, the internal ring oscillator switches off,
and the Clock counter starts counting the clock cycles of the external CLOCK input until a STOP pulse is
received. The internal ring oscillator again starts counting from the STOP signal until the next rising edge of the
CLOCK.
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Device Functional Modes (continued)
Input Clock
1-16 MHz
STARTx
STOPx
1st STOP
2nd STOP
Clock Counter Running
Clock Counter Running
Ring
oscillator
running
IQD
IQA IQB
TOF1
CLOCK_COUNT1
TIME1
IQA
+ IQB
IQB
TOF2
CLOCK_COUNT2
TIME2
Figure 23. Measurement Mode 2
IQA
+ IQD
IQB
TIME3
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Device Functional Modes (continued)
7.4.2.2.1 Calculating Time-of-Flight (TOF) (Measurement Mode 2)
The TOF between the START to the nth STOP can be calculated using Equation 2:
TOFn normLSB TIME1 TIMEn 1 CLOCK _ COUNTn CLOCKperiod
CLOCKperiod
normLSB
calCount
calCount CALIBRATION2 CALIBRATION1
CALIBRATION2 _ PERIODS 1
where
• TOFn [sec] = time-of-flight measurement from the START to the nth STOP
• TIME1 = TDCx_TIME1 register value = time 1 measurement given by the TDC7201 register address 0x10
• TIME(n+1) = TDCx_TIME(n+1) register value = (n+1) time measurement, where n = 1 to 5 (TDCx_TIME2 to
TDCx_TIME6 registers)
• normLSB [sec] = normalized LSB value from calibration
• CLOCK_COUNTn = nth clock count, where n = 1 to 5 (TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5)
• CLOCKperiod [sec] = external CLOCK period
• CALIBRATION1 = TDCx_CALIBRATION1 register value = TDC count for first calibration cycle
• CALIBRATION2 = TDCx_CALIBRATION2 register value = TDC count for second calibration cycle
• CALIBRATION2_PERIODS = setting for the second calibration; located in register TDCx_CONFIG2
(2)
For example, assume the time-of-flight between the START to the 1st STOP is desired, and the following
readouts were obtained:
• CALIBRATION2 = 23133 (decimal)
• CALIBRATION1 = 2315 (decimal)
• CALIBRATION2_PERIODS = 10
• CLOCK = 8 MHz
• TIME1 = 2147 (decimal)
• TIME2 = 201 (decimal)
• CLOCK_COUNT1 = 318 (decimal)
Therefore, the calculation for time-of-flight is:
calCount CALIBRATION2 CALIBRATION1 (23133 2315) 2313.11
(CALIBRATION2 _ PERIODS) 1
(10 1)
normLSB (CLOCKperiod) (1/ 8MHz) 54 ps
(calCount)
2313.11
TOF1 (TIME1)(normLSB) (CLOCK _ COUNT1)(CLOCKperiod) (TIME2)(normLSB)
TOF1 2147 5.40 10 11 (318)(1/ 8MHz) (201)(5.40 10 11)
TOF1 39.855Ps
(3)
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Device Functional Modes (continued)
7.4.3 Timeout
For one STOP, each TDCx of the TDC7201 performs the measurement by counting from the START signal to
the STOP signal. If no STOP signal is received, either the Clock Counter or Coarse Counter will overflow and will
generate an interrupt (see Coarse and Clock Counters Overflow). If no START signal is received, the timer waits
indefinitely for a START signal to arrive.
For multiple STOPs, each TDCx performs the measurement by counting from the START signal to the last STOP
signal. All earlier STOP signals are captured and stored into the corresponding Measurement Results registers
(TDCx_TIME1 to TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1,
TDCx_CALIBRATION2). The minimum time required between two consecutive STOP signals is defined in the
Recommended Operating Conditions table. The device can be programmed to measure up to 5 STOP signals by
setting the NUM_STOP bits in the TDCx_CONFIG2 register.
7.4.4 Multi-Cycle Averaging
In the Multi-Cycle Averaging Mode, the TDC7201 will perform a series of measurements on its own and will only
send an interrupt to the MCU (for example, MSP430, C2000, and so forth) for wake up after the series has been
completed. While waiting, the MCU can remain in sleep mode during the whole cycle (as shown in Figure 24).
Multi-Cycle Averaging Mode Setup and Conditions:
• The number of averaging cycles should be selected (1 to 128). This is done by programming the
AVG_CYCLES bit in the TDCx_CONFIG2 register.
• The results of all measurements are reported in the Measurement Results registers (TDCx_TIME1 to
TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1,
TDCx_CALIBRATION2 registers). The CLOCK_COUNTn registers should be right shifted by the
log2(AVG_CYCLES) before calculating the TOF. For example, if using the multi-cycle averaging mode,
Equation 2 should be rewritten as: TOFn = normLSB [TDCx_TIME1 - TDCx_TIME(n+1)] +
[TDCx_CLOCK_COUNTn >> log 2 (AVG_CYCLES)] x [CLOCKperiod]
• Following each average cycle, the TDCx generates either a trigger event on the TRIGGx pin after the
calibration measurement to commence a new measurement or an interrupt on the INTBx pin, indicating that
the averaging sequence has completed.
This mode allows multiple measurements without MCU interaction, thus optimizing power consumption for the
overall system.
TRIGGx
STARTx
STOPx
CLOCK
Trigger from
TDC7201 to AFE
INTBx
MCU Configuration
AFE & TDC
Sleep Mode
Retrieving Data
& Processing
Figure 24. Multi-Cycle Averaging Mode Example with 2 Averaging Cycles and 5 STOP Signals
7.4.5 START and STOP Edge Polarity
In order to achieve the highest measurement accuracy, having the same edge polarity for the START and STOP
input signals is highly recommended. Otherwise, slightly different propagation delays due to symmetry shift
between the rising and falling edge configuration will impact the measurement accuracy.
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Device Functional Modes (continued)
For highest measurement accuracy in measurement mode 2, TI recommends to choose for the START and
STOP signal the rising edge. This is done by setting the START_EDGE and STOP_EDGE bits in the
TDCx_CONFIG1 register to 0.
7.4.6 Measurement Sequence
The TDC7201 has two built-in TDCs with the capability to simultaneously and individually measure time delay on
two pairs of START and STOP pins. Each TDCx is a stopwatch that measures time between a single event
(edge on STARTx pin) and multiple subsequent events (edge on STOPx pin). The measurement sequence for
each TDCx is as follows:
1. After powering up the device, the ENABLE pin needs to be low. There is one low to high transition required
while VDD is supplied for correct initialization of the device.
NOTE
Pins VDD1 and VDD2 must be tied together at the board level and supplied from the
same source.
2. MCU software requests new TDCx measurements to be initiated through the SPI™ interface.
3. After the start new measurement bit START_MEAS has been set in the TDCx_CONFIG1 register, the TDCx
generates a trigger signal on the TRIGGx pin, which is typically used by the corresponding ultrasonic analog-
front-end (such as the TDC1000) as start trigger for a measurement (for example, transmit signal for the
ultrasonic burst).
4. Immediately after sending the trigger, the TDCx enables the STARTx pin and waits to receive the START
pulse edge.
5. After receiving a START, the TDCx resets the TRIGGx pin.
6. The Clock counter is started after the next rising edge of the external clock signal (Measurement Mode 2).
The Clock Counter STOP Mask registers (TDCx_CLOCK_CNTR_STOP_MASK_H and
TDCx_CLOCK_CNTR_STOP_MASK_L) determine the length of the STOP mask window.
7. After reaching the Clock Counter STOP Mask value, the STOPx pin waits to receive a single or multiple
STOP trigger signal from the analog-front-end (for example, detected echo signal of the ultrasonic burst
signal).
8. After the last STOP trigger has been received, the TDCx will signal to the MCU through interrupt (INTBx pin)
that there are new measurement results waiting in the registers. STARTx, STOPx and TRIGGx pins are
disabled (in Multi-Cycle Averaging Mode, the TDCx will start the next cycle automatically by generating a
new TRIGG signal). INTBx goes back to high whenever a new measurement is initiated through SPI or when
the TDCx_INT_STATUS register bit NEW_MEAS_INT is cleared by writing a 1 to it.
NOTE
INTBx must be utilized to determine TDCx measurement completion; polling the
TDCx_INT_STATUS register to determine measurement completion is NOT
recommended as it will interfere with the TDCx measurement.
9. After the results are retrieved, the MCU can then start a new measurement with the same register settings.
This is done by just setting the START_MEAS bit through SPI. It is not required to drive the ENABLE pin low
between measurements.
10. The ENABLE pin can be taken low, if the time duration between measurements is long, and it is desired to
put the TDC7201 in its lowest power state. However, upon taking ENABLE high again, the device will come
up with its default register settings and will need to be configured through SPI.
The two TDCs of TDC7201 can be used independently to measure TOF. When used independently, the TDCx
operation is as explained in the measurement sequence steps above. In this case, each TDCx has dedicated
START, STOP inputs and measures their STARTx to STOPx time individually when the START_MEAS bit in the
TDCx_CONFIG1 register is set. The MCU has to set up, control, and read the results from the two TDCs
individually through the master SPI interface. To set up the registers and read back measurement results of
TDCx, MCU needs to perform SPI read and write transactions with corresponding CSBx asserted.
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Device Functional Modes (continued)
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NOTE
START1, STOP1 and START2, STOP2 inputs can be separate from different sources or
can be identical with START1 connected to START2 and STOP1 connected to STOP2. In
the latter case, when the TDCx inputs are connected together and the TDCx register
setup is identical, then both the TDCs measure the same input in parallel and this can be
used to achieve finer resolution. By measuring the same time with both TDCs and taking
the average, the LSB resolution is halved.
7.4.7 Wait Times for TDC7201 Startup
The required wait time following the rising edge of the ENABLE pin of the TDC7201 is defined by three key
times, as shown in Figure 25. All three times relate to the startup of the TDCx’s internal dedicated LDO, which is
power gated when the device is disabled for optimal power consumption. The first parameter, T1SPI_RDY, is the
time after which the SPI interface is accessible. The second (T2LDO_SET1) parameter and third (T3LDO_SET2)
parameter are related to the performance of a measurement made while the internal LDO is settling. The LDO
supplies the TDC7201’s time measurement device, and a change in voltage on its supply during a measurement
translates directly to an inaccuracy. It is therefore recommended to wait until the LDO is settled before time
measurement begins.
The first time period relating to the measurement accuracy is T2LDO_SET1, the LDO settling time 1. This is the time
after which the LDO has settled to within 0.3% of its final value. A 0.3% error translates to a worst case time
error (due to the LDO settling) of 0.3% × tCLOCK, which is 375 ps in the case of an 8-MHz reference clock, or
187.5 ps if a 16-MHz clock is used. Finally, the time T3LDO_SET2 is the time after which the LDO has settled to its
final value. For best performance, TI recommends that a time measurement is not started before T3LDO_SET2 to
allow the LDO to fully settle. Typical times for these parameters are: T1SPI_RDY is 100 µs, for T2LDO_SET1 is 300
µs, and for T3LDO_SET2 is 1.5 ms.
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Device Functional Modes (continued)
TDC7201
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ENABLE
VREGx
T3 LDO_SET2
T2 LDO_SET1
T1 SPI_RDY
Time
Figure 25. VREGx Startup Time
7.5 Programming
7.5.1 Serial Peripheral Interface (SPI)
The serial interface consists of data input (DIN), data output (DOUTx), serial interface clock (SCLK), and chip
select bar (CSBx). The serial interface is used to configure the TDC7201 parameters available in various
configuration registers.
The two TDCs of TDC7201 share the serial interface DIN and SCLK pins but support dedicated CSB and DOUT
pins. Registers of the TDCx are selected for read/write access when their corresponding dedicated CSBx pin is
asserted. By connecting together DOUT1 and DOUT2, a single SPI master interface of the MCU can be used to
access both the TDC register sets by asserting the corresponding CSBx. Alternatively, by keeping DOUT1 and
DOUT2 separate, data can be read out of the TDCs in parallel using their dedicated DOUTx pins. This doubles
the data readout throughput but requires a second dedicated SPI interface of the MCU.
The communication on the SPI bus supports write and read transactions. A write transaction consists of a single
write command byte, followed by single data byte. A read transaction consists of a single read command byte
followed by 8 or 24 SCLK cycles. The write and read command bytes consist of a 1-bit auto-increment bit, a 1-bit
read or write instruction, and a 6-bit register address. Figure 26 shows the SPI protocol for a transaction
involving one byte of data (read or write).
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Programming (continued)
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CSBx
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
COMMAND FIELD
DATA FIELD
DIN
c7 c6
Auto-
Increment
R/W
c5
DOUTx
R/W = Instruction
0: Read
1: Write
c4 c3 c2 c1
Address (6 bits)
MSB
c0 d7
d6 d5 d4 d3 d2
Write Data (8-bits)
MSB
d7 d6 d5 d4 d3 d2
Figure 26. SPI Protocol
Read Data (8-bits)
LSB
d1 d0
LSB
d1 d0
7.5.1.1 CSBx
CSBx is an active-low signal and needs to be low throughout a transaction. That is, CSBx should not pulse
between the command byte and the data byte of a single transaction.
De-asserting CSBx always terminates an ongoing transaction, even if it is not yet complete. Re-asserting CSBx
will always bring the device into a state ready for the next transaction, regardless of the termination status of a
previous transaction.
Registers of the TDCx are selected for read/write access when their corresponding dedicated CSBx pin is
asserted.
7.5.1.2 SCLK
SPI clock can idle high or low. TI recommends to keep SCLK as clean as possible to prevent glitches from
corrupting the SPI frame.
7.5.1.3 DIN
Data In (DIN) is driven by the SPI master by sending the command and the data byte to configure the TDC7201.
7.5.1.4 DOUTx
Data Out (DOUTx) is driven by the TDC7201 when the SPI master initiates a read transaction with CSBx
asserted. When the TDC7201 is not being read out, the DOUT pin is in high impedance mode and is undriven.
Registers of the TDCx are selected for read/write access when their corresponding dedicated CSBx pin is
asserted. By connecting together DOUT1 and DOUT2, a single SPI master interface of the MCU can be used to
access both the TDC register sets by asserting the corresponding CSBx. Alternatively, by keeping DOUT1 and
DOUT2 separate, data can be read out of the TDCs in parallel using their dedicated DOUTx pins. This doubles
the data readout throughput but requires a second dedicated SPI interface of the MCU.
7.5.1.5 Register Read/Write
Access to the TDCx internal registers can be done through the serial interface formed by pins CSBx (Chip Select
- active low), SCLK (serial interface clock), DIN (data input), and DOUTx (data out).
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TDC7201
SNAS686 – MAY 2016
Programming (continued)
Serial shift of bits into the TDCx is enabled when CSBx is low. Serial data DIN is latched (MSB received first,
LSB received last) at every rising edge of SCLK when CSBx is active (low). The serial data is loaded into the
register with the last data bit SCLK rising edge when CSBx is low. In the case that the word length exceeds the
register size, the excess bits are ignored. The interface can work with SCLK frequency from 25 MHz down to
very low speeds (a few Hertz) and even with a non-50% duty-cycle SCLK.
The SPI transaction is divided in two main portions:
• Address and Control as shown in Table 1: Auto Increment Mode selection bit, Read/Write bit, Address 6 bits
• Data: 8 bit or 24 bit
When writing to a register with unused bits, these should be set to 0.
A7
Auto
Increment
0: OFF
1: ON
A6
RW
Read = 0
Write = 1
Table 1. Address and Control Byte of SPI transaction
Address and Control (A7 - A0)
A5 A4 A3
A2
A1
Register Address
00 h up to 3Fh
A0
7.5.1.6 Auto Increment Mode
When the Auto Increment Mode is OFF, only the register indicated by the Register Address will be accessed, all
cycles beyond the register length will be ignored. When the Auto Increment is ON, the register of the Register
Address is accessed first, then without interruption, subsequent registers are accessed.
The Auto Increment Mode can be either used to access the configuration (TDCx_CONFIG1 and
TDCx_CONFIG2) and status (TDCx_INT_STATUS) registers, or for the Measurement Results registers
(TDCx_TIME1 to TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1,
TDCx_CALIBRATION2). As both register block use registers with different length, it is not possible to access all
registers of the device within one single access cycle.
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7.6 Register Maps
7.6.1 Register Initialization
After power up (VDD supplied, ENABLE Pin low to high transition) the internal registers are initialized with the
default value. Disabling the part by pulling ENABLE pin to GND will set the device into total shutdown. As the
internal LDO is turned off settings in the register will be lost. The device initializes the registers with default
values with the next enable (ENABLE pin to VDD).
Table 2. TDCx_ Register Summary(1)
REGISTER ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
SIZE (BITS)
00h TDCx_CONFIG1
Configuration Register 1
01h TDCx_CONFIG2
Configuration Register 2
02h TDCx_INT_STATUS
Interrupt Status Register
03h TDCx_INT_MASK
Interrupt Mask Register
04h
TDCx_COARSE_CNTR_OVF_H
Coarse Counter Overflow Value High
05h
TDCx_COARSE_CNTR_OVF_L
Coarse Counter Overflow Value Low
06h
TDCx_CLOCK_CNTR_OVF_H
CLOCK Counter Overflow Value High
07h
TDCx_CLOCK_CNTR_OVF_L
CLOCK Counter Overflow Value Low
08h TDCx_CLOCK_CNTR_STOP_MASK_H CLOCK Counter STOP Mask High
09h TDCx_CLOCK_CNTR_STOP_MASK_L CLOCK Counter STOP Mask Low
10h TDCx_TIME1
Measured Time 1
11h TDCx_CLOCK_COUNT1
CLOCK Counter Value
12h TDCx_TIME2
Measured Time 2
13h TDCx_CLOCK_COUNT2
CLOCK Counter Value
14h TDCx_TIME3
Measured Time 3
15h TDCx_CLOCK_COUNT3
CLOCK Counter Value
16h TDCx_TIME4
Measured Time 4
17h TDCx_CLOCK_COUNT4
CLOCK Counter Value
18h TDCx_TIME5
Measured Time 5
19h TDCx_CLOCK_COUNT5
CLOCK Counter Value
1Ah TDCx_TIME6
Measured Time 6
1Bh TDCx_CALIBRATION1
Calibration 1, 1 CLOCK Period
1Ch TDCx_CALIBRATION2
Calibration 2, 2/10/20/40 CLOCK Periods
8
8
8
8
8
8
8
8
8
8
24
24
24
24
24
24
24
24
24
24
24
24
24
(1) Registers of the TDCx are selected for read/write access when their corresponding dedicated CSBx pin is asserted.
RESET
VALUE
00h
40h
00h
07h
FFh
FFh
FFh
FFh
00h
00h
00_0000h
00_0000h
00_0000h
00_0000h
00_0000h
00_0000h
00_0000h
00_0000h
00_0000h
00_0000h
00_0000h
00_0000h
00_0000h
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TDC7201
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7.6.2 TDCx_CONFIG1: TDCx Configuration Register 1 R/W (address = 00h, CSBx asserted) [reset = 0h]
Figure 27. TDCx_CONFIG1 Register
7654
FORCE_CAL PARITY_EN TRIGG_EDGE STOP_EDGE
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
START_EDGE
R/W-0
21
MEAS_MODE
R/W-0
R/W-0
0
START_MEAS
R/W-0
Table 3. TDCx_CONFIG1 Register Field Descriptions
Bit Field
7 FORCE_CAL
6 PARITY_EN
5 TRIGG_EDGE
4 STOP_EDGE
3 START_EDGE
[2:1] MEAS_MODE
0 START_MEAS
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
b00
0
Description
0: Calibration is automatic and performed every time after a measurement.
Only if a measurement is interrupted (for example, due to counter overflow or
missing STOP signal), calibration is not performed.
1: Calibration is always performed at the end (for example, after a counter
overflow) even if a measurement is interrupted.
0: Parity bit for Measurement Result Registers* disabled (Parity Bit always 0)
1: Parity bit for Measurement Result Registers enabled (Even Parity)
*The Measurement Results registers are the TDCx_TIME1 to TDCx_TIME6,
TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1,
TDCx_CALIBRATION2 registers.
0: TRIGG is output as a Rising edge signal
1: TRIGG is output as a Falling edge signal
0: Measurement is stopped on Rising edge of STOP signal
1: Measurement is stopped on Falling edge of STOP signal
0: Measurement is started on Rising edge of START signal
1: Measurement is started on Falling edge of START signal
00: Measurement Mode 1 (for expected time-of-flight < 2000 ns).
01: Measurement Mode 2 (recommended)
10, 11: Reserved for future functionality
Start New Measurement:
This bit is cleared when Measurement is Completed.
0: No effect
1: Start New Measurement. Writing a 1 will clear all bits in the Interrupt Status
Register and Start the measurement (by generating a TRIGG signal) and will
reset the content of all Measurement Results registers (TDCx_TIME1 to
TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5,
TDCx_CALIBRATION1, TDCx_CALIBRATION2) to 0.
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7.6.3 TDCx_CONFIG2: TDCx Configuration Register 2 R/W (address = 01h, CSBx asserted) [reset = 40h]
Figure 28. TDCx_CONFIG2 Register
7654
CALIBRATION2_PERIODS
AVG_CYCLES
R/W-0
R/W-1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
R/W-0
2
R/W-0
1
NUM_STOP
R/W-0
0
R/W-0
Table 4. TDCx_CONFIG2 Register Field Descriptions
Bit Field
Type
[7:6] CALIBRATION2_PERIODS R/W
Reset
b01
[5:3] AVG_CYCLES
R/W b000
[2:0] NUM_STOP
R/W b000
Description
00: Calibration 2 - measuring 2 CLOCK periods
01: Calibration 2 - measuring 10 CLOCK periods
10: Calibration 2 - measuring 20 CLOCK periods
11: Calibration 2 - measuring 40 CLOCK periods
000: 1 Measurement Cycle only (no Multi-Cycle Averaging Mode)
001: 2 Measurement Cycles
010: 4 Measurement Cycles
011: 8 Measurement Cycles
100: 16 Measurement Cycles
101: 32 Measurement Cycles
110: 64 Measurement Cycles
111: 128 Measurement Cycles
000: Single Stop
001: Two Stops
010: Three Stops
011: Four Stops
100: Five Stops
101, 110, 111: No Effect. Single Stop
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TDC7201
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7.6.4 TDCx_INT_STATUS: Interrupt Status Register (address = 02h, CSBx asserted) [reset = 00h]
Figure 29. TDCx_INT_STATUS Register
765
4
3
Reserved
MEAS_
COMPLETE_
FLAG
MEAS_STARTED_
FLAG
R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
CLOCK_
CNTR_
OVF_INT
R/W-0
1
COARSE_CNTR_
OVF_INT
R/W-0
0
NEW_MEAS_
INT
R/W-0
Table 5. TDCx_INT_STATUS Register Field Descriptions
Bit
7-5
4
Field
Reserved
MEAS_COMPLETE_FLAG
3 MEAS_STARTED_FLAG
2 CLOCK_CNTR_OVF_INT
1 COARSE_CNTR_OVF_INT
0 NEW_MEAS_INT
Type
R/W
R/W
Reset
b000
0
R/W 0
R/W 0
R/W 0
R/W 0
Description
Writing a 1 will clear the status
0: Measurement has not completed
1: Measurement has completed
NEW_MEAS_INT)
(same
information
as
Writing a 1 will clear the status
0: Measurement has not started
1: Measurement has started (START signal received)
Requires writing a 1 to clear interrupt status
0: No overflow detected
1: Clock overflow detected, running measurement will be
stopped immediately
Requires writing a 1 to clear interrupt status
0: No overflow detected
1: Coarse overflow detected, running measurement will be
stopped immediately
Requires writing a 1 to clear interrupt status
0: Interrupt not detected
1: Interrupt detected – New Measurement has been completed
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7.6.5 TDCx_INT_MASK: TDCx Interrupt Mask Register R/W (address = 03h, CSBx asserted) [reset = 07h]
Figure 30. TDCx_INT_MASK Register
7654
Reserved
3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
CLOCK_CNTR
_OVF_MASK
R/W-1h
1
COARSE_CNTR
_OVF_MASK
R/W-1h
Table 6. TDCx_INT_MASK Register Field Descriptions
Bit
7-3
2
Field
Reserved
CLOCK_CNTR_OVF_MASK
1 COARSE_CNTR_OVF_MASK
0 NEW_MEAS_MASK
Type
R/W
R/W
R/W
R/W
Reset
b0'0000
1
1
1
Description
0: CLOCK Counter Overflow Interrupt disabled
1: CLOCK Counter Overflow Interrupt enabled
0: Coarse Counter Overflow Interrupt disabled
1: Coarse Counter Overflow Interrupt enabled
0: New Measurement Interrupt disabled
1: New Measurement Interrupt enabled
0
NEW_MEAS
_MASK
R/W-1h
A disabled interrupt will no longer be visible on the device pin (INTB). The interrupt bit in the
TDCx_INT_STATUS register will still be active.
7.6.6 TDCx_COARSE_CNTR_OVF_H: Coarse Counter Overflow High Value Register (address = 04h,
CSBx asserted) [reset = FFh]
Figure 31. TDCx_COARSE_CNTR_OVF_H Register
76543
COARSE_CNTR_OVF_H
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
R/W-1
1
R/W-1
0
R/W-1
Table 7. TDCx_COARSE_CNTR_OVF_H Register Field Descriptions
Bit Field
7-0 COARSE_CNTR_OVF_H
Type
R/W
Reset
FFh
Description
Coarse Counter Overflow Value, upper 8 Bit
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7.6.7 TDCx_COARSE_CNTR_OVF_L: TDCx Coarse Counter Overflow Low Value Register (address =
05h, CSBx asserted) [reset = FFh ]
Figure 32. TDCx_COARSE_CNTR_OVF_L Register
76543
COARSE_CNTR_OVF_L
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
R/W-1
1
R/W-1
Table 8. TDCx_COARSE_CNTR_OVF_L Register Field Descriptions
Bit Field
7-0 COARSE_CNTR_OVF_L
Type
R/W
Reset
FFh
Description
Coarse Counter Overflow Value, lower 8 Bit
Note: Do not set COARSE_CNTR_OVF_L to 1.
0
R/W-1
7.6.8 TDCx_CLOCK_CNTR_OVF_H: Clock Counter Overflow High Register (address = 06h, CSBx
asserted) [reset = FFh]
Figure 33. TDCx_CLOCK_CNTR_OVF_H Register
76543
CLOCK_CNTR_OVF_H
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
R/W-1
1
R/W-1
0
R/W-1
Table 9. TDCx_CLOCK_CNTR_OVF_H Register Field Descriptions
Bit Field
7-0 CLOCK_CNTR_OVF_H
Type
R/W
Reset
FFh
Description
CLOCK Counter Overflow Value, upper 8 Bit
7.6.9 TDCx_CLOCK_CNTR_OVF_L: Clock Counter Overflow Low Register (address = 07h, CSBx
asserted) [reset = FFh]
Figure 34. TDCx_CLOCK_CNTR_OVF_L Register
76543
CLOCK_CNTR_OVF_L
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
R/W-1
1
R/W-1
0
R/W-1
Table 10. TDCx_CLOCK_CNTR_OVF_L Register Field Descriptions
Bit Field
7-0 CLOCK_CNTR_OVF_L
Type
R/W
Reset
FFh
Description
CLOCK Counter Overflow Value, lower 8 Bit
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7.6.10 TDCx_CLOCK_CNTR_STOP_MASK_H: CLOCK Counter STOP Mask High Value Register (address
= 08h, CSBx asserted) [reset = 00h]
Figure 35. TDCx_CLOCK_CNTR_STOP_MASK_H Register
76543
CLOCK_CNTR_STOP_MASK_H
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
R/W-0
1
R/W-0
Table 11. TDCx_CLOCK_CNTR_STOP_MASK_H Register Field Descriptions
Bit Field
Type
7-0 CLOCK_CNTR_STOP_MASK_H R/W
Reset
00h
Description
CLOCK Counter STOP Mask, upper 8 Bit
0
R/W-0
7.6.11 TDCx_CLOCK_CNTR_STOP_MASK_L: CLOCK Counter STOP Mask Low Value Register (address
= 09h, CSBx asserted) [reset = 00h]
Figure 36. TDCx_CLOCK_CNTR_STOP_MASK_L Register
76543
CLOCK_CNTR_STOP_MASK_L
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
R/W-0
1
R/W-0
0
R/W-0
Table 12. TDCx_CLOCK_CNTR_STOP_MASK_L Register Field Descriptions
Bit Field
Type
7-0 CLOCK_CNTR_STOP_MASK_L R/W
Reset
00h
Description
CLOCK Counter STOP Mask, lower 8 Bit
7.6.12 TDCx_TIME1: Time 1 Register (address: 10h, CSBx asserted) [reset = 00_0000h]
Figure 37. TDCx_TIME1 Register
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Parity Bit
TIME1: 23 bit integer value (Bit 22: MSB, Bit 0: LSB)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
23
22-0
Field
Parity Bit
TIME1
Table 13. TDCx_TIME1 Register Field Descriptions
Type
R
R
Reset
0
00 0000h
Description
Parity Bit
23 bits, TIME1 measurement result
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