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Low-Noise Positive and Negative Output Integrated Charge Pump Plus LDO

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LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
LM27762 Low-Noise Positive and Negative Output Integrated
Charge Pump Plus LDO
1 Features
1 Generates Low-Noise Adjustable Positive Supply
Voltage Between 1.5 V and 5 V and Negative
Supply Voltage Between –1.5 V and –5 V
• Input Voltage Range 2.7 V to 5.5 V
• ±250-mA Output Current
• Inverting Charge Pump Followed by Negative
LDO
• 2-MHz Low-Noise Fixed-Frequency Operation
• 2.5-Inverter Output Impedance, VIN = 5 V
• Negative LDO Dropout Voltage 30 mV at 100 mA,
VOUT = –5 V
• Positive LDO with 45-mV Dropout Voltage at 100
mA, VOUT = 5 V
• 390-µA Quiescent Current (Typical)
• Shutdown Quiescent Current to 0.5 µA (Typical)
• Current Limit and Thermal Protection
• Power Good Pin (Active Low)
• Create a Custom Design Using the LM27762 With
the WEBENCH® Power Designer
2 Applications
• Hi-Fi Audio Headphone Amplifiers
• Operational Amplifier Power Biasing
• Powering Data Converters
• Wireless Communication Systems
• Interface Power Supplies
• Handheld Instrumentation
3 Description
The LM27762 delivers very low-noise positive and
negative outputs that are adjustable between ±1.5 V
and ±5 V. Input-voltage range is from 2.7 V to 5.5 V,
and output current goes up to ±250 mA. With an
operating current of only 390 µA and 0.5-µA typical
shutdown current, the LM27762 provides ideal
performance for power amplifier and DAC bias and
other high-current, low-noise negative voltage needs.
The device provides a small solution size with few
external components.
Negative voltage is generated by a regulated
inverting charge pump followed by a low-noise
negative LDO. The inverting charge pump of the
LM27762 device operates at 2-MHz (typical)
switching frequency to reduce output resistance and
voltage ripple. Positive voltage is generated from the
input by a low-noise positive LDO.
Positive and negative outputs of LM27762 have
dedicated enable inputs. These outputs support
independent timing for the positive and negative rails
for specific system power-sequence needs. Enable
inputs can be also shorted together and connected to
the input voltage. The LM27762 has an optional
Power Good feature.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM27762
WSON (12)
2.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
Simplified Schematic
2.7 V to 5.5 V
VIN
CVIN
RPU
PGOOD
C1-
C1
C1+
EN+
EN-
LM27762
CP
1.5 V to 5 V
OUT+
R1
FB+
GND
R2
R4
FB-
OUT-
R3
-1.5 V to -5 V
CCP
COUT+
COUT-
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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Low-Noise Positive and Negative Output Integrated Charge Pump Plus LDO

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LM27762
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Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics .............................................. 6
7 Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8 Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1 Device Support...................................................... 19
11.2 Receiving Notification of Documentation Updates 19
11.3 Community Resources.......................................... 19
11.4 Trademarks ........................................................... 19
11.5 Electrostatic Discharge Caution ............................ 19
11.6 Glossary ................................................................ 19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2016) to Revision B
Page
• Added added ulinks for WEBENCH ...................................................................................................................................... 1
Changes from Original (July 2016) to Revision A
Page
• Changed "Switched Capacitor" to "Charge Pump" in title ..................................................................................................... 1
• Changed "Generates Low-Noise Adjustable Positive and Negative Supply Voltages From ±1.5 V and ±5 V" to
"Generates Low-Noise Adjustable Positive Supply Voltages Between 1.5 V and 5 V and Negative Supply Voltages
From –1.5 V to –5 V" in Features........................................................................................................................................... 1
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5 Pin Configuration and Functions
LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
DSS Package
12-Pin WSON With Thermal Pad
Top View
1 12
2 11
3 10
49
58
67
NAME
C1+
C1–
CP
EN+
EN–
FB+
PIN
NUMBER
10
9
5
12
8
2
FB– 7
GND
OUT+
OUT–
PGOOD
4
11
6
1
VIN
Thermal Pad
3
TYPE
Power
Power
Power
Input
Input
Power
Power
Ground
Power
Power
Output
Power
Ground
Pin Functions
DESCRIPTION
Positive terminal for C1
Negative terminal for C1
Negative unregulated output voltage
Enable input for the positive LDO, Active high
Enable input for the charge pump and negative LDO, Active high
Feedback input. Connect FB+ to an external resistor divider between OUT+ and
GND. DO NOT leave unconnected.
Feedback input. Connect FB– to an external resistor divider between OUT– and
GND. DO NOT leave unconnected.
Ground
Regulated positive output voltage
Regulated negative output voltage
Power Good flag; open drain; Logic 0 = power good, Logic 1 = power not good.
Connect to ground if not used.
Positive power supply input
Ground. DO NOT leave unconnected.
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LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
6 Specifications
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6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
VIN to GND or GND to VOUT
EN+, EN-
CPOUT, OUT+ and OUT- , continuous output current
OUT+, OUT- short-circuit duration to GND(3)
Continuous power dissipation(4)
TJMAX (4)
Operating input voltage, VIN
Operating output current, IOUT
Operating ambient temperature, TA
Operating junction temperature, TJ
Storage temperature, Tstg
MIN MAX
5.8
GND 0.3
VIN
300
1
Internally limited
150
2.7 5.5
0 250
–40 85
–40 125
–65 150
UNIT
V
V
mA
s
°C
V
mA
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
(3) OUT may be shorted to GND for one second without damage. However, shorting OUT to VIN may damage the device and must be
avoided. Also, for temperatures above TA = 85°C, VOUT must not be shorted to GND or VIN or device may be damaged.
(4) Internal thermal shutdown circuitry protects the device from damage.
6.2 ESD Ratings
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
VALUE
±1000
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Operating ambient temperature, TA
Operating junction temperature, TJ
MIN
MAX
UNIT
–40 85 °C
–40 125 °C
6.4 Thermal Information
THERMAL METRIC(1)
LM27762
DSS (WSON)
12 PINS
RθJA
RθJC(top)
RθJB
ψJT
ψJB
RθJC(bot)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
62.2
54.7
25.6
1.8
25.6
9.2
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
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LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
6.5 Electrical Characteristics
Typical limits apply for TA = 25°C; minimum and maximum limits apply over the full temperature range. Unless otherwise
specified VIN = 5 V, CIN = COUT+ = COUT– = 2.2 μF, C1 = 1 μF, CPOUT = 4.7 μF.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
IQ Supply current
Open circuit, no load, EN+, EN–
connected to VIN. (1)
390 µA
ISD
ƒSW
RNEG
VLDO–
PSRR
VN
VFB–
VOUT–
VLDO+
PSRR
VN+
VFB+
VOUT+
VIH
VIL
Shutdown supply current
Switching frequency
Output resistance to CPOUT
LDO dropout voltage
Power supply rejection ratio, OUT–
Output noise voltage
Feedback pin reference voltage
Adjustable output voltage
Load regulation
Line regulation
LDO dropout voltage
Power supply rejection ratio, OUT+
Output noise voltage
Feedback pin reference voltage
Adjustable output voltage
Load regulation
Line regulation
Enable pin input voltage high
Enable pin input voltage low
VIN = 3.6 V
VIN = 5.5 V, IL = 100 mA
IL = 100 mA, VOUT– = 5 V
IL = 100 mA, VOUT– = 1.8 V, 10 kHz
IL = 80 mA, 10 Hz to 100 kHz
5.5 V VIN 2.7 V
0 to 250 mA, VOUT = –1.8 V
5 V VIN 2.7 V, IL = 50 mA
IL = 100 mA, VOUT = 5 V
IL = 100 mA, VOUT+ = 1.8 V, 10 kHz
IL = 80 mA, 10 Hz to 100 kHz
5.5 V VIN 2.7 V
0 to 250 mA, VOUT = 1.8 V
5 V VIN 2.7 V, IL = 50 mA
5.5 V VIN 2.7 V
5.5 V VIN 2.7 V
1.7
–1.238
–5
1.182
1.5
1.2
0.5
2
2.5
30
50
22
–1.22
34
1.5
45
43
22
1.2
11
1.9
5
2.3
–1.202
–1.5
1.218
5
0.4
µA
MHz
Ω
mV
dB
µVRMS
V
V
µV/mA
mV/V
mV
dB
µVRMS
V
V
µV/mA
mV/V
V
V
(1) When VIN = 5.5V charge pump may enter PWM mode in hot conditions.
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LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
6.6 Typical Characteristics
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
25 50
VIN = 3.7 V
VOUT+
VOUT-
75 100 125 150 175 200 225 250
Output Current (mA)
D014
VOUT = ±3 V
Figure 1. Output Voltage Ripple vs Output Current
120
VOUT+
VOUT-
100
80
60
40
20
0
0 25 50
VOUT = ± 3.3 V
75 100 125 150 175 200 225 250
Output Current (mA)
D015
Figure 3. LDO Dropout Voltage vs Output Current
-3.1
-3.125
-3.15
0 mA
50 mA
100 mA
-3.175
-3.2
-3.225
-3.25
-3.275
-3.3
-3.325
-3.35
-3.375
3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Input Voltage (V)
D017
VOUT = –3.3 V
Figure 5. Line Regulation for OUT-
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3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
2.8 3 3.2 3.4 3.6 3.8
Input Voltage (V)
VOUT = ±3 V
IOUT = ±100 mA
VOUT-
VOUT+
4 4.2
D022
Figure 2. Output Voltage Ripple vs Input Voltage
500
85°C
25°C
-40°C
100
10
1
0.001
VIN = 5.5 V
0.01
IOUT(A)
0.1
0.5
D016
Figure 4. Charge Pump Output Resistance vs Output
Current
3.31
3.305
0 mA
50 mA
100 mA
3.3
3.295
3.29
3.285
3.28
3.275
3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Input Voltage (V)
D018
VOUT = 3.3 V
Figure 6. Line Regulation for OUT+
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Typical Characteristics (continued)
-3.29
-3.3
-3.31
-3.32
-3.33
-3.34
-3.35
-3.36
-3.37
-3.38
-3.39
-3.4
0
30 60
VIN = 4.3 V
-40 °C
+25 °C
+85 °C
90 120 150 180 210 240 270
Output Current (mA)
D019
VOUT = –3.3 V
Figure 7. Load Regulation for OUT-
100
90
80
70
60
50
40
30
20
10
0
0 25 50
VIN = 5.5 V
VOUT = -3.3V
VOUT= -5V
75 100 125 150 175 200 225 250
Output Current (mA)
D021
Figure 9. Efficiency for OUT–
LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
3.35
3.34
3.33
3.32
3.31
3.3
3.29
3.28
3.27
3.26
3.25
0
25 50
VIN = 4.3 V
-40 °C
+25 °C
+85 °C
75 100 125 150 175 200 225 250
Output Current (mA)
D020
VOUT = 3.3 V
Figure 8. Load Regulation for OUT+
Figure 10. Start-Up
Figure 11. Shutdown
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LM27762
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7 Detailed Description
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7.1 Overview
The LM27762 low-noise inverting charge pump with both positive and negative LDOs delivers very low-noise
adjustable positive and negative outputs between ±1.5 V and ±5 V. The output voltage levels of the positive and
negative LDO are independently controllable with external resistors. Input voltage range of LM27762 is from 2.7
V to 5.5 V. Five low-cost capacitors are used in this circuit to provide up to ±250 mA of output current. The
LM27762 operates at 2-MHz (typical) switching frequency to reduce output resistance and voltage ripple. With an
typical operating current of only 390 µA and 0.5-µA typical shutdown current, the LM27762 provides ideal
performance for power amplifiers and DAC bias and other high-current, low-noise negative voltage needs.
The LM27762 device has an enable input (EN+) for the positive LDO and another enable input (EN–) for the
negative charge pump and LDO. This supports independent timing for the positive and negative rails in system
power sequence. Enable inputs can be also shorted together and connected to VIN. When LDO is disabled,
output of the positive LDO has 50-kpulldown to ground, and output of the negative LDO has 50-kpullup to
ground. The LM27762 has power good monitoring for OUT+ and OUT– outputs. The PGOOD pin is an open-
drain output and requires an external pullup resistor. When Power Good feature is not used, PGOOD pin can be
connected to ground.
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7.2 Functional Block Diagram
LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
VIN Current Limit
2-MHz Oscillator
Switch Array
Switch
Drivers
EN-
Reference
C1+
C1-
CP
GND
EN+
LPF
Negative
Bandgap
LDO
LPF
Positive
Bandgap
LDO
EN-
PU
LPF
OUT-
FB-
Power Good
Monitoring
Current
Limit
EN+
PD
LPF
PGOOD
OUT+
FB+
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7.3 Feature Description
7.3.1 Undervoltage Lockout
The LM27762 has an internal comparator that monitors the voltage at VIN and forces the device into shutdown if
the input voltage drops to 2.4 V. If the input voltage rises above 2.6 V, the LM27762 resumes normal operation.
7.3.2 Input Current Limit
The LM27762 contains current limit circuitry that protects the device in the event of excessive input current
and/or output shorts to ground. The charge pump and positive LDO both have 500 mA (typical) input current limit
when the output is shorted directly to ground. When the LM27762 is current limiting, power dissipation in the
device is likely to be quite high. In this event, thermal cycling is expected.
7.3.3 PFM Operation
To minimize quiescent current during light load operation, the LM27762 allows PFM or pulse-skipping operation.
By allowing the charge pump to switch less when the output current is low, the quiescent current drawn from the
power source is minimized. The frequency of pulsed operation is not limited and can drop into the sub-2-kHz
range when unloaded. As the load increases, the frequency of pulsing increases until it transitions to constant
frequency. The fundamental switching frequency in the LM27762 is 2 MHz.
7.3.4 Output Discharge
In shutdown, the LM27762 actively pulls down on the outputs (OUT+, OUT–) of the device until the output
voltage reaches GND.
7.3.5 Power Good Output (PGOOD)
The LM27762 has monitoring for the OUT+ and OUT– output voltage levels and open-drain PGOOD output.
EN+
Low
High
High
Low
Low
High
High
High
EN–
Low
Low
Low
High
High
High
High
High
Table 1. PGOOD (Active Low) Operation
OUT+
Don't care
< 95% of target value
> 95% of target value
Don't care
Don't care
< 95% of target value
Don't care
> 95% of target value
OUT–
Don't care
Don't care
Don't care
< 95% of target value
> 95% of target value
Don't care
< 95% of target value
> 95% of target value
PGOOD
High
High
Low
High
Low
High
High
Low
7.3.6 Thermal Shutdown
The LM27762 implements a thermal shutdown mechanism to protect the device from damage due to
overheating. When the junction temperature rises to 150°C (typical), the device switches into shutdown mode.
The LM27762 releases thermal shutdown when the junction temperature is reduced to 130°C (typical).
Thermal shutdown is most often triggered by self-heating, which occurs when there is excessive power
dissipation in the device and/or insufficient thermal dissipation. The LM27762 device power dissipation increases
with increased output current and input voltage. When self-heating brings on thermal shutdown, thermal cycling
is the typical result. Thermal cycling is the repeating process where the part self-heats, enters thermal shutdown
(where internal power dissipation is practically zero), cools, turns on, and then heats up again to the thermal
shutdown threshold. Thermal cycling is recognized by a pulsing output voltage and can be stopped by reducing
the internal power dissipation (reduce input voltage and/or output current) or the ambient temperature. If thermal
cycling occurs under desired operating conditions, thermal dissipation performance must be improved to
accommodate the power dissipation of the device.
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LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
7.4 Device Functional Modes
7.4.1 Shutdown Mode
When enable pins (EN+, EN–) are low, both positive and negative outputs of LM27762 are disabled, and the
device is in shutdown mode reducing the quiescent current to minimum level. In shutdown, the outputs of the
LM27762 are pulled to ground (internal 50 kbetween each OUT pin and ground).
7.4.2 Enable Mode
Applying a voltage greater than 1.2 V to the EN+ pin enables the positive LDO. Applying a voltage greater than
1.2 V to the EN– pin enables the negative CP and LDO. When enabled, the positive and negative output
voltages are equal to levels set by external resistors. Care must be taken to both the positive LDO and the
inverting charge pump followed by negative LDO have enough headroom. Power Good ouput PGOOD indicates
the status of OUT+ and OUT– voltage levels.
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LM27762
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8 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM27762 input voltage range is from 2.7 V to 5.5 V. The positive LDO provides a positive voltage
configurable with external gain setting resistors R1, R2. The low-noise charge-pump voltage converter inverts the
input voltage V to a negative output voltage. Charge pump is followed by the negative LDO which regulates a
negative output voltage configurable with external gain setting resistors R3, R4. Output voltage range is ± 1.5 V to
± 5 V. When selecting input (VIN) and output (OUT+, OUT-) voltages ranges, headroom required by the charge
pump and LDOs must to be considered. Charge-pump minimum headroom can be estimated based on the
maximum load current and charge pump output resistance.
The device uses five low-cost capacitors to provide up to 250 mA of output current. The LM27762 operates at a
2-MHz oscillator frequency to reduce charge-pump output resistance and voltage ripple under heavy loads.
When using the optional open-drain PGOOD feature, connect a 10-kpullup resistor (RPU) to VIN. Connect pin
to ground if PGOOD is not used.
8.2 Typical Application
2.7 V to 5.5 V
VIN
CVIN
RPU
PGOOD
C1-
C1
C1+
EN+
EN-
LM27762
CP
1.5 V to 5 V
OUT+
R1
FB+
GND
R2
R4
FB-
OUT-
R3
-1.5 V to -5 V
CCP
COUT+
COUT-
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Figure 12. LM27762 Typical Application
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LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
Typical Application (continued)
8.2.1 Design Requirements
The following example describes powering an amplifier driving high impedance headphones. Input voltage is
from a smart-phone battery. Amplifier is driving 2-VRMS to 600-stereo headphones.
Table 2. Application Example Design Parameters
DESIGN PARAMETER
Input voltage
Output voltage
Output current
CVIN, COUT+, COUT–
CCP
RPU
EXAMPLE VALUE
3.3 V to 4.2 V
±3 V
10 mA (LM27762 capability 250 mA maximum)
2.2 μF
4.7 μF
10 k(optional, connect PGOOD pin to ground if feature is not used)
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM27762 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Positive Low-Dropout Linear Regulator and OUT+ Voltage Setting
LM27762 features a low-dropout, linear positive voltage regulator (LDO). The LDO output is rated for a current of
250 mA. This LDO allows the device to provide a very low noise output, low output voltage ripple, high PSRR,
and low line or load transient response.
The positive output voltage of the LM27762 is externally configurable. The value of R1 and R2 determines the
output voltage setting. The output voltage can be calculated using Equation 1:
VOUT = 1.2 V × (R1 + R2) / R2
(1)
The value for R2 must be no less than 50 kΩ.
8.2.2.3 Charge-Pump Voltage Inverter
The main application of the LM27762 is to generate a regulated negative supply voltage. The voltage inverter
circuit uses only three external capacitors, and the LDO regulator circuit uses one additional output capacitor.
The voltage inverter portion of the LM27761 contains four large CMOS switches which are switched in sequence
to invert the input supply voltage. Energy transfer and storage are provided by external capacitors. Figure 13
shows the voltage switches S2 and S4 are open. In the second time interval, S1 and S3 are open; at the same
time, S2 and S4 are closed, and C1 is charging CCP. After a number of cycles, the voltage across CCP is pumped
into VIN. Because the anode of CCP is connected to ground, the output at the cathode of CCP equals –(VIN) when
there is no load current. When a load is added, the output voltage drop is determined by the parasitic resistance
(RDSON of the MOSFET switches and the equivalent series resistance (ESR) of the capacitors) and the charge
transfer loss between the capacitors.
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VIN S1 C1+ S2
CIN C1
GND
S3 S4
C1-
OSC.
2 MHz
PFM COMP
+
GND
CCPOUT
CP
www.ti.com
VIN
Copyright © 2016, Texas Instruments Incorporated
Figure 13. Voltage Inverting Principle
The output characteristic of this circuit can be approximated by an ideal voltage source in series with a
resistance. The voltage source equals –(VIN). The output resistance ROUT is a function of the ON resistance of
the internal MOSFET switches, the oscillator frequency, the capacitance, and the ESR of C1 and CCP. Because
the switching current charging and discharging C1 is approximately twice as the output current, the effect of the
ESR of the pumping capacitor C1 is multiplied by four in the output resistance. The charge-pump output capacitor
CCP is charging and discharging at a current approximately equal to the output current; therefore, its ESR only
counts once in the output resistance. A good approximation of charge-pump ROUT is shown in Equation 2:
ROUT = (2 × RSW) + [1 / (ƒSW × C1)] + (4 × ESRC1) + ESRCCP
where
• RSW is the sum of the ON resistance of the internal MOSFET switches shown in Figure 13.
(2)
High capacitance and low-ESR ceramic capacitors reduce the output resistance.
8.2.2.4 Negative Low-Dropout Linear Regulator and OUT– Voltage Setting
At the output of the inverting charge-pump the LM27762 features a low-dropout, linear negative voltage regulator
(LDO). The LDO output is rated for a current of 250 mA. This negative LDO allows the device to provide a very
low noise output, low output voltage ripple, high PSRR, and low line or load transient response.
The negative output voltage of the LM27762 is externally configurable. The value of R3 and R4 determines the
output voltage setting. The output voltage can be calculated using Equation 1:
VOUT = –1.22 V × (R3 + R4) / R4
(3)
The value for R4 must be no less than 50 kΩ.
8.2.2.5 External Capacitor Selection
The LM27762 requires 5 external capacitors for proper operation. Surface-mount multi-layer ceramic capacitors
are recommended. These capacitors are small, inexpensive, and have very low ESR (15 mΩ typical). Tantalum
capacitors, OS-CON capacitors, and aluminum electrolytic capacitors generally are not recommended for use
with the LM27762 due to their high ESR compared to ceramic capacitors.
For most applications, ceramic capacitors with an X7R or X5R temperature characteristic are preferable for use
with the LM27762. These capacitors have tight capacitance tolerances (as good as ±10%) and hold their value
over temperature (X7R: ±15% over –55°C to +125°C; X5R ±15% over –55°C to +85°C).
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Using capacitors with a Y5V or Z5U temperature characteristic is generally not recommended for the LM27762.
These capacitors typically have wide capacitance tolerance (80%, ….20%) and vary significantly over
temperature (Y5V: 22%, –82% over –30°C to +85°C range; Z5U: 22%, –56% over 10°C to 85°C range). Under
some conditions a 1-µF-rated Y5V or Z5U capacitor could have a capacitance as low as 0.1 µF. Such
detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum capacitance
requirements of the LM27762.
Net capacitance of a ceramic capacitor decreases with increased DC bias. This degradation can result in lower-
than-expected capacitance on the input and/or output, resulting in higher ripple voltages and currents. Using
capacitors at DC bias voltages significantly below the capacitor voltage rating usually minimizes DC bias effects.
Consult capacitor manufacturers for information on capacitor DC bias characteristics.
Capacitance characteristics can vary quite dramatically with different application conditions, capacitor types, and
capacitor manufacturers. TI strongly recommends that the LM27762 circuit be evaluated thoroughly early in the
design-in process with the mass-production capacitor of choice. This helps ensure that any such variability in
capacitance does not negatively impact circuit performance.
8.2.2.5.1 Charge-Pump Output Capacitor
In typical applications, Texas Instruments recommends a 4.7-µF low-ESR ceramic charge-pump output capacitor
(CCP). Different output capacitance values can be used to reduce charge pump ripple, shrink the solution size,
and/or cut the cost of the solution. However, changing the output capacitor may also require changing the flying
capacitor or input capacitor to maintain good overall circuit performance.
In higher-current applications, a 10-µF, 10-V low-ESR ceramic output capacitor is recommended. If a small
output capacitor is used, the output ripple can become large during the transition between PFM mode and
constant switching. To prevent toggling, a 2-µF capacitance is recommended. For example, 10-µF, 10-V output
capacitor in a 0402 case size typically has only 2-µF capacitance when biased to 5 V.
8.2.2.5.2 Input Capacitor
The input capacitor (C2) is a reservoir of charge that aids in a quick transfer of charge from the supply to the
flying capacitors during the charge phase of operation. The input capacitor helps to keep the input voltage from
drooping at the start of the charge phase when the flying capacitors are connected to the input. It also filters
noise on the input pin, keeping this noise out of the sensitive internal analog circuitry that is biased off the input
line.
Input capacitance has a dominant and first-order effect on the input ripple magnitude. Increasing (decreasing) the
input capacitance results in a proportional decrease (increase) in input voltage ripple. Input voltage, output
current, and flying capacitance also affects input ripple levels to some degree.
In typical applications, a 4.7-µF low-ESR ceramic capacitor is recommended on the input. When operating near
the maximum load of 250 mA, after taking into the DC bias derating, a minimum recommended input capacitance
is 2 µF or larger. Different input capacitance values can be used to reduce ripple, shrink the solution size, and/or
cut the cost of the solution.
8.2.2.5.3 Flying Capacitor
The flying capacitor (C1) transfers charge from the input to the output. Flying capacitance can impact both output
current capability and ripple magnitudes. If flying capacitance is too small, the LM27762 may not be able to
regulate the output voltage when load currents are high. On the other hand, if the flying capacitance is too large,
the flying capacitor might overwhelm the input and charge pump output capacitors, resulting in increased input
and output ripple.
In typical high-current applications, 0.47-µF or 1-µF 10-V low-ESR ceramic capacitors are recommended for the
flying capacitors. Polarized capacitors (tantalum, aluminum, electrolytic, etc.) must not be used for the flying
capacitor, as they could become reverse-biased during LM27762 operation.
8.2.2.5.4 LDO Output Capacitor
The LDO output capacitor (COUT+, COUT-) value and the ESR affect stability, output ripple, output noise, PSRR
and transient response. The LM27762 only requires the use of a 2.2-µF ceramic output capacitor for stable
operation. For typical applications, a 2.2-µF ceramic output capacitor located close to the output is sufficient.
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8.2.2.6 Power Dissipation
The allowed power dissipation for any package is a measure of the ability of the device to pass heat from the
junctions of the device to the heatsink and the ambient environment. Thus, the power dissipation is dependent
on the ambient temperature and the thermal resistance across the various interfaces between the die junction
and ambient air.
The maximum allowable power dissipation can be calculated by Equation 4:
PD-MAX = (TJ-MAX – TA) / RθJA
(4)
The actual power being dissipated in the device can be represented by Equation 5:
PD = PIN – POUT = VIN × (–IOUT– + IOUT+ + IQ) – (VOUT+ × IOUT+ + VOUT– × IOUT–)
(5)
Equation 4 and Equation 5 establish the relationship between the maximum power dissipation allowed due to
thermal consideration, the voltage drop across the device, and the continuous current capability of the device.
These equations must be used to determine the optimum operating conditions for the device in a given
application.
In lower power dissipation applications the maximum ambient temperature (TA-MAX) may be increased. In higher
power dissipation applications the maximum ambient temperature(TA-MAX) may have to be derated. TA-MAX can be
calculated using Equation 6:
TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX)
where
• TJ-MAX-OP = maximum operating junction temperature (125°C)
• PD-MAX = the maximum allowable power dissipation
• RθJA = junction-to-ambient thermal resistance of the package
(6)
Alternately, if TA-MAX cannot be derated, the power dissipation value must be reduced. This can be accomplished
by reducing the input voltage as long as the minimum VIN is not violated, or by reducing the output current, or
some combination of the two.
8.2.3 Application Curves
Refer also to Typical Characteristics
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
10
VIN=3.7V,IOUT=100mA
VIN=3.7V,IOUT=10mA
VIN=3.3V,IOUT=10mA
100
1000
10000
Frequency(Hz)
Figure 14. PSRR for OUT-
100000
D023
0
-10
-20
-30
-40
-50
-60
-70
-80
10
VIN= 3.7V, IOUT=100mA
VIN= 3.3V, IOUT=100mA
VIN= 3.7V, IOUT=10mA
VIN= 3.3V, IOUT=10mA
100
1000
10000
Frequency (Hz)
Figure 15. PSRR for OUT+
100000
D024
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LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
9 Power Supply Recommendations
The LM27762 is designed to operate from an input voltage supply range between 2.7 V and 5.5 V. This input
supply must be well regulated and capable of supplying the required input current. If the input supply is located
far from the LM27762, additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
The high switching frequency and large switching currents of the LM27762 make the choice of layout important.
Use the following steps as a reference to ensure the device is stable and maintains proper LED current
regulation across its intended operating voltage and current range:
• Place CIN on the top layer (same layer as the LM27762) and as close as possible to the device. Connecting
the input capacitor through short, wide traces to both the VIN and GND pins reduces the inductive voltage
spikes that occur during switching, which can corrupt the VIN line.
• Place CCPOUT on the top layer (same layer as the LM27762) and as close as possible to the VOUT and GND
pins. The returns for both CIN and CCPOUT must come together at one point, as close as possible to the GND
pin. Connecting CCPOUT through short, wide traces reduces the series inductance on the VCPOUT and GND
pins that can corrupt the VCPOUT and GND lines and cause excessive noise in the device and surrounding
circuitry.
• Place C1 on top layer (same layer as the LM27762) and as close as possible to the device. Connect the flying
capacitor through short, wide traces to both the C1+ and C1– pins.
• Place COUT+, COUT– on the top layer (same layer as the LM27762) and as close to the respective OUT pin as
possible. For best performance the ground connection for COUT must connect back to the GND connection at
the thermal pad of the device.
• Place R1 to R4 on the top layer (same layer as LM27762) and as close as possible to the respective FB pin.
For best performance the ground connection of R2, R4 must connect back to the GND connection at the
thermal pad of the device.
Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. These
add parasitic inductance and resistance that results in inferior performance, especially during transient
conditions.
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10.2 Layout Example
R1
R2
Positive Rail, To Load
COUT+
C1
Thermal Pad
R3
R4
COUT-
CIN
To Supply
CCPOUT
To GND Plane
Figure 16. LM27762 Layout Example
(Note: Pullup resistor for PGOOD not shown in example.)
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11 Device and Documentation Support
LM27762
SNVSAF7B – AUGUST 2016 – REVISED FEBRUARY 2017
11.1 Device Support
Using the LM27762EVM Evaluation Module
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM27762 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Feb-2017
PACKAGING INFORMATION
Orderable Device
LM27762DSSR
LM27762DSST
Status Package Type Package Pins Package Eco Plan
(1) Drawing Qty (2)
ACTIVE
WSON
DSS
12 3000 Green (RoHS
& no Sb/Br)
ACTIVE
WSON
DSS 12 250 Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU
CU NIPDAU
MSL Peak Temp Op Temp (°C)
(3)
Level-2-260C-1 YEAR -40 to 85
Level-2-260C-1 YEAR -40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Device Marking
(4/5)
L27762
L27762
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
6-Feb-2017
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TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
7-Feb-2017
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LM27762DSSR
LM27762DSST
WSON
WSON
DSS
DSS
12
12
SPQ
3000
250
Reel Reel A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4 2.25
180.0
8.4 2.25
B0
(mm)
3.25
3.25
K0
(mm)
1.05
1.05
P1
(mm)
4.0
4.0
W Pin1
(mm) Quadrant
8.0 Q1
8.0 Q1
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PACKAGE MATERIALS INFORMATION
7-Feb-2017
*All dimensions are nominal
Device
LM27762DSSR
LM27762DSST
Package Type
WSON
WSON
Package Drawing Pins
DSS
DSS
12
12
SPQ
3000
250
Length (mm)
210.0
210.0
Width (mm)
185.0
185.0
Height (mm)
35.0
35.0
Pack Materials-Page 2


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DSS0012B
B
SCALE 4.500
2.1 A
1.9
PACKAGE OUTLINE
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
0.3
3.1 0.2
2.9
0.35
0.25
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
EXPOSED
THERMAL PAD
6
SEE TERMINAL
DETAIL
2X
2.5
1 0.1
SYMM
13
C
SEATING PLANE
0.08 C
0.05
0.00
7
SYMM
2.65 0.1
(0.2) TYP
10X 0.5
1
PIN 1 ID
(OPTIONAL)
12X
0.35
0.25
12
12X
0.3
0.2
0.1 C A B
0.05 C
4218908/A 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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DSS0012B
EXAMPLE BOARD LAYOUT
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
12X (0.5)
1
12X (0.25)
(1)
SYMM
12
10X (0.5)
13
SYMM
(2.65)
(R0.05) TYP
( 0.2) VIA
TYP
6
(1.075)
7
(1.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.05 MAX
ALL AROUND
EXPOSDE METAL
EXPOSED METAL
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218908/A 01/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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DSS0012B
EXAMPLE STENCIL DESIGN
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
12X (0.5)
1
12X (0.25)
SYMM
SYMM
13
EXPOSED METAL
TYP
12
(0.685)
10X (0.5)
(R0.05) TYP
6
2X (1.17)
7
2X (0.95)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 13:
83% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218908/A 01/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com


LM27762 (etcTI)
Low-Noise Positive and Negative Output Integrated Charge Pump Plus LDO

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