80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 80C188EC AND 80L186EC 80L188EC
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
X Fully Static Operation
X True CMOS Inputs and Outputs
Y Integrated Feature Set
Low-Power Static Enhanced 8086
CPU Core
Two Independent DMA Supported
UARTs each with an Integral Baud
Rate Generator
Four Independent DMA Channels
22 Multiplexed I O Port Pins
Two 8259A Compatible
Programmable Interrupt Controllers
Three Programmable 16-Bit Timer
Counters
32-Bit Watchdog Timer
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
Power Management Unit
On-Chip Oscillator
System Level Testing Support
(ONCE Mode)
Y Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I O
Y Low-Power Operating Modes
Idle Mode Freezes CPU Clocks but
Keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
Powersave Mode Divides All Clocks
by Programmable Prescalar
Y Available in Extended Temperature
Range (b40 C to a85 C)
Y Supports 80C187 Numerics Processor
Extension (80C186EC only)
Y Package Types
100-Pin EIAJ Quad Flat Pack (QFP)
100-Pin Plastic Quad Flat Pack
(PQFP)
100-Pin Shrink Quad Flat Pack
(SQFP)
Y Speed Versions Available (5V)
25 MHz (80C186EC25 80C188EC25)
20 MHz (80C186EC20 80C188EC20)
13 MHz (80C186EC13 80C188EC13)
Y Speed Version Available (3V)
16 MHz (80L186EC16 80L188EC16)
13 MHz (80L186EC13 80L188EC13)
The 80C186EC is a member of the 186 Integrated Processor Family The 186 Integrated Processor Family
incorporates several different VLSI devices all of which share a common CPU architecture the 8086 8088
The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common
system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic
silicon die
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT © INTEL CORPORATION, 2004
August, 2004
Order Number: 272434-006


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 80C188EC and 80L186EC 80L188EC
16-BIT HIGH-INTEGRATION
EMBEDDED PROCESSOR
CONTENTS
INTRODUCTION
80C186EC CORE ARCHITECTURE
Bus Interface Unit
Clock Generator
80C186EC PERIPHERAL
ARCHITECTURE
Programmable Interrupt Controllers
Timer Counter Unit
Serial Communications Unit
DMA Unit
Chip-Select Unit
I O Port Unit
Refresh Control Unit
Watchdog Timer Unit
Power Management Unit
80C187 Interface (80C186EC only)
ONCE Test Mode
PACKAGE INFORMATION
Prefix Identification
Pin Descriptions
Pinout
Package Thermal Specifications
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PAGE
4
4
4
4
5
7
7
7
7
7
7
7
7
8
8
8
8
8
8
15
24
25
25
CONTENTS
Recommended Connections
PAGE
25
DC SPECIFICATIONS
ICC versus Frequency and Voltage
PDTMR Pin Delay Calculation
26
29
29
AC SPECIFICATIONS
AC Characteristics 80C186EC25
AC Characteristics 80C186EC20 13
AC Characteristics 80L186EC13
AC Characteristics 80L186EC16
Relative Timings
Serial Port Mode 0 Timings
30
30
32
33
34
35
36
AC TEST CONDITIONS
37
AC TIMING WAVEFORMS
37
DERATING CURVES
40
RESET
40
BUS CYCLE WAVEFORMS
43
EXECUTION TIMINGS
50
INSTRUCTION SET SUMMARY
51
ERRATA
57
REVISION HISTORY
57
2


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
Figure 1 80C186EC 80L186EC Block Diagram
272434 – 1
3


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
INTRODUCTION
Unless specifically noted all references to the
80C186EC apply to the 80C188EC 80L186EC and
80L188EC References to pins that differ between
the 80C186EC 80L186EC and the 80C188EC
80L188EC are given in parentheses The ‘‘L’’ in the
part number denotes low voltage operation Physi-
cally and functionally the ‘‘C’’ and ‘‘L’’ devices are
identical
The 80C186EC is one of the highest integration
members of the 186 Integrated Processor Family
Two serial ports are provided for services such as
interprocessor communication diagnostics and mo-
dem interfacing Four DMA channels allow for high
speed data movement as well as support of the on-
board serial ports A flexible chip select unit simpli-
fies memory and peripheral interfacing The three
general purpose timer counters can be used for a
variety of time measurement and waveform genera-
tion tasks A watchdog timer is provided to insure
system integrity even in the most hostile of environ-
ments Two 8259A compatible interrupt controllers
handle internal interrupts and up to 57 external in-
terrupt requests A DRAM refresh unit and 24 multi-
plexed I O ports round out the feature set of the
80C186EC
The future set of the 80C186EC meets the needs of
low-power space-critical applications Low-power
applications benefit from the static design of the
CPU and the integrated peripherals as well as low
voltage operation Minimum current consumption is
achieved by providing a powerdown mode that halts
operaton of the device and freezes the clock cir-
cuits Peripheral design enhancements ensure that
non-initialized peripherals consume little current
The 80L186EC is the 3V version of the 80C186EC
The 80L186EC is functionally identical to the
80C186EC embedded processor Current
80C186EC users can easily upgrade their designs to
use the 80L186EC and benefit from the reduced
power consumption inherent in 3V operation
Figure 1 shows a block diagram of the 80C186EC
80C188EC The execution unit (EU) is an enhanced
8086 CPU core that includes dedicated hardware to
speed up effective address calculations enhanced
execution speed for multiple-bit shift and rotate in-
structions and for multiply and divide instructions
string move instructions that operate at full bus
bandwidth ten new instructions and fully static oper-
ation The bus interface unit (BIU) is the same as
that found on the original 186 family products ex-
cept the queue-status mode has been deleted and
buffer interface control has been changed to ease
system design timings An independent internal bus
is used for communication between the BIU and on-
chip peripherals
4
80C186EC CORE ARCHITECTURE
Bus Interface Unit
The 80C186EC core incorporates a bus controller
that generates local bus control signals In addition
it employs a HOLD HLDA protocol to share the local
bus with other bus masters
The bus controller is responsible for generating 20
bits of address read and write strobes bus cycle
status information and data (for write operations) in-
formation It is also responsible for reading data
from the local bus during a read operation A ready
input pin is provided to extend a bus cycle beyond
the minimum four states (clocks)
The bus controller also generates two control sig-
nals (DEN and DT R) when interfacing to external
transceiver chips This capability allows the addition
of transceivers for simple buffering of the multi-
plexed address data bus
Clock Generator
The 80C186EC provides an on-chip clock generator
for both internal and external clock generation The
clock generator features a crystal oscillator a divide-
by-two counter and three low-power operating
modes
The oscillator circuit is designed to be used with ei-
ther a parallel resonant fundamental or third-over-
tone mode crystal network Alternatively the oscilla-
tor circuit may be driven from an external clock
source Figure 2 shows the various operating modes
of the oscillator circuit
The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter This counter is
used to drive all internal phase clocks and the exter-
nal CLKOUT signal CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys-
tem components All AC timings are referenced to
CLKOUT
The following parameters are recommended when
choosing a crystal
Temperature Range
Application Specific
ESR (Equivalent Series Res )
40X max
C0 (Shunt Capacitance of Crystal)
7 0 pF max
CL (Load Capacitance)
Drive Level
20 pF g2 pF
1 mW (max)


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
272434 – 2
NOTE
1 The LC network is only required when using a third overtone crystal
Figure 2 80C186EC Clock Connections
80C186EC PERIPHERAL
ARCHITECTURE
The 80C186EC integrates several common system
peripherals with a CPU core to create a compact yet
powerful system The integrated peripherals are de-
signed to be flexbile and provide logical interconnec-
tions between supporting units (e g the DMA unit
can accept requests from the Serial Communica-
tions Unit)
The list of integrated peripherals includes
Two cascaded 8259A compatible Programma-
ble Interrupt Controllers
3-Channel Timer Counter Unit
2-Channel Serial Communications Unit
4-Channel DMA Unit
10-Output Chip-Select Unit
32-bit Watchdog Timer Unit
I O Port Unit
Refresh Control Unit
Power Management Unit
The registers associated with each integrated pe-
ripheral are contained within a 128 x 16-bit register
file called the Peripheral Control Block (PCB) The
base address of the PCB is programmable and can
be located on any 256 byte address boundary in ei-
ther memory or I O space
Figure 3 provides a list of the registers associated
with the PCB The Register Bit Summary individually
lists all of the registers and identifies each of their
programming attributes
5


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
PCB
Offset
Function
00H Master PIC Port 0
02H Master PIC Port 1
04H Slave PIC Port 0
06H Slave PIC Port 1
08H Reserved
0AH SCU Int Req Ltch
0CH DMA Int Req Ltch
0EH TCU Int Req Ltch
10H Reserved
12H Reserved
14H Reserved
16H Reserved
18H Reserved
1AH Reserved
1CH
Reserved
1EH Reserved
20H WDT Reload High
22H WDT Reload Low
24H WDT Count High
26H WDT Count Low
28H WDT Clear
2AH WDT Disable
2CH
Reserved
2EH Reserved
30H T0 Count
32H T0 Compare A
34H T0 Compare B
46H T0 Control
38H T1 Count
3AH T1 Compare A
3CH T1 Compare B
3EH T1 Control
PCB
Offset
Function
PCB
Offset
Function
40H T2 Count
80H GCS0 Start
42H T2 Compare
82H GCS0 Stop
44H Reserved
84H GCS1 Start
46H T2 Control
86H GCS1 Stop
48H Port 3 Direction
88H GCS2 Start
4AH Port 3 Pin State
8AH GCS2 Stop
4CH Port 3 Mux Control
8CH
GCS3 Start
4EH Port 3 Data Latch
8EH
GCS3 Stop
50H Port 1 Direction
90H GCS4 Start
52H Port 1 Pin State
92H GCS4 Stop
54H Port 1 Mux Control 94H GCS5 Start
56H Port 1 Data Latch 96H GCS5 Stop
58H Port 2 Direction
98H GCS6 Start
5AH Port 2 Pin State
9AH GCS6 Stop
5CH Port 2 Mux Control
9CH
GCS7 Start
5EH Port 2 Data Latch
9EH
GCS7 Stop
60H SCU 0 Baud
A0H LCS Start
62H SCU 0 Count
A2H LCS Stop
64H SCU 0 Control
A4H UCS Start
66H SCU 0 Status
A6H UCS Stop
68H SCU 0 RBUF
A8H Relocation Register
6AH SCU 0 TBUF
AAH
Reserved
6CH
Reserved
ACH
Reserved
6EH Reserved
AEH
Reserved
70H SCU 1 Baud
B0H Refresh Base Addr
72H SCU 1 Count
B2H Refresh Time
74H SCU 1 Control
B4H Refresh Control
76H SCU 1 Status
B6H Refresh Address
78H SCU 1 RBUF
B8H Power Control
7AH SCU 1 TBUF
BAH
Reserved
7CH
Reserved
BCH
Step ID
7EH Reserved
BEH
Powersave
Figure 3 Peripheral Control Block Registers
PCB
Offset
Function
C0H DMA 0 Source Low
C2H DMA 0 Source High
C4H DMA 0 Dest Low
C6H DMA 0 Dest High
C8H DMA 0 Count
CAH DMA 0 Control
CCH DMA Module Pri
CEH
DMA Halt
D0H DMA 1 Source Low
D2H DMA 1 Source High
D4H DMA 1 Dest Low
D6H DMA 1 Dest High
D8H DMA 1 Count
DAH DMA 1 Control
DCH
Reserved
DEH
Reserved
E0H DMA 2 Source Low
E2H DMA 2 Source High
E4H DMA 2 Dest Low
E6H DMA 2 Dest High
E8H DMA 2 Count
EAH DMA 2 Control
ECH
Reserved
EEH
Reserved
F0H DMA 3 Source Low
F2H DMA 3 Source High
F4H DMA 3 Dest Low
F6H DMA 3 Dest High
F8H DMA 3 Count
FAH DMA 3 Control
FCH
Reserved
FEH
Reserved
6


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Programmable Interrupt Controllers
The 80C186EC utilizes two 8259A compatible Pro-
grammable Interrupt Controllers (PIC) to manage
both internal and external interrupts The 8259A
modules are configured in a master slave arrange-
ment
Seven of the external interrupt pins INT0 through
INT6 are connected to the master 8259A module
The eighth external interrupt pin INT7 is connected
to the slave 8259A module
There are a total of 11 internal interrupt sources
from the integrated peripherals 4 Serial 4 DMA and
3 Timer Counter
Timer Counter Unit
The 80C186EC Timer Counter Unit (TCU) provides
three 16-bit programmable timers Two of these are
highly flexible and are connected to external pins for
external control or clocking The third timer is not
connected to any external pins and can only be
clocked internally However it can be used to clock
the other two timer channels The TCU can be used
to count external events time external events gen-
erate non-repetitive waveforms or generate timed in-
terrupts
Serial Communications Unit
The 80C186EC Serial Communications Unit (SCU)
contains two independent channels Each channel is
identical in operation except that only channel 0 is
directly supported by the integrated interrupt control-
ler (the channel 1 interrupts are routed to external
interrupt pins) Each channel has its own baud rate
generator and can be internally or externally clocked
up to one half the processor operating frequency
Both serial channels can request service from the
DMA unit thus providing block reception and trans-
mission without CPU intervention
Independent baud rate generators are provided for
each of the serial channels For the asynchronous
modes the generator supplies an 8x baud clock to
both the receive and transmit shifting register logic
A 1x baud clock is provided in the synchronous
mode
DMA Unit
The four channel Direct Memory Access (DMA) Unit
is comprised of two modules with two channels
each All four channels are identical in operation
DMA transfers can take place from memory to mem-
ory I O to memory memory to I O or I O to I O
DMA requests can be external (on the DRQ pins)
internal (from Timer 2 or a serial channel) or soft-
ware initiated
The DMA Unit transfers data as bytes only Each
data transfer requires at least two bus cycles one to
fetch data and one to deposit The minimum clock
count for each transfer is 8 but this will vary depend-
ing on synchronization and wait states
Chip-Select Unit
The 80C186EC Chip-Select Unit (CSU) integrates
logic which provides up to ten programmable chip-
selects to access both memories and peripherals In
addition each chip-select can be programmed to
automatically insert additional clocks (wait states)
into the current bus cycle and or automatically ter-
minate a bus cycle independent of the condition of
the READY input pin
I O Port Unit
The I O Port Unit on the 80C186EC supports two
8-bit channels and one 6-bit channel of input output
or input output operation Port 1 is multiplexed with
the chip select pins and is output only Port 2 is mul-
tiplexed with the pins for serial channels 1 and 2 All
Port 2 pins are input output Port 3 has a total of 6
pins four that are multiplexed with DMA and serial
port interrupts and two that are non-multiplexed
open drain I O
Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed A 9-bit
counter controls the number of clocks between re-
fresh requests
A 12-bit address generator is maintained by the RCU
and is presented on the A12 1 address lines during
the refresh bus cycle Address bits A19 13 are pro-
grammable to allow the refresh address block to be
located on any 8 Kbyte boundary
Watchdog Timer Unit
The Watchdog Timer Unit (WDT) allows for graceful
recovery from unexpected hardware and software
upsets The WDT consists of a 32-bit counter that
decrements every clock cycle If the counter reach-
es zero before being reset the WDTOUT pin is
7


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC/188EC, 80L186EC/188EC
pulled low for four clock cycles. Logically ANDing
the WDTOUT pin with the power-on reset signal al-
lows the WDT to reset the device in the event of a
WDT timeout. If a less drastic method of recovery is
desired. WDTOUT can be connected directly to NMI
or one of the INT input pins. The WDT may also be
used as a general purpose timer.
Power Management Unit
The 80C186EC Power Management Unit (PMU) is
provided to control the power consumption of the
device. The PMU provides four power management
modes: Active, Powersave, Idle and Powerdown.
Active Mode indicates that all units on the
80C186EC are operating at ½ the CLKIN frequency.
Idle Mode freezes the clocks of the Execution and
Bus units at a logic zero state (all peripherals contin-
ue to operate normally).
The Powerdown Mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator.
In Powersave Mode, all internal clock signals are di-
vided by a programmable prescalar (up to 1/64 the
normal frequency). Powersave Mode can be used
with Idle Mode as well as during normal (Active
Mode) operation.
80C187 Interface (80C186EC only)
The 80C186EC supports the direct connection of
the 80C187 Numerics Processor Extension. The
80C187 can dramatically improve the performance
of calculation intensive applications.
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system, the 80C186EC has a test
mode available which forces all output and input/
output pins to be placed in the high-impedance
state. ONCE stands for ‘‘ON Circuit Emulation’’,
The ONCE mode is selected by forcing the
A19/S6/ONCE pin low during a processor reset
(this pin is weakly held high during reset to prevent
inadvertant entrance into ONCE Mode).
PACKAGE INFORMATION
This section describes the pin functions, pinout and
thermal characteristics for the 80C186EC in the
Plastic Quad Flat Pack (JEDEC PQFP), the EIAJ
Quad Flat Pack (QFP) and the Shrink Quad Flat
Pack (SQFP). For complete package specifications
8
and information, see the Intel Packaging Outlines
and Dimensions Guide (Order Number: 231369).
Prefix Identification
Table 1 lists the prefix identifications.
Table 1: Prefix Identification
Prefix Note
Package
Type
Temperature
Range
x QFP (EIAJ) Extended
x 1 PQFP Extended/Commercial
x 1 SQFP Extended/Commercial
x 1 QFP (EIAJ) Commercial
NOTE:
1. The 5V 25 MHz version is only available in commercial
temperature range corresponding to 0 ˚C to a 70°C am-
bient.
1. To address the fact that many of the package prefix variables
have changed, all package prefix variables in this document
are now indicated with an "x".
Pin Descriptions
Each pin or logical set of pins is described in Table
2, There are four columns for each entry in the Pin
Description Table. The following sections describe
each column.
Column 1. Pin Name
In this column is a mnemonic that de-
scribes the pin function. Negation of the
signal name (i.e. RESIN) implies that the
signal is active low.
Column 2. Pin Type
A pin may be either power (P), ground
(G), input only (I), output only (O) or in-
put/output (I/O). Please note that some
pins have more than 1 function.
A19/S6/ONCE , for example, is normally
an output but functions as an input dur-
ing reset. For this reason
A19/S6/ONCE is classified as an input/
output pin.
Column 3. Input Type (for I and I/O types only)
There are two different types of input
pins on the 80C186EC: asynchronous
and synchronous. Asynchronous pins
require that setup and hold times be met
only to guarantee recognition . Synchro-
nous input pins require that the setup
and hold times be met to guarantee
proper operation . Stated simply, missing
a setup or hold on an asynchronous pin
will result in something minor (i.e. a timer
count will be missed) whereas missing a
setup or hold on a synchronous pin will
result in system failure (the system will
‘‘lock up’’).
An input pin may also be edge or level
sensitive.


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Column 4 Output States (for O and I O types
only)
The state of an output or I O pin is de-
pendent on the operating mode of the
device There are four modes of opera-
tion that are different from normal active
mode Bus Hold Reset Idle Mode Pow-
erdown Mode This column describes
the output pin state in each of these
modes
The legend for interpreting the information in the Pin
Descriptions is shown in Table 1
As an example please refer to the table entry for
AD12 0 The ‘‘I O’’ signifies that the pins are bidirec-
tional (i e have both an input and output function)
The ‘‘S’’ indicates that as an input the signal must
be synchronized to CLKOUT for proper operation
The ‘‘H(Z)’’ indicates that these pins will float while
the processor is in the Hold Acknowledge state
R(Z) indicates that these pins will float while RESIN
is low P(0) and I(0) indicate that these pins will drive
0 when the device is in either Powerdown or Idle
Mode
Some pins the I O Ports for example can be pro-
grammed to perform more than one function Multi-
function pins have a ‘‘ ’’ in their signal name be-
tween the different functions (i e P3 0 RXI1) If the
input pin type or output pin state differ between func-
tions then that will be indicated by separating the
state (or type) with a ‘‘ ’’ (i e H(X) H(Q)) In this
example when the pin is configured as P3 0 then its
hold output state is H(X) when configured as RXI1
its output state is H(Q)
All pins float while the processor is in the ONCE
Mode (with the exception of OSCOUT)
Symbol
P
G
I
O
IO
S(E)
S(L)
A(E)
A(L)
H(1)
H(0)
H(Z)
H(Q)
H(X)
R(WH)
R(1)
R(0)
R(Z)
R(Q)
R(X)
I(1)
I(0)
I(Z)
I(Q)
I(X)
P(1)
P(0)
P(Z)
P(Q)
P(X)
Table 1 Pin Description Nomenclature
Description
Power Pin (apply a VCC voltage)
Ground (connect to VSS)
Input only pin
Output only pin
Input Output pin
Synchronous edge sensitive
Synchronous level sensitive
Asynchronous edge sensitive
Asynchronous level sensitive
Output driven to VCC during bus hold
Output driven to VSS during bus hold
Output floats during bus hold
Output remains active during bus hold
Output retains current state during bus hold
Output weakly held at VCC during reset
Output driven to VCC during reset
Output driven to VSS during reset
Output floats during reset
Output remains active during reset
Output retains current state during reset
Output driven to VCC during Idle Mode
Output driven to VSS during Idle Mode
Output floats during Idle Mode
Output remains active during Idle Mode
Output retains current state during Idle Mode
Output driven to VCC during Powerdown Mode
Output driven to VSS during Powerdown Mode
Output floats during Powerdown Mode
Output remains active during Powerdown Mode
Output retains current state during Powerdown Mode
9


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Pin Name
VCC
VSS
CLKIN
OSCOUT
CLKOUT
RESIN
RESOUT
PDTMR
NMI
TEST BUSY
(TEST)
A19 S6 ONCE
Pin
Type
P
G
I
O
O
I
O
IO
I
I
IO
Input
Type
A(E)
A(L)
A(L)
A(E)
A(E)
A(L)
Table 2 Pin Descriptions
Output
States
Pin Description
POWER a5V g10% power supply connection
GROUND
CLocK INput is the external clock input An external
oscillator operating at two times the required processor
operating frequency can be connected to CLKIN For
crystal operation CLKIN (along with OSCOUT) are the
crystal connections to an internal Pierce oscillator
H(Q)
R(Q)
I(Q)
P(X)
OSCillator OUTput is only used when using a crystal to
generate the internal clock OSCOUT (along with CLKIN)
are the crystal connections to an internal Pierce oscillator
This pin can not be used as 2X clock output for non-
crystal applications (i e this pin is not connected for non-
crystal applications)
H(Q)
R(Q)
I(Q)
P(X)
CLocK OUTput provides a timing reference for inputs and
outputs of the processor and is one-half the input clock
(CLKIN) frequency CLKOUT has a 50% duty cycle and
transitions every falling edge of CLKIN
RESet IN causes the processor to immediately terminate
any bus cycle in progress and assume an initialized state
All pins will be driven to a known state and RESOUT will
also be driven active The rising edge (low-to-high)
transition synchronizes CLKOUT with CLKIN before the
processor begins fetching opcodes at memory location
0FFFF0H
H(0) RESet OUTput that indicates the processor is currently in
R(1) the reset state RESOUT will remain active as long as
I(0) RESIN remains active
P(0)
H(WH)
R(Z)
P(WH)
I(WH)
Power-Down TiMeR pin (normally connected to an
external capacitor) that determines the amount of time the
processors waits after an exit from Powerdown before
resuming normal operation The duration of time required
will depend on the startup characteristics of the crystal
oscillator
Non-Maskable Interrupt input causes a TYPE-2 interrupt
to be serviced by the CPU NMI is latched internally
TEST is used during the execution of the WAIT instruction
to suspend CPU operation until the pin is sampled active
(LOW) TEST is alternately known as BUSY when
interfacing with an 80C187 numerics coprocessor
(80C186EC only)
H(Z)
R(WH)
I(0)
P(0)
This pin drives address bit 19 during the address phase of
the bus cycle During T2 and T3 this pin functions as
status bit 6 S6 is low to indicate CPU bus cycles and high
to indicate DMA or refresh bus cycles During a processor
reset (RESIN active) this pin becomes the ONCE input
pin Holding this pin low during reset will force the part into
ONCE Mode
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
10


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Pin Name
A18 S5
A17 S4
A16 S3
(A15 8)
AD15 CAS2
AD14 CAS1
AD13 CAS0
AD12 0
(AD7 0)
S2 0
ALE
BHE
(RFSH)
Pin
Type
IO
IO
IO
O
O
O
Input
Type
A(L)
S(L)
S(L)
Table 2 Pin Descriptions (Continued)
Output
States
Pin Description
H(Z)
R(WH)
I(0)
P(0)
These pins drive address information during the address
phase of the bus cycle During T2 and T3 these pins drive
status information (which is always 0 on the 80C186EC)
These pins are used as inputs during factory test driving
these pins low during reset will cause unspecified operation
On the 80C188EC A15 8 provide valid address information
for the entire bus cycle
H(Z)
R(Z)
I(0)
P(0)
These pins are part of the multiplexed ADDRESS and DATA
bus During the address phase of the bus cycle address bits
15 through 13 are presented on these pins and can be
latched using ALE Data information is transferred during the
data phase of the bus cycle Pins AD15 13 CAS2 0 drive the
82C59 slave address information during interrupt
acknowledge cycles
H(Z)
R(Z)
I(0)
P(0)
These pins provide a multiplexed ADDRESS and DATA bus
During the address phase of the bus cycle address bits 0
through 12 (0 through 7 on the 80C188EC) are presented on
the bus and can be latched using ALE Data information is
transferred during the data phase of the bus cycle
H(Z)
R(1)
I(1)
P(1)
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
S2 S1 S0
Bus Cycle Initiated
000
001
010
011
100
101
110
111
Interrupt Acknowledge
Read I O
Write I O
Processor HALT
Instruction Queue Fetch
Read Memory
Write Memory
Passive (No bus activity)
H(0) Address Latch Enable output is used to strobe address
R(0) information into a transparent type latch during the address
I(0) phase of the bus cycle
P(0)
H(Z)
R(Z)
I(1)
P(1)
Byte High Enable output to indicate that the bus cycle in
progress is transferring data over the upper half of the data
bus BHE and A0 have the following logical encoding
A0 BHE
Encoding (for 80C186EC
80L186EC only)
00
01
10
11
Word transfer
Even Byte transfer
Odd Byte transfer
Refresh operation
On the 80C188EC 80L188EC RFSH is asserted low to
indicate a refresh bus cycle
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
11


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Pin Name
RD
WR
READY
DEN
DT R
LOCK
HOLD
HLDA
NCS
ERROR
Pin
Type
O
O
I
O
O
IO
I
O
O
I
Input
Type
A(L)
S(L)
(Note 1)
A(L)
A(L)
A(L)
Table 2 Pin Descriptions (Continued)
Output
States
Pin Description
H(Z)
R(Z)
I(1)
P(1)
ReaD output signals that the accessed memory or I O
device should drive data information onto the data bus
H(Z)
R(Z)
I(1)
P(1)
WRite output signals that data available on the data bus are
to be written into the accessed memory or I O device
READY input to signal the completion of a bus cycle READY
must be active to terminate any 80C186EC bus cycle unless
it is ignored by correctly programming the Chip-Select unit
H(Z)
R(Z)
I(1)
P(1)
H(Z)
R(Z)
I(X)
P(X)
H(Z)
R(Z)
I(X)
P(X)
H(1)
R(0)
I(0)
P(0)
H(1)
R(1)
I(1)
P(1)
Data ENable output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when
data is to be transferred on the bus
Data Transmit Receive output controls the direction of a bi-
directional buffer in a buffered system
LOCK output indicates that the bus cycle in progress is not
interruptable The processor will not service other bus
requests (such as HOLD) while LOCK is active This pin is
configured as a weakly held high input while RESIN is active
and must not be driven low
HOLD request input to signal that an external bus master
wishes to gain control of the local bus The processor will
relinquish control of the local bus between instruction
boundaries that are not LOCKed
HoLD Acknowledge output to indicate that the processor
has relinquished control of the local bus When HLDA is
asserted the processor will (or has) floated its data bus and
control signals allowing another bus master to drive the
signals directly
Numerics Coprocessor Select output is generated when
acessing a numerics coprocessor This signal does not exist
on the 80C188EC 80L188EC
ERROR input that indicates the last numerics processor
extension operation resulted in an exception condition An
interrupt TYPE 16 is generated if ERROR is sampled active
at the beginning of a numerics operation Systems not using
an 80C187 must tie ERROR to VCC This signal does not
exist on the 80C188EC 80L188EC
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
12


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Pin Name
PEREQ
UCS
LCS
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
T0OUT
T1OUT
T0IN
T1IN
INT7 0
INTA
P3 5
P3 4
P3 3 DMAI1
P3 2 DMAI0
Pin
Type
I
O
O
O
O
I
I
O
IO
O
Input
Type
A(L)
Table 2 Pin Descriptions (Continued)
Output
States
Pin Description
Processor Extension REQuest signals that a data
transfer between an 80C187 Numerics Processor
Extension and Memory is pending Systems not using an
80C187 must tie this pin to VSS This signal does not exist
on the 80C188EC 80L188EC
H(1) Upper Chip Select will go active whenever the address of
R(1) a memory or I O bus cycle is within the address range
I(1) programmed by the user After reset UCS is configured to
P(1) be active for memory accesses between 0FFC00H and
0FFFFFH
H(1) Lower Chip Select will go active whenever the address of
R(1) a memory or I O bus cycle is within the address range
I(1) programmed by the user LCS is inactive after a reset
P(1)
H(X) H(1)
R(1)
I(X) I(1)
P(X) P(1)
These pins provide a multiplexed function If enabled
each pin can provide a General purpose Chip Select
output which will go active whenever the address of a
memory or I O bus cycle is within the address limitations
programmed by the user When not programmed as a
Chip-Select each pin may be used as a general purpose
output port
H(Q)
R(1)
I(Q)
P(X)
Timer OUTput pins can be programmed to provide single
clock or continuous waveform generation depending on
the timer mode selected
A(L) Timer INput is used either as clock or control signals
A(E) depending on the timer mode selected This pin may be
either level or edge sensitive depending on the
programming mode
A(L) Maskable INTerrupt input will cause a vector to a specific
A(E) Type interrupt routine The INT6 0 pins can be used as
cascade inputs from slave 8259A devices The INT pins
can be configured as level or edge sensitive
H(1) INTerrupt Acknowledge output is a handshaking signal
R(1) used by external 82C59A Programmable Interrupt
I(1) Controllers
P(1)
A(L)
H(X)
Bidirectional open-drain port pins
R(Z)
I(X)
H(X)
H(X)
R(0)
I(Q)
P(X)
DMA Interrupt output goes active to indicate that the
channel has completed a transfer DMAI1 and DMAI0 are
multiplexed with output only port functions
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
13


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Pin Name
P3 1 TXI1
P3 0 RXI1
WDTOUT
P2 7 CTS1
P2 3 CTS0
P2 6 BCLK1
P2 2 BCLK0
P2 5 TXD1
P2 1 TXD0
P2 4 RXD1
P2 0 RXD0
DRQ3 0
Pin
Type
O
O
O
IO
IO
IO
IO
I
Input
Type
A(L)
A(L)
A(E)
A(L)
A(L)
A(L)
Table 2 Pin Descriptions (Continued)
Output
States
Pin Description
H(X) H(Q)
R(0)
I(Q)
P(X)
Transmit Interrupt output goes active to indicate that
serial channel 1 has completed a transfer TXI1 is
multiplexed with an output only Port function
H(X) H(Q)
R(0)
I(Q)
P(X)
Receive Interrupt output goes active to indicate that
serial channel 1 has completed a reception RXI1 is
multiplexed with an output only port function
H(Q)
R(1)
I(Q)
P(X)
WatchDog Timer OUTput is driven low for four clock
cycles when the watchdog timer reaches zero WDTOUT
may be ANDed with the power-on reset signal to reset the
processor when the watchdog timer is not properly reset
H(X)
R(Z)
I(X)
P(X)
Clear-To-Send input is used to prevent the transmission
of serial data on the TXD signal pin CTS1 and CTS0 are
multiplexed with an I O Port function
H(X)
R(Z)
I(X)
P(X)
Baud CLocK input can be used as an alternate clock
source for each of the integrated serial channels The
BCLK inputs are multiplexed with I O Port functions The
BCLK input frequency cannot exceed the operating
frequency of the processor
H(Q)
R(Z)
I(X) I(Q)
P(X)
Transmit Data output provides serial data information
The TXD outputs are multiplexed with I O Port functions
During synchronous serial communications TXD will
function as a clock output
H(X) H(Q)
R(Z)
I(X) I(Q)
P(X)
Receive Data input accepts serial data information The
RXD pins are multiplexed with I O Port functions During
synchronous serial communications RXD is bi-directional
and will become an output for transmission of data (TXD
becomes the clock)
DMA ReQuest input pins are used to request a DMA
transfer The timing of the request is dependent on the
programmed synchronization mode
NOTES
1 READY is A(E) for the rising edge of CLKOUT S(E) for the falling edge of CLKOUT
2 Pin names in parentheses apply to the 80C188EC 80L188EC
14


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Pinout
Tables 3 and 4 list the pin names with package loca-
tion for the 100-pin Plastic Quad Flat Pack (PQFP)
component Figure 4 depicts the PQFP package as
viewed from the top side of the component (i e con-
tacts facing down)
Tables 5 and 6 list the pin names with package loca-
tion for the 100-pin EIAJ Quad Flat Pack (QFP) com-
ponent Figure 5 depicts the QFP package as viewed
from the top side of the component (i e contacts
facing down)
Tables 7 and 8 list the pin names with package loca-
tion for the 100-pin Shrink Quad Flat Pack (SQFP)
component Figure 6 depicts the SQFP package as
viewed from the top side of the component (i e con-
tacts facing down)
AD Bus
Name
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 CAS0
(A13 CAS0)
AD14 CAS1
(A14 CAS1)
AD15 CAS2
(A15 CAS2)
A16 S3
A17 S4
A18 S5
A19 S6 ONCE
Pin
73
72
71
70
66
65
64
63
60
59
58
57
56
55
54
53
77
76
75
74
Table 3 PQFP Pin Functions with Location
Bus Control
Processor Control
Name
Pin
Name
Pin
ALE
BHE (RFSH)
S0
S1
S2
RD
WR
READY
DEN
DT R
LOCK
HOLD
HLDA
INTA
52
51
78
79
80
50
49
85
47
46
48
44
45
34
Power and Ground
Name
Pin
VCC 13
VCC 14
VCC 38
VCC 62
VCC 67
VCC 69
VCC 86
VSS 12
VSS 15
VSS 37
VSS 39
VSS 61
VSS 68
VSS 87
RESIN
RESOUT
CLKIN
OSCOUT
CLKOUT
TEST BUSY
(TEST)
PEREQ (VSS)
NCS (N C )
ERROR (VCC)
PDTMR
NMI
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
8
7
10
11
6
83
81
35
84
9
82
30
31
32
33
40
41
42
43
IO
Name
UCS
LCS
P1 7 GCS7
P1 6 GCS6
P1 5 GCS5
P1 4 GCS4
P1 3 GCS3
P1 2 GCS2
P1 1 GCS1
P1 0 GCS0
P2 7 CTS1
P2 6 BCLK1
P2 5 TXD1
P2 4 RXD1
P2 3 CTS0
P2 2 BCLK0
P2 1 TXD0
P2 0 RXD0
P3 5
P3 4
P3 3 DMAI1
P3 2 DMAI0
P3 1 TXI1
P3 0 RXI1
T0IN
T0OUT
T1IN
T1OUT
DRQ0
DRQ1
DRQ2
DRQ3
Pin
88
89
90
91
92
93
94
95
96
97
23
22
21
20
19
18
17
16
29
28
27
26
25
24
3
2
5
4
98
99
100
1
WDTOUT
36
15


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Pin Name
1 DRQ3
2 T0OUT
3 T0IN
4 T1OUT
5 T1IN
6 CLKOUT
7 RESOUT
8 RESIN
9 PDTMR
10 CLKIN
11 OSCOUT
12 VSS
13 VCC
14 VCC
15 VSS
16 P2 0 RXD0
17 P2 1 TXD0
18 P2 2 BCLK0
19 P2 3 CTS0
20 P2 4 RXD1
21 P2 5 TXD1
22 P2 6 BCLK1
23 P2 7 CTS1
24 P3 0 RXI1
25 P3 1 TXI1
Table 4 PQFP Pin Locations with Pin Name
Pin Name
Pin Name
26 DMAI0 P3 2
27 DMAI1 P3 3
28 P3 4
29 P3 5
30 INT0
31 INT1
32 INT2
33 INT3
34 INTA
35 NCS (N C )
36 WDTOUT
37 VSS
38 VCC
39 VSS
40 INT4
41 INT5
42 INT6
43 INT7
44 HOLD
45 HLDA
46 DT R
47 DEN
48 LOCK
49 WR
50 RD
51 BHE (RFSH)
52 ALE
53 AD15 (A15)
54 AD14 (A14)
55 AD13 (A13)
56 AD12 (A12)
57 AD11 (A11)
58 AD10 (A10)
59 AD9 (A9)
60 AD8 (A8)
61 VSS
62 VCC
63 AD7
64 AD6
65 AD5
66 AD4
67 VCC
68 VSS
69 VCC
70 AD3
71 AD2
72 AD1
73 AD0
74 A19 S6 ONCE
75 A18 S5
Pin Name
76 A17 S4
77 A16 S3
78 S0
79 S1
80 S2
81 PEREQ (VSS)
82 NMI
83 TEST
84 ERROR (VCC)
85 READY
86 VCC
87 VSS
88 UCS
89 LCS
90 P1 7 GCS7
91 P1 6 GCS6
92 P1 5 GCS5
93 P1 4 GCS4
94 P1 3 GCS3
95 P1 2 GCS2
96 P1 1 GCS1
97 P1 0 GCS0
98 DRQ0
99 DRQ1
100 DRQ2
16


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC/188EC, 80L186EC/188EC
x
NOTE:
This is the FPO number location (indicated by X’s).
Figure 4. 100-Pin Plastic Quad Flat Pack Package (PQFP)
272434 – 3
17


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
AD Bus
Name
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 CAS0
(A13 CAS0)
AD14 CAS1
(A14 CAS1)
AD15 CAS2
(A15 CAS2)
A16 S3
A17 S4
A18 S5
A19 S6 ONCE
Pin
76
75
74
73
69
68
67
66
63
62
61
60
59
58
57
56
80
79
78
77
Table 5 QFP Pin Names with Package Location
Bus Control
Processor Control
Name
Pin
Name
Pin
ALE
BHE (RFSH)
S0
S1
S2
RD
WR
READY
DEN
DT R
LOCK
HOLD
HLDA
INTA
55
54
81
82
83
53
52
88
50
49
51
47
48
37
Power and Ground
Name
Pin
VCC 16
VCC 17
VCC 41
VCC 65
VCC 70
VCC 72
VCC 89
VSS 15
VSS 18
VSS 40
VSS 42
VSS 64
VSS 71
VSS 90
RESIN
RESOUT
CLKIN
OSCOUT
CLKOUT
TEST BUSY
(TEST)
PEREQ (VSS)
NCS (N C )
ERROR (VCC)
PDTMR
NMI
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
11
10
13
14
9
86
84
38
87
12
85
33
34
35
36
43
44
45
46
IO
Name
UCS
LCS
P1 7 GCS7
P1 6 GCS6
P1 5 GCS5
P1 4 GCS4
P1 3 GCS3
P1 2 GCS2
P1 1 GCS1
P1 0 GCS0
P2 7 CTS1
P2 6 BCLK1
P2 5 TXD1
P2 4 RXD1
P2 3 CTS0
P2 2 BCLK0
P2 1 TXD0
P2 0 RXD0
P3 5
P3 4
P3 3 DMAI1
P3 2 DMAI0
P3 1 TXI1
P3 0 RXI1
T0IN
T0OUT
T1IN
T1OUT
DRQ0
DRQ1
DRQ2
DRQ3
WDTOUT
Pin
91
92
93
94
95
96
97
98
99
100
26
25
24
23
22
21
20
19
32
31
30
29
28
27
6
5
8
7
1
2
3
4
39
18


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Pin Name
1 DRQ0
2 DRQ1
3 DRQ2
4 DRQ3
5 T0OUT
6 T0IN
7 T1OUT
8 T1IN
9 CLKOUT
10 RESOUT
11 RESIN
12 PDTMR
13 CLKIN
14 OSCOUT
15 VSS
16 VCC
17 VCC
18 VSS
19 P2 0 RXD0
20 P2 1 TXD0
21 P2 2 BCLK0
22 P2 3 CTS0
23 P2 4 RXD1
24 P2 5 TXD1
25 P2 6 BCLK1
Table 6 QFP Package Location with Pin Names
Pin Name
Pin Name
26 P2 7 CTS1
27 P3 0 RXI1
28 P3 1 TXI1
29 DMAI0 P3 2
30 DMAI1 P3 3
31 P3 4
32 P3 5
33 INT0
34 INT1
35 INT2
36 INT3
37 INTA
38 NCS (N C )
39 WDTOUT
40 VSS
41 VCC
42 VSS
43 INT4
44 INT5
45 INT6
46 INT7
47 HOLD
48 HLDA
49 DT R
50 DEN
51 LOCK
52 WR
53 RD
54 BHE (RFSH)
55 ALE
56 AD15 (A15)
57 AD14 (A14)
58 AD13 (A13)
59 AD12 (A12)
60 AD11 (A11)
61 AD10 (A10)
62 AD9 (A9)
63 AD8 (A8)
64 VSS
65 VCC
66 AD7
67 AD6
68 AD5
69 AD4
70 VCC
71 VSS
72 VCC
73 AD3
74 AD2
75 AD1
Pin Name
76 AD0
77 A19 S6 ONCE
78 A18 S5
79 A17 S4
80 A16 S3
81 S0
82 S1
83 S2
84 PEREQ (VSS)
85 NMI
86 TEST
87 ERROR (VCC)
88 READY
89 VCC
90 VSS
91 UCS
92 LCS
93 P1 7 GCS7
94 P1 6 GCS6
95 P1 5 GCS5
96 P1 4 GCS4
97 P1 3 GCS3
98 P1 2 GCS2
99 P1 1 GCS1
100 P1 0 GCS0
19


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC/188EC, 80L186EC/188EC
x
NOTE:
This is the FPO number location (indicated by X’s).
Figure 5: Quad Flat Pack (EIAJ) Pinout Diagram
272434 – 4
20


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

AD Bus
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 (A13)
AD14 (A14)
AD15 (A15)
A16
A17
A18
A19 ONCE
73
72
71
70
66
65
64
63
60
59
58
57
56
55
54
53
77
76
75
74
80C186EC 188EC 80L186EC 188EC
Table 7 SQFP Pin Functions with Location
Bus Control
Processor Control
ALE
BHE (RFSH)
S0
S1
S2
RD
WR
READY
DT R
DEN
LOCK
HOLD
HLDA
52
51
78
79
80
50
49
85
46
47
48
44
45
RESIN
RESOUT
CLKIN
OSCOUT
CLKOUT
TEST BUSY
NMI
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INTA
PEREQ (VSS)
ERROR (VCC)
NCS (N C )
PDTMR
8
7
10
11
6
83
82
30
31
32
33
40
41
42
43
34
81
84
35
9
Power and Ground
VCC 13
VCC 14
VCC 38
VCC 62
VCC 67
VCC 69
VCC 86
VSS 12
VSS 15
VSS 37
VSS 39
VSS 61
VSS 68
VSS 87
UCS
LCS
IO
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
P2 0 RXD0
P2 1 TXD0
P2 2 BCLK0
P2 3 CTS0
P2 4 RXD1
P2 5 TXD1
P2 6 BCLK1
P2 7 CTS1
P3 0 RXI1
P3 1 TXI1
P3 2 DMAI0
P3 3 DMAI1
P3 4
P3 5
DRQ0
DRQ1
DRQ2
DRQ3
T0IN
T0OUT
T1IN
T1OUT
WDTOUT
88
89
97
96
95
94
93
92
91
90
16
17
18
19
20
21
22
23
24
25
26
27
28
29
98
99
100
1
3
2
5
4
36
21


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Pin Name
1 DRQ3
2 T0OUT
3 T0IN
4 T1OUT
5 T1IN
6 CLKOUT
7 RESOUT
8 RESIN
9 PDTMR
10 CLKIN
11 OSCOUT
12 VSS
13 VCC
14 VCC
15 VSS
16 P2 0 RXD0
17 P2 1 TXD0
18 P2 2 BCLK0
19 P2 3 CTS0
20 P2 4 RXD1
21 P2 5 TXD1
22 P2 6 BCLK1
23 P2 7 CTS1
24 P3 0 RXI1
25 P3 1 TXI1
Table 8 SQFP Pin Locations with Pin Names
Pin Name
Pin Name
26 P3 2 DMAI0
27 P3 3 DMAI1
28 P3 4
29 P3 5
30 INT0
31 INT1
32 INT2
33 INT3
34 INTA
35 NSC (N C )
36 WDTOUT
37 VSS
38 VCC
39 VSS
40 INT4
41 INT5
42 INT6
43 INT7
44 HOLD
45 HLDA
46 DT R
47 DEN
48 LOCK
49 WR
50 RD
51 BHE (RFSH)
52 ALE
53 AD15 (A15)
54 AD14 (A14)
55 AD13 (A13)
56 AD12 (A12)
57 AD11 (A11)
58 AD10 (A10)
59 AD9 (A9)
60 AD8 (A8)
61 VSS
62 VCC
63 AD7 (A7)
64 AD6 (A6)
65 AD5
66 AD4
67 VCC
68 VSS
69 VCC
70 AD3
71 AD2
72 AD1
73 AD0
74 A19 ONCE
75 AD18
Pin Name
76 A17
77 A16
78 S0
79 S1
80 S2
81 PEREQ (VSS)
82 MNI
83 TEST BUSY
(TEST)
84 ERROR (VCC)
85 READY
86 VCC
87 VSS
88 UCS
89 LCS
90 P1 7 GCS7
91 P1 6 GS6
92 P1 5 GCS5
93 P1 4 GCS4
94 P1 3 GCS3
95 P1 2 GCS2
96 P1 1 GCS1
97 P1 0 GCS0
98 DRQ0
99 DRQ1
100 DRQ2
22


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC/188EC, 80L186EC/188EC
x
NOTE:
This is the FPO number location (indicated by X’s)
Figure 6: 100-Pin Shrink Quad Flat Pack Package (SQFP)
272434 – 5
23


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
Package Thermal Specifications
The 80C186EC 80L186EC is specified for operation
when TC (the case temperature) is within the range
of b40 C to a100 C TC may be measured in any
environment to determine whether the processor is
within the specified operating range The case tem-
perature must be measured at the center of the top
surface
TA (the ambient temperature) can be calculated
from iCA (thermal resistance from the case to ambi-
ent) with the following equation
TA e TC b P iCA
Typical values for iCA at various airflows are given
in Table 9 P (the maximum power consumption
specified in Watts) is calculated by using the maxi-
mum ICC and VCC of 5 5V
iCA (PQFP)
iCA (QFP)
iCA (SQFP)
Table 9 Thermal Resistance (iCA) at Various Airflows (in C Watt)
Airflow in ft min (m sec)
0 200 400 600 800
(0)
(1 01)
(2 03)
(3 04)
(4 06)
27 0
22 0
18 0
15 0
14 0
64 5
55 5
51 0
TBD
TBD
62 0
TBD
TBD
TBD
TBD
1000
(5 07)
13 5
TBD
TBD
24


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Storage Temperature
b65 C to a150 C
Case Temperature Under Bias b65 C to a100 C
Supply Voltage
with Respect to VSS
Voltage on Other Pins
with Respect to VSS
b0 5V to a6 5V
b0 5V to VCC a 0 5V
NOTICE This data sheet contains preliminary infor-
mation on new products in production The specifica-
tions are subject to change without notice Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
Recommended Connections
Power and ground connections must be made to
multiple VCC and VSS pins Every 80C186EC-based
circuit board should include separate power (VCC)
and ground (VSS) planes Every VCC pin must be
connected to the power plane and every VSS pin
must be connected to the ground plane Liberal de-
coupling capacitance should be placed near the
processor The processor can cause transient pow-
er surges when its output buffers transition particu-
larly when connected to large capacitive loads
Low inductance capacitors and interconnects are
recommended for best high frequency electrical per-
formance Inductance is reduced by placing the de-
coupling capacitors as close as possible to the proc-
essor VCC and VSS package pins
Always connect any unused input to an appropriate
signal level In particular unused interrupt inputs
(NMI INT0 7) should be connected to VSS through a
pull-down resistor Leave any unused output pin un-
connected
25


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
DC SPECIFICATIONS (80C186EC 80C188EC)
Symbol
Parameter
Min
VCC
VIL
VIH
VOL
VOH
VHYR
ILI
Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Hysteresis on RESIN
Input Leakage Current for Pins
AD15 0 (AD7 0 A15 8) READY
HOLD RESIN
CLKIN TEST BUSY NMI INT7 0
T0IN T1IN P2 7–P2 0 P3 5–P3 0
DRQ3 0 PEREQ ERROR
45
b0 5
0 7 VCC
VCC b 0 5
05
ILIU Input Leakage for Pins with Pullups b0 275
Active During Reset
A19 16 LOCK
ILO Output Leakage for Floated Output
Pins
ICC Supply Current Cold (in RESET)
80C186EC25
80C186EC20
80C186EC13
IID Supply Current in Idle Mode
80C186EC25
80C186EC20
80C186EC13
IPD Supply Current in Powerdown Mode
80C186EC25
80C186EC20
80C186EC13
CIN
COUT
Input Pin Capacitance
Output Pin Capacitance
0
0
Max
55
0 3 VCC
VCC a 0 5
0 45
g15
b5
g15
125
100
70
92
76
50
100
100
100
15
15
Units
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
pF
pF
Notes
IOL e 3 mA (Min)
IOH e b2 mA (Min)
0 s VIN s VCC
VIN e 0 7 VCC
(Note 1)
0 45 s VOUT s VCC
(Note 2)
(Notes 3 7)
(Note 3)
(Note 3)
(Notes 4 7)
(Note 4)
(Note 4)
(Notes 5 7)
(Note 5)
(Note 5)
TF e 1 MHz
TF e 1 MHz (Note 6)
NOTES
1 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more
current than specified (on any of these pins) may invoke a factory test mode
2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD
3 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as
specified in AC Test Conditions and all floating outputs driven to VCC or GND
4 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL
outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
5 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with
ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
6 Output Capacitance is the capacitive load of a floating output pin
7 Operating conditions for 25 MHz is 0 C to a70 C VCC e 5 0 g10%
26


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
DC SPECIFICATIONS (80L186EC13 80L188EC13)
Symbol
Parameter
Min Max
VCC
VIL
VIH
VOL
VOH
VHYR
ILI
Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Hysteresis on RESIN
Input Leakage Current for Pins
AD15 0 (AD7 0 A15 8) READY
HOLD RESIN CLKIN
TEST BUSY NMI INT7 0
T0IN T1IN P2 7–P2 0 P3 5–P3 0
DRQ3 0 PEREQ ERROR
27
b0 5
0 7 VCC
VCC b 0 5
05
55
0 3 VCC
VCC a 0 5
0 45
g15
ILIU Input Leakage for Pins with Pullups b0 275
Active During Reset
A19 16 LOCK
b5
ILO Output Leakage for Floated Output
Pins
g15
ICC Supply Current Cold (in RESET)
80L186EC-13
36
IID Supply Current in Idle Mode
80L186EC-13
24
IPD Supply Current in Powerdown Mode
80L186EC-13
30
CIN
COUT
Input Pin Capacitance
Output Pin Capacitance
0 15
0 15
Units
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
pF
pF
Notes
IOL e 3 mA (Min)
IOH e b2 mA (Min)
0 s VIN s VCC
VIN e 0 7 VCC
(Note 1)
0 45 s VOUT s VCC
(Note 2)
(Note 3)
(Note 4)
(Note 5)
TF e 1 MHz
TF e 1 MHz (Note 6)
NOTES
1 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more
current than specified (on any of these pins) may invoke a factory test mode
2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD
3 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as
specified in AC Test Conditions and all floating outputs driven to VCC or GND
4 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL
outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
5 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with
ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
6 Output Capacitance is the capacitive load of a floating output pin
27


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
DC SPECIFICATIONS (80L186EC16 80L188EC16) (Operating Temperature 0 C to 70 C)
Symbol
Parameter
Min
Max
Units
Notes
VCC
VIL
VIH
VOL
VOH
VHYR
ILI
Supply Voltage
30 55 V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Hysteresis on RESIN
b0 5
0 3 VCC
V
0 7 VCC VCC a 0 5 V
0 45
V IOL e 3 mA (Min)
VCC b 0 5
V IOH e b2 mA (Min)
05 V
Input Leakage Current for Pins
AD15 0 (AD7 0 A15 8) READY
HOLD RESIN CLKIN
TEST BUSY NMI INT7 0
T0IN T1IN P2 7–P2 0 P3 5–P3 0
DRQ3 0 PEREQ ERROR
g15
mA 0 s VIN s VCC
ILIU Input Leakage for Pins with Pullups b0 275 b5 mA VIN e 0 7 VCC
Active During Reset
(Note 1)
A19 16 LOCK
ILO Output Leakage for Floated Output
Pins
g15
mA 0 45 s VOUT s VCC
(Note 2)
ICC Supply Current Cold (in RESET)
80L186EC-16
(Note 3)
45 mA
IID Supply Current in Idle Mode
80L186EC-16
(Note 4)
35 mA
IPD Supply Current in Powerdown Mode
80L186EC-16
(Note 5)
50 mA
CIN
COUT
Input Pin Capacitance
Output Pin Capacitance
0 15 pF TF e 1 MHz
0 15 pF TF e 1 MHz (Note 6)
NOTES
1 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more
current than specified (on any of these pins) may invoke a factory test mode
2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD
3 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as
specified in AC Test Conditions and all floating outputs driven to VCC or GND
4 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL
outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
5 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with
ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
6 Output Capacitance is the capacitive load of a floating output pin
28


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
ICC versus Frequency and Voltage
The ICC consumed by the processor is composed of
two components
1 IPD The quiescent current that represents inter-
nal device leakage Measured with all inputs at
either VCC or ground and no clock applied
2 ICCS The switching current used to charge and
discharge internal parasitic capacitance when
changing logic levels ICCS is related to both the
frequency of operation and the device supply
voltage (VCC) ICCS is given by the formula
Power e V I e V2 CDEV f
ICCS e V CDEV f
Where
V e Supply Voltage (VCC)
CDEV e Device Capacitance
f e Operating Frequency
Measuring CPD on a device like the 80C186EC
would be difficult Instead CPD is calculated using
the above formula with ICC values measured at
known VCC and frequency Using the CPD value the
user can calculate ICC at any voltage and frequency
within the specified operating range
Example Calculate typical ICC at 14 MHz 5 2V VCC
ICC e IPD a ICCS
e 0 1 mA a 5 2V
e 56 2 mA
0 77
14 MHz
PDTMR Pin Delay Calculation
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown Mode A delay is
required only when using the on chip oscillator to
allow the crystal or resonator circuit to stabilize
NOTE
The PDTMR pin function does not apply when
RESIN is asserted (i e a device reset while in Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabilized
To calculate the value of capacitor to use to provide
a desired delay use the equation
440 c t e CPD (5V 25 C)
Where
t e desired delay in seconds
CPD e capacitive load on PDTMR in microfarads
Example For a delay of 300 ms a capacitor value of
CPD e 440 c (300 c 10b6 e 0 132 mF is required
Round up to a standard (available) capacitor value
NOTE
The above equation applies to delay time longer
than 10 ms and will compute the TYPICAL capaci-
tance needed to achieve the desired delay A delay
variance of a50% to b25% can occur due to
temperature voltage and device process ex-
tremes In general higher VCC and or lower tem-
peratures will decrease delay time while lower VCC
and or higher temperature will increase delay time
Parameter
CPD
CPD (Idle Mode)
Typical
0 77
0 55
Max
Units
Notes
1 37
mA V MHz
12
0 96
mA V MHz
12
NOTES
1 Maximum CPD is measured at b40 C with all outputs loaded as specified in the AC test conditions and the device in reset
(or Idle Mode) Due to tester limitations CLKOUT and OSCOUT also have 50 pF loads that increase ICC by V C F
2 Typical CPD is calculated at 25 C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode)
29


80L186EC (Intel)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

No Preview Available !

Click to Download PDF File for PC

80C186EC 188EC 80L186EC 188EC
AC SPECIFICATIONS
AC Characteristics 80C186EC25
Symbol
Parameter
INPUT CLOCK
TF CLKIN Frequency
TC CLKIN Period
TCH CLKIN High Time
TCL CLKIN Low Time
TCR CLKIN Rise Time
TCF CLKIN Fall Time
OUTPUT CLOCK
TCD CLKIN to CLKOUT Delay
T CLKOUT Period
TPH CLKOUT High Time
TPL CLKOUT Low Time
TPR CLKOUT Rise Time
TPF CLKOUT Fall Time
OUTPUT DELAYS
TCHOV1 ALE S2 0 DEN DT R
BHE (RFSH) LOCK A19 16
TCHOV2
TCLOV1
GCS0 7 LCS UCS NCS RD WR
BHE (RFSH) DEN LOCK RESOUT
HLDA T0OUT T1OUT A19 16
TCLOV2 RD WR GCS7 0 LCS UCS AD15 0
(AD7 0 A15 8) NCS INTA1 0 S2 0
TCHOF RD WR BHE (RFSH) DT R
LOCK S2 0 A19 16
TCLOF DEN AD15 0 (AD7 0 A15 8)
25 MHz
Min Max
Units Notes
0 50 MHz 1
20 % ns 1
8 % ns 1 2
8 % ns 1 2
1 10 ns 1 3
1 10 ns 1 3
0
(T 2) b 5
(T 2) b 5
1
1
17
2 TC
(T 2) a 5
(T 2) a 5
6
6
ns
ns
ns
ns
ns
ns
14
1
1
1
15
15
3 17 ns 1 4 6 7
3 20 ns 1 4 6 8
3 17 ns 1 4 6
3 20 ns 1 4 6
0 20 ns 1
0 20 ns 1
30




80L186EC.pdf
Click to Download PDF File