GD5F2GQ4RF9FG (GigaDevice)
SPI(x1/x2/x4) NAND Flash

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SPI(x1/x2/x4) NAND Flash
2G
GD5F2GQ4xFxxG
DATASHEET
1


GD5F2GQ4RF9FG (GigaDevice)
SPI(x1/x2/x4) NAND Flash

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SPI(x1/x2/x4) NAND Flash
Contents
2G
1 FEATURE...........................................................................................................................................................4
2 GENERAL DESCRIPTION ...............................................................................................................................5
2.1 PRODUCT LIST ............................................................................................................................................................... 6
2.2 CONNECTION DIAGRAM .................................................................................................................................................. 6
2.3 PIN DESCRIPTION........................................................................................................................................................... 6
2.4 BLOCK DIAGRAM ........................................................................................................................................................... 7
3 ARRAY ORGANIZATION .................................................................................................................................8
4 MEMORY MAPPING.........................................................................................................................................9
5 DEVICE OPERATION .....................................................................................................................................10
5.1 SPI MODES ................................................................................................................................................................ 10
5.2 HOLD MODE ............................................................................................................................................................. 11
5.3 WRITE PROTECTION ..................................................................................................................................................... 11
5.4 POWER OFF TIMING..................................................................................................................................................... 11
6 COMMANDS DESCRIPTION.........................................................................................................................12
7 WRITE OPERATIONS ....................................................................................................................................13
7.1 WRITE ENABLE (WREN) (06H) ..................................................................................................................................... 13
7.2 WRITE DISABLE (WRDI) (04H) ..................................................................................................................................... 13
8 FEATURE OPERATIONS ...............................................................................................................................14
8.1 GET FEATURES (0FH) AND SET FEATURES (1FH) ............................................................................................................... 14
9 READ OPERATIONS......................................................................................................................................16
9.1 PAGE READ................................................................................................................................................................. 16
9.2 PAGE READ TO CACHE (13H)......................................................................................................................................... 16
9.3 READ FROM CACHE (03H) ............................................................................................................................................ 17
9.4 FAST READ FROM CACHE (0BH)..................................................................................................................................... 17
9.5 READ FROM CACHE X2 (3BH)........................................................................................................................................ 18
9.6 READ FROM CACHE X4 (6BH)........................................................................................................................................ 18
9.7 READ FROM CACHE DUAL IO (BBH) ............................................................................................................................... 19
9.8 READ FROM CACHE QUAD IO (EBH)............................................................................................................................... 20
10 READ ID (9FH) ............................................................................................................................................21
11 PROGRAM OPERATIONS.........................................................................................................................22
11.1 PAGE PROGRAM ........................................................................................................................................................ 22
11.2 PROGRAM LOAD (PL) (02H) ....................................................................................................................................... 23
11.3 PROGRAM LOAD X4 (PL X4) (32H)............................................................................................................................... 24
11.4 PROGRAM EXECUTE (PE) (10H)................................................................................................................................... 25
11.5 INTERNAL DATA MOVE ............................................................................................................................................... 26
11.6 PROGRAM LOAD RANDOM DATA (84H) ........................................................................................................................ 26
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SPI(x1/x2/x4) NAND Flash

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SPI(x1/x2/x4) NAND Flash
2G
11.7 PROGRAM LOAD RANDOM DATA X4 (C4H/34H)............................................................................................................ 27
12 ERASE OPERATIONS ...............................................................................................................................28
12.1 BLOCK ERASE (D8H) .................................................................................................................................................. 28
13 RESET OPERATIONS................................................................................................................................29
13.1 SOFT RESET (FFH) ..................................................................................................................................................... 29
14 ADVANCED FEATURES ............................................................................................................................30
14.1 OTP REGION ............................................................................................................................................................ 30
14.2 BLOCK PROTECTION ................................................................................................................................................... 31
14.3 STATUS REGISTER AND DRIVER REGISTER........................................................................................................................ 32
14.4 ASSISTANT BAD BLOCK MANAGEMENT .......................................................................................................................... 33
14.5 INTERNAL ECC .......................................................................................................................................................... 34
15 POWER ON TIMING ...................................................................................................................................35
16 ABSOLUTE MAXIMUM RATINGS ............................................................................................................36
17 CAPACITANCE MEASUREMENT CONDITIONS....................................................................................37
18 DC CHARACTERISTIC ..............................................................................................................................38
19 AC CHARACTERISTICS............................................................................................................................39
20 PERFORMANCE TIMING ..........................................................................................................................40
21 ORDERING INFORMATION ......................................................................................................................42
22 PACKAGE INFORMATION ........................................................................................................................43
23 REVISION HISTORY...................................................................................................................................45
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GD5F2GQ4RF9FG (GigaDevice)
SPI(x1/x2/x4) NAND Flash

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1 FEATURE
SPI(x1/x2/x4) NAND Flash
2G
2Gb SLC NAND Flash
2048-Byte+128-Byte Physical Page Size(2)
- Internal ECC Off (ECC_EN=0):
2048-Byte+128-Byte Full Access
- Internal ECC On (ECC_EN=1, default):
Program: 2048-Byte+64-Byte
Read: 2048-Byte+128-Byte
Program/Erase/Read Speed
- Page Program time: 400us typical
- Block Erase time: 3ms typical
- Page read time: 80us maximum(w/I ECC)
Reliability
- Endurance: 100K program/erase cycles
- Data retention: 10 Years
Standard, Dual, Quad SPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
High Speed Clock Frequency
- 120MHz for fast read with 30PF load
- Quad I/O Data transfer up to 480Mbits/s
Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Register protection with WP# Pin
- Top or Bottom, Block selection combination
Advanced security Features
- 8K-Byte OTP Region (4 page OTP)
Low Power Consumption
- 40mA maximum active current
- 110uA(1) maximum standby current
Enhanced access performance
- 2kbyte cache for fast random read
- Cache read and cache program
Advanced Feature for NAND
- Internal ECC option, per 528bytes
- Internal data move by page with ECC
The first block(Block0) is guaranteed to be a valid block
at the time of shipment.
Single Power Supply Voltage
- Full voltage range for 1.8V: 1.7V ~ 2.0V
- Full voltage range for 3.3V: 2.7V ~ 3.6V
Note (1): When Temperature is 105, the maximum standby current is 200uA
(2). 2048Byte+128Byte Page Size can accommodate more advanced ECC algorithm by user’s choice, even though
the internal 4-bit ECC algorithm only requires 64-Byte spare area.
Internal 4-bit ECC is set to on (ECC_EN=1) as shipment default, it can be disabled by setting ECC_EN=0.
- When Internal ECC is enabled, user can only program the first 64-Byte portion of the entire 128-Byte spare
area, and the rest 64-Byte spare area cannot be programed. User can still read the entire 128-Byte spare area.
- When Internal ECC is disabled, user can read and program the entire 128-Byte spare area.
4


GD5F2GQ4RF9FG (GigaDevice)
SPI(x1/x2/x4) NAND Flash

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SPI(x1/x2/x4) NAND Flash
2 GENERAL DESCRIPTION
2G
SPI (Serial Peripheral Interface) NAND Flash provides an ultra cost-effective while high density non-volatile memory
storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive
alternative to SPI-NOR and standard parallel NAND Flash, with advanced features:
Total pin count is 8, including VCC and GND
Density is 2Gbit
Superior write performance and cost per bit over SPI-NOR
Significant low cost than parallel NAND
This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the
same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to
handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash
memory, with specified designed features to ease host management:
User-selectable internal ECC. ECC code is generated internally during a page program operation. When a page
is read to the cache register, the ECC code is detect and correct the errors when necessary. The 64-bytes spare area
is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error status.
Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage
collection task, without need of shift in and out of data.
Power on Read with internal ECC. It is programmed and read in page-based operations, and erased in block-
based operations. Data is transferred to or from the NAND Flash memory array, page by page, to a data register and
a cache register. The cache register is closest to I/O control circuits and acts as a data buffer for the I/O data; the data
register is closest to the memory array and acts as a data buffer for the NAND Flash memory array operation. The
cache register functions as the buffer memory to enable page and random data READ/WRITE and copy back
operations. These devices also use a SPI status register that reports the status of device operation.
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SPI(x1/x2/x4) NAND Flash

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2.1 Product List
SPI(x1/x2/x4) NAND Flash
Product Number
GD5F2GQ4RFZIG
GD5F2GQ4RFZJG
GD5F2GQ4RFZFG
GD5F2GQ4RF9IG
GD5F2GQ4RF9JG
GD5F2GQ4RF9FG
GD5F2GQ4UFZIG
GD5F2GQ4UFZJG
GD5F2GQ4UFZFG
GD5F2GQ4UF9IG
GD5F2GQ4UF9JG
GD5F2GQ4UF9FG
Density
2Gbit
Voltage
1.7V to
2.0V
2.7V to
3.6V
Package Type
TFBGA24(6*4 Ball Array)
LGA8(6*8mm)
TFBGA24(6*4 Ball Array)
LGA8(6*8mm)
Temperature
-40to 85
-40to 105
-40to 85
-40to 85
-40to 105
-40to 85
-40to 85
-40to 105
-40to 85
-40to 85
-40to 105
-40to 85
2G
Page Size
2Kbytes +
128bytes
2.2 Connection Diagram
CS# 1
SO 2
WP# 3
VSS 4
Top View
8LEAD
2.3 Pin Description
Pin Name
CS#
SO/SIO1
WP#/SIO2
VSS
SI/SIO0
SCLK
HOLD#/SIO3
VCC
I/O
I
I/O
I/O
Ground
I/O
I
I/O
Supply
8 VCC
7 HOLD#
6 SCLK
5 SI
4
3
2
1
Top View
NC VCC WP# HOLD# NC NC
NC VSS NC SI NC NC
NC SCLK CS# SO NC NC
NC NC NC NC NC NC
A BCDE F
24-BALL TFBGA
Figure2-1 Connection Diagram
Description
Chip Select input, active low
Serial Data Output / Serial Data Input Output 1
Write Protect, active low / Serial Data Input Output 2
Ground
Serial Data Input / Serial Data Input Output 0
Serial Clock input
Hold input, active low /Serial Data Input Output3
Power Supply
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SPI(x1/x2/x4) NAND Flash

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2.4 Block Diagram
SPI(x1/x2/x4) NAND Flash
SCLK SI/SIO0 SO/SIO1
HOLD#/ WP#/
CS# RESET#/ SIO2
SIO3
Serial NAND controler
Vcc
Vss
Cache
NAND
memory
memory
core
ECC and status register
2G
Figure2-2 Block Diagram
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SPI(x1/x2/x4) NAND Flash
3 ARRAY ORGANIZATION
Each device has
2G
256M+16M
2048 x 64
2048
Each block has
128K+8K
64
-
Each page has
2K+128
-
-
Figure3-1. Array Organization
bytes
pages
blocks
Cache Register
Data Register
Per device:
2Gb: 2048blocks
2048
2048
128
128
1 block
SO
SI
1 page = (2K + 128 bytes)
1 block = (2K + 128 bytes) x 64 pages
= (128K + 8K) bytes
1 device:
For 2Gb = (128K + 8K) bytes x 2048 blocks
= 1Gb
2G
Cache Register
Data Register
Per device:
2Gb: 2048blocks
Internal ECC = OFF
2048
64
SO
SI
2048
64
1 block
1 page = (2K + 64 bytes)
1 block = (2K + 64 bytes) x 64 pages
= (128K + 4K) bytes
1 device:
For 2Gb = (128K + 4K) bytes x 2048 blocks
= 2Gb
Internal ECC= ON
Note:
1.When Internal ECC is enableduser can program the first 64 bytes of the entire 128 bytes spare area and the last 64
bytes of the whole spare area cannot be programeduser can read the entire 128 Byte spare area.
2.When Internal ECC is disableduser can read and program the entire 128 bytes spare area.
8


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SPI(x1/x2/x4) NAND Flash

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SPI(x1/x2/x4) NAND Flash
4 MEMORY MAPPING
<6 7 8
Blocks
RA<16:6>
0
1
2
15 16 >
1023 2047
2G
Pages
RA<5:0>
01
63
Bytes
CA<11:0>
0
1
2
2175
Note:
1. CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0
through 2175 are valid. Bytes 2176 through 4095 of each page are “out of bounds,” do not exist in the device,
and cannot be addressed.
2. RA: Row Address. RA<5:0> selects a page inside a block, and RA<16:6> selects a block:
9


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SPI(x1/x2/x4) NAND Flash
5 DEVICE OPERATION
2G
5.1 SPI Modes
SPI NAND supports two SPI modes:
• CPOL = 0, CPHA = 0 (Mode 0)
• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing
diagrams shown in this data sheet are mode 0. See Figure5-1 for more details.
Figure5-1. SPI Modes Sequence Diagram
CPOL CPHA
0 0 SCLK
1 1 SCLK
SI
SO
CS#
MSB
LSB
MSB
LSB
Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3).
Standard SPI
SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(CS#), Serial Data Input (SI) and Serial Data Output (SO).
Dual SPI
SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow
data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command
the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1.
Quad SPI
SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow
data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command
the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD# pins become SIO2 and SIO3.
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5.2 HOLD Mode
SPI(x1/x2/x4) NAND Flash
2G
The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated
data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesnt stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low
(if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of
HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK dont care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure5-2. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5.3 Write Protection
SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block lock
bits (BP0, BP1, BP2 and INV, CMP) from being over written. If the BRWD bit is set to 1 and WP# is LOW, the block protect
bits cannot be altered.
5.4 Power Off Timing
Please do not turn off the power before Write/Erase operation is complete. Avoid using the device when the battery is low.
Power shortage and/or power failure before Write/Erase operation is complete will cause loss of data and/or
damage to data.
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SPI(x1/x2/x4) NAND Flash
6 COMMANDS DESCRIPTION
2G
Command Name
Write Enable
Write Disable
Get Features
Set Feature
Page Read (to cache)
Read From Cache
Fast Read From Cache
Read From Cache x 2
Read From Cache x 4
Read From Cache Dual IO
Read From Cache Quad IO
Read ID(5)
Program Load
Program Load x4
Program Execute
Program Load Random Data
Program Load Random Data x4
Block Erase(128K)
Reset(6)
Table6-1. Commands Set
Byte 1
Byte 2 Byte 3
06H
04H
0FH
A7-A0
(D7-D0)
1FH
A7-A0
(D7-D0)
13H A23-A16 A15-A8
03H
dummy(2) A15-A8
0BH
3BH
dummy(2) A15-A8
dummy(2) A15-A8
6BH
dummy(2) A15-A8
BBH
A15-A0 dummy(3)
EBH
A15-A0(4) (D7-D0)x4
9FH MID DID
02H A15-A8 A7-A0
32H A15-A8 A7-A0
10H
84H(7)
A23-A16 A15-A8
A15-A8 A7-A0
C4H/34H(7) A15-A8 A7-A0
D8H
A23-A16 A15-A8
FFH
Byte 4
dummy(1)
A7-A0
A7-A 0(8)
A7-A0
A7-A0
A7-A0
(D7-D0)x2
DID
(D7-D0)
(D7-D0)x4
A7-A0
(D7-D0)
(D7-D0)x4
A7-A0
Byte 5
(D7-D0)
dummy(2)
dummy(2)
dummy(2)
Next byte
Next byte
Next byte
Next byte
Byte N
Wrap(9)
(D7-D0)
(D7-D0)x2
(D7-D0)x4
Byte N
Byte N
Byte N
Byte N
Notes:
1. The dummy byte can be inputted or not.
2. The x8 clock = dummy<7:0>.
3. The x8 clock = dummy<7:0>, D7-D0.
4. The x8 clock = A15-A0, dummy<7:0>, D7-D0.
5. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID.
6. Reset command:
During busy, Reset will reset PAGE READ/PROGRAM/ERASE operation.
During idle, Reset will reset status register bits P_FAIL/E_FAIL/ECCS bits.
7. Those commands are only available in Internal Data Move operation.
8. A0 need be 0 for the 03H command.
9. The output would be updated by real-time, until CS# is driven high.
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SPI(x1/x2/x4) NAND Flash
7 WRITE OPERATIONS
2G
7.1 Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit
must be set prior to following operations that change the contents of the memory array:
Page program
OTP program/OTP protection
Block erase
The WEL bit can be cleared after a reset command.
Figure7-1. Write Enable Sequence Diagram
CS#
SCLK
SI
SO
01234567
Command
06H
High-Z
7.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is also reset by following
condition:
Page program
OTP program/OTP protection
Block erase
Figure7-2. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
01234567
Command
04H
High-Z
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SPI(x1/x2/x4) NAND Flash
8 FEATURE OPERATIONS
2G
8.1 Get Features (0FH) and Set Features (1FH)
The GET FEATURES (0FH) and SET FEATURES (1FH) commands are used to monitor the device status and alter the
device behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified.
Features such as OTP and block locking can be enabled or disabled by setting specific feature bits (shown in the following
table). The status register is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06H) command.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise
specified in the following table, once the device is set, it remains set, even if a RESET (FFH) command is issued.
Table8-1. Features Settings
Register Addr.
7
6
5
4
3
2 10
Protection A0H BRWD Reserved
BP2
BP1
BP0
INV CMP Reserved
Feature B0H OTP_PRT OTP_EN Reserved ECC_EN Reserved Reserved Reserved QE
Status C0H Reserved ECCS2 ECCS1 ECCS0 P_FAIL E_FAIL
WEL
OIP
Feature D0H Reserved DS_IO[1] DS_IO[0] Reserved Reserved Reserved Reserved Reserved
Note: If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed.
If QE is enabled, the quad IO operations can be executed.
All the reserved bits must be held low when the feature is set.
00h is the default data byte value for Output Driver Register after power-up.
These registers are write/read type, except for Register of Status (C0H) is read only.
CS#
SCLK
SI
SO
Figure8-2. Get Features Sequence Diagram
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
0FH
High-Z
1 byte address
76543210
MSB
Data byte
76543210
MSB
Note: The output would be updated by real-time, until CS# is driven high.
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SPI(x1/x2/x4) NAND Flash
2G
The set features command supports a dummy byte mode after the data byte as well. The features in the feature byte B0H
are all volatile except OTP_PRT bit.
Figure8-3. Set Features Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SI
Command
1 byte address
Data byte
1FH 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
SO High-Z
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SPI(x1/x2/x4) NAND Flash
9 READ OPERATIONS
2G
9.1 Page Read
The PAGE READ (13H) command transfers the data from the NAND Flash array to the cache register. The command
sequence is as follows:
• 13H (PAGE READ to cache)
• 0FH (GET FEATURES command to read the status)
• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH (Read from cache
dual IO)/EBH (Read from cache quad IO)
The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts
the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE (0FH)
command can be issued to monitor the status. Followed the page read operation, the RANDOM DATAREAD
(03H/0BH/3BH/6BH/BBH/EBH) command must be issued in order to read out the data from cache. The output data starts
at the initial address specified in the command, and will continue until CS# is pulled high to terminate this operation.
Refer waveforms to view the entire READ operation.
9.2 Page Read to Cache (13H)
Figure9-1.Page Read to cache Sequence Diagram
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Command
13H
High-Z
24-bit address
23 22 21
3210
CS#
SLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
tCS Get Feature
1 byte address
0FH
76543210
High-Z
MSB
CS#
SCLK
16 17 18 19 20 21 22 23 24
SI
Data byte
SO 7 6 5 4 3 2 1 0 7
MSB
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SPI(x1/x2/x4) NAND Flash
9.3 Read From Cache (03H)
2G
CS#
SCLK
Figure9-2. Read From Cache Sequence Diagram
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
30 31
Command
SI
03H
SO High-Z
CS#
SCLK
32 33 34 35 36 37 38 39
Dummy Byte
A15-0
7 6 5 4 3 2 1 0 15 14 13 12 11
3210
SI
Byte 0
Byte 1
SO 7 6 5 4 3 2 1 0 7 6 5
MSB
MSB
9.4 Fast Read From Cache (0BH)
CS#
SCLK
Figure9-3. Read From Cache Sequence Diagram
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
30 31
SI
SO
CS#
SCLK
SI
SO
Command
0BH
High-Z
Dummy Byte
A15-0
7 6 5 4 3 2 1 0 15 14 13 12 11
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
76543210
Byte 0
Byte 1
76543210765
MSB
MSB
3210
17


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SPI(x1/x2/x4) NAND Flash

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SPI(x1/x2/x4) NAND Flash
9.5 Read From Cache x2 (3BH)
2G
Figure9-4. Read From Cache x2 Sequence Diagram
CS#
SCLK
SI
SO
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
30 31
Command
3BH
High-Z
Dummy Byte
A15-0
7 6 5 4 3 2 1 0 15 14 13 12 11
3210
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
76543210 64206420642
Byte 0
Byte 1
Byte 2
75317531753
MSB
MSB
9.6 Read From Cache x4 (6BH)
The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command.
Figure9-5. Read From Cache x4 Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
30 31
SI
Command
Dummy Byte
A15-0
6BH
7 6 5 4 3 2 1 0 15 14 13 12 11
SO High-Z
CS#
SCLK
SI(SIO0)
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
76543210 404040404
SO(SIO1)
515151515
3210
WP#(SIO2)
626262626
HOLD#(SIO3)
737373737
Byte0 Byte1 Byte2 Byte3
18


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SPI(x1/x2/x4) NAND Flash
2G
9.7 Read From Cache Dual IO (BBH)
The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH), followed by a 12bit
column address for the starting byte address and a dummy byte by SIO0 and SIO1, each bit being latched in during the
rising edge of SCLK, then the cache contents are shifted out 2-bit per clock cycle from SIO0 and SIO1. The first address
byte can be at any location. The address increments automatically to the next higher address after each byte of data shifted
out until the end of whole page.
CS#
SCLK
Figure9-6. Read From Cache Dual IO Sequence Diagram
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SI(SIO0)
Command
BBH
6420642064206420
SO(SIO1)
7531753175317531
Dummy, A11-8
A7-0
Dummy
Byte0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(SIO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
SO(SIO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1
Byte2
Byte3
Byte4
19


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SPI(x1/x2/x4) NAND Flash
9.8 Read From Cache Quad IO (EBH)
2G
The Read from Cache Quad IO command is similar to the Read from Cache x4 command, followed a 12-bit column address
for the starting byte address and a dummy byte by SIO0, SIO1, SIO3, SIO4, each bit being latched in during the rising
edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle from SIO0, SIO1, SIO2, SIO3. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out until the end of whole page. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read
from cache quad IO command.
Figure9-7. Read From Cache Quad IO Sequence Diagram
CS#
SCLK
SI(SIO0)
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
EBH
4040404040 4
5151515151 5
6262626262 6
7373737373 7
Dummy, A11-A8
A7-0 Dummy Byte0 Byte1
20


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SPI(x1/x2/x4) NAND Flash
10 Read ID (9FH)
The READ ID command is used to identify the NAND Flash device.
• The READ ID command outputs the Manufacturer ID and the device ID. See Table10-1 for details.
Figure10-1. Read ID Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
SI
9FH
SO
High-Z
Manufacturer ID
76543210
CS#
SCLK
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI
Device ID(Byte 1)
Device ID(Byte 2)
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
2G
ID
Manufacture ID (GigaDevice)
Device ID
(Byte 1)
Device ID
(Byte 2)
Table10-1. READ ID Table
Description
Part No
SPI NAND 3.3V
GD5F2GQ4UFxxG
SPI NAND 1.8V
GD5F2GQ4RFxxG
SPI NAND 3.3V
GD5F2GQ4UFxxG
SPI NAND 1.8V
GD5F2GQ4RFxxG
SPI NAND 2Gbit 3.3V
GD5F2GQ4UFxxG
SPI NAND 2Gbit 1.8V
GD5F2GQ4RFxxG
Value
C8h
B2h
A2h
48h
Page Size
2Kbyte +
128Byte
21


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SPI(x1/x2/x4) NAND Flash
11 PROGRAM OPERATIONS
2G
11.1 Page Program
The PAGE PROGRAM operation sequence programs 1 byte to 2176 bytes of data with in a page. The page program
sequence is as follows:
• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4)
06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4
dummy bits and a 12-bit column address, then the data bytes to be programmed. The data bytes are loaded into a cache
register that is 2176 bytes long. If more than 2176bytes are loaded, then those additional bytes are ignored by the cache
register. The command sequence ends when CS# goes from LOW to HIGH. Figure11-1 shows the PROGRAMLOAD
operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06H) command must
be issued. As with any command that changes the memory contents, the WRITEENABLE must be executed in order to set
the WEL bit. If this command is not issued, then the rest of the program sequence is ignored.
Note:
1. The contents of Cache Register doesn’t reset when Program Load (02h) command, Program Random Load (84h)
command and RESET (FFh) command.
2. When Program Execute (10h) command was issued just after Program Load (02h) command, SPI-NAND controller
outputs 0xFF data to the NAND for the address that data was not loaded by Program Load (02h) command.
3. When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, SPI-
NAND controller outputs contents of Cache Register to the NAND.
4. The addressing should be done in sequential order in a block.
22


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SPI(x1/x2/x4) NAND Flash
11.2 Program Load (PL) (02H)
CS#
SCLK
SI
Figure11-1. Program Load Sequence Diagram
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
22 23
Command
02H
Dummy<3:0>, A11-A0
0 0 0 0 11 10
3210
2G
CS#
SCLK
SI
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Data Byte0
Data Byte1
7654321076543210
MSB
17424
17431
Data Byte
2175/2111
76543210
Note: when internal ECC disabled the Data Byte is 2175, when internal ECC enabled the Data Byte is 2111.
23


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SPI(x1/x2/x4) NAND Flash
11.3 Program Load x4 (PL x4) (32H)
2G
The Program Load x4 command (32H) is similar to the Program Load command (02H) but with the capability to input the
data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE)
of feature (B0[0]) must be set to enable the program load x4 command.
CS#
SCLK
SI(SIO0)
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
Figure11-2. Program Load x4 Sequence Diagram
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
Command
32H
Dummy<3:0>, A11-A0 Byte0 Byte1 Byte2 Byte3
15 14 13
321040 404040
51515151
62626262
73737373
CS#
SCLK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SI(SIO0)
Byte4 Byte5 Byte6 Byte7 Byte8 Byte9 Byte10Byte11
4040404040404040
SO(SIO1)
5151515151515151
WP#(SIO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
HOLD#(SIO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
Byte
2175/2111
40404040
51515151
62626262
73737373
Note: when internal ECC disabled the Byte is 2175, when internal ECC enabled the Byte is 2111
24


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11.4 Program Execute (PE) (10H)
2G
After the data is loaded, a PROGRAM EXECUTE (10H) command must be issued to initiate the transfer of data from the
cache register to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. After
the page/block address is registered, the memory device starts the transfer from the cache register to the main array, and
is busy for tPROG time. This operation is shown in Figure11-3. During this busy time, the status register can be polled to
monitor the status of the operation (refer to Status Register). When the operation completes successfully, the next series
of data can be loaded with the PROGRAMLOAD command.
Figure11-3. Program Execute Sequence Diagram
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Command
10H
High-Z
24-bit address
23 22 21
3210
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
tCS
get feature
Status register address
0FH
76543210
High-Z
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out Status register data out
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
MSB
MSB
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SPI(x1/x2/x4) NAND Flash
11.5 Internal Data Move
2G
The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The
INTERNAL DATA MOVE command sequence is as follows:
• 13H (PAGE READ to cache)
Optional 84H/C4H/34H (PROGRAM LOAD RANDOM DATA)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Prior to performing an internal data move operation, the target page content must be read out into the cache register by
issuing a PAGE READ (13H) command. The PROGRAM LOAD RANDOM DATA (84H/C4H/34H) command can be
issued, if user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random
data is not sequential, another PROGRAM LOAD RANDOM DATA (84H/C4H/34H) command must be issued with the
new column address. After the data is loaded, the WRITE ENABLE command must be issued, and the na
PROGRAMEXECUTE (10H) command can be issued to start the programming operation.
11.6 Program Load Random Data (84H)
This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loaded
in the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOAD
RANDOM DATA (84H) command must be issued with a new column address, see Figure11-4 for details. This command is
only available during internal data move sequence.
Figure11-4. Program Load Random Data Sequence Diagram
CS#
SCLK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
22 23
Command
84H
Dummy<3:0>, A11-A0
0 0 0 0 11 10
3210
CS#
SCLK
SI
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Data Byte0
Data Byte1
7654321076543210
MSB
17424
17431
Data Byte
2175/2111
76543210
Note: when internal ECC disabled the Data Byte is 2175, when internal ECC enabled the Data Byte is 2111.
26


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11.7 Program Load Random Data x4 (C4H/34H)
2G
The Program Load Random Data x4 command (C4H/34H) is similar to the Program Load Random Data command (84H)
but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown
below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4 command.
See Figure11-5 for details. Those two commands are only available during internal data move sequence.
CS#
SCLK
SI(SIO0)
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
Figure11-5. Program Load Random Data x4 Sequence Diagram
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
Command
C4H/34H
Dummy<3:0>, A11-A0 Byte0 Byte1
15 14 13
321040 404040
51515151
62626262
73737373
CS#
SCLK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SI(SIO0)
Byte10Byte11
4040404040404040
SO(SIO1)
5151515151515151
WP#(SIO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
HOLD#(SIO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
Byte
2175/2111
40404040
51515151
62626262
73737373
Note: when internal ECC disabled the Data is 2175, when internal ECC enabled the Data is 2111.
27


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SPI(x1/x2/x4) NAND Flash
12 ERASE OPERATIONS
2G
12.1 Block Erase (D8H)
Figure12-1. Block Erase Sequence Diagram
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Command
D8H
High-Z
24-bit address
23 22 21
3210
CS#
SLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
tCS
get feature
Status register address
0FH
76543210
High-Z
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out Status register data out
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
MSB
MSB
The BLOCK ERASE (D8H) command is used to erase at the block level. The blocks are organized as 64 pages per
block, 2176 bytes per page (2048 + 128 bytes). Each block is136 Kbytes. The BLOCK ERASE command (D8H) operates
on one block at a time. The command sequence for the BLOCK ERASE operation is as follows:
• 06H (WRITE ENBALE command)
• D8H (BLOCK ERASE command)
• 0FH (GET FEATURES command to read the status register)
Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06H) command must be issued. As with any
command that changes the memory contents, the WRITEENABLE command must be executed in order to set the WEL
bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. A WRITE ENABLE
command must be followed by a BLOCK ERASE (D8H) command. This command requires a 24-bit address. After the
row address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy
for tERS time during the BLOCK ERASE operation. The GET FEATURES (0FH) command can be used to monitor the
status of the operation.
When a block erase operation is in progress, user can issue normal read from cache commands
(03H/0BH/3BH/6BH/BBH/EBH) to read the data in the cache.
28


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13 RESET OPERATIONS
2G
13.1 Soft Reset (FFH)
Figure13-1. Reset Sequence Diagram
CS#
SCLK
SI
SO
01234567
Command
FFH
High-Z
tCS
CS#
SLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
get feature
0FH
High-Z
Status register address
76543210
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out Status register data out
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
MSB
MSB
The RESET (FFH) command stops all operations. For example, in case of a program or erase or read operation, the
reset command can make the device enter the wait state.
During a cache program or cache read, a reset can also stops the previous operation and the pending operation. The
OIP status can be read from 300ns after the reset command is sent.
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SPI(x1/x2/x4) NAND Flash
14 ADVANCED FEATURES
2G
14.1 OTP Region
The serial device offers a protected, One-Time Programmable NAND Flash memory area. 4 full pages (2176 bytes per
page) are available on the device. Customers can use the OTP area any way they want, like programming serial
numbers, or other data, for permanent storage. When delivered from factory, feature bit OTP_PRT is 0.
To access the OTP feature, the user must set feature bits OTP_EN/OTP_PRT by SET FEATURES command. When the
OTP is ready for access, pages 00h03H can be programmed in sequential order by PROGRAM LOAD (02H) and
PROGRAM EXECUTE(10H) commands ( when not yet protected), and read out by PAGE READ (13H) command and
output data by READ from CACHE(03H/0BH/3BH/6BH/BBH/EBH).
Table14-1. OTP States
OTP_PRT
OTP_EN
State
x 0 Normal operation
0 1 Access OTP region, read and program data.
1 1 1. When the device power on state OTP_PRT is 0, user can set feature bit
OTP_PRT and OTP_EN to 1, then issue PROGRAM EXECUTE (10H) to
lock OTP, and after that OTP_PRT will permanently remain 1.
2. When the device power on state OTP_PRT is 1, user can only read the
OTP region data.
Note: The OTP space cannot be erased and after it has been protected, it cannot be programmed again, please use this
function carefully.
Access to OTP data
• Issue the SET FEATURES command (1FH)
Set feature bit OTP_EN
• Issue the PAGE PROGRAM (only when OTP_PRT is 0) or PAGE READ command
Protect OTP region
Only when the following steps are completed, the OTP_PRT will be set and users can get this feature out with 0FH
command.
• Issue the SET FEATURES command (1FH)
Set feature bit OTP_EN and OTP_PRT
• 06H (WRITE ENABLE)
• Issue the PROGRAM EXECUTE (10H) command.
30




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