ISL8202M (Renesas)
3A Single Channel High Efficiency DC/DC Step-Down Power Module

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DATASHEET
ISL8202M
3A Single Channel High Efficiency DC/DC Step-Down Power Module
FN8761
Rev.4.00
Mar 17, 2017
The ISL8202M power module is a single channel synchronous
step-down complete power supply, capable of delivering up to
3A of continuous current. Operating from a single 2.6V to 5.5V
input power rail and integrating controller, power inductor and
MOSFETs, the ISL8202M only requires a few external
components to operate and is optimized for space constrained
and portable battery operated applications.
Based on current mode PWM control scheme, the ISL8202M
provides a fast transient response and excellent loop stability
as well as a very low duty cycle with an adjustable output
voltage as low as 0.6V and better than 1.6% accuracy over line
and load conditions. Operation frequency is selectable through
an external resistor, with a 1.8MHz default setting, or may be
synchronized with an external clock signal up to 3.5MHz. The
ISL8202M also implements a selectable PFM mode to
improve light-load efficiency and a 100% duty cycle LDO mode
to extend battery life. A programmable soft-start reduces the
inrush current required from the input supply while an
automatic output discharge ensures a soft stop. Dedicated
enable pin and power-good flag allow for easy system power
rails sequencing.
An array of protection features, including input Undervoltage
Lockout (UVLO), over-temperature, overcurrent/short-circuit
with hiccup mode, overvoltage and negative overcurrent,
guarantees safe operations under abnormal operating
conditions.
The ISL8202M is available in a compact RoHS compliant
22 Ld 4.5x7.5x1.85mm QFN package.
Related Literature
TB389, “PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages”
UG071, “ISL8202MEVAL1Z Evaluation Board User Guide”
Features
• 3A single channel complete power supply
- Integrates controller, MOSFETs and inductor
- Pin compatible with the 5A ISL8205M
• 2.6V to 5.5V input voltage range
• Adjustable output voltage range
- As low as 0.6V with ±1.6% accuracy over
line/load/temperature
- Up to 95% efficiency
• Default 1.8MHz current mode control operations
- 680kHz to 3.5MHz resistor adjustable
- External synchronization up to 3.5MHz
- Selectable light-load efficiency mode
- 100% duty cycle LDO mode
• Programmable soft-start
• Soft-stop output discharge
• Dedicated enable pin and power-good flag
• UVLO, over-temperature, overcurrent, overvoltage and
negative overcurrent protections
- Overcurrent/short-circuit hiccup mode
• 4.5mmx7.5mmx1.85mm 22 Ld QFN package
Applications
• DC to DC POL power module
• µC/µP, FPGA and DSP power
• Portable equipment
• Battery operated equipment
2.6V TO 5.5V INPUT
CIN
2x22µF
RFS
133k
ISL8202M
VIN
EN
PG
SYNC
FS
SS
SGND
EPAD
VOUT
SW
VSENSE
COMP
FB
PGND
1.2V 3A OUTPUT
COUT
2x22µF
RSET
100k
CFF
560pF
FIGURE 1. TYPICAL APPLICATION DIAGRAM AT 5VIN, 1.2VOUT, 1.5MHz fSW, 3A
100
95
90
85
80
75
70
65
60
0
Vout=3.3V, Fsw=2MHz PWM
Vout=3.3V, Fsw=2MHz PFM
Vout=1.2V, Fsw=1.5MHz PFM
Vout=1.2V, Fsw=1.5MHz PWM
0.5 1 1.5 2 2.5
LOAD CURRENT (A)
FIGURE 2. EFFICIENCY vs LOAD 5VIN
3
FN8761 Rev.4.00
Mar 17, 2017
Page 1 of 25


ISL8202M (Renesas)
3A Single Channel High Efficiency DC/DC Step-Down Power Module

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ISL8202M
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Load Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Short-Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PFM (Skip) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Frequency Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External Synchronization Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programming the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Recommended Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Feed-Forward Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal Consideration and Current Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCB Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FN8761 Rev.4.00
Mar 17, 2017
Page 2 of 25


ISL8202M (Renesas)
3A Single Channel High Efficiency DC/DC Step-Down Power Module

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ISL8202M
Functional Block Diagram
SS 17
EN 15
SOFT-
START
SHUTDOWN
BANDGAP VREF
+
+ EAMP
FB 19
FB 1
0.8V
OV
+
0.85 x VREF
UV
+
PG 12
1ms
DELAY
0.5V
SCP
+
COMP
18
FS SYNC
16 13
SHUTDOWN
SLOPE
COMP
OSCILLATOR
COMP
PWM/PFM LOGIC
CONTROLLER
PROTECTION
HS DRIVER
LS
DRIVER
SGND
+
OCP
+
SKIP
+
CSA
ISET
THRESHOLD
NEGATIVE CURRENT
SENSING
ZERO-CROSSING
SENSING
100k
PGND
SHUTDOWN
11 VIN
21 SW
L
6 VOUT
9 SW
3 PGND
20 PGND
14 PGND
51
4 VSENSE
2 VSENSE
22 SGND
100k0.5%
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN8761 Rev.4.00
Mar 17, 2017
Page 3 of 25


ISL8202M (Renesas)
3A Single Channel High Efficiency DC/DC Step-Down Power Module

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ISL8202M
Pin Configuration
PGND SYNC PG
VIN
14 13 12
11
EN 15
FS 16
SS 17
COMP 18
20
PGND
21
SW
FB 19
22 SGND
NC
10
12
FB VSENSE
3 45
PGND VSENSE NC
ISL8202M
(22 LD QFN)
TOP VIEW
SW
9
8 NC
7 NC
6
VOUT
7.5mm
1.85mm
Pin Descriptions
PIN
NUMBER
1, 19
2, 4
3, 14
5, 7, 8, 10
6
9, 21
11
12
13
PIN
NAME
FB
VSENSE
PGND
NC
VOUT
SW
VIN
PG
SYNC
DESCRIPTION
Voltage setting pin. Module output voltage is set by connecting a resistor RSET from this pin to SGND. A ceramic
capacitor is also recommended to be placed in parallel with RSET from FB to SGND to ensure system stability in extreme
operation conditions. Refer to Table 2 on page 14 for the resistor and capacitor values for various typical output voltage.
Voltage sense pin. Pins 2 and 4 are shorted together internally. An internal 51Ω resistor is connected from VOUT (Pad 6)
to VSENSE for local output voltage feedback in case remote sensing is not present. To achieve best regulation
performance at point of load, remote sensing trace needs to be directly routed to VSENSE.
Power ground. Power ground pins. Place output capacitor across VOUT and PGND close to Pin 3 since it is the return
path for output current.
No connection pins. These pins have no connections inside. Leave these pins floating.
Power output. Power output of the module. Output capacitors should be placed across this pad and Pin 3 PGND and
close to the module. Apply load between this pin and PGND Pin 3. Output voltage range: 0.6V to 5.0V.
Switching node. These pins can be used to monitor switch node waveform to examine switching frequency. These pins
can also be used for snubber connection. To improve system efficiency, it is recommended to connect Pin 9 and Pin 21
with wide copper shape. However, avoid connecting SW to large copper shape to minimize radiated EMI noise.
Power input. Input voltage range: 2.6V to 5.5V. Tie directly to the input rail. It is required to have minimum total input
capacitance of 44µF at module input. Add additional capacitance if possible. Use X5R or X7R ceramic capacitors. It is
critical to place input ceramic capacitors as close as possible to module input. Refer to “PCB Layout
Recommendations” on page 19 for more information.
Power-good pin. Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. During power-up or EN pin start-up, PG rising edge is delayed by 1ms upon output reached within regulation.
Synchronization pin. Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low
or ground for PFM mode. Connect to an external clock for synchronization with the positive edge trigger. There is an
internal 1MΩ pull-down resistor to prevent an undefined logic state in case SYNC pin is floating. Therefore, PFM mode
is enabled when SYNC is left floating.
FN8761 Rev.4.00
Mar 17, 2017
Page 4 of 25


ISL8202M (Renesas)
3A Single Channel High Efficiency DC/DC Step-Down Power Module

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ISL8202M
Pin Descriptions (Continued)
PIN
NUMBER
15
16
17
18
Exposed
Pad 20
22
PIN
NAME
EN
FS
SS
COMP
PGND
SGND
DESCRIPTION
Power enable pin. Enable the output, when driven to high. Shutdown the output and discharge output capacitor when
driven to low. Typically tie to VIN pin directly. Do not leave this pin floating.
Frequency selection pin. This pin sets module switching frequency. The default frequency is 1.8MHz if FS is connected
to VIN. In spite of default setting, a resistor, RFS, can be connected from the FS pin to SGND to adjust switching
frequency ranging from 680kHz to 3.5MHz.
Soft-start pin. SS is used to adjust the soft-start time. Connect to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. The capacitor value should be less than 33nF to ensure proper operation.
Compensation pin. COMP is the output of voltage feedback error amplifier. For most applications, internal
compensation network can be used to stabilize the system and achieve optimal transient response. This can be done
by directly connecting COMP to VIN. For other applications where external compensation is desired, COMP needs to be
disconnected from VIN and tied to external compensation network.
The exposed pad is connected internally to PGND. Solid connection should be made between Pad 20 and PGND plane
on PCB. Place as many vias as possible under the pad connecting to PGND plane(s) for optimal electrical and thermal
performance. Refer to “PCB Layout Recommendations” on page 19 for more information.
Signal ground pin. Connect PCB SGND plane to this pin. Internally, this pin is single-point connected to module PGND.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
TAPE AND REEL
(UNITS)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL8202MIRZ-T
ISL8202M
-40 to +85
3k 22 Ld QFN
L22.4.5x7.5
ISL8202MIRZ-T7A
ISL8202M
-40 to +85
250 22 Ld QFN
L22.4.5x7.5
ISL8202MEVAL1Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products are RoHS compliant by EU exemption 7C-I. They employ special Pb-free material sets, molding
compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-
free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL8202M. For more information on MSL, please see Technical Brief
TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART
NUMBER
MAX OUTPUT CURRENT IOUT
(DC)
ISL8205M
5A
ISL8203M
3A dual, 6A single
ISL8202M
3A
FN8761 Rev.4.00
Mar 17, 2017
Page 5 of 25


ISL8202M (Renesas)
3A Single Channel High Efficiency DC/DC Step-Down Power Module

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ISL8202M
Absolute Maximum Ratings (Reference to GND)
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V (DC) to VIN +0.3V
SW . . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Ratings
Human Body Model (Tested per JS-001-2010) . . . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . 750V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Latch-Up (Tested per JESD-78D; Class 2, Level A) . . . . . 100mA at +85°C
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
22 Ld QFN (Notes 4, 5) . . . . . . . . . . . . . . . . 27.4
4.8
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6V to 5.5V
VOUT Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V to 5.0V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on the ISL8202MEVAL1Z evaluation board with “direct attach” features. Refer to
ISL8202MEVAL1Z User Guide for evaluation board details. Also see Tech Brief TB379 for general thermal metric information.
5. For JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications Unless otherwise noted, typical specifications are measured at VIN = 3.6V, VOUT = 1.2V, TA = +25°C. Boldface
limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6)
UNIT
INPUT SUPPLY
VIN Undervoltage Lockout Threshold (Note 7)
VUVLO
Rising, no load
Falling, no load
2.10
2.3
2.25
2.5
V
V
Quiescent Supply Current
Shutdown Supply Current
OUTPUT REGULATION
IVIN SYNC = GND, EN = high, IOUT = 0A
SYNC = VIN, fSW = 1.5MHz, EN = high,
IOUT = 0A
ISD SYNC = GND, VIN = 5.5V, EN = low
50
13 20
5 20
µA
mA
µA
Output Continuous Current Range
Line Regulation
Load Regulation
Output Voltage Accuracy (Note 8)
Output Ripple Voltage
IOUT(DC)
ΔVOUT/VOUT VIN = 2.6V to 5.5V, VOUT = 1.2V, fSW = 1.5MHz,
IOUT = 0A, PWM mode
VIN = 2.6V to 5.5V, VOUT = 1.2V, fSW = 1.5MHz,
IOUT = 3A, PWM mode
VIN = 5V, VOUT = 1.2V, fSW = 1.5MHz,
IOUT = 0A to 3A, PWM mode
VIN = 5V, VOUT = 3.3V, fSW = 2MHz,
IOUT = 0A to 3A, PWM mode
Over line/load/temperature range, PWM
mode, VOUT = 1.2V to 3.3V
ΔVOUT
VIN = 5V, 2x22µF ceramic output capacitor,
PWM mode
-1.6
0.58
0.66
0.34
0.21
3
1.6
A
%
%
%
%
%
Reference Voltage (Note 7)
VREF
IOUT = 0A, VOUT = 1.2V, fSW = 1.5MHz
IOUT = 3A, VOUT = 1.2V, fSW = 1.5MHz
IOUT = 0A, VOUT = 3.3V, fSW = 2MHz
IOUT = 3A, VOUT = 3.3V, fSW = 2MHz
7
8
7
8
0.594 0.600 0.606
mVP-P
mVP-P
mVP-P
mVP-P
V
FN8761 Rev.4.00
Mar 17, 2017
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ISL8202M (Renesas)
3A Single Channel High Efficiency DC/DC Step-Down Power Module

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ISL8202M
Electrical Specifications Unless otherwise noted, typical specifications are measured at VIN = 3.6V, VOUT = 1.2V, TA = +25°C. Boldface
limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6)
UNIT
VFB Bias Current (Note 7)
Soft-Start Ramp Time Cycle (Note 7)
IFB VFB = 0.75V
SS = GND
0.1 µA
1 ms
Soft-Start Charging Current (Note 7)
DYNAMIC CHARACTERISTICS
ISS VSS = 0.1V
1.45 1.85 2.25
µA
Voltage Change for Positive Load Step
ΔVOUT-DP Current slew rate = 1A/µs, VIN = 5V, 2x22µF
ceramic output capacitor
Voltage Change for Negative Load Step
ΔVOUT-DP
VOUT = 1.2V, IOUT = 0A to 3A, fSW = 1.5MHz
VOUT = 3.3V, IOUT = 0A to 3A, fSW = 2MHz
Current slew rate = 1A/µs, VIN = 5V, 2x22µF
ceramic output capacitor
59
47
mVP-P
mVP-P
OVERCURRENT PROTECTION (Note 7)
VOUT = 1.2V, IOUT = 3A to 0A, fSW = 1.5MHz
VOUT = 3.3V, IOUT = 3A to 0A, fSW = 2MHz
73
51
mVP-P
mVP-P
Current Limit Blanking Time
Overcurrent and Auto Restart Period
Positive Peak Overcurrent Limit
Positive Skip Limit
Zero Cross Threshold
tOCON
tOCOFF
IPLIMIT
ISKIP
17 Clock pulses
8 SS cycle
7.5 9 11
A
1 1.3 1.8
A
-300
300 mA
Negative Current Limit
COMPENSATION (Note 7)
INLIMIT
-4.5 -3 -1.5
A
Current Sensing Gain
Error Amplifier Transconductance
Rt
Internal compensation
0.119 0.140 0.166
60
Ω
µA/V
External compensation
120 µA/V
SWITCH NODE (Note 7)
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
SW Maximum Duty Cycle
VIN = 5V, IO = 200mA
VIN = 2.7V, IO = 200mA
VIN = 5V, IO = 200mA
VIN = 2.7V, IO = 200mA
36 63
52 89
13 30
17 36
100
mΩ
mΩ
mΩ
mΩ
%
SW Minimum On-Time
SYNC = High
115 ns
OSCILLATOR
Nominal Switching Frequency
SYNC Logic LOW to HIGH Transition Range
fSW SYNC = VIN
fSW with RFS = 261kΩ
fSW with RFS = 133kΩ
1600
0.70
1835
800
1500
0.75
2070
0.80
kHz
kHz
kHz
V
SYNC Hysteresis
0.15
V
SYNC Logic Input Leakage Current
VIN = 3.6V
3.6 5
µA
FN8761 Rev.4.00
Mar 17, 2017
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3A Single Channel High Efficiency DC/DC Step-Down Power Module

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ISL8202M
Electrical Specifications Unless otherwise noted, typical specifications are measured at VIN = 3.6V, VOUT = 1.2V, TA = +25°C. Boldface
limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6)
UNIT
PG (Note 7)
Output Low Voltage
0.3 V
PG Pin Leakage Current
OVP PG Rising Threshold
PG = VIN
0.01
0.80
0.10
µA
V
UVP PG Rising Threshold
80 85 90
%
UVP PG Hysteresis
30 mV
Delay Time (Rising Edge)
Time from VOUT_ reached regulation
0.5 1.0 2.0
ms
PGOOD Delay Time (Falling Edge)
7.5 µs
EN (Note 7)
Logic Input Low
0.4 V
Logic Input High
0.9 V
Enable Logic Input Leakage Current
Pulled up to 3.6V
0.1 1.0
µA
Thermal Shutdown
Temperature Rising
150 °C
Thermal Shutdown Hysteresis
Temperature Falling
25 °C
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. Parameters with MIN and/or MAX limits are 100% tested for internal IC prior to module assembly, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
8. A 0.1% tolerance resistor is used for RSET.
FN8761 Rev.4.00
Mar 17, 2017
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ISL8202M
Typical Performance Characteristics
Efficiency TA = +25°C.
100.0
95.0
90.0
85.0
80.0
75.0
70.0
65.0
Vout=1V , Fsw=1.3MHz
Vout=1.2V , Fsw=1.5MHz
Vout=1.8V , Fsw=2MHz
Vout=2.5V, Fsw=2MHz
60.0
0 0.5 1 1.5 2 2.5 3
LOAD CURRENT (A)
FIGURE 4. EFFICIENCY TA = +25°C, VIN = 3.3V PFM MODE
100.0
95.0
90.0
85.0
80.0
75.0
Vout=1V , Fsw=1.3MHz
Vout=1.2V , Fsw=1.5MHz
70.0 Vout=1.8V , Fsw=2MHz
Vout=2.5V, Fsw=2MHz
65.0 Vout=3.3V, Fsw=2MHz
60.0
0 0.5 1 1.5 2 2.5
LOAD CURRENT (A)
FIGURE 5. EFFICIENCY TA = +25°C, VIN = 5V PFM MODE
3
100.0
95.0
90.0
85.0
80.0
75.0
Vout=1V , Fsw=1.3MHz
70.0
65.0
Vout=1.2V , Fsw=1.5MHz
Vout=1.8V , Fsw=2MHz
Vout=2.5V, Fsw=2MHz
60.0
0 0.5 1 1.5 2 2.5 3
LOAD CURRENT (A)
FIGURE 6. EFFICIENCY TA = +25°C, VIN = 3.3V PWM MODE
Output Voltage Ripple TA = +25°C.
100.0
95.0
90.0
85.0
80.0
Vout=1V , Fsw=1.3MHz
75.0 Vout=1.2V , Fsw=1.5MHz
70.0 Vout=1.8V , Fsw=2MHz
Vout=2.5V, Fsw=2MHz
65.0 Vout=3.3V, Fsw=2MHz
60.0
0 0.5 1 1.5 2 2.5
LOAD CURRENT (A)
FIGURE 7. EFFICIENCY TA = +25°C, VIN = 5V PWM MODE
3
20mV/DIV
20mV/DIV
1µs/DIV
FIGURE 8. VIN = 5V, VOUT = 3.3V, IOUT = 0A, fSW = 2MHz,
COUT = 2x22µF CERAMIC CAPACITORS
1µs/DIV
FIGURE 9. VIN = 5V, VOUT = 3.3V, IOUT = 3A, fSW = 2MHz,
COUT = 2x22µF CERAMIC CAPACITORS
FN8761 Rev.4.00
Mar 17, 2017
Page 9 of 25


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3A Single Channel High Efficiency DC/DC Step-Down Power Module

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ISL8202M
Typical Performance Characteristics (Continued)
20mV/DIV
20mV/DIV
1µs/DIV
FIGURE 10. VIN = 5V, VOUT = 1.2V, IOUT = 0A, fSW = 1.5MHz,
COUT = 2x22µF CERAMIC CAPACITORS
1µs/DIV
FIGURE 11. VIN = 5V, VOUT = 1.2V, IOUT = 3A, fSW = 1.5MHz,
COUT = 2x22µF CERAMIC CAPACITORS
20mV/DIV
20mV/DIV
1µs/DIV
FIGURE 12. VIN = 3.3V, VOUT = 2.5V, IOUT = 0A, fSW = 2MHz,
COUT = 2x22µF CERAMIC CAPACITORS
1µs/DIV
FIGURE 13. VIN = 3.3V, VOUT =2.5V, IOUT = 3A, fSW = 2MHz,
COUT = 2x22µF CERAMIC CAPACITORS
Load Transient Response TA = +25°C, load current step slew rate: 1A/µs.
IOUT 1A/DIV
IOUT 1A/DIV
VOUT 50mV/DIV
VOUT 50mV/DIV
100µs/DIV
FIGURE 14. VIN = 5V, VOUT = 1V, IOUT = 0 TO 3A, fSW = 1.3MHz,
COUT = 3x22µF CERAMIC CAPACITORS
100µs/DIV
FIGURE 15. VIN = 5V, VOUT = 1.2V, IOUT = 0 TO 3A, fSW = 1.5MHz,
COUT = 2x22µF CERAMIC CAPACITORS
FN8761 Rev.4.00
Mar 17, 2017
Page 10 of 25


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ISL8202M
Typical Performance Characteristics (Continued)
IOUT 1A/DIV
IOUT 1A/DIV
VOUT 50mV/DIV
VOUT 50mV/DIV
100µs/DIV
FIGURE 16. VIN = 5V, VOUT = 2.5V, IOUT = 0 TO 3A, fSW = 2MHz,
COUT = 2x22µF CERAMIC CAPACITORS
Start-Up TA = +25°C, Resistor load is used in the test.
SW 5V/DIV
100µs/DIV
FIGURE 17. VIN = 5V, VOUT = 3.3V, IOUT = 0 TO 3A, fSW = 2MHz,
COUT = 2x22µF CERAMIC CAPACITORS
SW 5V/DIV
VOUT 500mV/DIV
PGOOD 5V/DIV
IOUT 1A/DIV
640µs/DIV
FIGURE 18. SOFT-START WITH 0A LOAD PWM MODE, VIN = 5V,
VOUT = 1.2V, IOUT = 0A, COUT = 2x22µF CERAMIC
CAPACITORS, CIN = 100µF POSCAP + 2x22µF CERAMIC
CAPACITORS
VOUT 500mV/DIV
PGOOD 5V/DIV
IOUT 1A/DIV
640µs/DIV
FIGURE 19. SOFT-START WITH 3A LOAD PWM MODE, VIN = 5V,
VOUT = 1.2V, IOUT = 3A, COUT = 2x22µF CERAMIC
CAPACITORS, CIN = 100µF POSCAP + 2x22µF CERAMIC
CAPACITORS
SW 5V/DIV
SW 5V/DIV
VOUT 500mV/DIV
PGOOD 5V/DIV
IOUT 1A/DIV
640µs/DIV
FIGURE 20. SOFT-START WITH 0A LOAD PFM MODE, VIN = 5V,
VOUT = 1.2V, IOUT = 0A, COUT = 2x22µF CERAMIC
CAPACITORS, CIN = 100µF POSCAP + 2x22µF CERAMIC
CAPACITORS
VOUT 500mV/DIV
PGOOD 5V/DIV
IOUT 1A/DIV
640µs/DIV
FIGURE 21. SOFT-START WITH 3A LOAD PFM MODE, VIN = 5V,
VOUT = 1.2V, IOUT = 3A, COUT = 2x22µF CERAMIC
CAPACITORS, CIN = 100µF POSCAP + 2x22µF CERAMIC
CAPACITORS
FN8761 Rev.4.00
Mar 17, 2017
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ISL8202M
Typical Performance Characteristics (Continued)
SW 5V/DIV
SW 5V/DIV
VOUT 500mV/DIV
VOUT 500mV/DIV
PGOOD 5V/DIV
IOUT 1A/DIV
640µs/DIV
FIGURE 22. PREBIAS SOFT-START WITH 0A LOAD PWM MODE,
VIN = 5V, VOUT = 1.2V, IOUT = 0A, COUT = 2x22µF
CERAMIC CAPACITORS, CIN = 100µF POSCAP +
2 x 22µF CERAMIC CAPACITORS
PGOOD 5V/DIV
IOUT 1A/DIV
640µs/DIV
FIGURE 23. PREBIAS SOFT-START WITH 0A LOAD PFM MODE,
VIN = 5V, VOUT = 1.2V, IOUT = 0A, COUT = 2x22µF
CERAMIC CAPACITORS, CIN = 100µF POSCAP +
2 x 22µF CERAMIC CAPACITORS
Short-Circuit Protection TA = +25°C, VIN = 5V, VOUT = 1.2V, CIN = 100µF POScap + 22µF ceramic capacitors, COUT = 2x22µF ceramic
capacitors, output short-circuit during normal operation.
SW 2V/DIV
VOUT 500mV/DIV
IIN 2A/DIV
PGOOD 2V/DIV
10µs/DIV
FIGURE 24. OUTPUT SHORT-CIRCUIT PROTECTION
SW 2V/DIV
VOUT 500mV/DIV
IIN 2A/DIV
PGOOD 2V/DIV
3.2ms/DIV
FIGURE 25. OUTPUT SHORT-CIRCUIT PROTECTION, HICCUP MODE
FN8761 Rev.4.00
Mar 17, 2017
VOUT 500mV/DIV
IIN 2A/DIV
SW 2V/DIV
PGOOD 2V/DIV
3.2ms/DIV
FIGURE 26. OUTPUT SHORT-CIRCUIT RECOVER FROM HICCUP
Page 12 of 25


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ISL8202M
Typical Performance Characteristics (Continued)
Overvoltage Protection TA = +25°C, VIN = 5V, VOUT = 1.2V, CIN = 100µF POScap + 22µF ceramic capacitors, COUT = 2x22µF ceramic
capacitors.
SW 5V/DIV
VOUT 500mV/DIV
PGOOD 5V/DIV
640µs/DIV
FIGURE 27. OUTPUT OVERVOLTAGE PROTECTION
Power Loss TA = +25°C, CIN = 100µF POScap + 22µF ceramic capacitors, COUT = 2x22µF ceramic capacitors.
1.0
0.9
0.8
0.7 Vout=1.2V , Fsw=1.5MHz
0.6 Vout=3.3V, Fsw=2MHz
0.5
0.4
0.3
0.2
0.1
0.0
0 0.5 1 1.5 2 2.5
LOAD CURRENT (A)
FIGURE 28. POWER LOSS AT VIN = 5V, TA = +25°C
3
1.0
0.9
0.8
0.7 Vout=1.2V , Fsw=1.5MHz
0.6 Vout=2.5V, Fsw=2MHz
0.5
0.4
0.3
0.2
0.1
0.0
0 0.5 1 1.5 2 2.5
LOAD CURRENT (A)
FIGURE 29. POWER LOSS AT VIN = 3.3V, TA = +25°C
3
Derating All of the following curves were plotted at TJ = +120°C.
4.0
3.5
3.0
2.5
2.0
1.5 0LFM
1.0 200LFM
0.5
0.0
0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
FIGURE 30. DERATING CURVES AT VIN = 5V, VOUT = 1.2V
4.0
3.5
3.0
2.5
2.0
0LFM
1.5
200LFM
1.0
0.5
0.0
0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
FIGURE 31. DERATING CURVES AT VIN = 5V, VOUT = 3.3V
FN8761 Rev.4.00
Mar 17, 2017
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ISL8202M
Typical Performance Characteristics (Continued)
4.0 4.0
3.5 3.5
3.0 3.0
2.5 2.5
2.0 2.0
1.5 1.5 0LFM
1.0
0LFM
1.0
200LFM
0.5
200LFM
0.5
0.0
0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
FIGURE 32. DERATING CURVES AT VIN = 3.3V, VOUT = 1.2V
0.0
0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
FIGURE 33. DERATING CURVES AT VIN = 3.3V, VOUT = 2.5V
VIN (V)
5
5
5
5
5
5
5
5
3.3
3.3
3.3
3.3
3.3
3.3
3.3
VOUT (V)
0.6
0.9
1
1.2
1.5
1.8
2.5
3.3
0.6
0.9
1
1.2
1.5
1.8
2.5
TABLE 2. ISL8202M DESIGN GUIDE MATRIX (REFER TO Figure 1)
fSW (MHz)
0.8
CIN (µF)
2x22
COUT (µF)
3x22
RFS (kΩ)
261
1.2
2x22
3x22
169
1.3
2x22
2x22
154
1.5
2x22
2x22
133
1.9
2x22
2x22
102
2
2x22
2x22
95.3
2
2x22
2x22
95.3
2
2x22
2x22
95.3
0.8
2x22
3x22
261
1.2
2x22
3x22
169
1.3
2x22
2x22
154
1.5
2x22
2x22
133
1.9
2x22
2x22
102
2
2x22
2x22
95.3
2
2x22
2x22
95.3
RSET (kΩ)
OPEN
200
150
100
66.5
49.9
31.6
22.1
OPEN
200
150
100
66.5
49.9
31.6
CFF (pF)
680
680
680
560
390
390
220
330
680
680
680
560
390
390
220
CLOCK
IL
0
VOUT
PWM
PFM
16 CYCLES
NOMINAL +1.2%
PFM CURRENT LIMIT
LOAD CURRENT
NOMINAL
NOMINAL -2.5%
FIGURE 34. PFM MODE OPERATION WAVEFORMS
PWM
FN8761 Rev.4.00
Mar 17, 2017
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3A Single Channel High Efficiency DC/DC Step-Down Power Module

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ISL8202M
Functional Description
The ISL8202M is a single channel 3A step-down high efficiency
power module optimized for FPGA, DSP and Li-ion battery power
devices. The module switches at 1.8MHz by default when the FS
pin is shorted to VIN. The switching frequency is also adjustable
from 680kHz to 3.5MHz through a resistor, RFS, from FS to
SGND. To boost light-load efficiency, ISL8202M can also be
configured to operate in PFM mode by pulling the SYNC pin to
SGND. Peak current mode control scheme is implemented for
fast transient response. By shorting the COMP pin to VIN, the
module utilizes internal compensation to stabilize system and
optimize transient response. Other excellent features include
external synchronization, 100% duty cycle operation and very low
quiescent current.
PWM Control Scheme
Pulling the SYNC pin high (>0.8V) forces the module into PWM
mode, regardless of output current. The ISL8202M employs the
current-mode Pulse-Width Modulation (PWM) control scheme for
fast transient response and pulse-by-pulse current limiting. As
shown in Figure 3 on page 3, the current loop consists of the
oscillator, the PWM comparator, current sensing circuit and the
slope compensation for the current loop stability. The slope
compensation is 440mV/Ts, which changes with frequency. The
gain for the current sensing circuit is typically 140mV/A. The control
reference for the current loops comes from the Error Amplifier's
(EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier, CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
PFET and turn on the N-channel MOSFET. The NFET stays on until
the end of the PWM cycle. Figure 35 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the slope compensation ramp and the Current-Sense
Amplifier’s (CSA) output.
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during
start-up and will be discussed separately, please refer to “Soft
Start-Up” on page 16. The error amplifier is a transconductance
amplifier that converts the voltage error signal to a current
output. When the COMP is tied to VIN, the voltage loop is
internally compensated with the 55pF and 100kΩ RC network.
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 35. PWM OPERATION WAVEFORMS
PFM (Skip) Mode
Pulling the SYNC pin LOW (<0.4V) forces the module into PFM
mode. The ISL8202M enters a pulse-skipping mode at light load
to minimize the switching losses by reducing the switching
frequency. Figure 34 illustrates the Skip mode operation. A
zero-cross sensing circuit shown in Figure 3 on page 3 monitors
the NFET current for zero crossing. When 16 consecutive cycles
are detected, the module enters the Skip mode. During the
sixteen detecting cycles, the current in the inductor is allowed to
become negative. The counter is reset to zero when the current in
any cycle does not cross zero.
Once the Skip mode is entered, the pulse modulation starts
being controlled by the skip comparator shown in Figure 3 on
page 3. Each pulse cycle is still synchronized by the PWM clock.
The PFET is turned on at the clock's rising edge and turned off
when the output is higher than 1.2% of the nominal regulation or
when its current reaches the peak skip current limit value. Then,
the inductor current is discharged to 0A and stays at zero (the
internal clock is disabled) and the output voltage reduces
gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the PFET will be turned on again at the rising edge of the internal
clock as it repeats the previous operations. The module resumes
normal PWM mode operation when the output voltage drops
2.5% below the nominal voltage.
Frequency Adjust
The switching frequency of ISL8202M is adjustable ranging from
680kHz to 3.5MHz via a simple resistor, RFS, across FS to SGND.
The switching frequency setting is based on Equation 1:
RFSk = -f-O--2---S2---0-C-------k1---H-0---3-z----14
(EQ. 1)
When the FS pin is directly tied to VIN, the frequency of operation is
fixed at 1.8MHz. For selections of switching frequency of typical
operation conditions, refer to Table 2 on page 14. More detailed
information on recommended switching frequency
recommendation is provided in “Recommended Switching
Frequency” on page 17.
FN8761 Rev.4.00
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ISL8202M
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3 on page 3.
The current sensing circuit has a gain of 140mV/A, from the PFET
current to the CSA output. When the CSA output reaches the
threshold, the OCP comparator is tripled and turns off the PFET
immediately. The overcurrent function protects the module from a
shorted output by monitoring the current flowing through the
upper MOSFET.
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to 1. If,
on the subsequent cycle, another overcurrent condition is
detected, the OC fault counter will be incremented. If there are
17 sequential OC fault detections, the module will be shut down
under an overcurrent fault condition. An overcurrent fault
condition will result in the module attempting to restart in a
hiccup mode within the delay of eight soft-start periods. At the
end of the 8th soft-start wait period, the fault counters are reset
and soft-start is attempted again. If the overcurrent condition
goes away during the delay of 8 soft-start periods, the output will
resume back into regulation after hiccup mode expires.
Negative Current Protection
Similar to overcurrent, the negative current protection is realized
by monitoring the current across the low-side NFET, as shown in
Figure 3 on page 3. When the valley point of the inductor current
reaches -3A for 4 consecutive cycles, both PFET and NFET are
turned off. The 100Ω in parallel to the NFET will activate
discharging the output into regulation. The control will begin to
switch when output is within regulation. The module will be in PFM
for 20µs before switching to PWM, if necessary.
Power-Good
PG is an open-drain output of a window comparator that
continuously monitors the module output voltage. PG is actively held
low when EN is low and during the module soft-start period. After
1ms delay of the soft-start period, PG becomes high impedance as
long as the output voltage is within the nominal regulation voltage
set by VFB. Under output overvoltage fault condition (output voltage
is 33% higher than nominal value) or output undervoltage fault
condition (output voltage is 15% lower than nominal value), the PG
will be pulled low. Any fault condition forces PG low until the fault
condition is cleared by attempts to soft-start. For logic level output
voltages, connect an external pull-up resistor, between PG and VIN.
A 100kΩ resistor works well in most applications.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the module is disabled.
Soft Start-Up
The soft start-up reduces the inrush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed, so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
FN8761 Rev.4.00
Mar 17, 2017
200kHz, so that the output can start-up smoothly at light load
condition. During soft-start, the IC operates in the Skip mode to
support prebiased output condition.
Tie SS to SGND for internal soft-start, which is approximately
1ms. Connect a capacitor from SS to SGND to adjust the
soft-start time. This capacitor, along with an internal 1.85µA
current source sets the soft-start interval of the module, tSS, as
shown by Equation 2:
CSSF= 3.1 tSSs
(EQ. 2)
CSS must be less than 33nF to insure proper soft-start reset after
fault condition.
External Synchronization Control
The frequency of operation can be synchronized up to 3.5MHz by
an external signal applied to the SYNC pin. The rising edge of
SYNC signal triggers the rising edge of PWM ON pulse. To ensure
proper operation, it is recommended that the external SYNC
frequency is within ±25% of the switching frequency set by FS
pin.
Enable
The enable (EN) input allows the user to control the turning on or off
of the module for purposes such as power-up sequencing. When the
module is enabled, there is typically a 600µs delay for waking up
the bandgap reference and then the soft start-up begins.
Discharge Mode (Soft-Stop)
When a transition to Shutdown mode occurs or the VIN UVLO is
set, the output discharges to PGND through an internal 100Ω
switch.
100% Duty Cycle
The ISL8202M features a 100% duty cycle operation to minimize
switching loss. When the input voltage drops to a level that the
ISL8202M can no longer maintain the regulation at the output,
the module completely turns on the PFET.
Thermal Shutdown
The ISL8202M has built-in thermal protection. When the internal
temperature reaches +150°C, the module is completely shut down.
As the temperature drops to +125°C, the ISL8202M resumes
operation by stepping through the soft-start.
Applications Information
Programming the Output Voltage
The output voltage of the module is programmed by an external
resistor, as RSET in Figure 1 on page 1 applied from FB pin to
SGND. RSET in combination with the internal 100kΩ 0.5%
resistor connected from FB to VSENSE forms resistor divider that
sets the output voltage. The output voltage is governed by
Equation 3:
VOUT = VREF R-----S----E----TR-----S+---E-1---T-0---0----k------
(EQ. 3)
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ISL8202M
. TABLE 3. TYPICAL VOLTAGE SETTING RESISTOR VALUES
VOUT (V)
0.6
RSET (kΩ)
OPEN
0.8 300
1.0 150
1.2 100
1.8 49.9
2.5 31.6
3.3 22.1
Please note that the output voltage accuracy is also dependent
on the resistor accuracy of RSET. The user needs to select high
accuracy resistors in order to achieve the overall output accuracy.
Recommended Switching Frequency
With varieties of input and output voltage combinations, one
must choose wisely on which frequency to operate at. Selection
of switching frequency for each VIN and VOUT combination needs
to take in to account a few trade-offs. Generally, lower switching
frequency will lead to higher efficiency. However, switching
frequency should not be decreased too low due to negative
current protection limit. Moreover, when output voltage is
relatively high, low switching frequency will result in more sub-
harmonic oscillation. Therefore, operating frequency needs to be
kept relatively high under high VOUT conditions. However, again,
switching frequency cannot be increased too much. Otherwise,
the minimum on-time limit could be violated. Based on these
considerations, Figure 36 provides the recommended switching
frequency under various typical VIN and across VOUT range.
3.0
2.5
2.0
1.5
1.0 VIN=5V
VIN=4V
0.5 VIN=3.3V
VIN=2.6V
0.0
0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5
OUTPUT VOLTAGE (V)
FIGURE 36. SWITCHING FREQUENCY RECOMMENDATION
Input Capacitor Selection
Selection of the input filter capacitor is based on how much
ripple the supply can tolerate on the DC input line. The larger the
capacitor, the less ripple expected, however, consideration
should be given to the higher surge current during power-up. The
ISL8202M provides a soft-start function that controls and limits
the current surge. The total capacitance the input capacitor can
be calculated based on Equation 4:
CINMIN= -I-O-V----P------D-P------1---f--S–----W-D-----
(EQ. 4)
Where:
• CIN(MIN) is the minimum required input capacitance (µF)
• IO is the output current (A)
• D is the duty cycle
• VP-P is the allowable peak-to-peak voltage (V)
• fSW is the switching frequency (Hz)
Low Equivalent Series Resistance (ESR) ceramic capacitance is
recommended to be placed as close as possible to the module
input to reduce input voltage ripple and decouple between the
VIN and PGND. This capacitance not only reduces voltage ringing
created by the switching current across parasitic circuit elements
but also reduce the input noise seen by the module. Moreover,
the estimated RMS ripple current should be considered in
choosing ceramic capacitors. The RMS ripple current can be
calculated by Equation 5:
IINRMS
=
I---o--------D-------1-----–----D-----
(EQ. 5)
Each 22µF X5R or X7R ceramic capacitor is typically good for 2A
to 3A of RMS ripple current. Refer to the capacitor vendor to
check the RMS current ratings.
Based on the above considerations, minimum total input
capacitance of 44µF is required for ISL8202M. Add additional
capacitance if possible. Use X5R or X7R ceramic capacitors. The
placement of the input ceramic capacitors should be as close as
possible to the module input. Refer to “PCB Layout Pattern
Design” on page 20 for more information. A bulk input
capacitance may also be needed if the input source does not
have enough output capacitance. A typical value of bulk input
capacitor is 100µF. In such conditions, this bulk input
capacitance can supply the current during output load transient
conditions.
Output Capacitor Selection
Ceramic capacitors are typically used as the output capacitors
for the ISL8202M. Refer to Table 2 on page 14 for recommended
output capacitor values. Bulk output capacitors that have
adequately low Equivalent Series Resistance (ESR), such as low
ESR polymer capacitors or a low ESR tantalum capacitor, may
also be used in combination with the ceramic capacitors,
depending on the output voltage ripple and transient
requirements.
Feed-Forward Capacitor Selection
In typical applications where the output capacitors are all ceramic, a
feed-forward capacitor, as shown as CFF in Figure 1 on page 1, is
needed to insure loop stability in extreme operating conditions. With
internal compensation mode enabled, the CFF values for typical
operating conditions are optimized and listed in Table 2 on page 14.
Please note that, for system parameters that are different from
Table 2 or external instead of internal compensation is used, the
optimized value of CFF needs to be adjusted.
FN8761 Rev.4.00
Mar 17, 2017
Page 17 of 25


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ISL8202M
Typical Application Circuit
Figure 1 on page 1 only illustrates the application circuit with
minimum external components required for operation in PWM
mode. A more comprehensive typical application circuit diagram is
shown in Figure 37. In this example, a pull-up resistor is added to
the PG pin to allow power-good signal monitoring. Soft start-up
time adjustment is achieved by adding a capacitor, CSS, to the SS
pin. Typical application circuit of PFM mode operation can also be
found in Figure 38.
2.6V TO 5.5V INPUT
CIN
2x22µF
RPU
10k
PGOOD
RFS
133k
CSS
15nF
ISL8202M
VIN
EN
SYNC
PG
FS
SS
SGND
EPAD
VOUT
SW
VSENSE
COMP
FB
PGND
1.2V 3A OUTPUT
COUT
2x22µF
RSET
100k
CFF
560pF
FIGURE 37. COMPLETE APPLICATION CIRCUIT DIAGRAM
2.6V TO 5.5V INPUT
CIN
2x22µF
RFS
133k
ISL8202M
VIN
EN
PG
SYNC
FS
SS
SGND
EPAD
VOUT
SW
VSENSE
COMP
FB
PGND
1.2V 3A OUTPUT
COUT
2x22µF
RSET
100k
CFF
560pF
FIGURE 38. TYPICAL APPLICATION CIRCUIT DIAGRAM IN PFM MODE
FN8761 Rev.4.00
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ISL8202M
Thermal Consideration and Current Derating
The ISL8202M’s thermally enhanced package offers typical
junction to ambient thermal resistance JA of approximately
27.4°C/W at natural convection with a typical 4-layer PCB board.
In applications with elevated ambient temperature, the
continuous current handling capability of the module may need
to be derated. The derating curves (Figure 30 through 33) are
fully tested. They are on the basis of determining the maximum
continuous load current while limiting the maximum junction
temperature to +120°C, which provides 5°C margin of safety
from the rated junction temperature of +125°C. The test was
done across various typical operation conditions, providing a
starting point for system thermal design. Note that all the
derating curves are obtained based on tests in free air with the
module mounted on the ISL8202MEVAL1Z evaluation board with
“direct attach” features. Refer to ISL8202MEVAL1Z User Guide
for evaluation board details. Also see Tech Brief TB379 for
general thermal metric information.
In real applications where the system parameters and layout are
different than the evaluation board, the customer can adjust the
margin of safety. Other heat sources and design margins also
need to be taken into consideration.
PCB Layout Recommendations
A few layout considerations need to be taken into account in
order to achieve proper operation of ISL8202M. An optimized
layout design also allows the module to have lower power loss
and good thermal performance. An illustrative layout example is
shown in Figures 39 and 40. Key points are listed in the
following:
• Place the input ceramic capacitors as close as possible to the
module input. These ceramic capacitors are used to minimize
the high frequency noise by reducing parasitic inductance of
the switching loop. Optimized placement of these capacitors
will not only lead to less switch node ringing but also minimize
the noise seen by the module to insure proper operation. It is
recommended to use X5R or X7R ceramic capacitors with
minimum total capacitance of 44µF at module input. It is a
MUST that one of the input capacitors (CIN1) with no less than
3.3µF capacitance should be placed on the same layer
(assuming top layer) as module and within less than 70 mil
clearance to module input (refer to Figure 39). For capacitors
on the bottom layer, it is recommended to have one (CIN2)
placed from VIN to PGND copper close to exposed pad
(Pad 20) vias (as shown in the layout example in Figure 40).
• Use large copper areas for power path (VIN, PGND) to minimize
conduction loss and thermal stress. Also, it is recommended to
use multiple vias to connect the power planes in different
layers. Use at least 5 vias on the exposed Pad 20 connected to
PGND plane(s) for the best thermal relief.
• Use a separate SGND ground copper area for components that
are connected to signal ground. Connect SGND copper to
module Pad 22 through multiple vias (refer to Figure 40).
Because Pad 22 is connected to module internal PGND at a
single location, the SGND copper area and PGND plane on the
PCB can be left separated.
• It is recommended to keep the SW pads only on the top and
inner layers of the PCB. Do not expose the SW pads to the
outside on the bottom layer of the PCB. In order to minimize
switch node resistance, connect Pads 21 and 9 using wide
trace or shape.
• If remote sense is needed, route remote sensing trace from
point-of-load to module VSENSE pin through quiet inner layer
that is shielded by PGND planes.
• Avoid routing noise-sensitive signal traces such as FB, COMP
near the noisy SW pins.
• The feedback and compensation network should be placed as
close as possible to the FB pins and far away from the SW pins.
FIGURE 39. LAYOUT EXAMPLE - TOP LAYER
FIGURE 40. LAYOUT EXAMPLE - BOTTOM LAYER
FN8761 Rev.4.00
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ISL8202M
Package Description
The ISL8202M is integrated into a Quad Flatpack No-lead (QFN)
package. This package has such advantages as good thermal
and electrical conductivity, low weight and small size. The QFN
package is applicable for surface mounting technology and is
becoming more common in the industry. The ISL8202M is a
copper leadframe based package with exposed copper thermal
pads, which have good electrical and thermal conductivity. The
copper leadframe and multicomponent assembly are
overmolded with polymer mold compound to protect these
devices.
The package outline, typical PCB layout pattern and typical
stencil pattern design are shown in the L22.4.5x7.5 “Package
Outline Drawing” on page 22. TB493 shows typical reflow profile
parameters. These guidelines are general design rules. Users can
modify parameters according to specific applications.
PCB Layout Pattern Design
The bottom of ISL8202M is a leadframe footprint, which is
attached to the PCB by surface mounting. The PCB layout pattern
is shown in the L22.4.5x7.5 “Package Outline Drawing” on
page 22. The PCB layout pattern is essentially 1:1 with the QFN
exposed pad and the I/O termination dimensions, except that the
PCB lands are slightly longer than the QFN terminations by about
0.2mm (0.4mm maximum). This extension allows for solder
filleting around the package periphery and ensures a more
complete and inspectable solder joint. The thermal lands on the
PCB layout should match 1:1 with the package exposed die pads.
Thermal Vias
A grid of 1.0mm to 1.2mm pitched thermal vias, which drops
down and connects to buried copper planes, should be placed
under the thermal land. The vias should be about 0.3mm to
0.33mm in diameter, with the barrel plated to about 2.0 ounce
copper. Although adding more vias (by decreasing pitch)
improves thermal performance, it also diminishes results as
more vias are added. Use only as many vias are needed for the
thermal land size and as your board design rules allow.
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2 mil to 3 mil) standoff height. The
solder paste stencil design is the first step in developing
optimized, reliable solder joins. The stencil aperture size to land
size ratio should typically be 1:1. Aperture width may be reduced
slightly to help prevent solder bridging between adjacent I/O
lands.
To reduce solder paste volume on the larger thermal lands, an
array of smaller apertures instead of one large aperture is
recommended. The stencil printing area should cover 50% to
80% of the PCB layout pattern. Consider the symmetry of the
whole stencil pattern when designing the pads.
A laser-cut, stainless-steel stencil with electropolished
trapezoidal walls is recommended. Electropolishing smooths the
aperture walls, resulting in reduced surface friction and better
paste release, which reduces voids. Using a Trapezoidal Section
Aperture (TSA) also promotes paste release and forms a
brick-like paste deposit, which assists in firm component
placement.
Reflow Parameters
Due to the low mount height of the QFN, “No Clean” Type 3 solder
paste, per ANSI/J-STD-005, is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board.
Thus it is not practical to define a specific soldering profile just
for the QFN. The profile given in TB493 is provided as a guideline
to customize for varying manufacturing practices and
applications.
FN8761 Rev.4.00
Mar 17, 2017
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ISL8202M
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
Mar 17, 2017
FN8761.4
Updated Ordering Information table tape and reel units for ISL8202MIRZ-T from 4k to 3k.
Aug 16, 2016
FN8761.3
Ordering Information table, Note 2 updated.
May 19, 2016
FN8761.2
Related Literature on page 1: Added UG071 link.
May 10, 2016
FN8761.1
Updated default setting from 1.9MHz to 1.8MHz throughout datasheet.
Updated title of datasheet.
Replaced Figure 1 on page 1.
Updated Figure 3 on page 3.
Updated typical specification for “Nominal Switching Frequency” on page 7 from 1900 to 1835.
Added Note 8 on page 8.
Added “Typical Application Circuit” section on page 18.
On page 25, replaced Recommended Stencil Perimeter Pads view to match POD.
Mar 21, 2016
FN8761.0
Initial release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2016-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8761 Rev.4.00
Mar 17, 2017
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Package Outline Drawing
L22.4.5x7.5
22 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/15
4.5 A
B
7.5
2x 1.610
2x 1.360
0.05 C A B
4x 0.390
1.300
2x 3.110
(2X) 0.05 C
(2X) 0.05 C
TOP VIEW
PIN 1
INDEX AREA
21x 0.250
0.450
1.000
For the most recent package outline drawing, see L22.4.5x7.5.
2x 0.390
4x 0.300
42x 0.220
0.10 C A B
0.05 C
38x 0.500 BSC
0.710
2x 0.350
11x 0.6
2x 0.890
2.900
2x 1.230
1.385
PIN 1 IDENTIFICATION
1.250
1.125
BOTTOM VIEW
1.500
1.885
1.500
1.000
1.000
1.90 MAX
0.05 C
(20x)
0.08 C 0.05
SIDE VIEW
SEE DETAIL “X”
C
SEATING PLANE
C 0.203 REF
0 - 0.05
DETAIL “X”
4
NOTES:
1. Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to ASMEY 14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05.
4. Tiebar shown (if present) is a non-functional feature.
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.


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2.450
1.650
1.125
1.360
1.140
1.250
0.860 0.865
0.640
0.250
0.365
1.000
0.360
0.140
0.00
0.140
0.360
0.640
0.650
0.950
1.360 1.250
1.700
1.650
1.800
2.450
PCB LAND PATTERN
2.450
1.950 1.860
0.640
0.360
0.140
0.00
0.140
0.360
0.640
1.860
1.950
2.450


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1.950
1.700
1.226
0.000
1.050
0.600
0.400
0.840
0.050
0.340
0.665
0.689
0.985
1.275
1.310
1.700
1.950
RECOMMENDED STENCIL INTERIOR PADS
1.950
1.659
1.445
1.245
0.741
0.000
0.741
1.245
1.445
1.659
1.950


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2.425
2.050
1.675
1.345
1.155
0.845
0.655
0.345
0.000
0.655
0.155
0.155
0.345
0.845
0.975
1.155
1.345
1.675
1.820
2.050
2.425
2.425
2.050
1.975
1.975
2.050
2.425
1.845
1.655
1.345
1.155
0.845
0.655
0.345
0.155
0.155
0.345
0.655
0.845
1.155
1.345
1.655
1.845
0.000
RECOMMENDED STENCIL PERIMETER PADS




ISL8202M.pdf
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