HYB25D128160CT (Infineon)
128 Mbit Double Data Rate SDRAM

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D a t a S h e e t , Rev. 1.0, A p r . 2 0 0 4
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Memory Products
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HYB25D128160CT (Infineon)
128 Mbit Double Data Rate SDRAM

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Edition 2004-04
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.


HYB25D128160CT (Infineon)
128 Mbit Double Data Rate SDRAM

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D a t a S h e e t , Rev. 1.0, A p r . 2 0 0 4
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
DDR SDRAM
Memory Products
Never stop thinking.


HYB25D128160CT (Infineon)
128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
Revision History:
Rev. 1.0
Previous Version:
Rev. 0.5
Page
Subjects (major changes since last revision)
removed Green and Standard form Cover Page
9 added Product Types removed Product Types
70 updated IDD values
2004-04
2003-11
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Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
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Template: mp_a4_v2.2_2003-10-07.fm


HYB25D128160CT (Infineon)
128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Table of Contents
1
1.1
1.2
2
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.3.1
3.3.2
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
4
4.1
4.2
4.3
4.3.1
5
6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Normal Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Weak Strength Pull-down and Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
IDD Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Data Sheet
5 Rev. 1.0, 2004-04


HYB25D128160CT (Infineon)
128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Pin Configuration P-TFBGA-60-9 Top View, see the balls throught the package . . . . . . . . . . . . . 15
Pin Configuration P-TSOPII-66-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Block Diagram 128Mbit ×16 Mbit ×16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Diagram 128Mbit ×32 Mbit ×8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Diagram 128Mbit ×64 Mbit ×4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Required CAS Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
tRCD and tRRD Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Burst: CAS Latencies (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . 31
Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . 32
Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . 33
Terminating a Read Burst: CAS Latencies (Burst Length = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read to Write: CAS Latencies (Burst Length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Read to Precharge: CAS Latencies (Burst Length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Write Burst (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Write to Write (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . 42
Random Write Cycles (Burst Length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4). . . . . . . . . . . . . . . . . . . . . . 44
Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8). . . . . . . . . . . . . . . . . . . . . . . . . . 45
Write to Read: Min. DQSS, Odd Number of Data (3-bit Write), Interrupting (CL2; BL8) . . . . . . . . 46
Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8) . . . . . . . . . . . . 47
Write to Precharge: Non-Interrupting (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Write to Precharge: Interrupting (Burst Length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Write to Precharge: Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (BL 4 or 8). 50
Write to Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length = 4 or 8) . . . . . . . . . 51
Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Normal Strength Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Normal Strength Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Weak Strength Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Weak Strength Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Data Input (Write), Timing Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Data Output (Read), Timing Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Initialize and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Auto Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Read without Auto Precharge (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Read with Auto Precharge (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Bank Read Access (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Write without Auto Precharge (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Write with Auto Precharge (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Bank Write Access (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Write DM Operation (Burst Length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
P-TFBGA-60-2 (Plastic Thin Fine-Pitch Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . . . . 84
P-TSOPII-66-1 (Plastic Thin Small Outline Package Type II). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Data Sheet
6 Rev. 1.0, 2004-04
10222003-25HM-16E0


HYB25D128160CT (Infineon)
128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 7
Table 6
Table 9
Table 8
Table 10
Table 11
Table 12
Table 13
Table 14
Table 16
Table 15
Table 17
Table 19
Table 18
Table 20
Table 21
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . 54
Truth Table 2: Clock Enable (CKE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . 56
Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Electrical Characteristics and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Evaluation Conditions for I/O Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Normal Strength Pull-down and Pull-up Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Weak Strength Driver Pull-down and Pull-up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100 . . . . . . . . . . . . . . . . . . . . 66
AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Data Sheet
7 Rev. 1.0, 2004-04
10222003-25HM-16E0


HYB25D128160CT (Infineon)
128 Mbit Double Data Rate SDRAM

No Preview Available !

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128 Mbit Double Data Rate SDRAM
DDR SDRAM
HYB25D128[400/800/160]C[C/E/T](L)
1 Overview
1.1 Features
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 2, 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8 µs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
VDDQ = 2.5 V ± 0.2 V (DDR266A, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400)
VDD = 2.5 V ± 0.2 V (DDR266, DDR333); VDD = 2.6 V ± 0.1 V (DDR400)
• P-TFBGA-60-2 package with 3 depopulated rows (12 × 8 mm2)
• P-TSOPII-66-1 package
• Lead- and halogene-free = green product
1.2 Description
The 128 Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 128 Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer
two data words per clock cycle at the I/O pins. A single read or write access for the 128 Mbit Double Data Rate
SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and
two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned with data for Writes.
The 128 Mbit Double Data Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going
HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are
registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and row to be accessed. The address bits
registered coincident with the Read or Write command are used to select the bank and the starting column location
for the burst access.
Data Sheet
8 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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128 Mbit Double Data Rate SDRAM
Overview
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled
mode of operation.
Table 1 Ordering Information
Part Number1)
Org. CAS-RCD- Clock
RP (MHz)
Latencies
CAS-RCD- Clock Speed
RP (MHz)
Latencies
Package
HYB25D128160CT-5
HYB25D128160CT-6
HYB25D128800CT-6
HYB25D128800CTL-6
HYB25D128400CT-7
HYB25D128400CC-6
×16 3-3-3
×16 2.5-3-3
×8
×8
×4
×4
200
166
2.5 - 3 - 3
2-3-3
166 DDR400B P-TSOPII-66-1
133 DDR333
DDR266A
DDR333 P-FBGA-60-2
HYB25D128160CE–5
HYB25D128400CE–6
HYB25D128800CE–6
HYB25D128800CEL–6
HYB25D128160CE–6
×16 3-3-3
×4 2.5-3-3
×8
×8
×16
200
166
2.5 - 3 - 3
2-3-3
166 DDR400B P-TSOPII-66-1
133 DDR333
1) HYB: designator for memory components
25D: DDR SDRAMs at VDDQ = 2.5 V
128: 128-Mbit density
400/800/160: Product variations x4, x8 and x16
C: Die revision C
T/E/C: Package type TSOP and FBGA
L: Low power version (optional) - these components are specifically selected for low IDD6 Self Refresh currents
-5/6/7/7F/8: speed grade - see Table 1
Data Sheet
9 Rev. 1.0, 2004-04


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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
2 Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 2 (60 pins). The abbreviations used in the
Pin#/Buffer# column are explained in Table 3 and Table 4 respectively. The pin numbering for FBGA is depicted
in Figure 1 and that of the TSOP package in Figure 2
Table 2 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
Clock Signals
G2, 45
CK1 I
SSTL Clock Signal
Note: CK and CK are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossings of CK and CK (both
directions of crossing).
G3, 46
CK1 I
SSTL Complementary Clock Signal
H3, 44
CKE
I
SSTL Clock Enable
Note: CKE HIGH activates, and CKE Low deactivates, internal
clock signals and device input buffers and output drivers.
Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down
(row Active in any bank). CKE is synchronous for power
down entry and exit, and for self refresh entry. CKE is
asynchronous for self refresh exit. CKE must be maintained
high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during power-
down. Input buffers, excluding CKE, are disabled during self
refresh.
Control Signals
H7, 23
RAS
I
SSTL Row Address Strobe
G8, 22
CAS
I
SSTL Column Address Strobe
G7, 21
WE I
SSTL Write Enable
H8, 24
CS I
SSTL Chip Select
Note: All commands are masked when CS is registered HIGH. CS
provides for external bank selection on systems with
multiple banks. CS is considered part of the command code.
The standard pinout includes one CS pin.
Address Signals
J8, 26
BA0 I
SSTL Bank Address Bus 2:0
J7, 27
BA1 I
SSTL
Note: BA0 and BA1 define to which bank an Active, Read, Write
or Precharge command is being applied. BA0 and BA1 also
determines if the mode register or extended mode register
is to be accessed during a MRS or EMRS cycle.
Data Sheet
10 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM
Pin Configuration
Table 2 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
K7, 29
A0 I
SSTL Address Bus 11:0
L8, 30
L7, 31
M8, 32
M2, 35
L3, 36
L2, 37
K3, 38
K2, 39
A1 I
A2 I
A3 I
A4 I
A5 I
A6 I
A7 I
A8 I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Note: Provide the row address for Active commands, and the
column address and Auto Precharge bit for Read/Write
commands, to select one location out of the memory array
in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to
one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0, BA1.
The address inputs also provide the op-code during a Mode
Register Set command.
J3, 40
A9 I
SSTL
K8, 28
A10 I
SSTL
AP I
SSTL
J2, 41
A11 I
SSTL
H2, 42
A12 I
SSTL Address Signal 12
Note: Module based on 256 Mbit or larger dies
NC NC —
Note: Module based on 128 Mbit or smaller dies
F9, 17
A13 I
SSTL Address Signal 13
Note: 1 Gbit based module
NC NC —
Note: Module based on 512 Mbit or smaller dies
Data Signals ×4 organization
B7, 5
DQ0 I/O SSTL Data Signal Bus 3:0
D7, 11
DQ1 I/O SSTL
D3, 56
DQ2 I/O SSTL
B3, 62
DQ3 I/O SSTL
Data Strobe ×4 organisation
E3, 51
DQS I/O
SSTL Data Strobe
Note: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write
data.
Data Mask ×4 organization
F3, 47
DM I
SSTL Data Mask
Note: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading
Data Sheet
11 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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128 Mbit Double Data Rate SDRAM
Pin Configuration
Table 2 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
Data Signals ×8 organization
A8, 2
DQ0 I/O SSTL Data Signal Bus 7:0
B7, 5
DQ1 I/O SSTL
C7, 8
DQ2 I/O SSTL
D7, 11
DQ3 I/O SSTL
D3, 56
DQ4 I/O SSTL
C3, 59
DQ5 I/O SSTL
B3, 62
DQ6 I/O SSTL
A2, 65
DQ7 I/O SSTL
Data Strobe ×8 organisation
E3, 51
DQS I/O
SSTL Data Strobe
Note: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write
data.
Data Mask ×8 organization
F3, 47
DM I
SSTL Data Mask
Note: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading.
Data Signals ×16 organization
A8, 2
DQ0 I/O SSTL Data Signal 15:0
B9, 4
DQ1 I/O SSTL
B7, 5
DQ2 I/O SSTL
C9, 7
DQ3 I/O SSTL
C7, 8
DQ4 I/O SSTL
D9, 10
DQ5 I/O SSTL
D7, 11
DQ6 I/O SSTL
E9, 13
DQ7 I/O SSTL
E1, 54
DQ8 I/O SSTL
D3, 56
DQ9 I/O SSTL
D1, 57
DQ10 I/O
SSTL
C3, 59
DQ11 I/O
SSTL
C1, 60
DQ12 I/O
SSTL
B3, 62
DQ13 I/O
SSTL
B1, 63
DQ14 I/O
SSTL
A2, 65
DQ15 I/O
SSTL
Data Strobe ×16 organization
E3, 51
UDQS I/O
SSTL Data Strobe Upper Byte
E7, 16
LDQS I/O
SSTL Data Strobe Lower Byte
Data Mask ×16 organization
Data Sheet
12 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
Table 2 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
F3, 47
UDM I
SSTL Data Mask Upper Byte
F7, 20
LDM
I
SSTL Data Mask Lower Byte
Power Supplies
F1, 49
A9, B2, C8,
D2, E8, 3, 9,
15, 55, 61
VREF
VDDQ
AI —
PWR —
I/O Reference Voltage
I/O Driver Power Supply
A7, F8, M3, VDD
M7, 1, 18, 33
PWR —
Power Supply
A1, B8, C2, VSSQ
D8, E2, 6, 12,
52, 58, 64
PWR —
Power Supply
F2, 34
VSS
Not Connected
PWR —
Power Supply
A2, 65
NC NC —
Not Connected
Note: ×4 organization
A8, 2
NC NC —
Not Connected
Note: ×4 organization
B1, 63
NC NC —
Not Connected
Note: ×8 and ×4 organisation
B9, 4
NC NC —
Not Connected
Note: ×8 and ×4 organization
C1, 60
NC NC —
Not Connected
Note: ×8 and ×4 organization
C3, 59
NC NC —
Not Connected
Note: ×4 organization
C7, 8
NC NC —
Not Connected
Note: ×4 organization
C9, 7
NC NC —
Not Connected
Note: ×8 and ×4 organization
D1, 57
NC NC —
Not Connected
Note: ×8 and ×4 organization
D9, 10
NC NC —
Not Connected
Note: ×8 and ×4 organization
E1, 54
NC NC —
Not Connected
Note: ×8 and ×4 organization
E7, 16
NC NC —
Not Connected
Note: ×8 and ×4 organization
E9, 13
NC NC —
Not Connected
Note: ×8 and ×4 organization
F7, 20
NC NC —
Not Connected
Note: ×8 and ×4 organization
Data Sheet
13 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
Table 2 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
14, 17, 19, 25, NC
43, 50
NC —
Not Connected
×168 and ×4 organization
Table 3
Abbreviations for Pin Type
Abbreviation
Description
I Standard input-only pin. Digital levels.
O Output. Digital levels.
I/O I/O is a bidirectional input/output signal.
AI Input. Analog levels.
PWR
Power
GND
Ground
NC Not Connected (JEDEC Standard)
Table 4
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Data Sheet
14 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
123456789
VSSQ N.C. VSS A VDD N.C. VDDQ
N.C. VDDQ DQ3 B DQ0 VSSQ N.C.
N.C. VSSQ N.C. C N.C. VDDQ N.C.
N.C. VDDQ DQ2 D DQ1 VSSQ N.C.
N.C. VSSQ DQS E N.C. VDDQ N.C.
VREF
VSS
DM
F N.C. VDD NC/A13
CK CK G WE CAS
NC/A12 CKE H RAS CS
A11 A9
J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS M VDD A3
(x4)
123456789
VSSQ DQ7 VSS A VDD DQ0 VDDQ
N.C. VDDQ DQ6 B DQ1 VSSQ N.C.
N.C. VSSQ DQ5 C DQ2 VDDQ N.C.
N.C. VDDQ DQ4 D DQ3 VSSQ N.C.
N.C. VSSQ DQS E N.C. VDDQ N.C.
VREF
VSS
DM
F N.C. VDD NC/A13
CK CK G WE CAS
NC/A12 CKE H RAS CS
A11 A9
J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS M VDD A3
(x8)
Figure 1
1 2 3 4 56 7 8 9
VSSQ DQ15 VSS
A VDD DQ0 VDDQ
DQ14 VDDQ DQ13 B DQ2 VSSQ DQ1
DQ12 VSSQ DQ11
C
DQ4 VDDQ DQ3
DQ10 VDDQ DQ9 D DQ6 VSSQ DQ5
DQ8 VSSQ UDQS E LDQS VDDQ DQ7
VREF VSS UDM F LDM VDD NC/A13
CK CK
G WE CAS
NC/A12 CKE H RAS CS
A11 A9
J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS
M VDD A3
(x16)
Pin Configuration P-TFBGA-60-9 Top View, see the balls throught the package
MPPD0060
Data Sheet
15 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
64 Mb x 4
32 Mb x 8
16 Mb x 16
V
DD
N.C.
V
DD
DQ0
V
DD
DQ0
V
DDQ
N.C.
V
DDQ
N.C.
V
DDQ
DQ1
DQ0 DQ1 DQ2
V
SSQ
N.C.
V
SSQ
N.C.
V
SSQ
DQ3
N.C. DQ2 DQ4
V
DDQ
N.C.
V
DDQ
N.C.
V
DDQ
DQ5
DQ1 DQ3 DQ6
V
SSQ
N.C.
V
SSQ
N.C.
V
SSQ
DQ7
N.C. N.C. N.C.
V
DDQ
N.C.
V
DDQ
N.C.
V
DDQ
LDQS
A13/N.C. A13/N.C. A13/N.C.
V
DD
N.C.
V
DD
N.C.
V
DD
N.C.
N.C. N.C. LDM
WE WE WE
CAS CAS CAS
RAS RAS RAS
CS CS CS
N.C. N.C. N.C.
BA0 BA0 BA0
BA1 BA1 BA1
A10/AP A10/AP A10/AP
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
V
DD
V
DD
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Figure 2 Pin Configuration P-TSOPII-66-1
66 V V V
SS SS SS
65 DQ15 DQ7 N.C.
64 V V V
SSQ
SSQ
SSQ
63 DQ14 N.C. N.C.
62 DQ13 DQ6 DQ3
61 V V V
DDQ
DDQ
DDQ
60 DQ12 N.C. N.C.
59 DQ11 DQ5 N.C.
58 V V V
SSQ
SSQ
SSQ
57 DQ10 N.C. N.C.
56 DQ9 DQ4 DQ2
55 V V V
DDQ
DDQ
DDQ
54 DQ8 N.C. N.C.
53 N.C. N.C. N.C.
52 V V V
SSQ
SSQ
SSQ
51 UDQS DQS DQS
50 N.C. N.C. N.C.
49 V V V
REF
REF
REF
48 V V V
SS SS SS
47
UDM DM
DM
46 CK CK CK
45 CK CK CK
44 CKE CKE CKE
43 N.C. N.C. N.C.
42 A12/N.C. A12/N.C. A12/N.C.
41 A11 A11 A11
40 A9 A9 A9
39 A8 A8 A8
38 A7 A7 A7
37 A6 A6 A6
36 A5 A5 A5
35 A4 A4 A4
34 V V V
SS SS SS
MPPD0070
Data Sheet
16 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
Drivers
Receivers
Read Latch
Bank0
Row-Address Latch
& Decoder
Bank Control Logic
Row-Address MUX
Refresh Counter
Address Register
Figure 3 Block Diagram 128Mbit ×16 Mbit ×16
Data Sheet
17 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
Drivers
Receivers
Read Latch
Bank0
Row-Address Latch
& Decoder
Bank Control Logic
Row-Address MUX
Refresh Counter
Figure 4 Block Diagram 128Mbit ×32 Mbit ×8
Address Register
Data Sheet
18 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
Drivers
Receivers
Read Latch
Bank0
Row-Address Latch
& Decoder
Bank Control Logic
Row-Address MUX
Refresh Counter
Figure 5 Block Diagram 128Mbit ×64 Mbit ×4
Address Register
Data Sheet
19 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3 Functional Description
The 128 Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing
268,435,456 bits. The 128 Mbit Double Data Rate SDRAM is internally configured as a quad-bank DRAM.
The 128 Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer
two data words per clock cycle at the I/O pins. A single read or write access for the 128 Mbit Double Data Rate
SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The address bits registered coincident with the Read or Write command are used
to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed
information covering device initialization, register definition, command descriptions and device operation.
3.1 Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation. The following criteria must be met:
No power sequencing is specified during power up or power down given the following criteria:
VDD and VDDQ are driven from a single power converter output
VTT meets the specification
• A minimum resistance of 42 limits the input current from the VTT supply into any pin and VREF tracks VDDQ/2
or the following relationship must be followed:
VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V
VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3 V
VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3 V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read
access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM
requires a 200 µs delay prior to applying an executable command.
Once the 200 µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode
Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode
Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. 200 clock cycles are required between the DLL reset and any executable command. During the
200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a
Precharge ALL command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set
command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without
resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
Data Sheet
20 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM
Functional Description
3.2 Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is
programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information
until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-
A6 specify the CAS latency, and A7-A11 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
MR
Mode Register Definition
(BA[1:0] = 00B)
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00
MODE
CL BT BL
reg. addr
w
www
Field
BL
Bits
[2:0]
Type1) Description
w Burst Length
Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1.
Note: All other bit combinations are RESERVED.
BT 3
w
CL [6:4] w
001 2
010 4
011 8
Burst Type
See Table 5 for internal address sequence of low order address bits; see Chapter 3.2.2.
0 Sequential
1 Interleaved
CAS Latency
Number of full clocks from read command to first data valid window; see Chapter 3.2.3.
Note: All other bit combinations are RESERVED.
MODE [12:7] w
010 2
011 3
101 1.5
Note: DDR200 components only
110 2.5
Operating Mode
See Chapter 3.2.4.
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) w = write
3.2.1 Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given Read or Write
command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Data Sheet
21 Rev. 1.0, 2004-04


HYB25D128160CT (Infineon)
128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst
length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst length applies to both Read and Write bursts.
3.2.2 Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 5.
Table 5
Burst
Length
2
4
8
Burst Definition
Starting Column Address
Order of Accesses Within a Burst
A2 A1 A0 Type = Sequential
Type = Interleaved
0 0-1
0-1
1 1-0
1-0
0 0 0-1-2-3
0-1-2-3
0 1 1-2-3-0
1-0-3-2
1 0 2-3-0-1
2-3-0-1
1 1 3-0-1-2
3-2-1-0
0 0 0 0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the
block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within
the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
3.2.3 Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and
the availability of the first burst of output data. The latency can be programmed 2, 2.5 and 3 clocks. CAS latency
of 1.5 is supported for DDR200 components only.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally
coincident with clock edge n + m (see Figure 6).
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Data Sheet
22 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3.2.4 Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A11 set to zero,
and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with
bits A7 and A9-A11 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register
Set command issued to reset the DLL should always be followed by a Mode Register Set command to select
normal operating mode.
All other combinations of values for A7-A11 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
CK
CK
Command
DQS
DQ
Read
NOP
CL=2
NOP
CAS Latency = 2, BL = 4
NOP
NOP
NOP
CK
CK
Command
DQS
DQ
Read
NOP
CL=2.5
NOP
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 6 Required CAS Latencies
CAS Latency = 2.5, BL = 4
NOP
NOP
NOP
Don’t Care
Data Sheet
23 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3.3 Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional
functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled
via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the
Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed
again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the
controller must wait the specified time before initiating any subsequent operation. Violating either of these
requirements result in unspecified operation.
EMR
Extended Mode Register Definition
(BA[1:0] = 01B)
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01
reg. addr
MODE
w
DS DLL
ww
Field
DLL
Bits
0
DS 1
MODE [12:2]
1) w = write
Type1)
w
w
w
Description
DLL Status
See Chapter 3.3.1.
0 Enabled
1 Disabled
Drive Strength
See Chapter 3.3.2, Chapter 4.1 and Chapter 4.2.
0 Normal
1 Weak
Operating Mode
Note: All other bit combinations are RESERVED.
00000000000Normal Operation
3.3.1 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is
automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self
refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command can be
issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon exit of self
refresh operation.
3.3.2 Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version
supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during
mode register set. I-V curves for the normal and weak drive strength are included in this document.
Data Sheet
24 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3.4 Commands
Deselect
The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is
effectively deselected. Operations already in progress are not affected.
No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted
commands from being registered during idle or wait states. Operations already in progress are not affected.
Mode Register Set
The mode registers are loaded via inputs A0-A11, BA0 and BA1. See mode register descriptions in Chapter 3.2.
The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A
subsequent executable command cannot be issued until tMRD is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row
remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that
bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before
opening a different row in the same bank.
Read
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1
inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don’t care] for x16, [i = 9,
j = don’t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on input A10
determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is
precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent
accesses.
Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1
inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where
[i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto
Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write
burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on
the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a
given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high,
the corresponding data inputs are ignored, and a Write is not executed to that byte/column location.
Precharge
The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge
command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t
Care”. Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write
commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that
bank, or if the previously open row is already in the process of precharging.
Data Sheet
25 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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128 Mbit Double Data Rate SDRAM
Functional Description
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction
with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write
command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent
in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that
the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to
the same bank until the precharge (tRP) is completed. This is determined as if an explicit Precharge command was
issued at the earliest possible time, as described for each burst type in Chapter 3.5.
Burst Terminate
The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most recently
registered Read command prior to the Burst Terminate command is truncated, as shown in Chapter 3.5.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR)
Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is
required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care”
during an Auto Refresh command. The 128 Mbit Double Data Rate SDRAM requires Auto Refresh cycles at an
average periodic interval of 7.8 µs (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight Auto Refresh commands can be posted in the system, meaning that the
maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is
9 × 7.8 µs (70.2 µs). This maximum absolute interval is short enough to allow for DLL updates internal to the
DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC between updates.
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self
Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is
automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh
(200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are
“Don’t Care” during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE
returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is
required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and
DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
Data Sheet
26 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
Table 6 Truth Table 1a: Commands
Name (Function)
Deselect (NOP)
No Operation (NOP)
Active (Select Bank And Activate Row)
Read (Select Bank And Column, And Start Read Burst)
Write (Select Bank And Column, And Start Write Burst)
CS RAS CAS WE Address MNE
H X X XX
NOP
L H H HX
NOP
L L H H Bank/Row ACT
L H L H Bank/Col Read
L H L L Bank/Col Write
Notes
1)2)
1)2)
1)3)
1)4)
1)4)
Burst Terminate
L H H LX
BST
1)5)
Precharge (Deactivate Row In Bank Or Banks)
L L H L Code
PRE
1)6)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L H X
AR/SR 1)7)8)
Mode Register Set
L L L L Op-Code MRS 1)9)
1) CKE is HIGH for all commands shown except Self Refresh.
2) Deselect and NOP are functionally interchangeable.
3) BA0-BA1 provide bank address and A0-A11 provide row address.
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4);
A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read
bursts with Auto Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the op-code to
be written to the selected Mode Register).
Table 7 Truth Table 1b: DM Operation
Name (Function)
Write Enable
Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
DM DQs Notes
L Valid 1)
H X 1)
Data Sheet
27 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3.5 Operations
3.5.1 Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must
be “opened” (activated). This is accomplished via the Active command and addresses A0-A11, BA0 and BA1 (see
Figure 7), which decode and select both the bank and the row to be activated. After opening a row (issuing an
Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A
subsequent Active command to a different row in the same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval between successive Active commands to the same
bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access overhead. The minimum time interval between
successive Active commands to different banks is defined by tRRD.
CK
CK
CKE
CS
RAS
CAS
WE
A0-A11
BA0, BA1
HIGH
RA
BA
RA = row address.
BA = bank address.
Don’t Care
Figure 7 Activating a Specific Row in a Specific Bank
CK
CK
Command
A0-A11
BA0, BA1
ACT
ROW
BA x
NOP
tRRD
Figure 8 tRCD and tRRD Definition
ACT
ROW
BA y
NOP
NOP
tRCD
RD/WR
COL
BA y
NOP
NOP
Don’t Care
Data Sheet
28 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3.5.2 Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are
initiated with a Read command, as shown on Figure 9.
The starting column and bank addresses are provided with the Read command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge
at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the
following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available following the CAS
latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or
negative clock edge (i.e. at the next crossing of CK and CK). Figure 10 shows general timing for each supported
CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is
known as the read preamble; the low state coincident with the last data-out element is known as the read
postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs goes High-Z.
Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command.
In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
The new Read command should be issued x cycles after the first Read command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Figure 11. A
Read command can be initiated on any clock cycle following a previous Read command. Nonconsecutive Read
data is illustrated on Figure 12. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
within a page (or pages) can be performed as shown on Figure 13.
CK
CK
CKE
CS
RAS
CAS
WE
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
A10
BA0, BA1
HIGH
CA
EN AP
DIS AP
BA
Figure 9 Read Command
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
Don’t Care
Data Sheet
29 Rev. 1.0, 2004-04


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128 Mbit Double Data Rate SDRAM

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CK
CK
Command
Address
DQS
DQ
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
CAS Latency = 2
Read
BA a,COL n
NOP
CL=2
NOP
NOP
DOa-n
NOP
NOP
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2.5
Read
BA a,COL n
NOP
NOP
NOP
CL=2.5
DOa-n
NOP
NOP
DO a-n = data out from bank a, column n.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 10 Read Burst: CAS Latencies (Burst Length = 4)
Don’t Care
Data Sheet
30 Rev. 1.0, 2004-04




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