PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
16-bit Microcontrollers (up to 256 KB Flash and
16 KB SRAM) with Advanced Analog
Operating Conditions
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
Core: 16-bit PIC24H CPU
• Code-efficient (C and Assembly) architecture
• Single-cycle mixed-sign MUL plus hardware divide
Clock Management
• ±2% internal oscillator
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast wake-up and start-up
Power Management
• Low-power management modes (Sleep, Idle,
Doze)
• Integrated Power-on Reset and Brown-out Reset
• 1.35 mA/MHz dynamic current (typical)
• 55 μA IPD current (typical)
Advanced Analog Features
• Two ADC modules:
- Configurable as 10-bit, 1.1 Msps with four
S&H or 12-bit, 500 ksps with one S&H
- 18 analog inputs on 64-pin devices and up to
32 analog inputs on 100-pin devices
• Flexible and independent ADC trigger sources
Timers/Output Compare/Input Capture
• Up to nine 16-bit timers/counters. Can pair up to
make four 32-bit timers.
• Eight Output Compare modules configurable as
timers/counters
• Eight Input Capture modules
Communication Interfaces
• Two UART modules (10 Mbps)
- With support for LIN 2.0 protocols and IrDA®
• Two 4-wire SPI modules (15 Mbps)
• Up to two I2C™ modules (up to 1 Mbaud) with
SMBus support
• Up to two Enhanced CAN (ECAN) modules
(1 Mbaud) with 2.0B support
• Data Converter Interface (DCI) module with I2S
codec support
Input/Output
• Sink/Source up to 10 mA (pin specific) for stan-
dard VOH/VOL, up to 16 mA (pin specific) for non-
standard VOH1
• 5V-tolerant pins
• Selectable open drain, pull-ups, and pull-downs
• Up to 5 mA overvoltage clamp current
• External interrupts on all I/O pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC)
• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)
• Class B Safety Library, IEC 60730
Debugger Development Support
• In-circuit and in-application programming
• Two program and two complex data breakpoints
• IEEE 1149.2-compatible (JTAG) boundary scan
• Trace and run-time watch
Packages
Type
QFN
Pin Count
64
Contact Lead/Pitch
0.50
I/O Pins
53
Dimensions
9x9x0.9
Note: All dimensions are in millimeters (mm) unless specified.
TQFP
64
0.50
53
10x10x1
TQFP
100
0.50
85
12x12x1
TQFP
100
0.40
85
14x14x1
2009-2012 Microchip Technology Inc.
DS70592D-page 1


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
PIC24H PRODUCT FAMILIES
The PIC24H Family of devices is ideal for a wide vari-
ety of 16-bit MCU embedded applications. The device
names, pin counts, memory sizes and peripheral avail-
ability of each device are listed below, followed by their
pinout diagrams.
PIC24H Family Controllers
Device
Program
Pins
Flash
Memory (KB)
PIC24HJ64GP206A 64
64
8898
8
0 1 ADC, 2 2 1
18 ch
PIC24HJ64GP210A 100
64
8898
8
0 1 ADC, 2 2 2
32 ch
PIC24HJ64GP506A 64
64
8898
8
0 1 ADC, 2 2 2
18 ch
PIC24HJ64GP510A 100
64
8898
8
0 1 ADC, 2 2 2
32 ch
PIC24HJ128GP206A 64
128
8898
8
0 1 ADC, 2 2 2
18 ch
PIC24HJ128GP210A 100
128
8898
8
0 1 ADC, 2 2 2
32 ch
PIC24HJ128GP506A 64
128
8898
8
0 1 ADC, 2 2 2
18 ch
PIC24HJ128GP510A 100
128
8898
8
0 1 ADC, 2 2 2
32 ch
PIC24HJ128GP306A 64
128
16 8 9 8
8
0 1 ADC, 2 2 2
18 ch
PIC24HJ128GP310A 100
128
16 8 9 8
8
0 1 ADC, 2 2 2
32 ch
PIC24HJ256GP206A 64
256
16 8 9 8
8
0 1 ADC, 2 2 2
18 ch
PIC24HJ256GP210A 100
256
16 8 9 8
8
0 1 ADC, 2 2 2
32 ch
PIC24HJ256GP610A 100
256
16 8 9 8
8
0 2 ADC, 2 2 2
32 ch
Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.
2: Maximum I/O pin count includes pins shared by the peripheral functions.
0 53 PT, MR
0 85 PF, PT
1 53 PT, MR
1 85 PF, PT
0 53 PT, MR
0 85 PF, PT
1 53 PT, MR
1 85 PF, PT
0 53 PT, MR
0 85 PF, PT
0 53 PT, MR
0 85 PF, PT
2 85 PF, PT
DS70592D-page 2
2009-2012 Microchip Technology Inc.


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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Pin Diagrams
64-Pin QFN(1)
PIC24HJXXXGPX06A/X08A/X10A
= Pins are up to 5V tolerant
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8 PIC24HJ64GP206A(2)
9
10
11
PIC24HJ128GP206A
PIC24HJ256GP206A
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
Note
1:
2:
3:
The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally.
The PIC24HJ64GP206A device does not have the SCL2 and SDA2 pins.
Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 3


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin QFN(1)
= Pins are up to 5V tolerant
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8
9
PIC24HJ128GP306A
41
40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally.
2: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
DS70592D-page 4
2009-2012 Microchip Technology Inc.


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin QFN(1)
= Pins are up to 5V tolerant
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
PIC24HJ64GP506A
10 PIC24HJ128GP506A
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally.
2: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 5


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ64GP206A
PIC24HJ128GP206A
PIC24HJ256GP206A
48 PGEC2/SOSCO/T1CK/CN0/RC14
47 PGED2/SOSCI/T4CK/CN1/RC13
46 OC1/RD0
45 IC4/INT4/RD11
44 IC3/INT3/RD10
43 IC2/U1CTS/INT2/RD9
42 IC1/INT1/RD8
41 VSS
40 OSC2/CLKO/RC15
39 OSC1/CLKIN/RC12
38 VDD
37 SCL1/RG2
36 SDA1/RG3
35 U1RTS/SCK1/INT0/RF6
34 U1RX/SDI1/RF2
33 U1TX/SDO1/RF3
Note 1: This pin is not present on the PIC24HJ64GP206A device.
2: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
DS70592D-page 6
2009-2012 Microchip Technology Inc.


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ128GP306A
48 PGEC2/SOSCO/T1CK/CN0/RC14
47 PGED2/SOSCI/T4CK/CN1/RC13
46 OC1/RD0
45 IC4/INT4/RD11
44 IC3/INT3/RD10
43 IC2/U1CTS/INT2/RD9
42 IC1/INT1/RD8
41 VSS
40 OSC2/CLKO/RC15
39 OSC1/CLKIN/RC12
38 VDD
37 SCL1/RG2
36 SDA1/RG3
35 U1RTS/SCK1/INT0/RF6
34 U1RX/SDI1/RF2
33 U1TX/SDO1/RF3
Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 7


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24HJ64GP506A
PIC24HJ128GP506A
48 PGEC2/SOSCO/T1CK/CN0/RC14
47 PGED2/SOSCI/T4CK/CN1/RC13
46 OC1/RD0
45 IC4/INT4/RD11
44 IC3/INT3/RD10
43 IC2/U1CTS/INT2/RD9
42 IC1/INT1/RD8
41 VSS
40 OSC2/CLKO/RC15
39 OSC1/CLKIN/RC12
38 VDD
37 SCL1/RG2
36 SDA1/RG3
35 U1RTS/SCK1/INT0/RF6
34 U1RX/SDI1/RF2
33 U1TX/SDO1/RF3
Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
DS70592D-page 8
2009-2012 Microchip Technology Inc.


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC24HJ64GP210A
PIC24HJ128GP210A
PIC24HJ128GP310A
PIC24HJ256GP210A
75 VSS
74 PGEC2/SOSCO/T1CK/CN0/RC14
73 PGED2/SOSCI/CN1/RC13
72 OC1/RD0
71 IC4/RD11
70 IC3/RD10
69 IC2/RD9
68 IC1/RD8
67 INT4/RA15
66 INT3/RA14
65 VSS
64 OSC2/CLKO/RC15
63 OSC1/CLKIN/RC12
62 VDD
61 TDO/RA5
60 TDI/RA4
59 SDA2/RA3
58 SCL2/RA2
57 SCL1/RG2
56 SDA1/RG3
55 SCK1/INT0/RF6
54 SDI1/RF7
53 SDO1/RF8
52 U1RX/RF2
51 U1TX/RF3
Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 9


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC24HJ64GP510A
PIC24HJ128GP510A
75 VSS
74 PGEC2/SOSCO/T1CK/CN0/RC14
73 PGED2/SOSCI/CN1/RC13
72 OC1/RD0
71 IC4/RD11
70 IC3/RD10
69 IC2/RD9
68 IC1/RD8
67 INT4/RA15
66 INT3/RA14
65 VSS
64 OSC2/CLKO/RC15
63 OSC1/CLKIN/RC12
62 VDD
61 TDO/RA5
60 TDI/RA4
59 SDA2/RA3
58 SCL2/RA2
57 SCL1/RG2
56 SDA1/RG3
55 SCK1/INT0/RF6
54 SDI1/RF7
53 SDO1/RF8
52 U1RX/RF2
51 U1TX/RF3
Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
DS70592D-page 10
2009-2012 Microchip Technology Inc.


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
RG15
VDD
AN29/RE5
AN30/RE6
AN31/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC24HJ256GP610A
75 VSS
74 PGEC2/SOSCO/T1CK/CN0/RC14
73 PGED2/SOSCI/CN1/RC13
72 OC1/RD0
71 IC4/RD11
70 IC3/RD10
69 IC2/RD9
68 IC1/RD8
67 INT4/RA15
66 INT3/RA14
65 VSS
64 OSC2/CLKO/RC15
63 OSC1/CLKIN/RC12
62 VDD
61 TDO/RA5
60 TDI/RA4
59 SDA2/RA3
58 SCL2/RA2
57 SCL1/RG2
56 SDA1/RG3
55 SCK1/INT0/RF6
54 SDI1/RF7
53 SDO1/RF8
52 U1RX/RF2
51 U1TX/RF3
Note 1: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin.
2009-2012 Microchip Technology Inc.
DS70592D-page 11


PIC24HJ64GP510A (Microchip)
16-bit Microcontrollers

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PIC24HJXXXGPX06A/X08A/X10A
Table of Contents
PIC24H Product Families....................................................................................................................................................................... 2
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers ........................................................................................................ 19
3.0 CPU ............................................................................................................................................................................................ 23
4.0 Memory Organization ................................................................................................................................................................. 29
5.0 Flash Program Memory .............................................................................................................................................................. 59
6.0 Reset ......................................................................................................................................................................................... 65
7.0 Interrupt Controller ..................................................................................................................................................................... 69
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 113
9.0 Oscillator Configuration ............................................................................................................................................................ 123
10.0 Power-Saving Features ............................................................................................................................................................ 133
11.0 I/O Ports ................................................................................................................................................................................... 141
12.0 Timer1 ...................................................................................................................................................................................... 145
13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 147
14.0 Input Capture............................................................................................................................................................................ 153
15.0 Output Compare ....................................................................................................................................................................... 155
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 159
17.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 165
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 173
19.0 Enhanced CAN (ECAN™) Module ........................................................................................................................................... 179
20.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 207
21.0 Special Features ...................................................................................................................................................................... 221
22.0 Instruction Set Summary .......................................................................................................................................................... 229
23.0 Development Support............................................................................................................................................................... 237
24.0 Electrical Characteristics .......................................................................................................................................................... 241
25.0 High Temperature Electrical Characteristics ............................................................................................................................ 287
26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 297
27.0 Packaging Information.............................................................................................................................................................. 301
Appendix A: Migrating from PIC24HJXXXGPX06/X08/X10 Devices to PIC24HJXXXGPX06A/X08A/X10A Devices ....................... 311
Appendix B: Revision History............................................................................................................................................................. 312
Index ................................................................................................................................................................................................. 317
The Microchip Web Site ..................................................................................................................................................................... 321
Customer Change Notification Service .............................................................................................................................................. 321
Customer Support .............................................................................................................................................................................. 321
Reader Response .............................................................................................................................................................................. 322
Product Identification System............................................................................................................................................................. 323
DS70592D-page 12
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PIC24HJXXXGPX06A/X08A/X10A
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-
mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We wel-
come your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2009-2012 Microchip Technology Inc.
DS70592D-page 13


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PIC24HJXXXGPX06A/X08A/X10A
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note:
To access the documents listed below,
browse to the documentation section of
the PIC24HJ256GP610A product page
on the Microchip web site
(www.microchip.com) or by selecting a
family reference manual section from
the following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
Section 1. “Introduction” (DS70197)
Section 2. “CPU” (DS70204)
Section 3. “Data Memory” (DS70202)
Section 4. “Program Memory” (DS70203)
Section 5. “Flash Programming” (DS70191)
Section 6. “Interrupts” (DS70184)
Section 7. “Oscillator” (DS70186)
Section 8. “Reset” (DS70192)
Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196)
Section 10. “I/O Ports” (DS70193)
Section 11. “Timers” (DS70205)
Section 12. “Input Capture” (DS70198)
Section 13. “Output Compare” (DS70209)
Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
Section 17. “UART” (DS70188)
Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195)
Section 20. “Data Converter Interface (DCI)” (DS70288)
Section 21. “Enhanced Controller Area Network (ECAN™)” (DS70185)
Section 22. “Direct Memory Access (DMA)” (DS70182)
Section 23. “CodeGuard™ Security” (DS70199)
Section 24. “Programming and Diagnostics” (DS70207)
Section 25. “Device Configuration” (DS70194)
DS70592D-page 14
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PIC24HJXXXGPX06A/X08A/X10A
1.0 DEVICE OVERVIEW
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to the latest
family reference sections of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
This document contains device specific information for
the following devices:
• PIC24HJ64GP206A
• PIC24HJ64GP210A
• PIC24HJ64GP506A
• PIC24HJ64GP510A
• PIC24HJ128GP206A
• PIC24HJ128GP210A
• PIC24HJ128GP506A
• PIC24HJ128GP510A
• PIC24HJ128GP306A
• PIC24HJ128GP310A
• PIC24HJ256GP206A
• PIC24HJ256GP210A
• PIC24HJ256GP610A
The PIC24HJXXXGPX06A/X08A/X10A device family
includes devices with different pin counts (64 and 100
pins), different program memory sizes (64 Kbytes, 128
Kbytes and 256 Kbytes) and different RAM sizes (8
Kbytes and 16 Kbytes).
This makes these families suitable for a wide variety of
high-performance digital signal control applications.
The devices are pin compatible with the dsPIC33F fam-
ily of devices, and also share a very high degree of
compatibility with the dsPIC30F family devices. This
allows easy migration between device families as may
be necessitated by the specific functionality, computa-
tional resource and system cost requirements of the
application.
The PIC24HJXXXGPX06A/X08A/X10A device family
employs a powerful 16-bit architecture, ideal for
applications that rely on high-speed, repetitive
computations, as well as control.
The 17 x 17 multiplier, hardware support for division
operations, multi-bit data shifter, a large array of 16-bit
working registers and a wide variety of data addressing
modes,
together
provide
the
PIC24HJXXXGPX06A/X08A/X10A Central Processing
Unit (CPU) with extensive mathematical processing
capability. Flexible and deterministic interrupt handling,
coupled with a powerful array of peripherals, renders
the PIC24HJXXXGPX06A/X08A/X10A devices suit-
able for control applications. Further, Direct Memory
Access (DMA) enables overhead-free transfer of data
between several peripherals and a dedicated DMA
RAM. Reliable, field programmable Flash program
memory ensures scalability of applications that use
PIC24HJXXXGPX06A/X08A/X10A devices.
Figure 1-1 shows a general block diagram of the
various core and peripheral modules in the
PIC24HJXXXGPX06A/X08A/X10A family of devices,
while Table 1-1 lists the functions of the various pins
shown in the pinout diagrams.
2009-2012 Microchip Technology Inc.
DS70592D-page 15


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PIC24HJXXXGPX06A/X08A/X10A
FIGURE 1-1:
PIC24HJXXXGPX06A/X08A/X10A GENERAL BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Interrupt
Controller
23
23
23
8 16
PCU PCH PCL
Program Counter
Stack
Control
Logic
Loop
Control
Logic
Data Bus
16
16
Data Latch
X RAM
Address
Latch
16
DMA
RAM
DMA
Controller
16
Address Latch
Address Generator Units
PORTA
PORTB
PORTC
Program Memory
Data Latch
24
Instruction
Decode and
Control
Control Signals
to Various Blocks
OSC2/CLKO Timing
OSC1/CLKI Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
ROM Latch
EA MUX
16 16
Instruction Reg
16
17 x 17 Multiplier
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
PORTD
PORTE
PORTF
PORTG
VCAP
VDD, VSS MCLR
Timers
1-9
ADC1,2
ECAN1,2
UART1,2
IC1-8
OC/
PWM1-8
CN1-23
SPI1,2
I2C1,2
Note:
Not all pins or features are implemented on all device pinout configurations. See Pin Diagrams for the specific pins and
features present on each device.
DS70592D-page 16
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PIC24HJXXXGPX06A/X08A/X10A
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Type
Buffer
Type
Description
AN0-AN31
AVDD
AVSS
CLKI
CLKO
CN0-CN23
C1RX
C1TX
C2RX
C2TX
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
IC1-IC8
INT0
INT1
INT2
INT3
INT4
I Analog Analog input channels.
P P Positive supply for analog modules. This pin must be connected at all times.
P P Ground reference for analog modules.
I ST/CMOS External clock source input. Always associated with OSC1 pin function.
O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
I ST Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
I ST ECAN1 bus receive pin.
O — ECAN1 bus transmit pin.
I ST ECAN2 bus receive pin.
O — ECAN2 bus transmit pin.
I/O ST Data I/O pin for programming/debugging communication channel 1.
I ST Clock input pin for programming/debugging communication channel 1.
I/O ST Data I/O pin for programming/debugging communication channel 2.
I ST Clock input pin for programming/debugging communication channel 2.
I/O ST Data I/O pin for programming/debugging communication channel 3.
I ST Clock input pin for programming/debugging communication channel 3.
I ST Capture inputs 1 through 8.
I ST External interrupt 0.
I ST External interrupt 1.
I ST External interrupt 2.
I ST External interrupt 3.
I ST External interrupt 4.
MCLR
I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I ST Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
I ST Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
O — Compare outputs 1 through 8.
OSC1
OSC2
I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
RA0-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST PORTA is a bidirectional I/O port.
ST
ST
RB0-RB15 I/O ST PORTB is a bidirectional I/O port.
RC1-RC4
RC12-RC15
I/O
I/O
ST PORTC is a bidirectional I/O port.
ST
RD0-RD15 I/O ST PORTD is a bidirectional I/O port.
RE0-RE7
I/O ST PORTE is a bidirectional I/O port.
RF0-RF8
RF12-RF13
I/O
ST PORTF is a bidirectional I/O port.
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST PORTG is a bidirectional I/O port.
ST
ST
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
O = Output
P = Power
I = Input
2009-2012 Microchip Technology Inc.
DS70592D-page 17


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PIC24HJXXXGPX06A/X08A/X10A
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
Description
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
SCL1
SDA1
SCL2
SDA2
SOSCI
SOSCO
TMS
TCK
TDI
TDO
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
U1CTS
U1RTS
U1RX
U1TX
U2CTS
U2RTS
U2RX
U2TX
VDD
VCAP
VSS
VREF+
VREF-
Legend:
I/O ST Synchronous serial clock input/output for SPI1.
I ST SPI1 data in.
O — SPI1 data out.
I/O ST SPI1 slave synchronization or frame pulse I/O.
I/O ST Synchronous serial clock input/output for SPI2.
I ST SPI2 data in.
O — SPI2 data out.
I/O ST SPI2 slave synchronization or frame pulse I/O.
I/O ST Synchronous serial clock input/output for I2C1.
I/O ST Synchronous serial data input/output for I2C1.
I/O ST Synchronous serial clock input/output for I2C2.
I/O ST Synchronous serial data input/output for I2C2.
I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
O — 32.768 kHz low-power oscillator crystal output.
I ST JTAG Test mode select pin.
I ST JTAG test clock input pin.
I ST JTAG test data input pin.
O — JTAG test data output pin.
I ST Timer1 external clock input.
I ST Timer2 external clock input.
I ST Timer3 external clock input.
I ST Timer4 external clock input.
I ST Timer5 external clock input.
I ST Timer6 external clock input.
I ST Timer7 external clock input.
I ST Timer8 external clock input.
I ST Timer9 external clock input.
I ST UART1 clear to send.
O — UART1 ready to send.
I ST UART1 receive.
O — UART1 transmit.
I ST UART2 clear to send.
O — UART2 ready to send.
I ST UART2 receive.
O — UART2 transmit.
P — Positive supply for peripheral logic and I/O pins.
P — CPU logic filter capacitor connection.
P — Ground reference for logic and I/O pins.
I Analog Analog voltage reference (high) input.
I Analog Analog voltage reference (low) input.
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
O = Output
P = Power
I = Input
DS70592D-page 18
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PIC24HJXXXGPX06A/X08A/X10A
2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
Note 1: This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see
the Microchip web site
(www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1 Basic Connection Requirements
Getting started with the
PIC24HJXXXGPX06A/X08A/X10A family of 16-bit
Microcontrollers (MCUs) requires attention to a minimal
set of device pin connections before proceeding with
development. The following is a list of pin names, which
must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
2009-2012 Microchip Technology Inc.
DS70592D-page 19


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PIC24HJXXXGPX06A/X08A/X10A
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
VDD
10 µF
Tantalum
0.1 µF
Ceramic
R
R1
MCLR
C
VSS
PIC24H
VDD
0.1 µF
Ceramic
VDD
VSS
0.1 µF
Ceramic
L1(1)
0.1 µF
Ceramic
0.1 µF
Ceramic
Note 1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1and the inductor
capacity greater than 10 mA.
Where:
f = -F----C---N----V-
2
(i.e., ADC conversion rate/2)
f = -----------1------------
2LC
L
=
---2-------f1------C-----
2
2.2.1 TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including MCUs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device, and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3 CPU Logic Filter Capacitor
Connection (VCAP)
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 µF and 10 µF, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 24.0
“Electrical Characteristics” for additional
information.
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 21.2
“On-Chip Voltage Regulator” for details.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R(1)
R1(2)
MCLR
JP PIC24H
C
Note 1:
2:
R 10 kis recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
R1 470will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
DS70592D-page 20
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PIC24HJXXXGPX06A/X08A/X10A
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the
“dsPIC33F/PIC24H Flash Programming Specification”
(DS70152) for information on capacitive loading limits
and pin input voltage high (VIH) and input low (VIL)
requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
“Using MPLAB® ICD 3 In-Circuit Debugger”
(poster) DS51765
“MPLAB® ICD 3 Design Advisory” DS51764
“MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
“Using MPLAB® REAL ICE™” (poster) DS51749
2.6 External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
13
14
15
16
17
18
19
20
2009-2012 Microchip Technology Inc.
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PIC24HJXXXGPX06A/X08A/X10A
2.7 Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 8 MHz for start-up with PLL enabled to comply with
device PLL start-up conditions. This means that if the
external oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8 Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or REAL ICE is selected as a debug-
ger, it automatically initializes all of the A/D input pins
(ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 3 or REAL ICE, must
not be cleared by the user application firmware;
otherwise, communication errors will result between
the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.
2.9 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor between VSS
and the unused pins.
DS70592D-page 22
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PIC24HJXXXGPX06A/X08A/X10A
3.0 CPU
Note 1: This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 2. “CPU” (DS70204) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC24HJXXXGPX06A/X08A/X10A CPU module
has a 16-bit (data) modified Harvard architecture with an
enhanced instruction set and addressing modes. The
CPU has a 24-bit instruction word with a variable length
opcode field. The Program Counter (PC) is 23 bits wide
and addresses up to 4M x 24 bits of user program
memory space. The actual amount of program memory
implemented varies by device. A single-cycle instruction
prefetch mechanism is used to help maintain throughput
and provides predictable execution. All instructions
execute in a single cycle, with the exception of
instructions that change the program flow, the double
word move (MOV.D) instruction and the table instructions.
Overhead-free, single-cycle program loop constructs are
supported using the REPEAT instruction, which is
interruptible at any point.
The PIC24HJXXXGPX06A/X08A/X10A devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a data,
address or address offset register. The 16th working
register (W15) operates as a software Stack Pointer (SP)
for interrupts and calls.
The PIC24HJXXXGPX06A/X08A/X10A instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the PIC24HJXXXGPX06A/X08A/X10A is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1,
and the programmer’s model for the
PIC24HJXXXGPX06A/X08A/X10A is shown in
Figure 3-2.
3.1 Data Addressing Overview
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K pro-
gram word boundary defined by the 8-bit Program Space
Visibility Page (PSVPAG) register. The program to data
space mapping feature lets any instruction access pro-
gram space as if it were data space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but may
be used as general purpose RAM.
3.2 Special MCU Features
The PIC24HJXXXGPX06A/X08A/X10A features a
17-bit by 17-bit, single-cycle multiplier. The multiplier
can perform signed, unsigned and mixed-sign
multiplication. Using a 17-bit by 17-bit multiplier for
16-bit by 16-bit multiplication makes mixed-sign
multiplication possible.
The PIC24HJXXXGPX06A/X08A/X10A supports 16/16
and 32/16 integer divide operations. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
2009-2012 Microchip Technology Inc.
DS70592D-page 23


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PIC24HJXXXGPX06A/X08A/X10A
FIGURE 3-1:
PIC24HJXXXGPX06A/X08A/X10A CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Interrupt
Controller
23
23
23
Address Latch
8 16
PCU PCH PCL
Program Counter
Stack
Control
Logic
Loop
Control
Logic
X Data Bus
16 16
Data Latch
X RAM
Address
Latch
16
Address Generator Units
DMA
RAM
DMA
Controller
Program Memory
Data Latch
24
Instruction
Decode and
Control
Control Signals
to Various Blocks
ROM Latch
EA MUX
16 16
Instruction Reg
16
17 x 17
Multiplier
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
16
To Peripheral Modules
DS70592D-page 24
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PIC24HJXXXGPX06A/X08A/X10A
FIGURE 3-2:
PIC24HJXXXGPX06A/X08A/X10A PROGRAMMER’S MODEL
D15
W0/WREG
W1
W2
W3
W4
W5
D0
PUSH.S Shadow
DO Shadow
Legend
W6
W7
W8
W9
W10
W11
W12
W13
W14/Frame Pointer
W15/Stack Pointer
Working Registers
SPLIM
Stack Pointer Limit Register
PC22
70
TBLPAG
Data Table Page Address
PC0
0
70
PSVPAG
Program Space Visibility Page Address
15
RCOUNT
0
Program Counter
REPEAT Loop Counter
15
CORCON
0
Core Configuration Register
— — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register
SRH
SRL
2009-2012 Microchip Technology Inc.
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PIC24HJXXXGPX06A/X08A/X10A
3.3 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
U-0
bit 15
U-0 U-0 U-0
— ——
R/W-0(1)
bit 7
R/W-0(2)
IPL<2:0>(2)
R/W-0(2)
R-0
RA
U-0
R/W-0
N
U-0
R/W-0
OV
U-0
R/W-0
Z
R/W-0
DC
bit 8
R/W-0
C
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 15-9
bit 8
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized
data) of the result occurred
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
Z: MCU ALU Zero bit
1 = An operation which affects the Z bit has set it at some time in the past
0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).
DS70592D-page 26
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PIC24HJXXXGPX06A/X08A/X10A
REGISTER 3-2:
U-0
bit 15
CORCON: CORE CONTROL REGISTER
U-0 U-0 U-0 U-0
— — ——
U-0
U-0 U-0
——
bit 8
U-0
bit 7
U-0
U-0
U-0
R/C-0
R/W-0
U-0
U-0
— IPL3(1) PSV
bit 0
Legend:
R = Readable bit
0’ = Bit is cleared
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-4
bit 3
bit 2
bit 1-0
Unimplemented: Read as ‘0
IPL3: CPU Interrupt Priority Level Status bit 3(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
Unimplemented: Read as ‘0
Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
2009-2012 Microchip Technology Inc.
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PIC24HJXXXGPX06A/X08A/X10A
3.4 Arithmetic Logic Unit (ALU)
The PIC24HJXXXGPX06A/X08A/X10A ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU may affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as
Borrow and Digit Borrow bits, respectively, for
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W reg-
ister array, or data memory, depending on the address-
ing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
Refer to the “16-bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
The PIC24HJXXXGPX06A/X08A/X10A CPU
incorporates hardware support for both multiplication
and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit divisor
division.
3.4.1 MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed or mixed-sign operation in
several multiplication modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
3.4.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.4.3 MULTI-BIT DATA SHIFTER
The multi-bit data shifter is capable of performing up to
16-bit arithmetic or logic right shifts, or up to 16-bit left
shifts in a single cycle. The source can be either a
working register or a memory location.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0
does not modify the operand.
DS70592D-page 28
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PIC24HJXXXGPX06A/X08A/X10A
4.0 MEMORY ORGANIZATION
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section 3.
“Data Memory” (DS70202) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
The PIC24HJXXXGPX06A/X08A/X10A architecture
features separate program and data memory spaces
and buses. This architecture also allows the direct
access of program memory from the data space during
code execution.
4.1 Program Address Space
The program address memory space of the
PIC24HJXXXGPX06A/X08A/X10A devices is 4M
instructions. The space is addressable by a 24-bit value
derived from either the 23-bit Program Counter (PC)
during program execution, or from table operation or
data space remapping as described in Section 4.4
“Interfacing Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24HJXXXGPX06A/X08A/
X10A family of devices are shown in Figure 4-1.
FIGURE 4-1: PROGRAM MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A FAMILY DEVICES
PIC24HJ64XXXXXA
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(22K instructions)
PIC24HJ128XXXXXA
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(44K instructions)
PIC24HJ256XXXXXA
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
User Program
Flash Memory
(88K instructions)
0x00ABFE
0x00AC00
0x0157FE
0x015800
Unimplemented
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
0x02ABFE
0x02AC00
0x7FFFFE
0x800000
Reserved
Device Configuration
Registers
Reserved
Reserved
Device Configuration
Registers
Reserved
Reserved
Device Configuration
Registers
0xF7FFFE
0xF80000
0xF80017
0xF80010
Reserved
DEVID (2)
2009-2012 Microchip Technology Inc.
DEVID (2)
DEVID (2)
0xFEFFFE
0xFF0000
0xFFFFFE
DS70592D-page 29


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PIC24HJXXXGPX06A/X08A/X10A
4.1.1
PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2 INTERRUPT AND TRAP VECTORS
All PIC24HJXXXGPX06A/X08A/X10A devices reserve
the addresses between 0x00000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTO instruction is programmed
by the user at 0x000000, with the actual address for the
start of code at 0x000002.
PIC24HJXXXGPX06A/X08A/X10A devices also have
two interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the many device interrupt sources
to be handled by separate Interrupt Service Routines
(ISRs). A more detailed discussion of the interrupt vec-
tor tables is provided in Section 7.1 “Interrupt Vector
Table”.
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
msw
Address
0x000001
0x000003
0x000005
0x000007
most significant word
00000000
00000000
00000000
00000000
23
16
least significant word
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
DS70592D-page 30
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