TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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TC58FVT641/B641FT/XB-70,-10
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64-MBIT (8M × 8 BITS / 4M × 16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVT641/B641 is a 67,108,864-bit, 3.0-V read-only electrically erasable and programmable flash memory
organized as 8,388,608 words × 8 bits or as 4,194,304 words × 16 bits. The TC58FVT641/B641 features commands
for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands are based
on the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The
TC58FVT641/B641 also features a Simultaneous Read/Write operation so that data can be read during a Write or
Erase operation.
FEATURES
Power supply voltage
Block erase architecture
VDD = 2.7 V~3.6 V
Operating temperature
Ta = −40°C~85°C
Organization
8M × 8 bits / 4M × 16 bits
Functions
Simultaneous Read/Write
Auto Program, Auto Erase
8 × 8 Kbytes / 127 × 64 Kbytes
Boot block architecture
TC58FVT641FT/XB: top boot block
TC58FVB641FT/XB: bottom boot block
Mode control
Compatible with JEDEC standard commands
Erase/Program cycles
105 cycles typ.
Fast Program Mode / Acceleration Mode
Access time
Program Suspend/Resume
70 ns (CL: 30 pF)
Erase Suspend/Resume
data polling / Toggle bit
block protection, boot block protection
Automatic Sleep, support for hidden ROM area
common flash memory interface (CFI)
Byte/Word Modes
100 ns (CL: 100 pF)
Power consumption
10 µA (Standby)
30 mA (Read operation)
15 mA (Program/Erase operations)
Package
TC58FVT641/B641FT:
TSOPI48-P-1220-0.50 (weight: 0.52 g)
TC58FVT641/B641XB:
P-TFBGA63-0911-0.80AZ (Weight: 0.170 g)
000707EBA1
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
The information contained herein is subject to change without notice.
2002-10-24 1/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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PIN ASSIGNMENT (TOP VIEW)
TC58FVT641/B641FT
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
A21
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TC58FVT641/B641XB
TC58FVT641/B641FT/XB-70,-10
PIN NAMES
48 A16
47 BYTE
A-1, A0~A21 Address Input
46 VSS
DQ0~DQ15 Data Input/Output
45 DQ15/A-1
44 DQ7
CE Chip Enable Input
43 DQ14
42 DQ6
OE Output Enable Input
41 DQ13
40 DQ5
BYTE
Word/Byte Select Input
39 DQ12
38 DQ4
WE Write Enable Input
37 VDD
36 DQ11
RY/BY Ready/Busy Output
35 DQ3
34 DQ10
RESET Hardware Reset Input
33 DQ2
32 DQ9
31 DQ1
WP/ACC
Write Protect /
Program Acceleration Input
30 DQ8
29 DQ0
VDD Power Supply
28 OE
27 VSS
VSS Ground
26 CE
25 A0
1
A NC
B NC
C
D
E
F
G
H
J
K
L NC
M NC
2345678
NC NC NC
NC NC
A3 A7 RY/BY WE A9 A13
A4
A17 WP/ACC RESET
A8
A12
A2 A6 A18 A21 A10 A14
A1 A5 A20 A19 A11 A15
A0
DQ0
DQ2
DQ5
DQ7
A16
CΕ
DQ8
DQ10
DQ12
DQ14
BYTE
OE
DQ9
DQ11
VDD
DQ13
DQ15
VSS DQ1 DQ3 DQ4 DQ6 VSS
NC NC NC
NC NC NC
2002-10-24 2/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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BLOCK DIAGRAM
VDD
VSS
WP/ACC
WE
BYTE
RESET
CE
OE
Control Circuit
Command Register
TC58FVT641/B641FT/XB-70,-10
RY/BY
RY/BY Buffer
DQ0
DQ15
I/O Buffer
Data Latch
Memory Cell
Array
Bank 0
Memory Cell
Array
Memory Cell
Array
Bank 15
Bank 16
A0
A21
A-1
2002-10-24 3/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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MODE SELECTION
TC58FVT641/B641FT/XB-70,-10
BYTE MODE WORD MODE
MODE
CE OE WE A9 A6 A1 A0 RESET WP/ACC DQ0~DQ7(1) DQ0~DQ15
Read
L L H A9 A6 A1 A0
H
*
DOUT
ID Read (Manufacturer Code)
L L H VID L L L
H
*
Code
ID Read (Device Code)
L L H VID L L H
H
*
Code
Standby
H* * * * * *
H
*
High-Z
Output Disable
Write
Block Protect 1
Verify Block Protect
*HH* * * *
*
* High-Z
L H (2) A9 A6 A1 A0
L VID (2) VID L H L
H
H
*
*
DIN
*
L L H VID L H L
H
*
Code
Temporary Block Unprotect
*******
VID
*
*
Hardware Reset / Standby
*******
L
* High-Z
Boot Block Protect
*******
*
L
*
Notes: * = VIH or VIL, L = VIL, H = VIH
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.
Addresses are A21~A0 in Word Mode ( BYTE = VIH), A21~A-1 in Byte Mode ( BYTE = VIL).
(2) Pulse input
DOUT
Code
Code
High-Z
High-Z
DIN
*
Code
*
High-Z
*
ID CODE TABLE
CODE TYPE
A21~A12
A6
A1
Manufacturer Code
*L
Device Code
TC58FVT641
TC58FVB641
Verify Block Protect
*
*
BA(2)
L
L
L
Notes: * = VIH or VIL, L = VIL, H = VIH
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.
(2) BA: Block Address
(3) 0001H - Protected Block
0000H - Unprotected Block
L
L
L
H
A0 CODE (HEX)(1)
L 0098H
H 0093H
H 0095H
L Data(3)
2002-10-24 4/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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TC58FVT641/B641FT/XB-70,-10
COMMAND SEQUENCES
COMMAND
SEQUENCE
BUS
WRITE
CYCLES
REQD
FIRST BUS
WRITE CYCLE
Addr. Data
SECOND BUS
WRITE CYCLE
Addr. Data
THIRD BUS FOURTH BUS
WRITE CYCLE WRITE CYCLE
Addr. Data Addr. Data
FIFTH BUS
WRITE CYCLE
Addr. Data
SIXTH BUS
WRITE CYCLE
Addr. Data
Read/Reset
1 XXXH F0H
Read/Reset
ID Read
Word
Byte
Word
Byte
3
3
555H
AAAH
AAH
2AAH
555H
555H
AAAH
AAH
2AAH
555H
555H
(1) (2)
55H
F0H RA
RD
AAAH
(3)
BK
+
555H
(4)
55H (3) 90H IA
BK +
(5)
ID
AAAH
Word
Auto-Program
Byte
Program Suspend
Program Resume
4
1
1
555H
2AAH
AAH
55H
555H
(6) (7)
A0H PA
PD
AAAH
555H
AAAH
(3)
BK B0H
(3)
BK 30H
Auto Chip
Erase
Word
Byte
6
555H
2AAH
555H
555H
2AAH
555H
AAH 55H 80H AAH 55H 10H
AAAH
555H
AAAH
AAAH
555H
AAAH
Auto Block
Erase
Word
Byte
Block Erase Suspend
Block Erase Resume
Block Protect 2
Verify Block
Protect
Word
Byte
6
1
1
4
3
555H
2AAH
AAH
55H
555H
555H
2AAH
(8)
80H AAH
55H BA
30H
AAAH
555H
AAAH
AAAH
555H
(3)
BK B0H
(3)
BK 30H
(9)
XXXH 60H BPA
60H
(9) (10)
XXXH 40H BPA BPD
555H
AAAH
AAH
2AAH
555H
(3)
BK +
555H
(9) (10)
55H (3) 90H BPA BPD
BK +
AAAH
Fast Program
Set
Word
Byte
Fast Program
Fast Program Reset
3
2
2
555H
AAAH
XXXH
XXXH
AAH
A0H
90H
2AAH
555H
(6)
PA
XXXH
55H
(7)
PD
(13)
F0H
555H
AAAH
20H
Hidden ROM
Mode Entry
Word
Byte
3
555H
2AAH
555H
AAH 55H 88H
AAAH
555H
AAAH
Hidden ROM
Program
Word
Byte
4
555H
2AAH
AAH
55H
555H
(6) (7)
A0H PA
PD
AAAH
555H
AAAH
Hidden ROM
Erase
Word
Byte
6
555H
2AAH
AAH
55H
555H
555H
2AAH
(8)
80H AAH
55H BA
30H
AAAH
555H
AAAH
AAAH
555H
Hidden ROM
Mode Exit
Word
Byte
4
555H
2AAH
555H
AAH 55H 90H XXXH 00H
AAAH
555H
AAAH
Query
Command
(3)
BK +
Word
55H (11) (12)
2
(3)
BK
+
98H
CA
CD
Byte
AAH
Notes: The system should generate the following address patterns:
Word Mode: 555H or 2AAH on address pins A10~A0
Byte Mode: AAAH or 555H on address pins A10~A-1
DQ8~DQ15 are ignored in Word Mode.
(1) RA: Read Address
(2) RD: Read Data
(3) BK: Bank Address = A21~A15
(4) IA: Bank Address and ID Read Address (A6, A1, A0)
Bank Address = A21~A15
Manufacturer Code = (0, 0, 0)
Device Code = (0, 0, 1)
(5) ID: ID Data
(6) PA: Program Address
(7) PD: Program Data
(8) BA: Block Address = A21~A12
(9) BPA: Block Address and ID Read Address (A6, A1, A0)
Block Address = A21~A12
ID Read Address = (0, 1, 0)
(10) BPD: Verify Data
(11) CA: CFI Address
(12) CD: CFI Data
(13) F0H: 00H is valid too
2002-10-24 5/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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SIMULTANEOUS READ/WRITE OPERATION
TC58FVT641/B641FT/XB-70,-10
The TC58FVT641/B641 features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation
enables the device to simultaneously write data to or erase data from a bank while reading data from another bank.
The TC58FVT641/B641 has a total of seventeen banks: 1 bank of 0.5 Mbits, 1 bank of 3.5 Mbits and 15 banks of 4
Mbits. Banks can be switched between using the bank addresses (A21~A15). For a description of bank blocks and
addresses, please refer to the Block Address Table and Block Size Table.
The Simultaneous Read/Write operation cannot perform multiple operations within a single bank. The table
below shows the operation modes in which simultaneous operation can be performed.
Note that during Auto-Program execution or Auto Block Erase operation, the Simultaneous Read/Write operation
cannot read data from addresses in the same bank which have not been selected for operation. Data from these
addresses can be read using the Program Suspend or Erase Suspend function, however.
SIMULTANEOUS READ/WRITE OPERATION
STATUS OF BANK ON WHICH OPERATION IS BEING
PERFORMED
STATUS OF OTHER BANKS
Read Mode
ID Read Mode(1)
Auto-Program Mode
Fast Program Mode(2)
Program Suspend Mode
Auto Block Erase Mode
Auto Multiple Block Erase Mode(3)
Read Mode
Erase Suspend Mode
Program Suspend during Erase Suspend
CFI Mode
(1) Only Command Mode is valid.
(2) Including times when Acceleration Mode is in use.
(3) If the selected blocks are spread across all nine banks, simultaneous operation cannot be carried out.
OPERATION MODES
In addition to the Read, Write and Erase Modes, the TC58FVT641/B641 features many functions including block
protection and data polling. When incorporating the device into a deign, please refer to the timing charts and
flowcharts in combination with the description below.
READ MODE
To read data from the memory cell array, set the device to Read Mode. In Read Mode the device can perform
high-speed random access as asynchronous ROM.
The device is automatically set to Read Mode immediately after power-on or on completion of automatic
operation. A software reset releases ID Read Mode and the lock state which the device enters if automatic
operation ends abnormally, and sets the device to Read Mode. A hardware reset terminates operation of the
device and resets it to Read Mode. When reading data without changing the address immediately after
power-on, either input a hardware Reset or change CE from H to L.
2002-10-24 6/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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ID Read Mode
TC58FVT641/B641FT/XB-70,-10
ID Read Mode is used to read the device maker code and device code. The mode is useful in that it allows
EPROM programmers to identify the device type automatically.
ID read can be executed in two ways, as follows:
(1) Applying VID to A9
This method is used mainly by EPROM programmers. Applying VID to A9 sets the device to ID Read
Mode, outputting the maker code from address 00H and the device code from address 01H. Releasing VID
from A9 returns the device to Read Mode. With this method all banks are set to ID Read Mode; thus,
simultaneous operation cannot be performed.
(2) Input command sequence
With this method simultaneous operation can be performed. Inputting an ID Read command sets the
specified bank to ID Read Mode. Banks are specified by inputting the bank address (BK) in the third Bus
Write cycle of the Command cycle. To read an ID code, the bank address as well as the ID read address must
be specified. The maker code is output from address BK + 00; the device code is output from address BK +
01. From other banks data are output from the memory cells. Inputting a Reset command releases ID Read
Mode and returns the device to Read Mode.
Access time in ID Read Mode is the same as that in Read Mode. For a list of the codes, please refer to the
ID Code Table.
Standby Mode
There are two ways to put the device into Standby Mode.
(1) Control using CE and RESET
With the device in Read Mode, input VDD ± 0.3 V to CE and RESET . The device will enter Standby
Mode and the current will be reduced to the standby current (IDDS1). However, if the device is in the
process of performing simultaneous operation, the device will not enter Standby Mode but will instead
cause the operating current to flow.
(2) Control using RESET only
With the device in Read Mode, input VSS ± 0.3 V to RESET . The device will enter Standby Mode and the
current will be reduced to the standby current (IDDS1). Even if the device is in the process of performing
simultaneous operation, this method will terminate the current operation and set the device to Standby
Mode. This is a hardware reset and is described later.
In Standby Mode DQ is put in High-Impedance state.
Auto-Sleep Mode
This function suppresses power dissipation during reading. If the address input does not change for 150 ns,
the device will automatically enter Sleep Mode and the current will be reduced to the standby current (IDDS2).
However, if the device is in the process of performing simultaneous operation, the device will not enter Standby
Mode but will instead cause the operating current to flow. Because the output data is latched, data is output in
Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new
address is output.
Output Disable Mode
Inputting VIH to OE disables output from the device and sets DQ to High-Impedance.
2002-10-24 7/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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TC58FVT641/B641FT/XB-70,-10
Command Write
The TC58FVT641/B641 uses the standard JEDEC control commands for a single-power supply E2PROM. A
Command Write is executed by inputting the address and data into the Command Register. The command is
written by inputting a pulse to WE with CE = VIL and OE = VIH ( WE control). The command can also be
written by inputting a pulse to CE with WE = VIL ( CE control). The address is latched on the falling edge of
either WE or CE . The data is latched on the rising edge of either WE or CE . DQ0~DQ7 are valid for data
input and DQ8~DQ15 are ignored.
To abort input of the command sequence use the Reset command. The device will reset the Command Register
and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device
will enter Read Mode.
Software Reset
Apply a software reset by inputting a Read/Reset command. A software reset returns the device from ID Read
Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and
clears the Command Register.
Hardware Reset
A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to RESET for tRP,
the device abandons the operation which is in progress and enters Read Mode after tREADY. Note that if a
hardware reset is applied during data overwriting, such as a Write or Erase operation, data at the address or
block being written to at the time of the reset will become undefined.
After a hardware reset the device enters Read Mode if RESET = VIH or Standby Mode if RESET = VIL.
The DQ pins are High-Impedance when RESET = VIL. After the device has entered Read Mode, Read
operations and input of any command are allowed.
Comparison between Software Reset and Hardware Reset
ACTION
Releases ID Read Mode or CFI Mode.
Clears the Command Register.
Releases the lock state if automatic operation has ended abnormally.
Stops any automatic operation which is in progress.
Stops any operation other than the above and returns the device to
Read Mode.
SOFTWARE RESET
True
True
True
False
False
HARDWARE RESET
True
True
True
True
True
BYTE/Word Mode
BYTE is used select Word Mode (16 bits) or Byte Mode (8 bits) for the TC58FVT641/B641. If VIH is input to
BYTE , the device will operate in Word Mode. Read data or write commands using DQ0~DQ15. When VIL is
input to BYTE , read data or write commands using DQ0~DQ7. DQ15/A-1 is used as the lowest address.
DQ8~DQ14 will become High-Impedance.
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64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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Auto-Program Mode
TC58FVT641/B641FT/XB-70,-10
The TC58FVT641/B641 can be programmed in either byte or word units. Auto-Program Mode is set using the
Program command. The program address is latched on the falling edge of the WE signal and data is latched
on the rising edge of the fourth Bus Write cycle (with WE control). Auto programming starts on the rising edge
of the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are automatically
executed by the chip. The device status during programming is indicated by the Hardware Sequence flag. To
read the Hardware Sequence flag, specify the address to which the Write is being performed.
During Auto Program execution, a command sequence for the bank on which execution is being performed
cannot be accepted. To terminate execution, use a hardware reset. Note that if the Auto-Program operation is
terminated in this manner, the data written so far is invalid.
Any attempt to program a protected block is ignored. In this case the device enters Read Mode 3 µs after the
rising edge of the WE signal in the fourth Bus Write cycle.
If an Auto-Program operation fails, the device remains in the programming state and does not automatically
return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or
a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails,
the block which contains the address to which data could not be programmed should not be used.
The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into
cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device
error. A cell containing 0 must be erased in order to set it to 1.
Fast Program Mode
Fast Program is a function which enables execution of the command sequence for the Auto Program to be
completed in two cycles. In this mode the first two cycles of the command sequence, which normally requires
four cycles, are omitted. Writing is performed in the remaining two cycles. To execute Fast Program, input the
Fast Program command. Write in this mode uses the Fast Program command but operation is the same at that
for ordinary Auto-Program. The status of the device is indicated by the Hardware Sequence flag and read
operations can be performed as usual. To exit this mode, the Fast Program Reset command must be input.
When the command is input, the device will return to Read Mode.
Acceleration Mode
The TC58FVT641/B641 features Acceleration Mode which allows write time to be reduced. Applying VACC to
WP or ACC automatically sets the device to Acceleration Mode. In Acceleration Mode, Block Protect Mode
changes to Temporary Block Unprotect Mode. Write Mode changes to Fast Program Mode. Modes are switched
by the WP/ACC signal; thus, there is no need for a Temporary Block Unprotect operation or to set or reset Fast
Program Mode. Operation of Write is the same as in Auto-Program Mode. Removing VACC from WP/ACC
terminates Acceleration Mode.
2002-10-24 9/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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Program Suspend/Resume Mode
TC58FVT641/B641FT/XB-70,-10
Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a
Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but
ignores the command in other modes. When the command is input, the address of the bank on which Write is
being performed must be specified. After input of the command, the device will enter Program Suspend Read
Mode after tSUSP.
During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write
is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read
are the same as usual.
After completion of Program Suspend input a Program Resume command to return to Write Mode. When
inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or
CFI Data Read functions is being used, abort the function before inputting the Resume command. On receiving
the Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag
for the bank to which data is being written.
Program Suspend can be run in Fast Program Mode or Acceleration Mode. However, note that when running
Program Suspend in Acceleration Mode, VACC must not be released.
Auto Chip Erase Mode
The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the
rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and
verified as erased by the chip. The device status is indicated by the Hardware Sequence flag.
Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase
operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence an additional
Erase operation must be performed.
Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not
be executed and the device will enter Read mode 100 µs after the rising edge of the WE signal in the sixth bus
cycle.
If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to Read
Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware
reset is required to return the device to Read Mode after a failure.
In this case it cannot be ascertained which block the failure occurred in. Either abandon use of the device
altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host
processor must take measures to prevent subsequent use of the failed block.
2002-10-24 10/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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Auto Block Erase / Auto Multi-Block Erase Modes
TC58FVT641/B641FT/XB-70,-10
The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The
block address is latched on the falling edge of the WE signal in the sixth bus cycle. The block erase starts as
soon as the Erase Hold Time (tBEH) has elapsed after the rising edge of the WE signal. When multiple blocks
are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block Erase command being
input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command other
than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the
device will reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive
rising edge of WE . Once operation starts, all memory cells in the selected block are automatically
preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the setting of
the Hardware Sequence flag. When the Hardware Sequence flag is read, the addresses of the blocks on which
auto-erase operation is being performed must be specified. If the selected blocks are spread across all nine
banks, simultaneous operation cannot be carried out.
All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase
operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it
cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing.
Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase
operation is not executed and the device returns to Read Mode 100 µs after the rising edge of the WE signal in
the last bus cycle.
If an auto-erase operation fails, the device remains in Erasing state and does not return to Read Mode. The
device status is indicated by the Hardware Sequence flag. After a failure either a Reset command or a Hardware
Reset is required to return the device to Read Mode. If multiple blocks are selected, it will not be possible to
ascertain the block in which the failure occurred. In this case either abandon use of the device altogether, or
perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take
measures to prevent subsequent use of the failed block.
Erase Suspend / Erase Resume Modes
Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block.
The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other
oreration modes. When the command is input, the address of the bank on which Erase is being performed must
be specified.
In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend
command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after tSUSE. The
device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is
read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output
will stop toggling and RY/BY will be set to High-Impedance.
Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has
not been selected for the Auto Block Erase. Data is written in the usual manner.
To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of
the bank on which the Write was being performed must be specified. On receiving an Erase Resume command,
the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend
command is input during the Erase Hold Time, the device will return to the state it was in at the start of the
Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input
during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on
RY/BY .
2002-10-24 11/53


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64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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BLOCK PROTECTION
TC58FVT641/B641FT/XB-70,-10
Block Protection is a function for disabling writing and erasing specific blocks. Block protection can be carried
out in two ways: by supplying a high voltage (VID) to the device (see Block protection 1) or by supplying a high
voltage and a command sequence (see Block protection 2).
(1) Block protection 1
Specify a device block address and make the following signal settings A9 = OE = VID, A1 = VIH and CE
= A0 = A6 = VIL. Now when a pulse is input to WE for tPPLH, the device will start to write to the block
protection circuit. Block protection can be verified using the Verify Block Protect command. Inputting VIL
on OE sets the device to Verify Mode. 01H is output if the block is protected and 00H is output if the block
is unprotected. If block protection was unsuccessful, the operation must be repeated. Releasing VID from A9
and OE terminates this mode.
(2) Block protection 2
Applying VID to RESET and inputting the Block Protect 2 command also performs block protection. The
first cycle of the command sequence is the Set-up command. In the second cycle, the Block Protect command
is input, in which a block address and A1 = VIH and A0 = A6 = VIL are input. Now the device writes to the
block protection circuit. There is a wait of tPPLH until this write is completed; however, no intervention is
necessary during this time. In the third cycle the Verify Block Protect command is input. This command
verifies the write to the block protection circuit. Read is performed in the fourth cycle. If the protection
operation is complete, 01H is output. If a value other than 01H is output, block protection is not complete
and the Block Protect command must be input again. Removing the VID input from RESET exits this
mode.
Temporary Block Unprotection
The TC58FVT641/B641 has a temporary block unprotection feature which disables block protection for all
protected blocks. Unprotection is enabled by applying VID to the RESET pin. Now Write and Erase operations
can be performed on all blocks except the boot blocks which have been protected by the Boot Block Protect
operation. The device returns to its previous state when VID is removed from the RESET pin. That is,
previously protected blocks will be protected again.
Verify Block Protect
The Verify Block Protect command is used to ascertain whether a block is protected or unprotected.
Verification is performed either by inputting the Verify Block Protect command or by applying VID to the A9 pin,
as for ID Read Mode, and setting the block address = A0 = A6 = VIL and A1 = VIH. If the block is protected, 01H
is output. If the block is unprotected, 00H is output.
Boot Block Protection
Boot block protection temporarily protects certain boot blocks using a method different from ordinary block
protection. Neither VID nor a command sequence is required. Protection is performed simply by inputting VIL
on WP/ACC . The target blocks are the two pairs of boot blocks. The top boot blocks are BA133 and BA134; the
bottom boot blocks are BA0 and BA1. Inputting VIH on WP/ACC releases the mode. From now on, if it is
necessary to protect these blocks, the ordinary Block Protection Mode must be used.
2002-10-24 12/53


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64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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Hidden ROM Area
TC58FVT641/B641FT/XB-70,-10
The TC58FVT641/B641 features a 64-Kbyte hidden ROM area which is separate from the memory cells. The
area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot
be released, once the block is protected, data in the block cannot be overwritten.
The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS
TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters
Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations
are the same as auto operations except that the device is in Hidden ROM Mode. However, regarding write
operation, Accelaration mode can not be performed during Hidden ROM Mode. To protect the hidden ROM area,
use the block protection function. The operation of Block Protect here is the same as a normal Block Protect
except that VIH rather than VID is input to RESET . Once the block has been protected, protection cannot be
released, even using the temporary block unprotection function. Use Block Protect carefully. Note that in
Hidden ROM Mode, simultaneous operation cannot be performed. Therefore, do not attempt to access areas
other than the hidden ROM area.
To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read
Mode.
HIDDEN ROM AREA ADDRESS TABLE
TYPE
BOOT BLOCK
ARCHITECTURE
BYTE MODE
ADDRESS RANGE
SIZE
TC58FVT641
TOP BOOT BLOCK
TC58FVB641 BOTTOM BOOT BLOCK
7F0000H~7FFFFFH
000000H~00FFFFH
64 Kbytes
64 Kbytes
WORD MODE
ADDRESS RANGE
SIZE
3F8000H~3FFFFFH
000000H~007FFFH
32 Kwords
32 Kwords
2002-10-24 13/53


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64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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COMMON FLASH MEMORY INTERFACE (CFI)
TC58FVT641/B641FT/XB-70,-10
The TC58FVT641/B641 conforms to the CFI specifications. To read information from the device, input the
Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the
Reset command.
CFI CODE TABLE
ADDRESS A6~A0
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
DATA DQ15~DQ0
0051H
0052H
0059H
0002H
0000H
0040H
0000H
0000H
0000H
0000H
0000H
0027H
0036H
0000H
0000H
0004H
0000H
000AH
0000H
0005H
0000H
0004H
0000H
0017H
0002H
0000H
0000H
0000H
DESCRIPTION
ASCII string QRY
Primary OEM command set
2: AMD/FJ standard type
Address for primary extended table
Alternate OEM command set
0: none exists
Address for alternate OEM extended table
VDD (min) (Write/Erase)
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
VDD (max) (Write/Erase)
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
VPP (min) voltage
VPP (max) voltage
Typical time-out per single byte/word write (2N µs)
Typical time-out for minimum size buffer write (2N µs)
Typical time-out per individual block erase (2N ms)
Typical time-out for full chip erase (2N ms)
Maximum time-out for byte/word write (2N times typical)
Maximum time-out for buffer write (2N times typical)
Maximum time-out per individual block erase (2N times typical)
Maximum time-out for full chip erase (2N times typical)
Device Size (2N byte)
Flash device interface description
2: ×8/×16
Maximum number of bytes in multi-byte write (2N)
2002-10-24 14/53


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TC58FVT641/B641FT/XB-70,-10
ADDRESS A6~A0
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
DATA DQ15~DQ0
0002H
0007H
0000H
0020H
0000H
007EH
0000H
0000H
0001H
0050H
0052H
0049H
0031H
0031H
0000H
0002H
0001H
0001H
0004H
0001H
0000H
0000H
0085H
0095H
000XH
0001H
DESCRIPTION
Number of erase block regions within device
Erase Block Region 1 information
Bits 0~15: y = block number
Bits 16~31: z = block size
(z × 256 bytes)
Erase Block Region 2 information
ASCII string PRI
Major version number, ASCII
Minor version number, ASCII
Address-Sensitive Unlock
0: Required
1: Not required
Erase Suspend
0: Not supported
1: For Read-only
2: For Read & Write
Block Protect
0: Not supported
X: Number of blocks per group
Block Temporary Unprotect
0: Not supported
1: Supported
Block Protect/Unprotect scheme
Simultaneous operation
0: Not supported
1: Supported
Burst Mode
0: Not supported
Page Mode
0: Not supported
VACC (min) voltage
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
VACC (max) voltage
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
Top/Bottom Boot Block Flag
2: TC58FVB641
3: TC58FVT641
Program Suspend
0: Not supported
1: Supported
2002-10-24 15/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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HARDWARE SEQUENCE FLAGS
TC58FVT641/B641FT/XB-70,-10
The TC58FVT641/B641 has a Hardware Sequence flag which allows the device status to be determined during an
auto mode operation. The output data is read out using the same timing as that used when CE = OE = VIL in
Read Mode. The RY/BY output can be either High or Low.
The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The
Hardware Sequence flag is read to determine the device status and the result of the operation is verified by
comparing the read-out data with the original data.
STATUS
DQ7
DQ6
DQ5
DQ3
DQ2 RY/BY
In Progress
Auto Programming
Read in Program Suspend(1)
In Auto
Erase
Selected(2)
Erase Hold Time Not-selected(3)
Auto Erase
Selected
Not-selected
DQ7
Data
0
0
0
0
Toggle
Data
Toggle
Toggle
Toggle
Toggle
0
Data
0
0
0
0
0
Data
0
0
1
1
1
Data
Toggle
1
Toggle
1
0
High-Z
0
0
0
0
In Erase
Suspend
Read
Programming
Selected
Not-selected
Selected
Not-selected
1
Data
DQ7
DQ7
1
Data
Toggle
Toggle
0
Data
0
0
0
Data
0
0
Toggle
Data
Toggle
1
High-Z
High-Z
0
0
Time Limit
Exceeded
Auto Programming
Auto Erase
Programming in Erase Suspend
DQ7
0
DQ7
Toggle
Toggle
Toggle
1
1
1
010
1 NA 0
0 NA 0
Notes:DQ outputs cell data and RY/BY goes High-Impedence when the operation has been completed.
DQ0 and DQ1 pins are reserved for future use.
0 is output on DQ0, DQ1 and DQ4.
(1) Data output from an address to which Write is being performed is undefined.
(2) Output when the block address selected for Auto Block Erase is specified and data is read from there.
During Auto Chip Erase, all blocks are selected.
(3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is
read from there.
DQ7 ( DATA polling)
During an Auto-Program or auto-erase operation, the device status can be determined using the data polling
function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation,
DQ7 outputs inverted data during the programming operation and outputs actual data after programming has
finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase
operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data.
When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE
signal.
2002-10-24 16/53


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64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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DQ6 (Toggle bit 1)
TC58FVT641/B641FT/XB-70,-10
The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase
operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately
outputs a 0 or a 1 for each OE access while CE = VIL while the device is busy. When the internal operation
has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the
operation fails, the DQ6 output toggles.
If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around
3 µs. It will then stop toggling. If an attempt is made to execute an auto erase operation on a protected block,
DQ6 will toggle for around 100 µs. It will then stop toggling. After toggling has stopped the device will return to
Read Mode.
DQ5 (internal time-out)
If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the
operation has not been completed within the allotted time.
Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case DQ5
outputs a 1. Either a hardware reset or a software Reset command is required to return the device to Read
Mode.
DQ3 (Block Erase timer)
The Block Erase operation starts 50 µs (the Erase Hold Time) after the rising edge of WE in the last
command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase
operation starts. Additional Block Erase commands can only be accepted during the Block Erase Hold Time.
Each Block Erase command input within the hold time resets the timer, allowing additional blocks to be marked
for erasing. DQ3 outputs a 1 if the Program or Erase operation fails.
DQ2 (Toggle bit 2)
DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the
device is in Erase Suspend Mode.
If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle.
Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If data is read
continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2
output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase
Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in
Programming Mode, DQ2 will output a 1.
RY/BY (READY/ BUSY )
TC58FVT641/B641 has a RY/BY signal to indicate the device status to the host processor. A 0 (Busy state)
indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates that the
operation has finished and that the device can now accept a new command. RY/BY outputs a 0 when an
operation has failed.
RY/BY outputs a 0 after the rising edge of WE in the last command cycle.
During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/BY outputs a
1 during an Erase Suspend operation. The output buffer for the RY/BY pin is an open-drain type circuit,
allowing a wired-OR connection. A pull-up resistor must be inserted between VDD and the RY/BY pin.
2002-10-24 17/53


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64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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DATA PROTECTION
TC58FVT641/B641FT/XB-70,-10
The TC58FVT641/B641 includes a function which guards against malfunction or data corruption.
Protection against Program/Erase Caused by Low Supply Voltage
To prevent malfunction at power-on or power-down, the device will not accept commands while VDD is below
VLKO. In this state, command input is ignored.
If VDD drops below VLKO during an Auto Operation, the device will terminate Auto-Program execution. In
this case, Auto operation is not executed again when VDD return to recommended VDD voltage Therefore,
command need to be input to execute Auto operation again.
When VDD > VLKO, make up countermeasure to be input accurately command in system side please.
Protection against Malfunction Caused by Glitches
To prevent malfunction during operation caused by noise from the system, the device will not accept pulses
shorter than 3 ns (Typ.) input on WE , CE or OE . However, if a glitch exceeding 3 ns (Typ.) occurs and the
glitch is input to the device malfunction may occur.
The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be
misinterpreted as part of a command sequence input and that the device will acknowledge it. Then, even if a
proper command is input, the device may not operate. To avoid this possibility, clear the Command Register
before command input. In an environment prone to system noise, Toshiba recommend input of a software or
hardware reset before command input.
Protection against Malfunction at Power-on
To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CE =
VIL the device does not latch the command on the first rising edge of WE or CE . Instead, the device
automatically Resets the Command Register and enters Read Mode.
2002-10-24 18/53


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64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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ABSOLUTE MAXIMUM RATINGS
TC58FVT641/B641FT/XB-70,-10
SYMBOL
PARAMETER
VDD
VDD Supply Voltage
VIN Input Voltage
VDQ
Input/Output Voltage
VIDH
Maximum Input Voltage for A9, OE and RESET
VACCH
Maximum Input Voltage for WP/ACC
PD Power Dissipation
Tsolder
Soldering Temperature (10s)
Tstg Storage Temperature
Topr
IOSHORT
Operating Temperature
Output Short-Circuit Current(1)
(1) Outputs should be shorted for no more than one second.
No more than one output should be shorted at a time.
RANGE
0.6~4.6
0.6~VDD + 0.5 (4.6)
0.6~VDD + 0.5 (4.6)
13.0
10.5
126
260
55~150
40~85
100
UNIT
V
V
V
V
V
mW
°C
°C
°C
mA
CAPACITANCE (Ta = 25°C, f = 1 MHz)
TSOPI
SYMBOL
PARAMETER
CIN Input Pin Capacitance
COUT
Output Pin Capacitance
CIN2
Control Pin Capacitance
This parameter is periodically sampled and is not tested for every device.
TFBGA
SYMBOL
PARAMETER
CIN Input Pin Capacitance
COUT
Output Pin Capacitance
CIN2
Control Pin Capacitance
This parameter is periodically sampled and is not tested for every device.
CONDITION
VIN = 0 V
VOUT = 0 V
VIN = 0 V
MAX
4
8
7
UNIT
pF
pF
pF
CONDITION
VIN = 0 V
VOUT = 0 V
VIN = 0 V
MAX
4
8
7
UNIT
pF
pF
pF
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
MAX
UNIT
VDD
VIH
VIL
VID
VACC
VDD Supply Voltage
Input High-Level Voltage
Input Low-Level Voltage
High-Level Voltage for A9, OE and RESET (3)
High-Level Voltage for WP/ACC (3)
2.7
0.7 × VDD
0.3(1)
3.6
VDD + 0.3(2)
0.2 × VDD
11.4 12.6
8.5 9.5
V
Ta Operating Temperature
40 85
°C
(1) 2 V (pulse width of 20 ns max)
(2) +2 V (pulse width of 20 ns max)
(3) Do not apply VID/VACC when the supply voltage is not within the devices recommended operating voltage range.
2002-10-24
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DC CHARACTERISTICS
TC58FVT641/B641FT/XB-70,-10
SYMBOL
PARAMETER
CONDITION
MIN
ILI
ILO
VOH
VOL
IDDO1
IDDO2
IDDO3
IDDO4
IDDO5
IDDO6
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
VDD Average Read Current
VDD Average Program Current
VDD Average Erase Current
VDD Average
Read-While-Program Current
VDD Average Read-while-Erase
Current
VDD Average Program-while-
Erase-Suspend Current
0 V VIN VDD
0 V VOUT VDD
IOH = −0.1 mA
IOH = −2.5 mA
IOL = 4.0 mA
VIN = VIH/VIL, IOUT = 0 mA
tCYCLE = tRC = 100 ns
VIN = VIH/VIL, IOUT = 0 mA
VIN = VIH/VIL, IOUT = 0 mA
VIN = VIH/VIL, IOUT = 0 mA
tCYCLE = tRC = 100 ns
VIN = VIH/VIL, IOUT = 0 mA
tCYCLE = tRC = 100 ns
VIN = VIH/VIL, IOUT = 0 mA
VDD 0.4
0.85 × VDD
IDDS1
IDDS2
IID
VDD Standby Current
(VADuDtoSmtaantidcbSyleCeuprrMenotde(1))
High-Voltage Input Current for
A9, OE and RESET
CE = RESET = VDD
or RESET = VSS
VIH = VDD
VIL = VSS
11.4 V VID 12.6 V
IACC
High-Voltage Input Current for
WP/ACC
8.5 V VACC 9.5 V
VLKO
Low-VDD Lock-out Voltage
2.3
(1) The device enters Automatic Sleep Mode in which the address remains fixed for during 150 ns.
MAX
±1
±1
0.4
30
15
15
45
45
15
10
10
35
20
2.5
UNIT
µA
V
mA
µA
mA
V
AC TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Pulse Rise and Fall Time (10%~90%)
Timing Measurement Reference Level (input)
Timing Measurement Reference Level (output)
Output Load
CONDITION
VDD, 0.0 V
5 ns
1.5 V, 1.5 V
1.5 V, 1.5 V
CL (100 pF) + 1 TTL Gate / CL (30 pF) + 1 TTL Gate
2002-10-24 20/53


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TC58FVT641/B641FT/XB-70,-10
AC CHARACTERISTICS AND OPERATING CONDITIONS
READ CYCLE
PRODUCT NAME
-70 -10
SYMBOL
OUTPUT CAPACITANCE LOAD (CL)
30pF
100pF
30pF
100pF
PARAMETER
MIN MAX MIN MAX MIN MAX MIN MAX UNIT
tRC
tACC
tCE
tOE
tCEE
tOEE
tOH
tDF1
tDF2
Read Cycle Time
Address Access Time
CE Access Time
OE Access Time
CE to Output Low-Z
OE to Output Low-Z
Output Data Hold Time
CE to Output High-Z
OE to Output High-Z
70 80 90 100 ns
70 80 90 100 ns
70 80 90 100 ns
30 35 35 40 ns
0 0 0 0 ns
0 0 0 0 ns
0 0 0 0 ns
25 25 30 30 ns
25 25 30 30 ns
BLOCK PROTECT
SYMBOL
tVPT
tVPS
tCESP
tVPH
tPPLH
VID Transition Time
VID Set-up Time
CE Set-up Time
OE Hold Time
WE Low-Level Hold Time
PARAMETER
PROGRAM AND ERASE CHARACTERISTICS
SYMBOL
PARAMETER
tPPW
tPCEW
tPBEW
tEW
Auto-Program Time (Byte Mode)
Auto-Program Time (Word Mode)
Auto Chip Erase Time
Auto Block Erase Time
Erase/Program Cycle
MIN
MAX
UNIT
4
4
4
4
100
µs
µs
µs
µs
µs
MIN
TYP.
MAX
UNIT
8 300 µs
11 300 µs
95 1350
s
0.7
105
10 s
Cycles
2002-10-24 21/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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TC58FVT641/B641FT/XB-70,-10
COMMAND WRITE/PROGRAM/ERASE CYCLE
SYMBOL
PARAMETER
tCMD
tAS
tAH
tAHW
tDS
tDH
tWELH
tWEHH
tCES
tCEH
tCELH
tCEHH
tWES
tWEH
tOES
tOEHP
tOEHT
tAHT
tAST
tBEH
tVDS
tBUSY
tRP
tREADY
tRB
tRH
tCEBTS
tBTD
tSUSP
tRESP
tSUSE
tRESE
Command Write Cycle Time
Address Set-up Time / BYTE Set-up Time
Address Hold Time / BYTE Hold Time
Address Hold Time from WE High level
Data Set-up Time
Data Hold Time
WE Low-Level Hold Time
WE High-Level Hold Time
( WE Control)
( WE Control)
CE Set-up Time to WE Active
( WE Control)
CE Hold Time from WE High Level
( WE Control)
CE Low-Level Hold Time
( CE Control)
CE High-Level Hold Time
( CE Control)
WE Set-up time to CE Active
( CE Control)
WE Hold Time from CE High Level
( CE Control)
OE Set-up Time
OE Hold Time (Toggle, Data Polling)
OE High-Level Hold Time (Toggle)
Address Hold Time (Toggle)
Address Set-up Time (Toggle)
Erase Hold Time
VDD Set-up Time
Program/Erase Valid to RY/BY Delay
Program/Erase Valid to RY/BY Delay during Suspend Mode
RESET Low-Level Hold Time
RESET Low-Level to Read Mode
RY/BY Recovery Time
RESET Recovery Time
CE Set-up time BYTE Transition
BYTE to Output High-Z
Program Suspend Command to Suspend Mode
Program Resume Command to Program Mode
Erase Suspend Command to Suspend Mode
Erase Resume Command to Erase Mode
70
MIN MAX
70
0
40
20
40
0
40
20
0
0
40
20
0
0
0
90
20
0
0
50
500
90
300
500
20
0
50
5
30
1.5
1
15
1
10
MIN MAX
UNIT
100
ns
0 ns
50 ns
20 ns
50 ns
0 ns
50 ns
20 ns
0 ns
0 ns
50 ns
20 ns
0 ns
0 ns
0 ns
90 ns
20 ns
0 ns
0 ns
50  µs
500
µs
90 ns
300 ns
500
ns
20 µs
0 ns
50 ns
5 ns
30 ns
1.5 µs
1 µs
15 µs
1 µs
2002-10-24 22/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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TIMING DIAGRAMS
VIH or VIL
Read / ID Read Operation
Address
CE
OE
tAHW
WE tOEH
TC58FVT641/B641FT/XB-70,-10
Data invalid
tRC
tACC
tCE
tOE
tOEE
tCEE
tOH
tDF1
tDF2
DOUT
Hi-Z
Output data Valid
Hi-Z
ID Read Operation (apply VID to A9)
A0
tRC
A1
tACC
A6
VID
VIH tVPS
A9
tCE
CE
tOE
OE
WE
DOUT
Hi-Z
Read Mode
Manufacturer
code
ID Read Mode
Hi-Z
Device
code
Hi-Z
Read Mode
2002-10-24 23/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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Command Write Operation
TC58FVT641/B641FT/XB-70,-10
This is the timing of the Command Write Operation. The timing which is described in the following pages is
essentially the same as the timing shown on this page.
WE Control
Address
tCMD
Command address
tAS tAH
CE
tCES
tCEH
WE
DIN
tWEL
tDS
tWEHH
tDH
Command data
CE Control
Address
CE
WE
DIN
tCMD
Command address
tAS tAH
tWES
tCELH
tCEHH
tWEH
tDS tDH
Command data
2002-10-24 24/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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ID Read Operation (input command sequence)
TC58FVT641/B641FT/XB-70,-10
Address
CE
555H
tCMD
2AAH
BK + 555H
BK + 00H
tRC
BK + 01H
OE
tOES
WE
DIN AAH 55H 90H
DOUT
Hi-Z
Read Mode (input of ID Read command sequence)
(Continued)
Address
CE
555H
tCMD
2AAH
555H
Manufacturer code Device code
ID Read Mode
OE
WE
DIN AAH 55H F0H
DOUT
Hi-Z
ID Read Mode (input of Reset command sequence) Read Mode
Note: Word Mode address shown.
BK: Bank address
2002-10-24 25/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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Auto-Program Operation (WE Control)
TC58FVT641/B641FT/XB-70,-10
Address
CE
555H
tCMD
2AAH
555H
PA
PA
OE
tOES
WE
tOEHP
tPPW
DIN
AAH
55H
A0H
PD
DOUT
tVDS
VDD
Hi-Z
Note: Word Mode address shown.
PA: Program address
PD: Program data
DQ7 DOUT
Auto Chip Erase / Auto Block Erase Operation (WE Control)
Address
CE
555H
tCMD
2AAH
555H
555H
2AAH
555H/BA
OE
tOES
WE
DIN AAH 55H 80H
tVDS
VDD
Note: Word Mode address shown.
BA: Block address for Auto Block Erase operation
AAH
55H 10H/30H
2002-10-24 26/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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Auto-Program Operation (CE Control)
TC58FVT641/B641FT/XB-70,-10
Address
CE
555H
tCMD
2AAH
555H
OE
tOES
WE
DIN
AAH
55H
A0H
DOUT
tVDS
VDD
Hi-Z
Note: Word Mode address shown.
PA: Program address
PD: Program data
PA PA
tPPW
tOEHP
PD
DQ7 DOUT
Auto Chip Erase / Auto Block Erase Operation (CE Control)
Address
CE
555H
tCMD
2AAH
555H
555H
OE
tOES
WE
2AAH
555H/BA
DIN AAH 55H 80H AAH
tVDS
VDD
Note: Word Mode address shown.
BA: Block address for Auto Block Erase operation
55H 10H/30H
2002-10-24 27/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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Program/Erase Suspend Operation
Address
BK
TC58FVT641/B641FT/XB-70,-10
RA
CE
OE
WE
DIN B0H
DOUT
Hi-Z
tSUSP/tSUSE
RY/BY
Program/Erase Mode
RA: Read address
tOE
tCE
DOUT
Hi-Z
Suspend Mode
Program/Erase Resume Operation
Address RA
BK
PA/BA
CE
OE
tOES
WE tDF1
tDF2
DIN
tRESP/tRESE
30H
DOUT DOUT
Hi-Z
RY/BY
Suspend Mode
PA: Program address
BK: Bank address
BA: Block address
RA: Read address
Flag: Hardware Sequence flag
tOE
tCE
Flag
Hi-Z
Program/Erase Mode
2002-10-24 28/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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RY/BY during Auto Program/Erase Operation
TC58FVT641/B641FT/XB-70,-10
CE
WE
RY / BY
Command input sequence
tBUSY During operation
Hardware Reset Operation
WE
RESET
RY/BY
tRB
tRP
tREADY
Read after RESET
Address
RESET
DOUT
tRH
Hi-Z
tRC
tACC
tOH
Output data valid
2002-10-24 29/53


TC58FVB641 (Toshiba)
64-MBIT (8M x 8 BITS / 4M x 16 BITS) CMOS FLASH MEMORY

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BYTE during Read Operation
TC58FVT641/B641FT/XB-70,-10
CE
OE
BYTE
DQ0~DQ7
DQ8~DQ14
DQ15/A-1
tCEBTS
tBTD
Data Output
Data Output
Data Output
Data Output
tACC
Address Input
BYTE during Write Operation
CE
WE
BYTE
tAS
tAH
2002-10-24 30/53




TC58FVB641.pdf
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