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Datasheet
Revision 1.3_B8
3GBit/s Digital
Automotive Pixel Link
Transmitter
INAP375T
INAP375TAQ
The INAP375T together with an APIX2 receiver device
offers the next generation high speed digital serial link for
DISPLAY and CAMERA applications. It provides a
DC-balanced, AC coupled low latency, point-to-point link
over shielded twisted pair (STP) cables. Its scalable
physical layer provides bandwidth of up to 3 GBit/s at
lowest EMI. The INAP375T supports popular automotive
displays with video resolutions such as 1600x600 pixels
and refresh rates of up to 100Hz. The device offers a
flexible video interface, configurable to handle 1 or 2
independent video streams, with input interfaces such as
parallel RGB (1x24 Bit or 2x10 Bit) or openLDI (“LVDS”)
e.g. 2x (4 lanes + clock). Software adjustable driver
characteristics and configurable operating modes allow the
transmission of 3 GBit/s at distances of up to 12m over a
single pair of wires. In addition to the video transmission
the INAP375T provides completely independent Full
Duplex Communication channels. Using the internal
AShell protocol, data transfers are protected by error
detection and retransmission mechanisms. Offering a
Media Independent Interface (MII), the INAP375T can be
directly connected to an ethernet Media Access Controller,
offering full network capabilities through the APIX link.
Additionally, the link is optimized to carry low latency GPIO
signals for reset or synchronization purposes. The built-in
audio path allows synchronous transmission of up to
4 stereo audio channels, with highly precise clock regener-
ation at the receiver for high-end rear-seat entertainment
applications.
Applications:
• Central Information Displays
• Round View Camera Systems
• Head up Displays
• Cluster Displays
• Rear-Seat Entertainment Systems
• Stereo Camera Systems
• Rear View Camera Systems
• Sensor Fusion Systems
• Automotive Driver Assistance
• Surveillance Systems
• Inspection Systems
Features:
• Backwards compatibility with APIX1
• 500 MBit/s, 1 GBit/s and 3 GBit/s sustained
downstream link bandwidth for video data
rates up to 2591 MBit/s
• up to 187.5 MBit/s upstream link bandwidth
• Supports 2 independent video streams
• Configurable video interface
– Parallel RGB (10,12,18 or 24 Bit)
– OpenLDI compliant LVDS interface[1] with
Single Pixel Format (18 or 24 Bit)
– Parallel Bulk Data Mode (10,12,18,24 Bit)
• Video resolutions up to HD resolutions
• Configurable full duplex communication
channel for up to 2 receivers (daisy chain)
• Media Independent Interface
• SPI data interfaces
• I²C Master interface
• GPIOs for direct signalling and camera
synchronization support
• Embedded AShell
• I²S Audio interface
– supports 16/24/32 Bit word length
– supports up to 192kHz sampling
– TDM support for up to 8 channels
• Diagnostic Features:
– Built-In PRBS Generator
– Embedded diagnostics
• Up to 12m distance at 3 GBit/s
Packages:
• 100 pin LQFP
• 104 pin AQFN
Temperature/Quality:
• LQFP: -40°C to +105°C
• aQFN: -40°C to +95°C/+105°C
• AEC-Q100
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1.0 Characteristics
Video
Audio
GPIO
I2C Dev.
EEPROM
Ethernet
Data
EEPROM
Data
Configuration
2xLVDS
2x parallel
video
I2S
GPIOs
I2C M
MII /
Nibble
SPI M
SPI S
Integrity support
FIFO
FIFO
Audio
MCLK
Framer
Serializer
FIR
I2C
AShell
Deserializer
Deframer
CML
Configuration,
Control, Status
Reset Osc.
VCO
APIX
Downstream
APIX
Upstream
Reset 10MHz
Figure 1-1: INAP375T Block Diagramm
1.1 Absolute Maximum Ratings
The absolute maximum ratings define values beyond which damage to the device may occur. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. The functional operation
of the device at these or any other conditions beyond the recommended operating ratings is not guaranteed.
Parameter
Symbol
Min. Max. Units
DC Supply Voltage
VDVDD,
VDVDD_XTAL,
VAVDD_LD
-0.5
5.0
Input Voltage
VVDD, VAVDD,
VAVDD_LVDS,
VVDD_XTAL
-0.5
3.0
I/O Current (DC or transient any pin)
ID -20 +20
Storage Temperature
Tstg -55 +150
Table 1-1: Absolute maximum ratings
V
V
mA
°C
Note
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Parameter
Max Soldering Temperature
ESD Protection HBM
JEDEC JESD22/A114
ESD Protection CDM
EIA/JEDEC JESD22/C101
ESD Protection MM
EIA/JEDEC JESD22-A115A
Symbol
TSLD / TSLD
Min.
Max. Units
Note
260 ° C 40 seconds maximum
-3 +3 kV RD=1.5k, CS=100pF
-1 +1 kV
-200 +200
Table 1-1: Absolute maximum ratings
V
1.2 Recommended Operating Conditions
Parameter
Description
Min. Typ. Max. Units
VVDD, VVDD_XTAL
VDVDD,
VDVDD_XTAL
VAVDD, VAVDD_VCO
VAVDD_LD
VAVDD_LVDS_PLL,
VAVDD_LVDS
VSUPPLY_NOISE
Ta
Digital Core supply, Oscillator supply
1.71 1.8 1.89
Digital IO Supply,
Digital Oscillator supply
3.0 3.3 3.6
CML PHY supply voltage, VCO supply 1.71 1.8 1.89
CML IO supply
3.0 3.3 3.6
LVDS PLL & Core supply
1.71 1.8 1.89
Analog and Digital Supply Noise
50
Ambient Temperature
-40 - +105
Table 1-2: Recommended operating conditions
V
V
V
V
V
mV
°C
Note
1.3 Electrical Characteristics
1.3.1 Serial Interface
The INAP375T downstream serial interface offers a flexible serial interface, with configurable pre-emphasis
and digital filter structure. Data dependent deterministic jitter components, mainly introduced by ISI due to ca-
ble attenuation, can be compensated by pre-emphasis and equalization. Therefore only periodic and random
jitter components are considered.
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Datasheet
Parameter
Symbol
Min. Typ. Max. Units
Note
Effective serial bit rise and fall
time
trf_ser_effective
75
140
-
ps
CML Drive current
Periodic Jitter
Iout_dwn
JPδ-δ
15 -
- mA
using PRBS12 sig-
nal; parameter
-
5.9
-
mUI
depends on applica-
tion board, measured
on characterization
test board
Random Jitter
JRrms
- 1.6 - ps using PRBS12 signal
Table 1-3: Downstream interface characteristics (SD_DWN_OUT_P, SD_DWN_OUT_N)
Parameter
Differential input voltage range
Serial input common mode
range
Symbol
Vdiff_in
Vcmm_SDIN
Min.
± 50
GND +0.7V +
(Vdiff_in/2)
Max.
± 500
VAVDD +0.5V -
(Vdiff_in/2)
Units
mV
V
Table 1-4: Upstream interface characteristics (SD_UP_IN_P,SD_UP_IN_N)
Note
1.3.2 Supply Current
Parameter
Symbol
Typ.a Max. Unit Comment
Digital Core & Oscillator Supply current
IVDD + IVDD_XTAL
51 120 mA
Digital IO & Oscillator Supply Current
IDVDD + IDVDD_XTAL
3
50 mA
LVDS Core & PLL Supply Current
IAVDD_LVDS +
IAVDD_LVDS_PLL
- 30 mA
CML PHY Supply Current
IAVDD
111 190 mA see Figure 1-15
VCO Supply Current
IAVDD_VCO
5 15 mA
CML IO Supply Current
IAVDD_LD
26 95 mA see Figure 1-15
Table 1-5: Supply current
a. 24bit RGB with 95MHz pixel clock and 5m cable setting
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1.3.3 Pixel Interface
The INAP375T‘s pixel interface can be configured to RGB or/and LVDS inputs. For further informations please
refer to the INAP375T user manual.
1.3.3.1 RGB Interface
Parameter
Description
Test Condition
Min.
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Current a Vin = VDVDD
IIL Input Low Current a Vin = 0 V
VOH Output High Voltage IOH= -4mA
VOL Output Low Voltage IOL= 4mA
Table 1-6: RGB characteristics
a. input with Schmitt Trigger (current feedback of ~100μA)
2.0
0
-10
-10
2.4
-
Max.
VDVDD
0.8
10
10
-
0.4
Units
V
V
μA
μA
V
V
 
  






Figure 1-2: RGB Interface Timing
The capturing edge of pixel clock can be set to rising or falling. For further information please refer to the
INAP375T user manual. fPIXEL_CLOCK = 1/tPERIOD . All values specified for TA=25°C.
Parameter
fPIXEL_CLOCK
tSETUP
tHOLD
Description
Test Condition
Pixel Clock Input Frequency
Setup Time Pixel Data To Pixel Clock slew rate 2V/ns
Hold Time Pixel Data to Pixel Clock
slew rate 2V/ns
Table 1-7: RGB Interface timing
Min.
5
2
1
Max.
120
-
-
Units
MHz
ns
ns
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1.3.3.2 LVDS Interface[1]
OpenLDI interface with inputs according to LVDS specification[2]. Exceptions are listed at table 1-8.
Parameter
VOD
VOS
VOD
VOS
ISA
IIN
VTH
VIN
fLVDS_CLK
Description
Differential Output Voltage
Min.
247
Max.
454
Offset Voltage
1.125
1.375
|Change to VOD|
|Change to VOs|
Short Circuit Current
- 50
- 50
- 24
Input Current
- 20
Receiver Threshold Voltage
-
+100
Input Voltage Range
0 1.8
LVDS Clock Frequency
5
80
Table 1-8: LVDS interface exceptions to TIA/EIA644 specification
Units
mV
V
mV
mV
mA
μA
mV
V
MHz
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1.3.4 Data Interface
1.3.4.1 General Characteristics
The following characteristics are valid for SPI, SBDOWN, SBUP, GPIO, I²S, MII / Nibble data and I²C function-
ality. The pins I2C_SCL/INBOUND_TS and I2C_SD/OUTBOUND_TS are open drain outputs and require
external pull up circuitry. All values specified for TA=25°C.
Parameter
Symbol Test Condition
Min.
Input High Voltage
VIH
2.0
Input Low Voltage
Pull Down Current a
VIL
IIH_PD
Vin = VDVDD
0
30
Input High Current
IIH Vin = VDVDD
-10
Input Low Current
Output High Voltage b
IIL Vin = 0 V
-10
VOH IOH= -4mA, Figure 1-16 2.4
Output Low Voltage
Output Rise Time b
Output Fall Time b
VOL IOL= 4mA, Figure 1-16
tRO CL=5pF
tFO CL=5pF
-
-
-
Table 1-9: General IO Characteristics
a. pins with internal pull down to GND
b. not relevant for open drain outputs
Max.
VDVDD
0.8
120
10
10
-
0.4
2.6
2.1
Units
V
V
μA
μA
μA
V
V
ns
ns
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1.3.4.2 SPI Slave Interface timing









  




  




 


 
  


  

Figure 1-3: SPI Slave Timing Diagram (CPHA=0)


















  




  


 


 




  


  


Figure 1-4: SPI Slave Timing Diagram (CPHA=1)
The SPI Slave interface can be flexible configured with the parameters cfg_spi_s_cpol, cfg_spi_s_cpha. For
further informations please refer to the INAP375T user manual.
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Core clock frequency for APIX1 Mode = 125MHz and for APIX2 Mode = 187.5MHz. All values specified for
TA=25°C. tSCK = 1/fSCK.
Parameter
fSCK
tSCKH
tSCKL
tCSH
tCSS
tCSHO
tDISU
tDIHO
tDOV
tDOHO
tDODIS
tA
APIX1 Mode
APIX2 Mode
Description
Min.
Max.
Min
Max
SCK Clock Frequency
- 11 -
SCK High Time
45 - 33
SCK Low Time
45 - 33
CS# High Time
20 - 15
CS# Setup Time
CS# Hold Time
1/2 tSCK - 1/2 tSCK
50 - 34
Data In Setup Time
16 - 12
Data in Hold Time
16 - 12
Data Output Valid
- 40 -
Data Output Hold Time
8-5
Data Output Disable Time
- 50 -
Data Access Time
20 - 15
Table 1-10: SPI Slave Interface characteristics (Read Access)
15
-
-
-
-
-
-
-
29
-
45
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
fSCK
tSCKH
tSCKL
tCSH
tCSS
tCSHO
tDISU
tDIHO
Description
SCK Clock Frequency
SCK High Time
SCK Low Time
CS# High Time
CS# Setup Time
CS# Hold Time
Data In Setup Time
Data In Hold Time
APIX1 Mode
Min.
-
1/2 tSCK
1/2 tSCK
20
1/2 tSCK
50
16
16
Max.
31
-
-
-
-
-
-
-
APIX2 Mode
Min
-
1/2 tSCK
1/2 tSCK
15
1/2 tSCK
34
12
12
Max
41
-
-
-
-
-
-
-
Table 1-11: SPI Slave Interface characteristics (Write Only Access)
Units
MHz
ns
ns
ns
ns
ns
ns
ns
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1.3.4.3 SPI Master Interface timing









 






 


  

Figure 1-5: SPI Master Timing Diagram (CPHA=0)















 




 






  

Figure 1-6: SPI Master Timing Diagram (CPHA=1)
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The SPI Master interface can be flexible configured with the parameters cfg_spi_m_cpol, cfg_spi_m_cpha,
cfg_spi_m_clock_div, cfg_spi_m_cs_delay and cfg_byte_cnt. For further informations please refer to the
INAP375T user manual.
Core clock frequency for APIX1 Mode = 125MHz and for APIX2 Mode = 187.5MHz. All values specified for
TA=25°C.
APIX1 mode
APIX2 mode
Parameter Description
Min.
Max.
Min.
Max.
Units
fSCKa
SCK Clock Frequency
0.007
15.63
0.011
23.44
tSCKH
SCK High Time
18 - 12 -
tSCKL
SCK Low Time
22 - 16 -
tCSH CS# High Time
8-6-
tCSSb
CS# Setup Time (configurable)
125
-
85
-
tCSHO
CS# Hold Time
40 - 30 -
tDOV Data Output Valid Time
- 8 - 10
tDOHO
Data Output Hold Time
-10 - -5 -
tCSDOV
CS To Data Valid Time
- 140 - 100
Table 1-12: SPI Master Interface characteristics
a. can be configured from core clock/16384 to core clock/8 by cfg_spi_m_clock_div
b. can be configured from 16 to 48 core clock cycles by cfg_spi_m_cs_delay and depends on CPOL, CPHA
MHz
ns
ns
ns
ns
ns
ns
ns
ns
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1.3.4.4 SPI EEPROM Master Interface timing
SPI_M_CS2#
SPI_M_SCK
SPI_M_SDO
t
CSS
t
SCKL
t
SCKH
t
DOV
t
CSHO
SPI_M_SDI
t
DIDIS
Figure 1-7: SPI EEPROM Master Timing Diagram
t
DIHO
The SPI Master timings depend on the accuracy of the external 10MHz reference clock and are therefore listed
as typical values. For the EEPROM Master Timing the internal parameters are used: CPOL=0, CPHA=0,
tCSS delay = 48 wait core cycles and divider = core clock/128. Core clock frequency for APIX1 Mode =125MHz
and for APIX2 Mode =187.5MHz. All values specified for TA=25°C.
Parameter
fSCK
tSCKH
tSCKL
tCSS
tCSHO
tDISU
tDIHO
tDOV
APIX1 mode
APIX2 mode
Description
Min. Max. Min
SCK Clock Frequency
- 0.98 -
SCK High Time
- 512 -
SCK Low Time
- 512 -
CS# Setup Time
896 - 597
CS# Hold Time
30 - 30
Data In Setup Time
30 - 30
Data In Hold Time
30 - 30
Data Output Valid Time
-5 5 -5
Table 1-13: SPI Master EEPROM Interface characteristics
Max.
1.46
341
341
-
-
-
-
5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
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1.3.4.5 I²C Interface timing




     
Figure 1-8: I2C Timing Diagram
   
The I2C timings depend on the accuracy of the external 10MHz reference clock and are therefore listed as typ-
ical values. All values specified for TA=25°C
Parameter
fSCL
tHIGH
tLOW
tHDSTA
tHDDATa
tSUDAT
tSUSTA
tSUSTO
Description
Min.
SCL Clock Frequency
Standard Mode
Fast Mode
-
SCL High Time
Standard Mode
Fast Mode
-
SCL Low Time
Standard Mode
Fast Mode
-
Hold Time (repeated) START conditon
Standard Mode
Fast Mode
-
Data Hold Time
Standard Mode
Fast Mode
-
Data Setup Time
Standard Mode
Fast Mode
-
Setup Time for repeated START conditon
Standard Mode
Fast Mode
-
Setup Time for STOP conditon
Standard Mode
Fast Mode
-
Table 1-14: I2C Interface characteristics
Typ.
-
4.03
1.08
6.0
1.5
4.0
1.0
4.0
1.0
2.0
0.5
6.03
1.58
4.03
1.08
Max. Units
100 kHz
400
- μs
- μs
- μs
- μs
- μs
- μs
- μs
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Parameter
Description
Min.
Typ.
Max. Units
Bus Free Time
tBUF Standard Mode
Fast Mode
-
10.0
-
μs
2.5
fall time of SDA and SCL
tf
Standard Mode
Fast Modeb
- - 300 ns
300
pulse width of spike supression
tSP
Standard Mode
Fast Modec
- - - ns
50
Table 1-14: I2C Interface characteristics
a. max. valid time (tVD) non-applicable, since device stretches the LOW period (tLOW) of the SCL signal
b. output buffers without slope control for falling edges, use series resistors to slow down falling egdes if needed
c. valid for SCL signal, no spike supression on SDA signal
1.3.4.6 RESET and Boot Strap timing
The INAP375T offers several boot strap pins to define, how the device will come up and check for a configuration
after boot up or hardware reset. The correct boot strap selection is necessary for proper operation of the INAP375T
device. For more information please refer to the INAP375T user manual.

Figure 1-9: Reset and Boot Strap Timing Diagram
For a valid Reset Low Time (tRESLOW) all supply voltages needs to be stable in the operating condition. At reset
release (rising edge of RESET#) a stable reference clock is required. All values specified for TA=25°C.
Parameter
tRESLOW
tBSU
tBHO
Description
Min.
Reset Low Time
1
Boot Strap In Setup Time
0
Boot Strap in Hold Time
500
Table 1-15: Boot Strap Reset Timing
Typ.
-
-
-
Max.
-
-
-
Units
ms
ns
ns
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1.3.4.7 GPIO Interface
1.3.4.7.1 GPIO Interface Downstream
The GPIO interface is only available in APIX2 mode. At transmitter side GPIO data input ports are sampled
asynchronously and transmitted to configurable GPIO output ports at receiver side. Sampling frequency can
be flexible configured using parameters GPIO Bandwidth (gpio_bw_dwn) and GPIO halved (gpio_bw_div). For
further information please refer to the INAP375T user manual. All values specified for TA=25°C.
Downstream
Bandwidth
3 GBit/s
3 GBit/s
3 GBit/s
3 GBit/s
3 GBit/s
3 GBit/s
3 GBit/s
3 GBit/s
1 GBit/s
1 GBit/s
1 GBit/s
1 GBit/s
1 GBit/s
1 GBit/s
1 GBit/s
1 GBit/s
500 MBit/s
500 MBit/s
500 MBit/s
500 MBit/s
500 MBit/s
500 MBit/s
500 MBit/s
500 MBit/s
GPIO
ports
GPIO
Bandwidth
GPIO
halved
Sampling Frequency.
1 high off
26.768
1 low off
6.696
1 high on
13.393
1 low on
2 high off
2 low off
3.348
13.393
3.348
2 high on
6.696
2 low on unsupported
1 high off
17.857
1 low off
1 high on
1 low on
4.468
8.929
2.232
2 high off
8.929
2 low off
2.232
2 high on
4.464
2 low on
1
high
off
1 low off
1 high on
1.116
17.857
4.468
8.929
1 low on
2.232
2
high
off
8.929
2 low off
2.232
2 high on
4.464
2 low on
1.116
Table 1-16: GPIO Interface Downstream
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
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1.3.4.7.2 GPIO interface upstream
Transmitter GPIO upstream interface outputs GPIO data coming from either one or two APIX2 receiver devic-
es. Output frequency can be configured using parameter GPIO Bandwidth (gpio_bw_up). For further informa-
tions please refer to the INAP375T user manual. All values specified for TA=25°C.
Number of
Rx
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
Upstream
Bandwidth
187.5 MBit/s
187.5 MBit/s
187.5 MBit/s
187.5 MBit/s
62.5 MBit/s
62.5 MBit/s
62.5 MBit/s
62.5 MBit/s
187.5 MBit/s
187.5 MBit/s
187.5 MBit/s
187.5 MBit/s
62.5 MBit/s
62.5 MBit/s
62.5 MBit/s
62.5 MBit/s
GPIO ports
GPIO
Bandwidth
Maximum Output frequency
1 high
13.39
1 low
3.35
2 high
13.39
2 low
3.35
1 high
4.46
1 low
1.12
2 high
4.46
2 low
1.12
1 high
6.69
1 low
3.35
2 high
6.96
2 low
3.35
1 high
2.23
1 low
1.12
2 high
2.23
2 low
Table 1-17: GPIO Interface Upstream
1.12
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
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Datasheet
1.3.4.8 Sideband Interface
1.3.4.8.1 Sideband Interface Downstream
The Sideband interface is only available in APIX1 mode. At transmitter side sideband data input ports are sam-
pled asynchronously and transmitted to the corresponding output ports at receiver side. All values specified for
TA=25°C.
Downstream Bandwidth
1 GBit / s
500 MBit / s
Sampling frequency
13.89
6.94
Table 1-18: Sideband Interface Downstream
Units
MHz
MHz
1.3.4.8.2 Sideband Interface Upstream
Transmitter Sideband interface outputs sideband data coming from receiver side. All values specified for
TA=25°C.
Upstream Bandwidth
62.5 MBit / s
31.25 MBit / s
Maximum output frequency
10.41
5.21
Table 1-19: Sideband Interface Upstream
Units
MHz
MHz
1.3.4.9 MCLK clock output
The granularity of the frequency output of MCLK is definded by pulse width. For further informations please
refer to the INAP375T user manual. All values specified for TA=25°C.
Parameter
fMCLK_OUT
Description
Min
MCLK output frequency
2.953
Table 1-20: MCLK output frequency range
Max
187.5
Units
MHz
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1.3.4.10 I2S Audio Interface
fBCK = 1 / tPERIOD. All values specified for TA=25°C.

 
 

 
Parameter
fBCK
tHIGH
tLOW
tSETUP
tHOLD
Figure 1-10: I2S Audio Interface Timing Diagram
Description
Min
I2S_BCK frequency
0.75
I2S_BCK high time
7
I2S_BCK low time
7
Setup time
2
Hold time
7
Table 1-21: I2S Audio Interface Timing
Max
26.78
-
-
-
-
Units
MHz
ns
ns
ns
ns
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Datasheet
1.3.4.11 MII / NIBBLE Interface Timings
fMII_CLK = 1 / tPERIOD. All values specified for TA=25°C.

 



Figure 1-11: MII / NIBBLE Interface Timing Diagram Transmit


  

 


Figure 1-12: MII / NIBBLE Interface Timing Diagram Receive
Parameter
fMII_CLK
fMII_CLK
tSETUP
tHOLD
tOUTV
Description
Min Typ
Clock Frequency
Clock Frequency
(100BASE-T)
Setup Time
3.125
-
9
-
25
-
Hold Time
0-
Output Valid
1-
Table 1-22: MII / NIBBLE Interface Timings
Max Units
62.5
MHz
- MHz
- ns
- ns
7 ns
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Datasheet
1.3.5 Reference Clock
The INAP375T requires an external clock source like a crystal or oscillator, acting as reference for the internal
PLL.
Parameter
Description
Min.
Typ.
Max.
Unit
fref_osc
FTOL
ESRXTAL
Nominal Reference Frequency
-
10
Frequency Tolerance
-100
-
Equivalent Series Resistance
-
-
Drive Level
see Table 1-24
Table 1-23: Reference clock requirements
-
+100
80
MHz
ppm
Ohm
The INAP375T core clock frequency is generated by an internal PLL controlled by an external 10 MHz crystal.
Alternatively a stable 10 MHz clock signal (3.3V CMOS TTL) can be directly connected to XTAL_IN with
XTAL_OUT left open. Figure 1-13 shows a typical crystal design required for the oscillator circuit. The values
for C1, C2 and R1 need to be selected to match the oscillation requirements of the crystal Q1.
Figure 1-13: Crystal clock schematic example
For resonance at the correct frequency, the crystal needs to be loaded with its specified load capacitance CL,
which is the value of capacitance used in conjunction with the oscillation unit. The INAP375T oscillator provides
some of the load with internal capacitance which is specified within the range of 10pF to 12.5pF. The remainder
is generated by the external capacitors and tuning capacitors labeled C1 and C2.
The load capacitance CL can be calculated from CL = Cint + C1//C2. E.g. selecting C1 and C2 with 15pF, CL
can be calculated to CL = 12.5pF + 7.5pF = 20pF.
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Datasheet
The crystal needs to be able to withstand the power dissipation, produced by the INAP375T. The power dissi-
pation depends on the ESR of the crystal and is reflected by the maximum drive level of the crystal. Table 1-24
illustrates the power dissipation of the INAP375T and therefore the minimum drive level capabilities of the crys-
tal at different crystal ESR levels.
Crystal ESR
30
50
80
INAP375T Power dissipation /
Minimum crystal drive level
77
121
179
Table 1-24: Minimum Drive level
Unit
μW
μW
μW
1.3.6 Power Up Sequencing
To avoid high IO currents, 1.8V supply voltages have to ramp before 3.3V supply on power-up. On pow-
er-down, 3.3V supply have to be powered down before 1.8V. On power-up all supply voltages have to rise
steadily from GND level up to the VCCMIN level without turn to negative direction. The ramping times must be
within the limits as specified in Figure 1-25. All 1.8V supplies have to be ramped up simultaneously starting
from GND according Figure 1-14. Reset has to be held low until all supplies reached recommended operating
conditions.
  
Figure 1-14: Steady voltage ramp-up
Parameter
tRAMP
Description
Supply Ramp Up Time for all supplies GND to VCCmin
Min.
0.05
Table 1-25: Power supply ramp-up time
Typ.
1
Max.
10
Unit
ms
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Datasheet
1.4 Typical Operating Characteristics
    


70

0  1
0  1
(IVDD+IVDD_XTAL)
 60

  50
 
40
 


  
30
0

20 40 60 80 100
RGB pixel clock frequency in MHz

/
120
   !"# $ %& '"( ) *+,
$ '-. -- !' '2 3 ) .
Figure 1-15: Typical supply current characteristics



      ! 
   

        


 

   

Figure 1-16: Typical device I-V curve for 3.3V data interface IO under nominal conditions
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Datasheet
1.5 External Circuits
1.5.1 External Termination Resistors
There are no external termination resistors required. For both Upstream and Downstream the dedicated
50 Ohm termination resistors are integrated in the circuit.
1.5.2 External Coupling Capacitors
1.5.2.1 Downstream Coupling Capacitors
The serial data path in downstream direction requires coupling capacitors according Figure 1-17. Recommend-
ed value for all capacitors is 100nF (X7R) for all operation modi.



Figure 1-17: Downstream Coupling Capacitors
1.5.2.2 Upstream Coupling Capacitors
The serial data path in upstream direction requires coupling capacitors according Figure 1-18. Recommended
value for all capacitors is 100nF (X7R). Values depend on cable length and serial upstream data rate in com-
bination with the selected APIX operation mode.



Figure 1-18: Upstream Coupling Capacitors
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Datasheet
2.0 Pin Description
Signal Name
PX[30:1]
SPI_M_SDO/
MII_CLK/
BST5
SPI_M_SDI/
MII_TX_EN
SPI_M_SCK/
MII_RXD1/
BST2
SPI_M_CS0#/
MII_RXD0
SPI_M_CS1#/
MII_RXD3/
SPI_M_CS2#
SPI_S_SDO/
BST3
SPI_S_SDI
SPI_S_SCK
SPI_S_STALL/ MII_STALL
MII_COL/
BST4
SPI_S_CS0#/
MII_TXD0/
SBDWN_DATA0
SPI_S_CS1#/
MII_TXD1/
SBDWN_DATA1
SPI_S_CS2#
Type Description
I e Video Interface pin
SPI_M_SDO: SPI Master Data Output
I/O f MII_CLK: MII Interface Clock Output
BST5: Boot strap option 5 input
I
SPI_M_SDI: SPI Master Data Input
MII_TX_EN: MII Transmit Enable Input
SPI_M_SCK: SPI Master Serial Clock Output
I/O f MII_RXD1: MII Receive Data Output 1
BST2: Boot strap option 2 input
SPI_M_CS0#: SPI Master Chip-select 0 Output (Data Channel
O 0)
MII_RXD0: MII Receive Data Output 0
SPI_M_CS1#: SPI Master Chip-select 1 Output (Data Channel
O 1)
MII_RXD3: MII Receive Data Output 3
O SPI_M_CS2#: SPI Master Chip-select 2 Output (Configuration)
I/O f
SPI_S_SDO: SPI Slave Data Output
BST3: Boot strap option 3 input
I a SPI Slave Data Input
I a SPI Slave Serial Clock Input
SPI_S_STALL:
High: SPI Slave not ready or buffer full
Low: SPI Slave ready to receive data
I/O f
MII_STALL:
High: Nibble IF not ready or buffer full
Low: Nibble IF ready to receive data
MII_COL: MII Collision Detect output
BST4: Boot strap option 4 input
SPI_S_CS0#: SPI Slave Chip-select 0 Input (Data channel 0)
I a MII_TXD0: MII Transmit Data Input 0
SBDWN_DATA0: APIX1 Downstream data input 0
SPI_S_CS0#: SPI Slave Chip-select 1 input (Data channel 1)
I a MII_TXD1: MII Transmit Data input 1
SBDWN_DATA1: APIX1 Downstream data input 1
I a SPI Slave Chip-select 2 input (Configuration)
Table 2-1: Pin description
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Datasheet
Signal Name
SPI_S_RW/
MII_TXD2
SPI_S_MB0/
MII_RXD2/
SBUP_DATA0/
BST1
SPI_S_MB1/
MII_RX_DV/
SBUP_DATA1/
BST6
MII_TXD3
I²C_SCL/
INBOUND_TS
I²C_SD/
OUTBOUND_TS
SD_UP_IN_P
SD_UP_IN_N
SD_DWN_OUT_N
SD_DWN_OUT_P
XTAL_IN
XTAL_OUT
I2S_FRCK
I2S_BCK
I2S_SDATA
I2S_MCLK
GPIO1/SBDWN_CLK
GPIO0/SBUP_CLK
STATUS
RESET#
DS_INAP375T Revision 1.3_B8
Type Description
SPI_S_RW: SPI Slave Read/Write input, only used in single
I SPI mode
MII_TXD2: MII Transmit Data Input 2
SPI_S_MB0: SPI Slave mailbox 0 output
I/O f
MII_RXD2: MII Receive Data Output 2
SBUP_DATA0: APIX1 Upstream data output 0
BST1: Boot strap option 1 input
SPI_S_MB1: SPI slave mailbox 1 output
I/O f
MII_RX_DV: MII Receive Data Valid output
SBUP_DATA1: APIX1 Upstream data output 1
BST6: Boot strap option 6 input
I MII_TXD3: MII Transmit Data Input 3
I/O b
I²C_SCL: I²C Clock output
INBOUND_TS: Inbound Nibble Data Target select output
I/O b
Ic
Ic
Oc
Oc
I²C_SD: I²C Data pin
OUTBOUND_TS: Outbound Nibble Data Target select input
Serial Link, Upstream Serial Link Input from RX
Serial Link, Upstream Serial Link Input from RX
Serial Link, Downstream Serial Link output to RX
Serial Link, Downstream Serial Link output to RX
I 10MHz Oscillator input
O 10MHz Oscillator output
I a I2S Interface, Frame clock input
I a I2S Interface, Bit clock input
I a I2S Interface, Data input
I/O I2S Interface, Master Clock input/output
GPIO1: General purpose I/O
I/O
SBDWN_CLK: Sampling clock output for SBDWN_DATA[1:0]
(APIX1 Mode)
DEBUG Interface : Debug Output Pin1
GPIO0: General purpose I/O
I/O
SBUP_CLK: Sampling clock output for SBUP_DATA[1:0]
(APIX1 Mode)
DEBUG Interface : Debug Output Pin0
O STATUS: Device status output
I d Reset
Table 2-1: Pin description
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Datasheet
Signal Name
Type Description
PLL_VCO_TUNE
DVDD
O reserved, do not connect
Power Digital I/O power supply
AVDD_LVDS_PLL
VDD
Power LVDS PLL power supply
Power Core supply
AVDD_LVDS
AVDD_LD
AVDD
AVDD_VCO
Power LVDS I/O power supply
Power Serial Link I/O Power supply
Power Serial Link core power supply
Power Serial Link VCO Power supply
VDD_XTAL
DVDD_XTAL
Power 10MHz Oscillator core supply
Power 10MHz Oscillator digital supply
GND_XTAL
GND
GND
GND
10MHz Oscillator Ground
Ground
Exposed PAD (EP)
GND must be connected to GND-plane
TEST
I a reserved, pull down external over 100kOhm to GND
Table 2-1: Pin description
a. with internal pull-down
b. n-channel open drain
c. CML interface
d. schmitt trigger input
e. external 100 Ohm termination is required in case of LDI input
f. BST pins require defined level during hardware reset (pull-up or pull-down)
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Datasheet
2.1 Reset
The pin RESET# triggers an asynchronous reset (active low) and can be activated any time. This reset erases
all configuration settings. Please see Table 2-2 for the status of all pins during reset.
Signal Name
Reset State
PX[30:1]
SPI_M_SDO / MII_CLK / BST5
Input
Input
SPI_M_SDI / MII_TX_EN
Input
SPI_M_SCK / MII_RXD1 / BST2
Input
SPI_M_CS0# / MII_RXD0
Output
SPI_M_CS1# / MII_RXD3/
Output
SPI_M_CS2#
Output
SPI_S_SDO / BST3
SPI_S_SDI
SPI_S_SCK
Input
Input
Input
SPI_S_STALL / MII_COL / BST4
Input
SPI_S_CS0# / MII_TXD0 / SBDWN_DATA0
Input
SPI_S_CS1# / MII_TXD1 / SBDWN_DATA1
Input
SPI_S_CS2#
SPI_S_RW / MII_TXD2
SPI_S_MB0 / MII_RXD2 / SBUP_DATA0 / BST1
Input
Input
Input
SPI_S_MB1 / MII_RX_DV / SBUP_DATA1 / BST6
Input
MII_TXD3
Input
I²C_SCL / INBOUND_TS
I²C_SD / OUTBOUND_TS
I2S_FRCK
Tri-State
Tri-State
Input
I2S_BCK
I2S_SDATA
I2S_MCLK
Input
Input
Tri-State
GPIO1 / SBDWN_CLK
Input
GPIO0 / SBUP_CLK
Input
STATUS
Output
Table 2-2: Reset States
Functional State
Input
Output
Input
Output
Output
Output
Output
Output
Input
Input
Output
Input
Input
Input
Input
Output
Output
Input
Tri-State / Output
Tri-State / Input / Output
Input
Input
Input
Tri-State / Input / Output
Input / Output
Input / Output
Output
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Datasheet
3.0 Package Information
3.1 100 Pin LQFP package
3.1.1 Pinout Diagram - LQFP package
!
"
!

  
"
!



 %'



   
   
  
 
   
   
   
   
 !
       
     
 
  
      
Figure 3-1: Pinout diagram - LQFP
* Exposed PAD connect to GND-plane
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Datasheet
3.1.2 Signal Mapping - LQFP package
Pin
Signal
Pin
Signal
LQFP
pin
Signal
1
PX15
27 SPI_S_CS2# 53
2
PX4
28
SPI_S_RW /
MII_TXD2
54
SPI_S_MB0 /
3
PX5
29
MII_RXD2 /
SBUP_DATA0 /
55
BST1
SPI_S_MB1 /
4
PX6
30
MII_RX_DV/
SBDWN_DATA1/
56
BST6
5 PX3 31 MII_TXD3 57
6
PX2
32
I2C_SCL /
INBOUND_TS
58
7
DVDD
33
I2C_SD /
OUTBOUND_TS
59
8 GND 34 GND 60
9
AVDD_LVDS
35
VDD
61
10 PX1 36 VDD 62
SPI_M_SDO /
11 MII_CLK / 37 SD_UP_IN_P 63
BST5
12
SPI_M_SDI /
MII_TX_EN
38 SD_UP_IN_N 64
SPI_M_SCK /
13 MII_PXD1 / 39
BST2
GND
65
14
SPI_M_CS0# /
MII_RXD0
40
GND
66
15
SPI_M_CS1# /
MII_RXD3
41
AVDD_VCO
67
16 GND 42 PLL_VCO_TUNE 68
17 VDD 43 AVDD 69
18 SPI_M_CS2# 44
GND
70
19
SPI_S_SDO /
BST3
45 SD_DWN_OUT_N 71
20 SPI_S_SDI 46 SD_DWN_OUT_P 72
21 SPI_S_SCK 47
AVDD_LD
73
SPI_S_STALL /
22 MII_COL / 48
BST4
GND
74
SPI_S_CS0# /
23 MIITXD0 / 49
SBDWN_DATA0
AVDD_LD
75
24 DVDD 50 AVDD 76
25 GND 51 XTAL_GND 77
SPI_S_CS1# /
26 MII_TXD1 / 52
SBDWN_DATA1
XTAL_IN
78
XTAL_OUT
VDD_XTAL
DVDD_XTAL
I2S_FRCK
I2S_BCK
I2S_SDATA
VDD
GND
I2S_MCLK
GPIO1
GPIO0
STATUS
TEST
RESET#
AVDD_LVDS
GND
DVDD
PX16
PX17
PX21
PX22
PX18
PX19
GND
DVDD
PX28
Table 3-1: Signal Mapping List - LQFP
LQFP
pin
79
80
81
Signal
PX27
PX26
PX25
82 PX30
83 PX29
84 PX24
85 PX23
86 PX20
87 AVDD_LVDS_PLL
88 GND
89 VDD
90 GND
91 PX8
92 PX7
93 PX14
94 PX13
95 PX10
96 PX9
97 PX12
98 PX11
99 DVDD
100 GND
Video Interface
Data Interface
Serial Interface
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Datasheet
Supply Name
VDD
DVDD
AVDD
AVDD_LD
AVDD_LVDS
AVDD_LVDS_PLL
Pins
Supply Name
17, 35, 36, 59, 89
GND
7, 24, 69, 77, 99
43, 50
AVDD_VCO
47, 49
VDD_XTAL
9, 67
DVDD_XTAL
87 XTAL_GND
Table 3-2: Supply Pins - LQFP
Pins
8, 16, 25, 34, 39, 40, 44,
48, 60, 68, 76, 88, 90, 100
41
54
55
51
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