54AC11533 (Texas)
OCTAL D-TYPE TRANSPARENT LATCHES

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8-Latches in a Single Package
3-State Bus-Driving Inverting Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
tEPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
54AC11533, 74AC11533
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS004 – D2957, JULY 1987 – REVISED APRIL 1993
54AC11533 . . . JT PACKAGE
74AC11533 . . . DW OR NT PACKAGE
(TOP VIEW)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
2
3
4
5
6
7
8
9
10
11
12
24 OC
23 1D
22 2D
21 3D
20 4D
19 VCC
18 VCC
17 5D
16 6D
15 7D
14 8D
13 C
description
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the AC11533 are transparent
D-type latches. While the enable (C) is high, the
Q outputs will follow the complements of the (D)
inputs. When the output control OC is taken low,
the Q outputs will be latched. The AC11533 is
functionally equivalent to the AC11373 except for
having inverted outputs.
54AC11533 . . . FK PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
2D 5
25 7D
1D 6
24 8D
OC 7
23 C
NC 8
22 NC
1Q 9
21 8Q
2Q 10
20 7Q
3Q 11
19 6Q
12 13 14 15 16 17 18
A buffered output-control (OC) input can be used
to place the eight outputs in either a normal logic
NC – No internal connection
state (high or low logic levels) or a high-
impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive
provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up
components.
The output control (OC) does not affect the internal operations of the latches. Old data can be retained or new
data can be entered while the outputs are off.
The 54AC11533 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
74AC11533 is characterized for operation from – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1993, Texas Instruments Incorporated
2–1


54AC11533 (Texas)
OCTAL D-TYPE TRANSPARENT LATCHES

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54AC11533, 74AC11533
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS004 – D2957, JULY 1987 – REVISED APRIL 1993
FUNCTION TABLE
(each latch)
INPUTS
OC C
OUTPUT
DQ
L HH L
LHLH
L L X Q0
HXXZ
logic symbol
logic diagram (positive logic)
24
OC
13
C
23
1D
22
2D
21
3D
20
4D
17
5D
16
6D
15
7D
14
8D
EN
C1
1D
1
1Q
2
2Q
3
3Q
4
4Q
9
5Q
10
6Q
11
7Q
12
8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
24
OC
13
C
23
1D
22
2D
21
3D
20
4D
17
5D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
1
1Q
2
2Q
3
3Q
4
4Q
9
5Q
16
6D
C1
1D
10
6Q
15
7D
C1
1D
11
7Q
Pin numbers shown are for the DW, JT, and NT packages.
14
8D
C1
1D
12
8Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–2
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54AC11533 (Texas)
OCTAL D-TYPE TRANSPARENT LATCHES

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recommended operating conditions
VCC
VIH
Supply voltage
High-level input voltage
VIL Low-level input voltage
VI Input voltage
VO Output voltage
IOH High-level output current
IOL
Dt /Dv
TA
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
54AC11533, 74AC11533
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS004 – D2957, JULY 1987 – REVISED APRIL 1993
54AC11533
MIN NOM MAX
3 5 5.5
2.1
3.15
3.85
0.9
1.35
1.65
0 VCC
0 VCC
–4
– 24
– 24
12
24
24
0 10
– 55 125
74AC11533
MIN NOM MAX
3 5 5.5
2.1
3.15
3.85
0.9
1.35
1.65
0 VCC
0 VCC
–4
– 24
– 24
12
24
24
0 10
– 40 85
UNIT
V
V
V
V
V
mA
mA
ns/ V
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
54AC11533
MIN TYP MAX MIN MAX
IOH = – 50 mA
3V
4.5 V
5.5 V
2.9
4.4
5.4
2.9
4.4
5.4
VOH
IOH = – 4 mA
IOH = – 24 mA
IOH = – 50 mA{
IOH = – 75 mA{
IOL = 50 mA
3V
4.5 V
5.5 V
5.5 V
5.5 V
3V
4.5 V
5.5 V
2.58
3.94
4.94
2.4
3.7
4.7
3.85
0.1 0.1
0.1 0.1
0.1 0.1
VOL
IOL = 12 mA
IOL = 24 mA
3V
4.5 V
5.5 V
0.36 0.5
0.36 0.5
0.36 0.5
IOL = 50 mA{
IOL = 75 mA{
5.5 V
5.5 V
1.65
IOZ VO = VCC or GND
5.5 V
± 0.5
± 10
II VI = VCC or GND
5.5 V
± 0.1
±1
ICC
VI = VCC or GND,
IO = 0
5.5 V
8 160
Ci VI = VCC or GND
5V 4
Co VO = VCC or GND
5 V 10
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
74AC11533
MIN MAX
2.9
4.4
5.4
2.48
3.8
4.8
3.85
0.1
0.1
0.1
0.44
0.44
0.44
1.65
±5
±1
80
UNIT
V
V
mA
mA
mA
pF
pF
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2–3


54AC11533 (Texas)
OCTAL D-TYPE TRANSPARENT LATCHES

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54AC11533, 74AC11533
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS004 – D2957, JULY 1987 – REVISED APRIL 1993
timing requirements (see Figure 1)
tw Pulse duration, C high
tsu Setup time, data before C
th Hold time, data after C
VCC
RANGE
3.3 ± 0.3 V
5 ± 0.5 V
3.3 ± 0.3 V
5 ± 0.5 V
3.3 ± 0.3 V
5 ± 0.5 V
TA = 25°C
MIN MAX
5.5
4
4
3.5
2
2
54AC11533
MIN MAX
5.5
4
4
3.5
2
2
74AC11533
MIN MAX
5.5
4
4
3.5
2
2
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
54AC11533 74AC11533
MIN TYP MAX MIN MAX MIN MAX
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
1.5 8.5 12.6 1.5 15.2 1.5 14.3
DQ
1.5 7.5 10.1 1.5
12 1.5 11.3
1.5 10 14.5 1.5 17.6 1.5 16.5
C Any Q
1.5 9.5 12.8 1.5 15.2 1.5 14.3
1.5 9 13.1 1.5 15.7 1.5 14.7
OC
Any Q
1.5 8.5 11.6 1.5 14.1 1.5 13.1
1.5 9.5
12 1.5 13.2 1.5 12.8
OC Any Q
1.5 7.5 10.2 1.5 11.4 1.5
11
UNIT
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
54AC11533 74AC11533
MIN TYP MAX MIN MAX MIN MAX
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
1.5 5.5 8.4 1.5 10.6 1.5 9.8
DQ
1.5 5 7.1 1.5 8.6 1.5 8
1.5 6.5
10 1.5 12.1 1.5 11.3
C Any Q
1.5 6.5 9.1 1.5
11 1.5 10.3
1.5 6.5 9.5 1.5 11.7 1.5 10.8
OC Any Q
1.5 6 8.6 1.5 10.9 1.5 9.7
1.5 8.5 10.7 1.5 11.7 1.5 11.4
OC Any Q
1.5 6 8.2 1.5 9.3 1.5 8.9
UNIT
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd Power dissipation capacitance per latch
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF, f = 1 MHz
TYP UNIT
55
pF
44
2–4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


54AC11533 (Texas)
OCTAL D-TYPE TRANSPARENT LATCHES

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From Output
Under Test
CL = 50 pF
(see Note A)
54AC11533, 74AC11533
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS004 – D2957, JULY 1987 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
500
500
2 × VCC
S1 Open
GND
TEST
tPLH /tPHL
tPLZ /tPZL
tPHZ /tPZH
S1
Open
2 × VCC
GND
LOAD CIRCUIT
Timing Input
(see Note B)
tsu
Data Input
50%
th
50%
50%
VOLTAGE WAVEFORMS
VCC
0V
VCC
0V
Input
(see Note B)
tPHL
Output
50%
50%
VCC
0V
50% VCC
tPLH
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling) tPZL
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
tPZH
50%
50%
tPLZ
50% VCC
tPHZ
20% VCC
50% VCC
80% VCC
VOLTAGE WAVEFORMS
VCC
0V
[ VCC
VOL
VOH
[0V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2–5


54AC11533 (Texas)
OCTAL D-TYPE TRANSPARENT LATCHES

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54AC11533, 74AC11533
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS004 – D2957, JULY 1987 – REVISED APRIL 1993
2–6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


54AC11533 (Texas)
OCTAL D-TYPE TRANSPARENT LATCHES

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