TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
PRODUCT PREVIEW
BYTE-WIDE
SMART 5 FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004S5, 28F008S5, 28F016S5
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
Smart 5 Flash: 5V VCC and 5V or
12V VPP
n High-Performance
4, 8 Mbit: 85 ns Read Access Time
16 Mbit: 95 ns Read Access Time
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Write Lockout during Power
Transitions
n Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
n High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
n Extended Cycling Capability
100,000 Block Erase Cycles
n Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Program and Block Erase
Command User Interface
Status Register
n SRAM-Compatible Write Interface
n ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide Smart 5 FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide Smart 5 FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
June 1997
Order Number: 290597-003


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F004S5, 28F008S5, 28F016S5 may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intel’s Website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION, 1997
*Third-party brands and names are the property of their respective owners
CG-041493


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
CONTENTS
PAGE
1.0 INTRODUCTION .............................................5
1.1 New Features...............................................5
1.2 Product Overview.........................................5
1.3 Pinout and Pin Description ...........................6
2.0 PRINCIPLES OF OPERATION .......................9
2.1 Data Protection ..........................................10
3.0 BUS OPERATION .........................................10
3.1 Read ..........................................................10
3.2 Output Disable ...........................................10
3.3 Standby......................................................10
3.4 Deep Power-Down .....................................10
3.5 Read Identifier Codes Operation ................11
3.6 Write ..........................................................11
4.0 COMMAND DEFINITIONS ............................11
4.1 Read Array Command................................14
4.2 Read Identifier Codes Command ...............14
4.3 Read Status Register Command................14
4.4 Clear Status Register Command................14
4.5 Block Erase Command ..............................14
4.6 Program Command....................................15
4.7 Block Erase Suspend Command................15
4.8 Program Suspend Command .....................16
4.9 Set Block and Master Lock-Bit Commands 16
4.10 Clear Block Lock-Bits Command..............17
5.0 DESIGN CONSIDERATIONS ........................25
5.1 Three-Line Output Control..........................25
5.2 RY/BY# Hardware Detection ......................25
5.3 Power Supply Decoupling ..........................25
5.4 VPP Trace on Printed Circuit Boards...........25
5.5 VCC, VPP, RP# Transitions .........................25
5.6 Power-Up/Down Protection ........................25
PAGE
6.0 ELECTRICAL SPECIFICATIONS..................26
6.1 Absolute Maximum Ratings........................26
6.2 Commercial Temperature Operating
Conditions .................................................26
6.2.1 Capacitance.........................................26
6.2.2 AC Input/Output Test Conditions .........27
6.2.3 Commercial Temperature
DC Characteristics..............................28
6.2.4 Commercial Temperature
AC Characteristics - Read-Only
Operations..........................................30
6.2.5 Commercial Temperature Reset
Operations..........................................31
6.2.6 Commercial Temperature
AC Characteristics - Write Operations 32
6.2.7 Commercial Temperature Block Erase,
Program, and Lock-Bit Configuration
Performance .......................................34
6.3 Extended Temperature Operating
Conditions .................................................35
6.3.1 Extended Temperature
DC Characteristics..............................35
6.3.2 Extended Temperature
AC Characteristics - Read-Only
Operations..........................................35
APPENDIX A. Ordering Information ..........36
APPENDIX B. Additional Information........37
PRODUCT PREVIEW
3


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
Number
-001
-002
-003
REVISION HISTORY
Description
Original version
Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program.
Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead
PSOP to TB = Ext. Temp. 44-Lead PSOP
Updated Ordering Information and table
Correction to table, Section 6.2.3. Under ILO Test Conditions, previously read VIN = VCC
or GND, corrected to VOUT = VCC or GND
Section 6.2.7, modified Program and Block Erase Suspend Latency Times
Updated disclaimer
4 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
1.0 INTRODUCTION
This datasheet contains 4-, 8-, and 16-Mbit Smart 5
FlashFile memory specifications. Section 1
provides a flash memory overview. Sections 2, 3, 4,
and 5 describe the memory organization and
functionality. Section 6 covers electrical
specifications for commercial and extended
temperature product offerings. The byte-wide Smart
5 FlashFile memory family documentation also
includes application notes and design tools which
are referenced in Appendix B.
1.1 New Features
The byte-wide Smart 5 FlashFile memory family
maintains backwards-compatibility with Intel’s
28F008SA. Key enhancements include:
SmartVoltage Technology
Enhanced Suspend Capabilities
In-System Block Locking
They share a compatible status register, software
commands, and pinouts. These similarities enable
a clean upgrade from the 28F008SA to byte-wide
Smart 5 FlashFile products. When upgrading, it is
important to note the following differences:
Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
VPPLK has been lowered from 6.5V to 1.5V to
support low VPP voltages during block erase,
program, and lock-bit configuration operations.
Designs that switch VPP off during read
operations should transition VPP to GND.
To take advantage of SmartVoltage tech-
nology, allow VPP connection to 5V.
For more details see application note AP-625,
28F008SC Compatibility with 28F008SA (order
number 292180).
1.2 Product Overview
The byte-wide Smart 5 FlashFile memory family
provides density upgrades with pinout compatibility
for the 4-, 8-, and 16-Mbit densities. The 28F004S5,
28F008S5, and 28F016S5 are high-performance
memories arranged as 512 Kbyte, 1 Mbyte, and
2 Mbyte of 8 bits. This data is grouped in eight,
sixteen, and thirty-two 64-Kbyte blocks which are
individually erasable, lockable, and unlockable in-
system. Figure 4 illustrates the memory
organization.
SmartVoltage technology enables fast factory
programming and low power designs. Specifically
designed for 5V systems, Smart 5 FlashFile
components support read operations at 5V VCC and
block erase and program operations at 5V and 12V
VPP. The 12V VPP option renders the fastest
program performance which will increase your
factory throughput. With the 5V VPP option, VCC and
VPP can be tied together for a simple 5V design. In
addition to the voltage flexibility, the dedicated VPP
pin gives complete data protection when
VPP VPPLK.
Internal VPP detection circuitry automatically
configures the device for optimized block erase and
program operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within 1 second
(12V VPP), independent of other blocks. Each block
can be independently erased 100,000 times
(1.6 million block erases per device). A block erase
suspend operation allows system software to
suspend block erase to read data from or program
data to any other block.
Data is programmed in byte increments typically
within 6 µs (12V VPP). A program suspend
operation permits system software to read data or
execute code from any other flash memory array
location.
PRODUCT PREVIEW
5


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a block erase, program, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA.
When CE# and RP# pins are at VCC, the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized.
1.3 Pinout and Pin Description
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Package).
Pinouts are shown in Figures 2 and 3.
DQ0 - DQ 7
Output
Buffer
Input
Buffer
4-Mbit: A0 - A18 ,
8-Mbit: A0 - A19 ,
16-Mbit: A0 - A20
Input
Buffer
Address
Latch
Address
Counter
Y
Decoder
X
Decoder
Identifier
Register
Status
Register
Data
Comparator
Y Gating
4-Mbit: Eight
8-Mbit: Sixteen
16-Mbit: Thirty-Two
64-Kbyte Blocks
Command
Register
I/O Logic
VCC
CE#
WE#
OE#
RP#
Write State
Machine
Program/Erase
Voltage Switch
RY/BY#
VPP
VCC
GND
Figure 1. Block Diagram
6 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
Table 1. Pin Descriptions
Sym
Type
Name and Function
A0–A20
INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
4 Mbit A0–A18
8 Mbit A0–A19
16 Mbit A0–A20
DQ0–DQ7
INPUT/ DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
OUTPUT outputs data during memory array, status register, and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
CE#
INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption to
standby levels.
RP#
INPUT
RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during power transitions, puts the device in deep
power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP# at VHH enables setting of the master lock-bit and enables configuration of block
lock-bits when the master lock-bit is set. RP# = VHH overrides block lock-bits,
thereby enabling block erase and program operations to locked memory blocks.
Block erase, program, or lock-bit configuration with VIH < RP# < VHH produce
spurious results and should not be attempted.
OE#
INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE#
INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
RY/BY#
OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, program, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase or
program is suspended, or the device is in deep power-down mode. RY/BY# is
always active.
VPP SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
For erasing array blocks, programming data, or configuring lock-bits.
Smart 5 Flash 5V and 12V VPP
With VPP VPPLK, memory contents cannot be altered. Block erase, program, and
lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious
results and should not be attempted.
VCC SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device
for optimized read performance. Do not float any power pins.
Smart 5 Flash 5V VCC
With VCC VLKO, all write attempts to the flash memory are inhibited. Device
operations at invalid VCC voltages (see DC Characteristics) produce spurious
results and should not be attempted.
GND
SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
PRODUCT PREVIEW
7


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
VPP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
VPP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
NC
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
VPP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28F016S5
28F008S5
28F004S5
40-LEAD TSOP
STANDARD PINOUT
10 mm x 20 mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Figure 2. TSOP 40-Lead Pinout
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
GND
GND
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ 4
VCC
GND
GND
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
GND
GND
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
VPP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
GND
GND
VPP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
GND
GND
V PP
RP#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
GND
GND
28F016S5
28F008S5
28F004S5
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 44-LEAD PSOP 35
11 13.3 mm x 28.2 mm 34
12
TOP VIEW
33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
VCC
CE#
A12
A13
A14
A15
A16
A17
A18
NC
NC
NC
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
VCC
CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
VCC
CE#
A12
A13
A14
A15
A16
A17
A18
A19
A20
NC
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
Figure 3. PSOP 44-Lead Pinout
8 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
2.0 PRINCIPLES OF OPERATION
The byte-wide Smart 5 FlashFile memories include
an on-chip WSM to manage block erase, program,
and lock-bit configuration functions. It allows for:
100% TTL-level control inputs, fixed power supplies
during block erasure, program, and lock-bit
configuration, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation of
external memory control pins allow array read,
standby, and output disable operations.
Status register and identifier codes can be
accessed through the CUI independent of the VPP
voltage. High voltage on VPP enables successful
block erasure, program, and lock-bit configuration.
All functions associated with altering memory
contents—block erase, program, lock-bit
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.
Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM that controls block erase,
program, and lock-bit configuration operations. The
internal algorithms are regulated by the WSM,
including pulse repetition, internal verification, and
margining of data. Addresses and data are
internally latched during write cycles. Writing the
appropriate command outputs array data, accesses
the identifier codes, or outputs status register data.
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read data
from or program data to any other block. Program
suspend allows system software to suspend a
program to read data from any other flash memory
array location.
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
16-Mbit
15
14
13
12
11
10
9
8-Mbit
8
7
6
5
4
4-Mbit
3
2
1
0
Figure 4. Memory Map
PRODUCT PREVIEW
9


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
2.1 Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when memory block
erases, programs, or lock-bit configurations are
required) or hardwired to VPPH1/2. The device
accommodates either design practice and
encourages optimization of the processor-memory
interface.
When VPP VPPLK, memory contents cannot be
altered. When high voltage is applied to VPP, the
two-step block erase, program, or lock-bit
configuration command sequences provides pro-
tection from unwanted operations. All write
functions are disabled when VCC voltage is below
the write lockout voltage VLKO or when RP# is at
VIL. The device’s block locking capability provides
additional protection from inadvertent code or data
alteration by gating erase and program operations.
3.0 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1 Read
Block information, identifier codes, or status register
can be read independent of the VPP voltage. RP#
can be at either VIH or VHH.
The first task is to write the appropriate read-mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-
down mode, the device automatically resets to read
array mode. Four control pins dictate the data flow
in and out of the component: CE#, OE#, WE#, and
RP#. CE# and OE# must be driven active to obtain
data at the outputs. CE# is the device selection
control, and when active enables the selected
memory device. OE# is the data output (DQ0–DQ7)
control and when active drives the selected
memory data onto the I/O bus. WE# must be at VIH
and RP# must be at VIH or VHH. Figure 15
illustrates a read cycle.
10
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ7 are
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0–DQ7 outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase, program, or
lock-bit configuration, the device continues
functioning and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be held
low for time tPLPH. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval,
normal operation is restored. The CUI resets to
read array mode, and the status register is set to
80H.
During block erase, program, or lock-bit
configuration, RP#-low will abort the operation.
RY/BY# remains low until the reset operation is
complete. Memory contents being altered are no
longer valid; the data may be partially erased or
written. Time tPHWL is required after RP# goes to
logic-high (VIH) before another command can be
written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
program, or lock-bit configuration modes. If a CPU
reset occurs with no flash memory reset, proper
CPU initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
1FFFFF
Block 31
Reserved for
Future Implementation
1F0002
1F0000
Block 31 Lock Configuration
Reserved for
Future Implementation
(Blocks 16 through 30)
0FFFFF
Block 15
Reserved for
Future Implementation
0F0002
0F0000
Block 15 Lock Configuration
Reserved for
Future Implementation
07FFFF
(Blocks 8 through 14)
Block 7
Reserved for
Future Implementation
16-Mbit
070002
070000
01FFFF
Block 7 Lock Configuration
Reserved for
Future Implementation
(Blocks 2 through 14)
8-Mbit
Block 1
Reserved for
Future Implementation
4-Mbit
010002
010000
00FFFF
000003
000002
000001
000000
Block 1 Lock Configuration
Reserved for
Future Implementation
Block 0
Reserved For
Future Implementation
Master Lock Configuration
Block 0 Lock Configuration
Device Code
Manufacturer Code
3.5 Read Identifier Codes
Operation
The read identifier codes operation outputs the
manufacturer code, device code, block lock
configuration codes for each block, and master lock
configuration code (see Figure 5). Using the
manufacturer and device codes, the system
software can automatically match the device with its
proper algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
3.6 Write
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active
and OE# = VIH. The address and data needed to
execute a command are latched on the rising edge
of WE# or CE# (whichever goes high first).
Standard microprocessor write timings are used.
Figure 17 illustrates a write operation.
4.0 COMMAND DEFINITIONS
When the VPP voltage VPPLK, read operations
from the status register, identifier codes, or blocks
are enabled. Placing VPPH1/2 on VPP enables
successful block erase, program, and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
Figure 5. Device Identifier Code Memory Map
PRODUCT PREVIEW
11


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
Table 2. Bus Operations
Mode
Notes RP# CE# OE# WE# Address VPP DQ0–7 RY/BY#
Read
1,2,3 VIH or VIL VIL VIH
VHH
X
X DOUT
X
Output Disable
3 VIH or VIL VIH VIH
VHH
X
X High Z
X
Standby
3 VIH or VIH
X
X
X
X High Z
X
VHH
Deep Power-Down 4 VIL X X X X X High Z VOH
Read Identifier Codes
VIH or VIL VIL VIH
See
X Note 5 VOH
VHH Figure 5
Write
3,6,7 VIH or VIL VIH VIL
VHH
X
X DIN
X
NOTES:
1. Refer to DC Characteristics. When VPP VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and
VPPH1/2 voltages.
3. RY/BY# is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH
when the WSM is not busy, in block erase suspend mode (with program inactive), program suspend mode, or deep power-
down mode.
4. RP# at GND ± 0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPP = VPPH1/2 and
VCC = VCC1/2 (see Section 6.2 for operating conditions).
7. Refer to Table 3 for valid DIN during a write operation.
12 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
Table 3. Command Definitions(9)
Bus Cycles
First Bus Cycle
Second Bus Cycle
Command
Req’d. Notes Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)
Read Array/Reset
Read Identifier Codes
Read Status Register
1 Write X FFH
2
4 Write X 90H Read IA
ID
2 Write X 70H Read X SRD
Clear Status Register
1
Write X 50H
Block Erase
Program
2 5 Write BA 20H Write BA D0H
2 5,6 Write PA 40H Write PA PD
or
10H
Block Erase and Program
Suspend
Block Erase and Program
Resume
1 5 Write X B0H
1 5 Write X D0H
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
2 7 Write BA 60H Write BA 01H
2 7 Write X 60H Write X F1H
2 8 Write X 60H Write X D0H
NOTES:
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
IA = Identifier Code Address: see Figure 5.
BA = Address within the block being erased or locked.
PA = Address of memory location to be programmed.
3. SRD = Data read from status register. See Table 6 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at VHH to enable block erase or program operations. Attempts to issue a block erase or
program to a locked block while RP# is VIH will fail.
6. Either 40H or 10H are recognized by the WSM as the program setup.
7. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the
master lock-bit is not set, a block lock-bit can be set while RP# is VIH.
8. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH.
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
PRODUCT PREVIEW
13


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
4.1 Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, program or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or
Program Suspend command. The Read Array
command functions independently of the VPP
voltage and RP# can be VIH or VHH.
4.2 Read Identifier Codes
Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Figure 5 retrieve the manufacturer, device, block
lock configuration and master lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage and RP# can be
VIH or VHH. Following the Read Identifier Codes
command, the subsequent information can be read.
Table 4. Identifier Codes
Code
Address Data
Manufacturer Code
000000
89
4-Mbit 000001
A7
Device Code
8-Mbit 000001
A6
16-Mbit 000001 AA
Block Lock Configuration XX0002(1)
Block Is Unlocked
DQ0 = 0
Block Is Locked
DQ0 = 1
Reserved for Future Use
DQ1–7
Master Lock Configuration 000003
Device Is Unlocked
DQ0 = 0
Device Is Locked
DQ0 = 1
Reserved for Future Use
DQ1–7
NOTE:
1. X selects the specific block lock configuration code to
be read. See Figure 5 for the device identifier code
memory map.
14
4.3 Read Status Register
Command
The status register may be read to determine when
a block erase, program, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs first. OE# or CE# must
toggle to VIH to update the status register latch. The
Read Status Register command functions
independently of the VPP voltage. RP# can be VIH
or VHH.
4.4 Clear Status Register
Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP# can
be VIH or VHH. This command is not functional
during block erase or program suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
written first, followed by a block erase confirm. This
command sequence requires appropriate se-
quencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register
data when read (see Figure 6). The CPU can detect
block erase completion by analyzing the RY/BY#
pin or status register bit SR.7.
PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to “1.” Also,
reliable block erasure can only occur when
VCC = VCC1/2 and VPP = VPPH1/2. In the absence of
this high voltage, block contents are protected
against erasure. If block erase is attempted while
VPP VPPLK, SR.3 and SR.5 will be set to “1.”
Successful block erase requires that the
corresponding block lock-bit be cleared or, if set,
that RP# = VHH. If block erase is attempted when
the corresponding block lock-bit is set and
RP# = VIH, the block erase will fail, and SR.1 and
SR.5 will be set to “1.” Block erase operations with
VIH < RP# < VHH produce spurious results and
should not be attempted.
4.6 Program Command
Program is executed by a two-cycle command
sequence. Program setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the program and write verify algorithms
internally. After the program sequence is written,
the device automatically outputs status register
data when read (see Figure 7). The CPU can detect
the completion of the program event by analyzing
the RY/BY# pin or status register bit SR.7.
When program is complete, status register bit SR.4
should be checked. If program error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
successfully program to “0”s. The CUI remains in
read status register mode until it receives another
command.
Reliable programs only occurs when VCC = VCC1/2
and VPP = VPPH1/2. In the absence of this high
voltage, memory contents are protected against
programs. If program is attempted while VPP
VPPLK, the operation will fail, and status register bits
SR.3 and SR.5 will be set to “1.”
PRODUCT PREVIEW
Successful program also requires that the
corresponding block lock-bit be cleared or, if set,
that RP# = VHH. If program is attempted when the
corresponding block lock-bit is set and RP# = VIH,
program will fail, and SR.1 and SR.4 will be set to
“1.” Program operations with VIH < RP# < VHH
produce spurious results and should not be
attempted.
4.7 Block Erase Suspend
Command
The Block Erase Suspend command allows
block-erase interruption to read data from or
program data to another block of memory. Once the
block erase process starts, writing the Block Erase
Suspend command requests that the WSM
suspend the block erase sequence at a
predetermined point in the algorithm. The device
outputs status register data when read after the
Block Erase Suspend command is written. Polling
status register bits SR.7 and SR.6 can determine
when the block erase operation has been
suspended (both will be set to “1”). RY/BY# will also
transition to VOH. Specification tWHRH2 defines the
block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.8), a program operation
can also be suspended. During a program operation
with block erase suspended, status register bit
SR.7 will return to “0” and the RY/BY# output will
transition to VOL. However, SR.6 will remain “1” to
indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to VOL. After the Erase
Resume command is written, the device
automatically outputs status register data when
read (see Figure 8). VPP must remain at VPPH1/2
(the same VPP level used for block erase) while
block erase is suspended. RP# must also remain at
VIH or VHH (the same RP# level used for block
erase). Block erase cannot resume until program
operations initiated during block erase suspend
have completed.
15


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
4.8 Program Suspend Command
The Program Suspend command allows program
interruption to read data in other flash memory
locations. Once the program process starts, writing
the Program Suspend command requests that the
WSM suspend the program sequence at a
predetermined point in the algorithm. The device
continues to output status register data when read
after the Program Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the program operation has been
suspended (both will be set to “1”). RY/BY# will also
transition to VOH. Specification tWHRH1 defines the
program suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
program is suspended are Read Status Register
and Program Resume. After Program Resume
command is written to the flash memory, the WSM
will continue the program process. Status register
bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to VOL. After the Program
Resume command is written, the device
automatically outputs status register data when
read (see Figure 9). VPP must remain at VPPH1/2
(the same VPP level used for program) while in
program suspend mode. RP# must also remain at
VIH or VHH (the same RP# level used for program).
4.9 Set Block and Master Lock-Bit
Commands
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program
and erase operations while the master lock-bit
gates block-lock bit modification. With the master
lock-bit not set, individual block lock-bits can be set
using the Set Block Lock-Bit command. The Set
Master Lock-Bit command, in conjunction with
RP# = VHH, sets the master lock-bit. After the
master lock-bit is set, subsequent setting of block
lock-bits requires both the Set Block Lock-Bit
command and VHH on the RP# pin. See Table 5 for
a summary of hardware and software write
protection options.
Set block lock-bit and master lock-bit are initiated
using two-cycle command sequence. The set block
or master lock-bit setup along with appropriate
block or device address is written followed by either
the set block lock-bit confirm (and an address within
the block to be locked) or the set master lock-bit
confirm (and any device address). The WSM then
controls the set lock-bit algorithm. After the
sequence is written, the device automatically
outputs status register data when read (see
Figure 10). The CPU can detect the completion of
the set lock-bit event by analyzing the RY/BY# pin
output or status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of setup followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to “1.” Also, reliable operations
occur only when VCC = VCC1/2 and VPP = VPPH1/2. In
the absence of this high voltage, lock-bit contents
are protected against alteration.
A successful set block lock-bit operation requires
that the master lock-bit be cleared or, if the master
lock-bit is set, that RP# = VHH. If it is attempted with
the master lock-bit set and RP# = VIH, the operation
will fail, and SR.1 and SR.4 will be set to “1.” A
successful set master lock-bit operation requires
that RP# = VHH. If it is attempted with RP# = VIH,
the operation will fail, and SR.1 and SR.4 will be set
to “1.” Set block and master lock-bit operations with
VIH < RP# < VHH produce spurious results and
should not be attempted.
16 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
4.10 Clear Block Lock-Bits
Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits
requires both the Clear Block Lock-Bits command
and VHH on the RP# pin. See Table 5 for a
summary of hardware and software write protection
options.
Clear block lock-bits operation is initiated using a
two-cycle command sequence. A clear block
lock-bits setup is written first. Then, the device
automatically outputs status register data when
read (see Figure 11). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block
Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a
reliable clear block lock-bits operation can only
occur when VCC = VCC1/2 and VPP = VPPH1/2. If a
clear block lock-bits operation is attempted while
VPP VPPLK, SR.3 and SR.5 will be set to “1.” In the
absence of this high voltage, the block lock-bits
content are protected against alteration. A suc-
cessful clear block lock-bits operation requires that
the master lock-bit is not set or, if the master lock-
bit is set, that RP# = VHH. If it is attempted with the
master lock-bit set and RP# = VIH, SR.1 and SR.5
will be set to “1” and the operation will fail. A clear
block lock-bits operation with VIH < RP# < VHH
produce spurious results and should not be
attempted.
If a clear block lock-bits operation is aborted due to
VPP or VCC transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-
bits is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
Operation
Block Erase or
Program
Set Block
Lock-Bit
Set Master
Lock-Bit
Clear Block
Lock-Bits
Table 5. Write Protection Alternatives
Master Block
Lock-Bit Lock-Bit
RP#
Effect
0 VIH or VHH Block Erase and Program Enabled
X1
VIH Block is Locked. Block Erase and Program Disabled
VHH Block Lock-Bit Override. Block Erase and Program
Enabled
0 X VIH or VHH Set Block Lock-Bit Enabled
1X
VIH Master Lock-Bit is Set. Set Block Lock-Bit Disabled
VHH Master Lock-Bit Override. Set Block Lock-Bit
Enabled
XX
VIH Set Master Lock-Bit Disabled
VHH Set Master Lock-Bit Enabled
0 X VIH or VHH Clear Block Lock-Bits Enabled
1X
VIH Master Lock-Bit is Set. Clear Block Lock-Bits
Disabled
VHH Master Lock-Bit Override. Clear Block Lock-Bits
Enabled
PRODUCT PREVIEW
17


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
WSMS
ESS
Table 6. Status Register Definition
ECLBS
PSLBS
VPPS
PSS
DPS
R
76543210
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
Check RY/BY# or SR.7 to determine block erase,
program, or lock-bit configuration completion.
SR.6–0 are invalid while SR.7 = “0.”
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITS
STATUS
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
If both SR.5 and SR.4 are “1”s after a block erase or
lock-bit configuration attempt, an improper
command sequence was entered.
SR.4 = PROGRAM AND SET LOCK-BIT
STATUS
1 = Error in Program or Set Master/Block
Lock-Bit
0 = Successful Program or Set Master/Block
Lock-Bit
SR.3 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.3 does not provide a continuous indication of
VPP level. The WSM interrogates and indicates the
VPP level only after a block erase, program, or lock-
bit configuration operation. SR.3 is not guaranteed
to reports accurate feedback only when VPP
VPPH1/2.
SR.2 = PROGRAM SUSPEND STATUS
1 = Program Suspended
0 = Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or
RP# Lock Detected, Operation Abort
0 = Unlock
SR.1 does not provide a continuous indication of
master and block lock-bit values. The WSM
interrogates the master lock-bit, block lock-bit, and
RP# only after a block erase, program, or lock-bit
configuration operation. It informs the system,
depending on the attempted operation, if the block
lock-bit is set, master lock-bit is set, and/or
RP# VHH.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
SR.0 is reserved for future use and should be
masked out when polling the status register.
18 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read Status
Register
SR.7 =
0
1
Full Status
Check if Desired
Bus
Operation
Write
Command
Erase Setup
Write
Erase
Confirm
Comments
Data = 20H
Addr = Within Block to be Erased
Data = D0H
Addr = Within Block to be Erased
Read
Status Register Data
Suspend Block
Erase Loop
No
Suspend
Block Erase
Yes
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase, or after a
sequence of block erasures.
Write FFH after the last operation to place device in read array mode.
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
0
SR.1 =
1
0
SR.4,5 =
1
0
SR.5 =
0
1
Block Erase
Successful
VPP Range Error
Device Protect Error
Command Sequence
Error
Block Erase
Error
Bus
Operation
Standby
Standby
Standby
Standby
Command
Comments
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
RP# = VIH, Block Lock-Bit Is Set
Only required for systems
implementing lock-bit configuration
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.5
1 = Block Erase Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Figure 6. Automated Block Erase Flowchart
PRODUCT PREVIEW
19


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
Start
Write 40H,
Address
Write Byte
Data and Address
Read
Status Register
SR.7 =
0
1
Full Status
Check if Desired
Program Complete
Bus
Operation
Write
Write
Command
Comments
Setup
Program
Data = 40H
Addr = Location to Be Programmed
Program
Data = Data to Be Programmed
Addr = Location to Be Programmed
Read
Status Register Data
Suspend
Program Loop
No
Suspend
Program
Yes
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent byte writes.
SR full status check can be done after each program, or after a
sequence of program operations.
Write FFH after the last program operation to reset device to
read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
0
SR.1 =
1
0
SR.4 =
0
1
VPP Range Error
Device Protect Error
Program Error
Program Successful
Bus
Operation
Command
Comments
Standby
Standby
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
RP# = V IH , Block Lock-Bit Is Set
Only required for systems
implementing lock-bit configuration
Standby
Check SR.4
1 = Program Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Figure 7. Automated Program Flowchart
20 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
Start
Write B0H
Read
Status Register
SR.7 =
0
1
SR.6 =
0
Block Erase Completed
1
Read
Read or
Program
?
Read Array
Data
No
Done?
Program
Program
Loop
Yes
Write D0H
Write FFH
Bus
Operation
Write
Read
Standby
Standby
Write
Command
Comments
Erase
Suspend
Erase
Resume
Data = B0H
Addr = X
Status Register Data
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
Data = D0H
Addr = X
Block Erase Resumed
Read Array Data
Figure 8. Block Erase Suspend/Resume Flowchart
PRODUCT PREVIEW
21


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
Start
Write B0H
Read
Status Register
SR.7 =
0
1
SR.2 =
0
1
Write FFH
Program Completed
Read Array Data
Done
Reading
No
Yes
Write D0H
Write FFH
Bus
Operation
Write
Read
Standby
Standby
Write
Read
Write
Command
Comments
Program
Suspend
Read Array
Program
Resume
Data = B0H
Addr = X
Status Register Data
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.2
1 =Program Suspended
0 = Program Completed
Data = FFH
Addr = X
Read array locations other
than that being data written.
Data = D0H
Addr = X
Program Resumed
Read Array Data
Figure 9. Program Suspend/Resume Flowchart
22 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Read Status
Register
SR.7 =
0
1
Full Status
Check if Desired
Set Lock-Bit Complete
Bus
Operation
Write
Write
Read
Command
Comments
Set
Block/Master
Lock-Bit Setup
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Set
Block or Master
Lock-Bit Confirm
Data = 01H (Block),
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
0
SR.1 =
1
0
SR.4,5 =
1
0
SR.4 =
0
1
VPP Range Error
Device Protect Error
Command Sequence
Error
Set Lock-Bit Error
Set Lock-Bit Successful
Bus
Operation
Command
Comments
Standby
Standby
Standby
Standby
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
RP# = VIH,
(Set Master Lock-Bit Operation)
RP# = VHH, Master Lock-Bit Is Set
(Set Block Lock-Bit Operation)
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.4
1 = Set Lock-Bit Reset Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set before
full status is checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Figure 10. Set Block and Master Lock-Bit Flowchart
PRODUCT PREVIEW
23


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
Start
Write 60H
Write D0H
Read Status Register
SR.7 =
0
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
Bus
Operation
Command
Comments
Write
Write
Read
Clear Block
Lock-Bits Setup
Data = 60H
Addr = X
Clear Block
Lock-Bits Confirm
Data = D0H
Addr = X
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write FFH after the clear block lock-bits operation to place device in
read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
0
SR.1 =
1
0
1
SR.4,5 =
0
SR.5 =
0
1
Clear Block Lock-Bits
Successful
VPP Range Error
Device Protect Error
Command Sequence
Error
Clear Block Lock-Bits
Error
Bus
Operation
Standby
Standby
Standby
Standby
Command
Comments
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
RP# = VIH,
Master Lock-Bit Is Set
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.5
1 = Clear Block Lock Bits Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Figure 11. Clear Block Lock-Bits Flowchart
24 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
5.0 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
Intel provides three control inputs to accommodate
multiple memory connections: CE#, OE#, and RP#.
Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Data bus contention avoidance.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while de-
selected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 RY/BY# Hardware Detection
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, program
and lock-bit configuration completion. This output
can be directly connected to an interrupt input of
the system CPU. RY/BY# transitions low when the
WSM is busy and returns to VOH when it is finished
executing the internal algorithm. During suspend
and deep power-down modes, RY/BY# remains at
VOH.
5.3 Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues: standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Two-line control and proper
decoupling capacitor selection will suppress
transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its
VCC and GND and between its VPP and GND.
These high-frequency, low-inductance capacitors
should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed at the array’s
power supply connection between VCC and GND.
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
PRODUCT PREVIEW
5.4 VPP Trace on Printed Circuit
Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the VPP power supply
trace. The VPP pin supplies the memory cell current
for byte writing and block erasing. Use similar trace
widths and layout considerations given to the VCC
power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
overshoots.
5.5 VCC, VPP, RP# Transitions
Block erase, program and lock-bit configuration are
not guaranteed if VPP or VCC fall outside of a valid
voltage range (VCC1/2 and VPPH1/2) or
RP# VIH or VHH. If VPP error is detected, status
register bit SR.3 is set to “1” along with SR.4 or
SR.5, depending on the attempted operation. If RP#
transitions to VIL during block erase, program, or
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-
down. The aborted operation may leave data
partially altered. Therefore, the command sequence
must be repeated after normal operation is
restored.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit
configuration during power transitions. Upon power-
up, the device is indifferent as to which power
supply (VPP or VCC) powers-up first. Internal
circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CE# must be low for a
command write, driving either input signal to VIH will
inhibit writes. The CUI’s two-step command
sequence architecture provides an added level of
protection against data alteration.
In-system block lock and unlock renders additional
protection during power-up by prohibiting block
erase and program operations. The device is
disabled while RP# = VIL regardless of its control
inputs state.
25


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
6.0 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Temperature under Bias .................–10°C to +80°C
Storage Temperature....................–65°C to +125°C
Voltage On Any Pin
(except VPP, and RP#)............–2.0V to +7.0V(2)
VPP Voltage ............................. –2.0V to +14.0V(1,2)
RP# Voltage .......................... –2.0V to +14.0V(1,2,4)
Output Short Circuit Current .................... 100 mA(3)
NOTICE: This datasheet contains information on products
in the design phase of development. Do not finalize a
design with this information. Revised information will be
published when the product is available. Verify with your
local Intel Sales office that you have the latest datasheet
before finalizing a design.
*WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” may affect device
reliability.
NOTES:
1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5V on input/output pins and –0.2V on VCC, RP#,
and VPP pins. During transitions, this level may undershoot to –2.0V for periods <20 ns. Maximum DC voltage on
input/output pins and VCC is VCC +0.5V which, during transitions, may overshoot to VCC +2.0V for periods <20 ns.
2. Maximum DC voltage on VPP and RP# may overshoot to +14.0V for periods <20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. RP# voltage is normally at VIL or VIH. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours.
6.2 Commercial Temperature Operating Conditions
Symbol
Commercial Temperature and VCC Operating Conditions
Parameter
Notes Min Max Unit
Test Condition
TA Operating Temperature
0 +70 °C Ambient Temperature
VCC1
VCC Supply Voltage (5V ± 5%)
4.75 5.25
V
VCC2
VCC Supply Voltage (5V ± 10%)
4.50 5.50
V
6.2.1
CAPACITANCE (1)
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
NOTE:
1. Sampled, not 100% tested.
TA = +25°C, f = 1 MHz
Typ Max
68
8 12
Unit
pF
pF
Condition
VIN = 0.0V
VOUT = 0.0V
26 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
6.2.2
AC INPUT/OUTPUT TEST CONDITIONS
3.0
INPUT
1.5
TEST POINTS
1.5 OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 12. Transient Input/Output Reference Waveform for VCC = 5.0V ± 5%
(High Speed Testing Configuration)
2.4 2.0
INPUT
TEST POINTS
2.0
OUTPUT
0.8
0.45
0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for VCC = 5.0V ± 10%
(Standard Testing Configuration)
DEVICE
UNDER
TEST
1.3V
1N914
RL = 3.3 K
OUT
CL
Test Configuration Capacitance Loading Value
Test Configuration
CL (pF)
VCC = 5.0V ± 5%
30
VCC = 5.0V ± 10%
100
NOTE:
CL includes Jig Capacitance
Figure 14. Transient Equivalent Testing
Load Circuit
PRODUCT PREVIEW
27


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
6.2.3
COMMERCIAL TEMPERATURE DC CHARACTERISTICS
Commercial Temperature DC Characteristics for
4-, 8-, and 16-Mbit Smart 5 FlashFile™ Memories
Sym
Parameter
5.0V VCC
Notes Typ Max Unit
Test
Conditions
ILI Input Load Current
1
±1 µA VCC = VCC Max, VIN = VCC or GND
ILO Output Leakage Current
1
ICCS VCC Standby Current
1,3,6 25
±10 µA VCC = VCC Max, VOUT = VCC or GND
100 µA CMOS Inputs
VCC = VCC Max
CE# = RP# = VCC ± 0.2V
0.4
ICCD
ICCR
VCC Deep Power-Down
Current
VCC Read Current
1
1,5,6 17
20
ICCW VCC Program/Set
Lock-Bit Current
1,7
2 mA TTL Inputs
VCC = VCC Max, CE# = RP# = VIH
10 µA RP# = GND ± 0.2V
IOUT (RY/BY#) = 0 mA
35 mA CMOS Inputs
VCC = VCC Max, CE# = GND
f = 8 MHz, IOUT = 0 mA
50 mA TTL Inputs
VCC = VCC Max, CE# = GND
f = 8 MHz, IOUT = 0 mA
35 mA VPP = 5.0V ± 10%
30 mA VPP = 12.0V ± 5%
ICCE VCC Block Erase/Clear
Block Lock-Bits Current
1,7
30 mA VPP = 5.0V ± 10%
25 mA VPP = 12.0V ± 5%
ICCWS VCC Program/Block
1,2 1
ICCES Erase Suspend Current
10 mA CE# = VIH
IPPS VPP Standby Current
1 ± 2 ± 15 µA VPP VCC
IPPR VPP Read Current
1 10 200 µA VPP > VCC
IPPD VPP Deep Power-Down
Current
1 0.1 5 µA RP# = GND ± 0.2V
IPPW
VPP Program or
Set Lock-Bit Current
1,7
40 mA VPP = 5.0V ± 10%
15 mA VPP = 12.0V ± 5%
IPPE VPP Block Erase or Clear 1,7
Block Lock-Bits Current
20 mA VPP = 5.0V ± 10%
15 mA VPP = 12.0V ± 5%
IPPWS VPP Program or Block
IPPES Erase Suspend Current
1 10 200 µA VPP = VPPH1/2
28 PRODUCT PREVIEW


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
Commercial Temperature DC Characteristics for
4-, 8-, and 16-Mbit Smart 5 FlashFile™ Memories (Continued)
Sym
Parameter
5.0V VCC
Notes Min Max Unit
Test
Conditions
VIL Input Low Voltage
VIH Input High Voltage
7 –0.5 0.8 V
7 2.0 VCC V
+ 0.5
VOL Output Low Voltage
VOH1 Output High Voltage
(TTL)
VOH2 Output High Voltage
(CMOS)
VPPLK VPP Lockout Voltage
VPPH1 VPP Voltage
VPPH2 VPP Voltage
VLKO VCC Lockout Voltage
VHH RP# Unlock Voltage
3,7 0.45 V VCC = VCC Min
IOL = 5.8 mA
3,7 2.4
V VCC = VCC Min
IOH = –2.5 mA
3,7 0.85
VCC
V VCC = VCC Min
IOH = –2.5 mA
VCC
–0.4
V VCC = VCC Min
IOH = –100 µA
4,7 1.5 V
4.5 5.5 V
11.4 12.6 V
2.0 V
8,9 11.4 12.6 V Set Master Lock-Bit
Override Lock-Bit
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25°C. These currents are
valid for all product versions (packages and speeds).
2. ICCWS and ICCES are specified with the device de-selected. If read or written while in erase suspend mode, the device’s
current is the sum of ICCWS or ICCES and ICCR or ICCW.
3. Includes RY/BY#.
4. Block erases, programs, and lock-bit configurations are inhibited when VPP VPPLK, and not guaranteed in the range
between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), and above VPPH2 (max).
5. Automatic Power Savings (APS) reduces typical ICCR to 1 mA in static operation.
6. CMOS inputs are either VCC ± 0.2V or GND ± 0.2V. TTL inputs are either VIL or VIH.
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the
master lock-bit is set and RP# = VIH. Block erases and programs are inhibited when the corresponding block-lock bit is set
and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
attempted with VIH < RP# < VHH.
9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
PRODUCT PREVIEW
29


TB28F004S5 (Intel)
SMART 5 FlashFile MEMORY

No Preview Available !

Click to Download PDF File for PC

BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
6.2.4
COMMERCIAL TEMPERATURE AC CHARACTERISTICS - READ-ONLY OPERATIONS(1)
Commercial Temperature Read-Only Operations for
4-, 8-, and 16-Mbit Smart 5 FlashFile™ Memories at TA = 0°C to +70°C
5V ± 5% VCC –85/–95(5)
Versions(4)
5V ± 10% VCC
–90/–100(6)
–120(6)
# Sym
Parameter
Notes Min Max Min Max Min Max Unit
R1 tAVAV Read Cycle Time
4, 8 Mbit
85
90 120 ns
16 Mbit
95 100 120 ns
R2 tAVQV Address to Output 4, 8 Mbit
85 90 120 ns
Delay
16 Mbit
95 100 120 ns
R3 tELQV CE# to Output Delay 4, 8 Mbit 2 85 90 120 ns
16 Mbit
2
95 100 120 ns
R4 tGLQV OE# to Output Delay
2 40 45 50 ns
R5 tPHQV RP# High to Output Delay
400 400 400 ns
R6 tELQX CE# to Output in Low Z 3 0 0 0 ns
R7 tGLQX OE# to Output in Low Z 3 0 0 0 ns
R8 tEHQZ CE# High to Output in High Z
3
55
55
55 ns
R9 tGHQZ OE# High to Output in High Z
3
10
10
15 ns
R10 tOH Output Hold from Address, CE# 3 0 0 0 ns
or OE# Change, Whichever
Occurs First
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, not 100% tested.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed
Configuration) for testing characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration)
for testing characteristics.
30 PRODUCT PREVIEW




TB28F004S5.pdf
Click to Download PDF File