N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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28F512
512K (64K x 8) CMOS FLASH MEMORY
Y Flash Electrical Chip-Erase
1 Second Typical Chip-Erase
Y Quick-Pulse Programming Algorithm
10 ms Typical Byte-Program
1 Second Chip-Program
Y 100 000 Erase Program Cycles
Y 12 0V g5% VPP
Y High-Performance Read
120 ns Maximum Access Time
Y CMOS Low Power Consumption
10 mA Typical Active Current
50 mA Typical Standby Current
0W Data Retention Power
Y Integrated Program Erase Stop Timers
Y Command Register Architecture for
Microprocessor Microcontroller
Compatible Write Interface
Y Noise Immunity Features
g10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
Y ETOX II Nonvolatile Flash Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Y JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
(See Packaging Spec Order 231369)
Y Extended Temperature Options
Intel’s 28F512 CMOS flash memory offers the most cost-effective and reliable alternative for read write
random access nonvolatile memory The 28F512 adds electrical chip-erasure and reprogramming to familiar
EPROM technology Memory contents can be rewritten in a test socket in a PROM-programmer socket on-
board during subassembly test in-system during final test and in-system after-sale The 28F512 increases
memory flexibility while contributing to time- and cost-savings
The 28F512 is a 512-kilobit nonvolatile memory organized as 65 536 bytes of 8 bits Intel’s 28F512 is offered
in 32-pin plastic dip or 32-lead PLCC packages Pin assignments conform to JEDEC standards for byte-wide
EPROMs
Extended erase and program cycling capability is designed into Intel’s ETOX II (EPROM Tunnel Oxide) pro-
cess technology Advanced oxide processing an optimized tunneling structure and lower electric field com-
bine to extend reliable cycling beyond that of traditional EEPROMs With the 12 0V VPP supply the 28F512
performs 100 000 erase and program cycles well within the time limits of the Quick-Pulse Programming and
Quick-Erase algorithms
Intel’s 28F512 employs advanced CMOS circuitry for systems requiring high-performance access speeds low
power consumption and immunity to noise Its 120 nanosecond access time provides no-WAIT-state perform-
ance for a wide range of microprocessors and microcontrollers Maximum standby current of 100 mA trans-
lates into power savings when the device is deselected Finally the highest degree of latch-up protection is
achieved through Intel’s unique EPI processing Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins from b1V to VCC a 1V
With Intel’s ETOX II process base the 28F512 levers years of EPROM experience to yield the highest levels of
quality reliability and cost-effectiveness
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1994
Order Number 290204-008


N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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28F512
Figure 1 28F512 Block Diagram
290204 – 1
2


N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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28F512
Symbol
A0 – A15
DQ0 – DQ7
CE
OE
WE
VPP
VCC
VSS
NC
Graphic Not to Scale
290204 – 2
Figure 2 28F512 Pin Configurations
290204 – 3
Type
INPUT
INPUT OUTPUT
INPUT
INPUT
INPUT
Table 1 Pin Description
Name and Function
ADDRESS INPUTS for memory addresses Addresses are internally
latched during a write cycle
DATA INPUT OUTPUT Inputs data during memory write cycles
outputs data during memory read cycles The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled Data is internally latched during a write cycle
CHIP ENABLE Activates the device’s control logic input buffers
decoders and sense amplifiers CE is active low CE high
deselects the memory device and reduces power consumption to
standby levels
OUTPUT ENABLE Gates the devices output through the data buffers
during a read cycle OE is active low
WRITE ENABLE Controls writes to the control register and the array
Write enable is active low Addresses are latched on the falling edge
and data is latched on the rising edge of the WE pulse
Note With VPP s 6 5V memory contents cannot be altered
ERASE PROGRAM POWER SUPPLY for writing the command
register erasing the entire array or programming bytes in the array
DEVICE POWER SUPPLY (5V g10%)
GROUND
NO INTERNAL CONNECTION to device Pin may be driven or left
floating
3


N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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28F512
APPLICATIONS
The 28F512 flash memory provides nonvolatility
along with the capability to perform over 100 000
electrical chip-erasure reprogram cycles These fea-
tures make the 28F512 an innovative alternative to
disk EEPROM and battery-backed static RAM
Where periodic updates of code and data-tables are
required the 28F512’s reprogrammability and non-
volatility make it the obvious and ideal replacement
for EPROM
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process This results in dramatic enhancement of
performance and substantial reduction of power
consumption a consideration particularly impor-
tant in portable equipment Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and applica-
tion code With updatable BIOS system manufactur-
ers can easily accommodate last-minute changes as
revisions are made
In diskless workstations and terminals network traf-
fic reduces to a minimum and systems are instant-
on Reliability exceeds that of electromechanical
media Often in these environments power interrup-
tions force extended re-boot periods for all net-
worked terminals This mishap is no longer an issue
if boot code operating systems communication pro-
tocols and primary applications are flash-resident in
each terminal
For embedded systems that rely on dynamic RAM
disk for main system memory or nonvolatile backup
storage the 28F512 flash memory offers a solid
state alternative in a minimal form factor The
28F512 provides higher performance lower power
consumption instant-on capability and allows an
‘‘execute in place’’ memory hierarchy for code and
data table reading Additionally the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail
The need for code updates pervades all phases of a
system’s life from prototyping to system manufac-
ture to after-sale service The electrical chip-erasure
and reprogramming ability of the 28F512 allows in-
circuit alterability this eliminates unnecessary han-
dling and less-reliable socketed connections while
adding greater test manufacture and update flexi-
bility
Material and labor costs associated with code
changes increases at higher levels of system inte-
gration the most costly being code updates after
sale Code ‘‘bugs’’ or the desire to augment system
functionality prompt after-sale code updates Field
revisions to EPROM-based code requires the re-
moval of EPROM components or entire boards With
the 28F512 code updates are implemented locally
via an edge-connector or remotely over a commun-
cation link
For systems currently using a high-density static
RAM battery configuration for data accumulation
flash memory’s inherent nonvolatility eliminates the
need for battery backup The concern for battery
failure no longer exists an important consideration
for portable equipment and medical instruments
both requiring continuous performance In addition
flash memory offers a considerable cost advantage
over static RAM
Flash memory’s electrical chip erasure byte pro-
grammability and complete nonvolatility fit well with
data accumulation and recording needs Electrical
chip-erasure gives the designer a ‘‘blank slate’’ in
which to log or record data Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new ‘‘blank slate’’
A high degree of on-chip feature integration simpli-
fies memory-to-processor interfacing Figure 3 de-
picts two 28F512s tied to the 80C186 system bus
The 28F512’s architecture minimizes interface cir-
cuitry needed for complete in-circuit updates of
memory contents
With cost-effective in-system reprogramming ex-
tended cycling capability and true nonvolatility
the 28F512 offers advantages to the alternatives
EPROMs EEPROMs battery backed static RAM
or disk EPROM-compatible read specifications
straight-forward interfacing and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today’s designs
4


N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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28F512
Figure 3 28F512 in a 80C186 System
290204 – 5
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming The
28F512 introduces a command register to manage
this new functionality The command register allows
for 100% TTL-level control inputs fixed power sup-
plies during erasure and programming and maxi-
mum EPROM compatibility
In the absence of high voltage on the VPP pin the
28F512 is a read-only memory Manipulation of the
external memory-control pins yields the standard
EPROM read standby output disable and Intelli-
gent Identifier operations
The same EPROM read standby and output disable
operations are available when high voltage is ap-
plied to the VPP pin In addition high voltage on VPP
enables erasure and programming of the device All
functions associated with altering memory con-
tents Intelligent Identifier erase erase verify pro-
gram and program verify are accessed via the
command register
Commands are written to the register using standard
microprocessor write timings Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry Write
cycles also internally latch addresses and data
needed for programming or erase operations With
the appropriate command written to the register
standard microprocessor read timings output array
data access the Intelligent Identifier codes or out-
put data for erase and program verification
Integrated Stop Timer
Successive command write cycles define the dura-
tion of program and erase operations specifically
the program or erase time durations are normally
terminated by associated program or erase verify
commands An integrated stop timer provides simpli-
fied timing control over these operations thus elimi-
nating the need for maximum program erase timing
specifications Programming and erase pulse
durations are minimums only When the stop timer
terminates a program or erase operation the device
enters an inactive state and remains inactive until
receiving the appropriate verify or reset command
Write Protection
The command register is only active when VPP is at
high voltage Depending upon the application the
system designer may choose to make the VPP pow-
er supply switchable available only when memory
updates are desired When VPP e VPPL the con-
tents of the register default to the read command
making the 28F512 a read-only memory In this
mode the memory contents cannot be altered
5


N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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28F512
Table 2 28F512 Bus Operations
Operation
Pins VPP(1) A0 A9 CE OE WE
DQ0 – DQ7
Read
VPPL A0 A9 VIL VIL VIH Data Out
Output Disable
VPPL X X VIL VIH VIH Tri-State
READ-ONLY Standby
Intelligent Identifier (Mfr)(2)
VPPL X X VIH X
X Tri-State
VPPL VIL VID(3) VIL VIL VIH Data e 89H
Intelligent Identifier (Device)(2) VPPL VIH VID(3) VIL VIL VIH Data e B8H
Read
VPPH A0 A9 VIL VIL VIH Data Out(4)
READ WRITE Output Disable
Standby(5)
VPPH X X VIL VIH VIH Tri-State
VPPH X X VIH X
X Tri-State
Write
VPPH A0 A9 VIL VIH VIL Data In(6)
NOTES
1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not written or erased
2 Manufacturer and device codes may also be accessed via a command register write sequence Refer to Table 3 All other
addresses low
3 VID is the Intelligent Identifier high voltage Refer to DC Characteristics
4 Read operations with VPP e VPPH may access array data or the Intelligent Identifier codes
5 With VPP at high voltage the standby current equals ICC a IPP (standby)
6 Refer to Table 3 for valid Data-In during a write operation
7 X can be VIL or VIH
Or the system designer may choose to ‘‘hardwire’’
VPP making the high voltage supply constantly
available In this case all Command Register func-
tions are inhibited whenever VCC is below the write
lockout voltage VLK0 (See Power Up Down Protec-
tion) The 28F512 is designed to accommodate ei-
ther design practice and to encourage optimization
of the processor-memory interface
The two-step program erase write sequence to the
Command Register provides additional software
write protection
BUS OPERATIONS
Read
The 28F512 has two control functions both of which
must be logically active to obtain data at the out-
puts Chip-Enable (CE ) is the power control and
should be used for device selection Output-Enable
(OE ) is the output control and should be used
to gate data from the output pins independent of
device selection Refer to AC read timing
waveforms
Output Disable
With Output-Enable at a logic-high level (VIH) output
from the device is disabled Output pins are placed
in a high-impedance state
Standby
With Chip-Enable at a logic-high level the standby
operation disables most of the 28F512’s circuitry
and substantially reduces device power consump-
tion The outputs are placed in a high-impedance
state independent of the Output-Enable signal
If the 28F512 is deselected during erasure pro-
gramming or program erase verification the
device draws active current until the operation is
terminated
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manu-
facturer code (89H) and device code (B8H) Pro-
gramming equipment automatically matches the de-
vice with its proper erase and programming algo-
rithms
When VPP is high (VPPH) the read operation can be
used to access array data to output the Intelligent
Identifier codes and to access data for program
erase verification When VPP is low (VPPL) the read
operation can only access the array data
6


N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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28F512
With Chip-Enable and Output-Enable at a logic low
level raising A9 to high voltage VID (see DC Charac-
teristics) activates the operation Data read from lo-
cations 0000H and 0001H represent the manufac-
turer’s code and the device code respectively
The manufacturer- and device-codes can also be
read via the command register for instances where
the 28F512 is erased and reprogrammed in the tar-
get system Following a write of 90H to the com-
mand register a read from address location 0000H
outputs the manufacturer code (89H) A read from
address 0001H outputs the device code (B8H)
used to store the command along with address and
data information needed to execute the command
The command register is written by bringing Write-
Enable to a logic-low level (VIL) while Chip-Enable is
low Addresses are latched on the falling edge of
Write-Enable while data is latched on the rising
edge of the Write-Enable pulse Standard microproc-
essor write timings are used
Refer to AC Write Characteristics and the Erase
Programming Waveforms for specific timing
parameters
Write
Device erasure and programming are accomplished
via the command register when high voltage is ap-
plied to the VPP pin The contents of the register
serve as input to the internal state-machine The
state-machine outputs dictate the function of the
device
The command register itself does not occupy an ad-
dressable memory location The register is a latch
COMMAND DEFINITIONS
When low voltage is applied to the VPP pin the con-
tents of the command register default to 00H en-
abling read-only operations
Placing high voltage on the VPP pin enables read
write operations Device operations are selected by
writing specific data patterns into the command reg-
ister Table 3 defines these 28F512 register
commands
Table 3 Command Definitions
Command
Bus
Cycles
First Bus Cycle
Second Bus Cycle
Req’d Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)
Read Memory
1 Write
X 00H
Read Intelligent Identifier Code(4) 3
Write
X 90H Read
(4) (4)
Set-up Erase Erase(5)
2 Write
X 20H Write
X 20H
Erase Verify(5)
2 Write
EA
A0H
Read
X EVD
Set-up Program Program(6)
2 Write
X 40H Write
PA PD
Program Verify(6)
2 Write
X
C0H
Read
X PVD
Reset(7)
2 Write
X FFH Write
X FFH
NOTES
1 Bus operations are defined in Table 2
2 IA e Identifier address 00H for manufacturer code 01H for device code
EA e Address of memory location to be read during erase verify
PA e Address of memory location to be programmed
Addresses are latched on the falling edge of the Write-Enable pulse
3 ID e Data read from location IA during device identification (Mfr e 89H Device e B8H)
EVD e Data read from location EA during erase verify
PD e Data to be programmed at location PA Data is latched on the rising edge of Write-Enable
PVD e Data read from location PA during program verify PA is latched on the Program command
4 Following the Read Intelligent ID command two read operations access manufacturer and device codes
5 Figure 5 illustrates the Quick-Erase algorithm
6 Figure 4 illustrates the Quick-Pulse Programming algorithm
7 The second bus cycle must be followed by the desired command register write
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512K (64K x 8) CMOS FLASH MEMORY

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28F512
Read Command
While VPP is high for erasure and programming
memory contents can be accessed via the read
command The read operation is initiated by writing
00H into the command register Microprocessor
read cycles retrieve array data The device remains
enabled for reads until the command register con-
tents are altered
The default contents of the register upon VPP pow-
er-up is 00H This default value ensures that no spu-
rious alteration of memory contents occurs during
the VPP power transition Where the VPP supply is
hard-wired to the 28F512 the device powers-up and
remains enabled for reads until the command-regis-
ter contents are changed Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters
Intelligent Identifier Command
Flash-memories are intended for use in applications
where the local CPU alters memory contents As
such manufacturer- and device-codes must be ac-
cessible while the device resides in the target sys-
tem PROM programmers typically access signature
codes by raising A9 to a high voltage However mul-
tiplexing high voltage onto address lines is not a de-
sired system-design practice
The 28F512 contains an Intelligent Identifier opera-
tion to supplement traditional PROM-programming
methodology The operation is initiated by writing
90H into the command register Following the com-
mand write a read cycle from address 0000H re-
trieves the manufacturer code of 89H A read cycle
from address 0001H returns the device code of
B8H To terminate the operation it is necessary to
write another valid command into the register
Set-up Erase Erase Commands
Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array The set-up erase operation is performed
by writing 20H to the command register
To commence chip-erasure the erase command
(20H) must again be written to the register The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (i e Erase-Veri-
fy Command)
This two-step sequence of set-up followed by execu-
tion ensures that memory contents are not acciden-
tally erased Also chip-erasure can only occur when
high voltage is applied to the VPP pin In the absence
of this high voltage memory contents are protected
against erasure Refer to AC Erase Characteristics
and Waveforms for specific timing parameters
Erase-Verify Command
The erase command erases all bytes of the array in
parallel After each erase operation all bytes must
be verified The erase verify operation is initiated by
writing A0H into the command register The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the Write-Enable
pulse The register write terminates the erase opera-
tion with the rising edge of its Write-Enable pulse
The 28F512 applies an internally-generated margin
voltage to the addressed byte Reading FFH from
the addressed byte indicates that all bits in the byte
are erased
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address The process continues for each
byte in the array until a byte does not return FFH
data or the last address is accessed
In the case where the data read is not FFH another
erase operation is performed (Refer to Set-up
Erase Erase) Verification then resumes from the
address of the last-verified byte Once all bytes in
the array have been verified the erase step is com-
plete The device can be programmed At this point
the verify operation is terminated by writing a valid
command (e g Program Set-up) to the command
register Figure 5 the Quick-Erase algorithm illus-
trates how commands and bus operations are com-
bined to perform electrical erasure of the 28F512
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters
Set-up Program Program Commands
Set-up program is a command-only operation that
stages the device for byte programming Writing 40H
into the command register performs the set-up
operation
Once the program set-up operation is performed
the next Write-Enable pulse causes a transition to
an active programming operation Addresses are in-
ternally latched on the falling edge of the Write-En-
able pulse Data is internally latched on the rising
edge of the Write-Enable pulse The rising edge of
Write-Enable also begins the programming opera-
tion The programming operation terminates with the
next rising edge of Write-Enable used to write the
program-verify command Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters
8


N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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28F512
Program-Verify Command
The 28F512 is programmed on a byte-by-byte basis
Byte programming may occur sequentially or at ran-
dom Following each programming operation the
byte just programmed must be verified
The program-verify operation is initiated by writing
C0H into the command register The register write
terminates the programming operation with the ris-
ing edge of its Write-Enable pulse The program-ver-
ify operation stages the device for verification of the
byte last programmed No new address information
is latched
The 28F512 applies an internally-generated margin
voltage to the byte A microprocessor read cycle
outputs the data A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed Programming then
proceeds to the next desired byte location Figure 4
the 28F512 Quick-Pulse Programming algorithm il-
lustrates how commands are combined with bus op-
erations to perform byte programming Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters
Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation Memory contents will not be altered
A valid command must then be written to place the
device in the desired state
EXTENDED ERASE PROGRAM CYCLING
EEPROM cycling failures have always concerned
users The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions To combat this some sup-
pliers have implemented redundancy schemes re-
ducing cycling failures to insignificant levels Howev-
er redundancy requires that cell size be doubled
an expensive solution
Intel has designed extended cycling capability into
its ETOX II flash memory technology Resulting im-
provements in cycling reliability come without in-
creasing memory cell size or complexity First an
advanced tunnel oxide increases the charge carry-
ing ability ten-fold Second the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs minimizing the probabili-
ty of oxide defects in the region Finally the peak
electric field during erasure is approximately 2 MV
cm lower than EEPROM The lower electric field
greatly reduces oxide stress and the probability of
failure increasing time to wearout by a factor of
100 000 000
The 28F512 is capable of 100 000 program erase
cycles The device is programmed and erased using
Intel’s Quick-Pulse Programming and Quick-Erase
algorithms Intel’s algorithmic approach uses a se-
ries of operations (pulses) along with byte verifica-
tion to completely and reliably erase and program
the device
For further information see Reliability Report RR-60
(ETOX-II Reliability Data Summary)
QUICK-PULSE PROGRAMMING ALGORITHM
The Quick-Pulse Programming algorithm uses pro-
gramming operations of 10 ms duration Each opera-
tion is followed by a byte verification to determine
when the addressed byte has been successfully pro-
grammed The algorithm allows for up to 25 pro-
gramming operations per byte although most bytes
verify on the first or second operation The entire
sequence of programming and byte verification is
performed with VPP at high voltage Figure 4 illus-
trates the Quick-Pulse Programming algorithm
QUICK-ERASE ALGORITHM
Intel’s Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents The algo-
rithm employs a closed-loop flow similar to the
Quick-Pulse Programming algorithm to simulta-
neously remove charge from all bits in the array
Erasure begins with a read of memory contents The
28F512 is erased when shipped from the factory
Reading FFH data from the device would immedi-
ately be followed by device programming
For devices being erased and reprogrammed uni-
form and reliable erasure is ensured by first pro-
gramming all bits in the device to their charged state
(Data e 00H) This is accomplished using the
Quick-Pulse Programming algorithm in approxi-
mately one second
Erase execution then continues with an initial erase
operation Erase verification (data e FFH) begins at
address 0000H and continues through the array to
the last address or until data other than FFH is en-
countered With each erase operation an increasing
number of bytes verify to the erased state Erase
efficiency may be improved by storing the address of
the last byte verified in a register Following the next
erase operation verification starts at that stored ad-
dress location Erasure typically occurs in one sec-
ond Figure 5 illustrates the Quick-Erase algorithm
9


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
Bus
Operation
Command
Comments
Standby
Wait for VPP Ramp to VPPH(1)
Initialize Pulse-Count
Write
Write
Set-up
Program
Program
Data e 40H
Valid Address Data
Standby
Write
Standby
Read
Program(2)
Verify
Duration of Program
Operation (tWHWH1)
Data e C0H Stops Program
Operation(3)
tWHGL
Read Byte to Verify
Programming
Standby
Compare Data Output to Data
Expected
Write
Read
Standby
Data e 00H Resets the
Register for Read Operations
Wait for VPP Ramp to VPPL(1)
290204 – 6
NOTES
1 See DC Characteristics for value of VPPH and VPPL
2 Program Verify is only performed after byte program-
ming A final read compare may be performed (option-
al) after the register is written with the Read command
3 Refer to principles of operation
4 CAUTION The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice
Figure 4 28F512 Quick-Pulse Programming Algorithm
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512K (64K x 8) CMOS FLASH MEMORY

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28F512
Bus
Operation
Command
Comments
Entire memory must e 00H
before erasure
Standby
Use Quick-Pulse
Programming Algorithm
(Figure 4)
Wait for VPP Ramp to VPPH(1)
Initialize Addresses and
Pulse-Count
Write
Write
Set-up
Erase
Erase
Data e 20H
Data e 20H
Standby
Write
Standby
Read
Erase(2)
Verify
Duration of Erase Operation
(tWHWH2)
Addr e Byte to Verify
Data e A0H Stops Erase
Operation(3)
tWHGL
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
Write
Read
Standby
Data e 00H Resets the
Register for Read Operations
Wait for VPP Ramp to VPPL(1)
290204 – 7
NOTES
1 See DC Characteristics for value of VPPH and VPPL
2 Erase Verify is performed only after chip-erasure A
final read compare may be performed (optional) after
the register is written with the read command
3 Refer to principles of operation
4 CAUTION The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice
Figure 5 28F512 Quick-Erase Algorithm
11


N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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28F512
DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory ar-
rays Intel provides two read-control inputs to ac-
commodate multiple memory connections Two-line
control provides for
a the lowest possible memory power dissipation
and
b complete assurance that output bus contention
will not occur
To efficiently use these two control inputs an ad-
dress-decoder output should drive chip-enable
while the system’s read signal controls all flash-
memories and other parallel memories This assures
that only enabled memory devices have active out-
puts while deselected devices maintain the low
power standby condition
Power Supply Decoupling
Flash-memory power-switching characteristics re-
quire careful device decoupling System designers
are interested in three supply current (ICC) issues
standby active and transient current peaks pro-
duced by falling and rising edges of chip-enable The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks
Each device should have a 0 1 mF ceramic capacitor
connected between VCC and VSS and between VPP
and VSS
Place the high-frequency low-inherent-inductance
capacitors as close as possible to the devices Also
for every eight devices a 4 7 mF electrolytic capaci-
tor should be placed at the array’s power supply
connection between VCC and VSS The bulk capaci-
tor will overcome voltage slumps caused by printed-
circuit-board trace inductance and will supply
charge to the smaller capacitors as needed
VPP Trace on Printed Circuit Boards
Programming flash-memories while they reside in
the target system requires that the printed circuit
board designer pay attention to the VPP power sup-
ply trace The VPP pin supplies the memory cell cur-
rent for programming Use similar trace widths and
layout considerations given the VCC power bus Ad-
equate VPP supply traces and decoupling will de-
crease VPP voltage spikes and overshoots
Power Up Down Protection
The 28F512 is designed to offer protection against
accidental erasure or programming during power
transitions Upon power-up the 28F512 is indifferent
as to which power supply VPP or VCC powers up
first Power supply sequencing is not required Inter-
nal circuitry in the 28F512 ensures that the com-
mand register is reset to the read mode on power
up
A system designer must guard against active writes
for VCC voltages above VLKO when VPP is active
Since both WE and CE must be low for a com-
mand write driving either to VIH will inhibit writes
The control register architecture provides an added
level of protection since alteration of memory con-
tents only occurs after successful completion of the
two-step command sequences
28F512 Power Dissipation
When designing portable systems designers must
consider battery power consumption not only during
device operation but also for data retention during
system idle time Flash memory nonvolatility in-
creases the usable battery life of your system be-
cause the 28F512 does not consume any power to
retain code or data when the system is off Table 4
illustrates the power dissipated when updating the
28F512
Table 4 28F512 Typical Update
Power Dissipation(4)
Operation
Notes Power Dissipation
(Watt-Seconds)
Array Program
Program Verify
1
0 085
Array Erase
Erase Verify
2 0 092
One Complete Cycle
3
0 262
NOTES
1 Formula to calculate typical Program Program Verify
Power e VPP c Bytes x Typical Prog Pulses
(tWHWH1 c IPP2 Typical a tWHGL c IPP4 Typical) a
VCC c Bytes c Typical Prog Pulses (tWHWH1 c
ICC2 Typical a tWHGL c ICC4 Typical)
2 Formula to calculate typical Erase Erase Verify Power
e VPP(IPP3 Typical c tERASE Typical a IPP5 Typical c
tWHGL c Bytes) a VCC(ICC3 Typical c tERASE Typi-
cal a ICC5 Typical c tWHGL c Bytes)
3 One Complete Cycle e Array Preprogram a Array
Erase a Program
4 ‘‘Typicals’’ are not guaranteed but based on a limited
number of samples from production lots
12


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
During Read
During Erase Program
Operating Temperature
During Read
During Erase Program
Temperature Under Bias
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with
Respect to Ground
Voltage on Pin A9 with
Respect to Ground
0 C to a70 C(1)
0 C to a70 C(1)
b40 C to a85 C(2)
b40 C to a85 C(2)
b10 C to a80 C(1)
b50 C to a95 C(2)
b65 C to a125 C
b2 0V to a7 0V(2)
b2 0V to a13 5V(2 3)
VPP Supply Voltage with
Respect to Ground
During Erase Program
VCC Supply Voltage with
Respect to Ground
Output Short Circuit Current
b2 0V to a14 0V(2 3)
b2 0V to a7 0V(2)
100 mA(4)
NOTICE This is a production data sheet The specifi-
cations are subject to change without notice
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
NOTES
1 Operating temperature is for commercial product defined by this specification
2 Operating temperature is for extended temperature product defined by this specification
3 Minimum DC input voltage is b0 5V During transitions inputs may undershoot to b2 0V for periods less than 20 ns
Maximum DC voltage on output pins is VCC a 0 5V which may overshoot to VCC a 2 0V for periods less than 20 ns
4 Maximum DC voltage on A9 or VPP may overshoot to a14 0V for periods less than 20 ns
5 Output shorted for no more than one second No more than one output shorted at a time
OPERATING CONDITIONS
Symbol
Parameter
Limits
Min Max
Unit
Comments
TA
Operating Temperature(1)
0
70
C For Read-Only and
Read Write Operations
for Commercial Products
TA
Operating Temperature(2) b40 a85
C For Read-Only and
Read Write Operations
for Extended Temperature Products
VCC VCC Supply Voltage
4 50 5 50
V
DC CHARACTERISTICS TTL NMOS COMPATIBLE Commercial Products
Symbol
Parameter
Limits
Notes
Unit
Min Typ(4) Max
Test Conditions
ILI
ILO
ICCS
ICC1
ICC2
Input Leakage Current
1
Output Leakage Current
1
VCC Standby Current
1
VCC Active Read Current 1
VCC Programming
Current
12
g1 0
mA VCC e VCC Max
VIN e VCC or VSS
g10 0 mA VCC e VCC Max
VOUT e VCC or VSS
0 3 1 0 mA VCC e VCC Max
CE e VIH
10 30 mA VCC e VCC Max CE e VIL
f e 6 MHz IOUT e 0 mA
1 0 10 mA Programming in Progress
ICC3
ICC4
VCC Erase Current
VCC Program Verify
Current
12
12
5 0 15 mA Erasure in Progress
5 0 15 mA VPP e VPPH
Program Verify in Progress
13


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
DC CHARACTERISTICS TTL NMOS COMPATIBLE Commercial Products
(Continued)
Symbol
Parameter
Limits
Notes
Min Typ(4) Max
Unit
Test Conditions
ICC5
VCC Erase Verify Current
12
5 0 15 mA VPP e VPPH
Erase Verify in Progress
IPPS VPP Leakage Current
IPP1 VPP Read Current Standby
Current or ID Current
1
1
g10 0 mA VPP s VCC
90 200 mA VPP l VCC
IPP2 VPP Programming Current
12
g10 0
VPP s VCC
8 0 30 mA VPP e VPPH
Programming in Progress
IPP3 VPP Erase Current
1 2 4 0 30 mA VPP e VPPH
Erasure in Progress
IPP4 VPP Program Verify Current
12
2 0 5 0 mA VPP e VPPH
Program Verify in Progress
IPP5 VPP Erase Verify Current
12
2 0 5 0 mA VPP e VPPH
Erase Verify in Progress
VIL
VIH
VOL
VOH1
VID
IID
VPPL
VPPH
Input Low Voltage
b0 5
08 V
Input High Voltage
2 0 VCC a 0 5 V
Output Low Voltage
0 45
V IOL e 5 8 mA
VCC e VCC Min
Output High Voltage
24
V IOH e b2 5 mA
VCC e VCC Min
A9 Intelligent Identifier Voltage
11 50
13 00
V
A9 Intelligent Identifier Current 1 2
90 200 mA A9 e VID
VPP during Read-Only
Operations
0 00
6 5 V NOTE Erase Program are
Inhibited when VPP e VPPL
VPP during Read Write
Operations
11 40
12 60
V
VLKO VCC Erase Write Lock Voltage
25
V
DC CHARACTERISTICS CMOS COMPATIBLE Commercial Products
Symbol
Parameter
Limits
Notes
Unit
Min Typ(4) Max
Test Conditions
ILI Input Leakage Current
1
g1 0
mA VCC e VCC Max
VIN e VCC or VSS
ILO Output Leakage Current
1
g10 0 mA VCC e VCC Max
VOUT e VCC or VSS
ICCS
VCC Standby Current
1 50 100 mA VCC e VCC Max
CE e VCC g0 2V
ICC1
VCC Active Read Current
1
10 30 mA VCC e VCC Max CE e VIL
f e 6 MHz IOUT e 0 mA
14


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
DC CHARACTERISTICS CMOS COMPATIBLE Commercial Products (Continued)
Symbol
Parameter
Limits
Notes
Unit
Min Typ(4) Max
Test Conditions
ICC2
VCC Programming
Current
12
1 0 10 mA Programming in Progress
ICC3
ICC4
VCC Erase Current
VCC Program Verify
Current
12
12
5 0 15 mA Erasure in Progress
5 0 15 mA VPP e VPPH
Program Verify in Progress
ICC5
VCC Erase Verify Current 1 2
5 0 15 mA VPP e VPPH
Erase Verify in Progress
IPPS VPP Leakage Current
IPP1 VPP Read Current ID
Current or Standby
Current
1
1
g10 0
mA VPP s VCC
90 200 mA VPP l VCC
g10 0
VPP s VCC
IPP2 VPP Programming
Current
12
8 0 30 mA VPP e VPPH
Programming in Progress
IPP3 VPP Erase Current
12
4 0 30 mA VPP e VPPH
Erasure in Progress
IPP4 VPP Program Verify
Current
12
2 0 5 0 mA VPP e VPPH
Program Verify in Progress
IPP5 VPP Erase Verify Current 1 2
2 0 5 0 mA VPP e VPPH
Erase Verify in Progress
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH1 Output High Voltage
VOH2
VID A9 Intelligent Identifier
Voltage
b0 5
0 7 VCC
0 85 VCC
VCC b 0 4
11 50
08 V
VCC a 0 5 V
0 45
V IOL e 5 8 mA
VCC e VCC Min
V
IOH e b2 5 mA
VCC e VCC Min
IOH e b100 mA
VCC e VCC Min
13 00
V A9 e VID
IID
A9 Intelligent Identifier
12
Current
90 200 mA A9 e VID
VPPL
VPP during Read-Only
Operations
VPPH
VPP during Read Write
Operations
0 00
11 40
65
12 60
V NOTE Erase Program
are Inhibited when
VPP e VPPL
V
VLKO
VCC Erase Write Lock
Voltage
25
V
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512K (64K x 8) CMOS FLASH MEMORY

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28F512
DC CHARACTERISTICS TTL NMOS COMPATIBLE Extended Temperature
Products
Symbol
Parameter
Limits
Notes
Min Typ(4) Max
Unit
Test Conditions
ILI Input Leakage Current
ILO Output Leakage Current
ICCS VCC Standby Current
ICC1 VCC Active Read Current
ICC2
ICC3
ICC4
VCC Programming Current
VCC Erase Current
VCC Program Verify Current
1
1
1
1
12
12
12
g1 0
mA VCC e VCC Max
VIN e VCC or VSS
g10 0
mA VCC e VCC Max
VOUT e VCC or VSS
0 3 1 0 mA VCC e VCC Max
CE e VIH
10 30 mA VCC e VCC Max CE e VIL
f e 6 MHz IOUT e 0 mA
1 0 30 mA Programming in Progress
5 0 30 mA Erasure in Progress
5 0 30 mA VPP e VPPH
Program Verify in Progress
ICC5 VCC Erase Verify Current
12
5 0 30 mA VPP e VPPH
Erase Verify in Progress
IPPS
IPP1
IPP2
VPP Leakage Current
VPP Read Current Standby
Current or ID Current
VPP Programming Current
1
1
12
g10 0 mA VPP s VCC
90 200 mA VPP l VCC
g10 0
VPP s VCC
8 0 30 mA VPP e VPPH
Programming in Progress
IPP3 VPP Erase Current
1 2 4 0 30 mA VPP e VPPH
Erasure in Progress
IPP4 VPP Program Verify Current
12
2 0 5 0 mA VPP e VPPH
Program Verify in Progress
IPP5 VPP Erase Verify Current
12
2 0 5 0 mA VPP e VPPH
Erase Verify in Progress
VIL
VIH
VOL
VOH1
VID
IID
VPPL
VPPH
Input Low Voltage
b0 5
08 V
Input High Voltage
2 0 VCC a 0 5 V
Output Low Voltage
0 45
V IOL e 5 8 mA
VCC e VCC Min
Output High Voltage
24
V IOH e b2 5 mA
VCC e VCC Min
A9 Intelligent Identifier Voltage
11 50
13 00 V
A9 Intelligent Identifier Current 1 2
90 500 mA A9 e VID
VPP during Read-Only
Operations
0 00
6 5 V NOTE Erase Program are
Inhibited when VPP e VPPL
VPP during Read Write
Operations
11 40
12 60 V
VLKO VCC Erase Write Lock Voltage
25
V
16


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
DC CHARACTERISTICS CMOS COMPATIBLE Extended Temperature
Products
Symbol
Parameter
Limits
Notes
Min Typ(4)
Max
Unit
Test Conditions
ILI
ILO
ICCS
ICC1
ICC2
ICC3
ICC4
Input Leakage Current
1
Output Leakage Current
1
VCC Standby Current
1
VCC Active Read Current
1
VCC Programming Current
VCC Erase Current
VCC Program Verify
Current
12
12
12
g1 0
mA VCC e VCC Max
VIN e VCC or VSS
g10 0
mA VCC e VCC Max
VOUT e VCC or VSS
50 100 mA VCC e VCC Max
CE e VCC g0 2V
10 50 mA VCC e VCC Max CE e VIL
f e 6 MHz IOUT e 0 mA
1 0 10 mA Programming in Progress
5 0 15 mA Erasure in Progress
5 0 30 mA VPP e VPPH
Program Verify in Progress
ICC5
VCC Erase Verify Current 1 2
5 0 30 mA VPP e VPPH
Erase Verify in Progress
IPPS VPP Leakage Current
IPP1 VPP Read Current ID
Current or Standby
Current
1
1
g10 0 mA VPP s VCC
90 200 mA VPP l VCC
g10 0
VPP s VCC
IPP2 VPP Programming Current 1 2
8 0 30 mA VPP e VPPH
Programming in Progress
IPP3 VPP Erase Current
12
4 0 30 mA VPP e VPPH
Erasure in Progress
IPP4 VPP Program Verify
Current
12
2 0 5 0 mA VPP e VPPH
Program Verify in Progress
IPP5 VPP Erase Verify Current 1 2
2 0 5 0 mA VPP e VPPH
Erase Verify in Progress
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
b0 5
0 7 VCC
08 V
VCC a 0 5 V
0 45
V IOL e 5 8 mA
VCC e VCC Min
17


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
DC CHARACTERISTICS CMOS COMPATIBLE Extended Temperature
Products (Continued)
Symbol
Parameter
Notes
Limits
Unit Test Conditions
Min Typ(4) Max
VOH1 Output High Voltage
VOH2
VID
IID
VPPL
A9 Intelligent Identifier Voltage
A9 Intelligent Identifier Current
VPP during Read-Only Operations
VPPH
VLKO
VPP during Read Write Operations
VCC Erase Write Lock Voltage
0 85 VCC
V IOH e b2 5 mA
VCC e VCC Min
VCC b 0 4
IOH e b100 mA
VCC e VCC Min
11 50
13 00 V A9 e VID
1 2 90 500 mA A9 e VID
0 00
6 5 V NOTE Erase
Program
are Inhibited
when
VPP e VPPL
11 40
12 60 V
25 V
CAPACITANCE TA e 25 C f e 1 0 MHz
Symbol
Parameter
Limits
Notes
Unit Conditions
Min Max
CIN
COUT
Address Control Capacitance
Output Capacitance
3
3
8 pF VIN e 0V
12 pF VOUT e 0V
NOTES
1 All currents are in RMS unless otherwise noted Typical values at VCC e 5 0V VPP e 12 0V T e a25 C These
currents are valid for all product versions (packages and speeds)
2 Not 100% tested characterization data available
3 Sampled not 100% tested
4 ‘‘Typicals’’ are not guaranteed but based on a limited number of samples from production lots
18


N28F512 (Intel)
512K (64K x 8) CMOS FLASH MEMORY

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AC TESTING INPUT OUTPUT WAVEFORM
AC TESTING LOAD CIRCUIT
28F512
290204 – 8
AC Testing Inputs are driven at 2 4V for a logic ‘‘1’’ and 0 45V for
a logic ‘‘0’’ Testing measurements are made at 2 0V for a logic
‘‘1’’ and 0 8V for a logic ‘‘0’’ Rise Fall time s 10 ns
CL e 100 pF
CL includes Jig Capacitance
290204 – 9
AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%)
10 ns
Input Pulse Levels
0 45V and 2 4V
Input Timing Reference Level
0 8V and 2 0V
Output Timing Reference Level
0 8V and 2 0V
AC CHARACTERISTICS Read-Only Operations
Versions(1)
Notes
N28F512-120
TN28F512-120
P28F512-120
TP28F512-120
Symbol
Characteristic
Min Max
tAVAV tRC Read Cycle Time
120
tELQV tCE Chip Enable Access Time
tAVQV tACC Address Access Time
tGLQV tOE Output Enable Access Time
tELQX tLZ Chip Enable to Output in Low Z
23 0
tEHQZ
Chip Disable to Output in High Z
2
tGLQX tOLZ Output Enable to Output in Low Z
23 0
tGHQZ tDF Output Disable to Output in High Z
2
tOH
Output Hold from Address CE or 2 4
0
OE Change
120
120
50
55
30
tWHGL
Write Recovery Time before Read
6
NOTES
1 Model number prefixes N e PLCC P e PDIP T e Extended Temperature
2 Sampled not 100% tested
3 Guaranteed by design
4 Whichever occurs first
N28F512-150
P28F512-150
Unit
Min Max
150 ns
150 ns
150 ns
55 ns
0 ns
55 ns
0 ns
35 ns
0 ns
6 ms
19


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
Figure 6 AC Waveforms for Read Operations
20


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
AC CHARACTERISTICS Write Erase Program Operations(1 4)
Versions
Symbol
Characteristic
28F512-120
Notes
Min Max
28F512-150
Min Max
tAVAV tWC
tAVWL tAS
tWLAX tAH
tDVWH tDS
tWHDX tDH
tWHGL
tGHWL
tELWL tCS
tWHEH tCH
tWLWH tWP
tWHWL tWPH
tWHWH1
tWHWH2
tVPEL
Write Cycle Time
Address Set-Up Time
Address Hold Time
Data Set-up Time
Data Hold Time
Write Recovery Time before Read
Read Recovery Time before Write
Chip Enable Set-Up Time before Write
Chip Enable Hold Time
Write Pulse Width
Write Pulse Width High
Duration of Programming Operation
Duration of Erase Operation
VPP Set-Up Time to Chip Enable Low
2
3
3
2
120
0
60
50
10
6
0
20
0
60
20
10
95
10
150
0
60
50
10
6
0
20
0
60
20
10
95
10
Unit
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ms
ms
ms
NOTES
1 Read timing characteristics during read write operations are the same as during read-only operations Refer to AC Char-
acteristics for Read-Only Operations
2 Guaranteed by design
3 The integrated stop timer terminates the programming erase operations thereby eliminating the need for a maximum
specification
4 Erase Program cycles on extended temperature products is 1 000 cycles
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Notes
N P28F512-120 150
TN TP28F512-120(6)
Min Typ
Max
Min Typ
Max
Chip Erase
Time
134
1 10
1 10
Chip Program
Time
124
1 6 25
1 6 25
Unit
Sec
Sec
NOTES
1 ‘‘Typicals’’ are not guaranteed but based on a limited number of samples from production lots Data taken at 25 C 12 0V
VPP at 0 cycles
2 Minimum byte programming time excluding system overhead is 16 ms (10 ms program a 6 ms write recovery) while
maximum is 400 ms byte (16 ms c 25 loops allowed by algorithm) Max chip programming time is specified lower than the
worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte
3 Excludes 00H Programming Prior to Erasure
4 Excludes System-Level Overhead
5 Refer to RR-60 ‘‘ETOX II Flash Memory Reliability Data Summary’’ for typical cycling data and failure rate calculations
6 Extended temperature products
21


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
Figure 7 28F512 Typical Program Time at 12V
290204 – 14
290204 – 15
Figure 8 28F512 Typical Programming Capability
22


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
NOTE
Does not include Pre-Erase program
Figure 9 28F512 Typical Erase Time at 12V
290204 – 16
NOTE
Does not include Pre-Erase program
Figure 10 28F512 Typical Erase Capability
290204 – 17
23


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
Figure 11 AC Waveforms for Programming Operations
24


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
ALTERNATIVE CE -CONTROLLED WRITES
Versions
Symbol
Characteristic
Notes
tAVAV
Write Cycle
Time
tAVEL
Address Set-
Up Time
tELAX
Address Hold
Time
tDVEH
Data Set-Up
Time
tEHDX
Data Hold
Time
tEHGL
Write
Recovery Time
before Read
tGHEL
Read
Recovery Time
before Write
2
tWLEL
Write Enable
Set-Up Time
before Chip
Enable
tEHWH
Write Enable
Hold Time
tELEH
Write Pulse
Width
1
tEHEL
Write Pulse
Width High
tVPEL
VPP Set-Up
Time to Chip
Enable Low
2
28F512-120
Min Max
120
0
80
50
10
6
0
0
0
70
20
10
28F512-150
Min Max
150
0
80
50
10
6
0
0
0
70
20
10
Unit
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ms
NOTE
1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of Chip-Enable and Write-Enable In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform
2 Guaranteed by design
25


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
Figure 12 AC Waveforms for Erase Operations
26


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
Figure 13 Alternate AC Waveforms for Programming Operations
27


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512K (64K x 8) CMOS FLASH MEMORY

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28F512
Ordering Information
Valid Combinations
P28F512-120
P28F512-150
N28F512-120
N28F512-150
TP28F512-120
TN28F512-120
290204 – 13
ADDITIONAL INFORMATION
ER-20 ‘‘ETOX II Flash Memory Technology’’
ER-24 ‘‘Intel Flash Memory’’
RR-60 ‘‘ETOX II Flash Memory Reliability Data Summary’’
AP-316 ‘‘Using Flash Memory for In-System Reprogrammable
Nonvolatile Storage’’
AP-325 ‘‘Guide to Flash Memory Reprogramming’’
Order Number
294005
294008
293002
292046
292059
REVISION HISTORY
Number
006
007
008
Description
Removed 200 ns speed bin
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000
Clarified AC and DC test conditions
Corrected AC Waveforms
Added Extended Temperature devices TP28F512-120 TN28F512-120
Revised symbols i e CE OE etc to CE OE etc
28




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