TE28F010 (Intel)
1024K (128K x 8) CMOS FLASH MEMORY

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28F010 1024K (128K X 8) CMOS
FLASH MEMORY
8
n Flash Electrical Chip-Erase
1 Second Typical Chip-Erase
n Quick-Pulse Programming Algorithm
10 µs Typical Byte-Program
2 Second Chip-Program
n 100,000 Erase/Program Cycles
n 12.0 V ±5% VPP
n High-Performance Read
90 ns Maximum Access Time
n CMOS Low Power Consumption
10 mA Typical Active Current
50 µA Typical Standby Current
0 Watts Data Retention Power
n Integrated Program/Erase Stop Timer
n Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
n Noise Immunity Features
±10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
n ETOX™ Nonvolatile Flash Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
n JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
32-Lead TSOP
(See Packaging Spec., Order #231369)
n Extended Temperature Options
Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-
board during subassembly test; in-system during final test; and in-system after sale. The 28F010 increases
memory flexibility, while contributing to time and cost savings.
The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of eight bits. Intel’s 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel's ETOX™ (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0 V VPP supply, the
28F010 performs 100,000 erase and program cycles—well within the time limits of the quick-pulse
programming and quick-erase algorithms.
Intel's 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to noise. Its 90 ns access time provides zero wait-state performance
for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 µA translates into
power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved
through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on
address and data pins, from –1 V to VCC + 1 V.
With Intel's ETOX process technology base, the 28F010 builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
December 1997
Order Number: 290207-012


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1024K (128K x 8) CMOS FLASH MEMORY

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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F010 may contain design defects or errors known as errata. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s website at http://www.intel.com
Copyright © Intel Corporation 1996, 1997.
* Third-party brands and names are the property of their respective owners.


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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
CONTENTS
PAGE
1.0 APPLICATIONS ..............................................5
2.0 PRINCIPLES OF OPERATION .......................8
2.1 Integrated Stop Timer ..................................8
2.2 Write Protection ...........................................9
2.2.1 Bus Operations......................................9
2.2.1.1 Read...............................................9
2.2.1.2 Output Disable ................................9
2.2.1.3 Standby ........................................10
2.2.1.4 Intelligent Identifier Operation .......10
2.2.1.5 Write .............................................10
2.2.2 Command Definitions ..........................10
2.2.2.1 Read Command............................11
2.2.2.2 Intelligent Identifier Command ......11
2.2.2.3 Set-Up Erase/Erase Commands...12
2.2.2.4 Erase Verify Command.................12
2.2.2.5 Set-Up Program/Program
Commands ..................................12
2.2.2.6 Program Verify Command ............12
2.2.2.7 Reset Command...........................13
2.2.3 Extended Erase/Program Cycling........13
2.2.4 Quick-Pulse Programming Algorithm ...13
2.2.5 Quick-Erase Algorithm.........................13
3.0 DESIGN CONSIDERATIONS ........................16
3.1 Two-Line Output Control ............................16
3.2 Power Supply Decoupling ..........................16
3.3 VPP Trace on Printed Circuit Boards...........16
3.4 Power-Up/Down Protection ........................16
3.5 28F010 Power Dissipation .........................16
PAGE
4.0 ELECTRICAL SPECIFICATIONS..................18
4.1 Absolute Maximum Ratings........................18
4.2 Operating Conditions..................................18
4.3 Capacitance ...............................................18
4.4 DC Characteristics—TTL/NMOS
Compatible—Commercial Products...........19
4.5 DC Characteristics—CMOS Compatible—
Commercial Products ................................20
4.6 DC Characteristics—TTL/NMOS
Compatible—Extended Temperature
Products ....................................................22
4.7 DC Characteristics—CMOS Compatible—
Extended Temperature Products...............23
4.8 AC Characteristics—Read-Only
Operations—Commercial and Extended
Temperature Products...............................25
4.9 AC Characteristics—Write/Erase/Program
Only Operations —Commercial and
Extended Temperature Products...............27
4.10 AC Characteristics—Alternative CE#-
Controlled Writes— Commercial and
Extended Temperature..............................31
4.11 Erase and Programming Performance......32
5.0 ORDERING INFORMATION..........................33
6.0 ADDITIONAL INFORMATION .......................33
3


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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
REVISION HISTORY
Number
Description
-007
Removed 200 ns Speed Bin
Revised Erase Maximum Pulse Count for Figure 4 from 3000 to 1000
Clarified AC and DC Test Conditions
Added “dimple” to F TSOP Package
Corrected Serpentine Layout
-008 Corrected AC Waveforms
Added Extended Temperature Options
-009
Added 28F010-65 and 28F010-90 speeds
———— ———
Revised Symbols, i.e., CE, OE, etc. to CE#, OE#, etc.
-010
-011
-012
Completion of Read Operation Table
Labelling of Program Time in Erase/Program Table
Textual Changes or Edits
Corrected Erase/Program Times
Minor changes throughout document
Removed 65 ns speed bin
Removed TSOP package
Added Extended Temperature options
Modified AC Test Conditions
Modified AC Characteristics
E
4


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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
1.0 APPLICATIONS
The 28F010 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These
features make the 28F010 an innovative alternative
to disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data tables are
required, the 28F010’s reprogrammability and
nonvolatility make it the obvious and ideal
replacement for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption—a consideration particularly important
in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and
application code. With updatable code, system
manufacturers can easily accommodate last-minute
changes as revisions are made.
In diskless workstations and terminals, network
traffic reduces to a minimum and systems are
instant-on. Reliability exceeds that of electro-
mechanical media. Often in these environments,
power interruptions force extended re-boot periods
for all networked terminals. This mishap is no
longer an issue if boot code, operating systems,
communication protocols and primary applications
are flash resident in each terminal.
For embedded systems that rely on dynamic
RAM/disk for main system memory or nonvolatile
backup storage, the 28F010 flash memory offers a
solid state alternative in a minimal form factor. The
28F010 provides higher performance, lower power
consumption, instant-on capability, and allows an
“eXecute in place” (XIP) memory hierarchy for code
and data table reading. Additionally, the flash
memory is more rugged and reliable in harsh
environments where extreme temperatures and
shock can cause disk-based systems to fail.
The need for code updates pervades all phases of
a system's life—from prototyping to system
manufacture to after sale service. The electrical
chip-erasure and reprogramming ability of the
28F010 allows in-circuit alterability; this eliminates
unnecessary handling and less reliable socketed
connections, while adding greater test,
manufacture, and update flexibility.
Material and labor costs associated with code
changes increases at higher levels of system
integration—the most costly being code updates
after sale. Code “bugs,” or the desire to augment
system functionality, prompt after sale code
updates. Field revisions to EPROM-based code
requires the removal of EPROM components or
entire boards. With the 28F010, code updates are
implemented locally via an edge connector, or
remotely over a communcation link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory's electrical chip erasure, byte
programmability and complete nonvolatility fit well
with data accumulation and recording needs.
Electrical chip-erasure gives the designer a “blank
slate” in which to log or record data. Data can be
periodically off-loaded for analysis and the flash
memory erased producing a new “blank slate.”
A high degree of on-chip feature integration
simplifies memory-to-processor interfacing. Figure 3
depicts two 28F010s tied to the 80C186 system
bus. The 28F010's architecture minimizes interface
circuitry needed for complete in-circuit updates of
memory contents.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. TSOP is
particularly suited for portable equipment and
applications requiring large amounts of flash
memory.
With cost-effective in-system reprogramming,
extended cycling capability, and true nonvolatility,
the 28F010 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straightforward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs.
5


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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
290207-1
Figure 1. 28F010 Block Diagram
Table 1. Pin Description
Symbol
Type
Name and Function
A0–A16
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
DQ0–DQ7
INPUT/OUTPUT
DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs
data during memory read cycles. The data pins are active high and float to
tri-state off when the chip is deselected or the outputs are disabled. Data is
internally latched during a write cycle
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers, decoders
and sense amplifiers. CE# is active low; CE# high deselects the memory
device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE# pulse.
Note: With VPP 6.5 V, memory contents cannot be altered.
6


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1024K (128K x 8) CMOS FLASH MEMORY

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Symbol
VPP
VCC
VSS
NC
Type
28F010
Table 1. Pin Description (Continued)
Name and Function
ERASE/PROGRAM POWER SUPPLY for writing the command register,
erasing the entire array, or programming bytes in the array.
DEVICE POWER SUPPLY (5 V ±10%)
GROUND
NO INTERNAL CONNECTION to device. Pin may be driven or left floating.
Figure 2. 28F010 Pin Configurations
7


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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
290207-4
Figure 3. 28F010 in a 80C186 System
2.0 PRINCIPLES OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F010 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power
supplies during erasure and programming; and
maximum EPROM compatibility.
In the absence of high voltage on the VPP pin, the
28F010 is a read-only memory. Manipulation of the
external memory control pins yields the standard
EPROM read, standby, output disable, and
intelligent identifier operations.
The same EPROM read, standby, and output
disable operations are available when high voltage
is applied to the VPP pin. In addition, high voltage
on VPP enables erasure and programming of the
device. All functions associated with altering
memory contents—intelligent identifier, erase,
erase verify, program, and program verify—are
accessed via the command register.
8
Commands are written to the register using
standard microprocessor write timings. Register
contents serve as input to an internal state machine
which controls the erase and programming circuitry.
Write cycles also internally latch addresses and
data needed for programming or erase operations.
With the appropriate command written to the
register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output data for erase and program
verification.
2.1 Integrated Stop Timer
Successive command write cycles define the
durations of program and erase operations;
specifically, the program or erase time durations are
normally terminated by associated Program or
Erase Verify commands. An integrated stop timer
provides simplified timing control over these
operations; thus eliminating the need for maximum
program/erase timing specifications. Programming
and erase pulse durations are minimums only.
When the stop timer terminates a program or erase
operation, the device enters an inactive state and
remains inactive until receiving the appropriate
Verify or Reset command.


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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
Table 2. 28F010 Bus Operations
Mode
VPP(1) A0
A9 CE# OE# WE# DQ0–DQ7
Read
VPPL A0 A9 VIL VIL VIH Data Out
Output Disable
VPPL X
X VIL VIH VIH Tri-State
READ-ONLY Standby
VPPL X
X VIH X X Tri-State
Intelligent Identifier (Mfr)(2)
VPPL VIL VID(3) VIL VIL VIH Data = 89H
Intelligent Identifier (Device)(2) VPPL VIH VID(3) VIL VIL VIH Data = B4H
Read
VPPH A0 A9 VIL VIL VIH Data Out(4)
READ/WRITE Output Disable
VPPH X
X VIL VIH VIH Tri-State
Standby(5)
VPPH X
X VIH X X Tri-State
Write
VPPH A0 A9 VIL VIH VIL Data In(6)
NOTES:
1. Refer to DC Characteristics. When VPP = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VID is the intelligent identifier high voltage. Refer to DC Characteristics.
4. Read operations with VPP = VPPH may access array data or the intelligent identifier codes.
5. With VPP at high voltage, the standby current equals ICC + IPP (standby).
6. Refer to Table 3 for valid data-in during a write operation.
7. X can be VIL or VIH.
2.2 Write Protection
The command register is only active when VPP is at
high voltage. Depending upon the application, the
system designer may choose to make the VPP
power supply switchable—available only when
memory updates are desired. When VPP = VPPL, the
contents of the register default to the Read
command, making the 28F010 a read-only memory.
In this mode, the memory contents cannot be
altered.
Or, the system designer may choose to “hardwire”
VPP, making the high voltage supply constantly
available. In this case, all command register
functions are inhibited whenever VCC is below the
write lockout voltage VLKO. (See Section 3.4,
Power-Up/Down Protection.) The 28F010 is
designed to accommodate either design practice,
and to encourage optimization of the processor
memory interface.
The two-step program/erase write sequence to the
command register provides additional software
write protections.
2.2.1
BUS OPERATIONS
2.2.1.1
Read
The 28F010 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE#) is the power control
and should be used for device selection. Output
Enable (OE#) is the output control and should be
used to gate data from the output pins, independent
of device selection. Refer to the AC read timing
waveforms.
When VPP is high (VPPH), the read operation can be
used to access array data, to output the intelligent
identifier codes, and to access data for
program/erase verification. When VPP is low (VPPL),
the read operation can only access the array data.
2.2.1.2
Output Disable
With OE# at a logic-high level (VIH), output from the
device is disabled. Output pins are placed in a high-
impedance state.
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28F010
2.2.1.3
Standby
With CE# at a logic-high level, the standby
operation disables most of the 28F010’s circuitry
and substantially reduces device power
consumption. The outputs are placed in a high-
impedance state, independent of the OE# signal. If
the 28F010 is deselected during erasure,
programming, or program/erase verification, the
device draws active current until the operation is
terminated.
2.2.1.4
Intelligent Identifier Operation
The intelligent identifier operation outputs the
manufacturer code (89H) and device code (B4H).
Programming equipment automatically matches the
device with its proper erase and programming
algorithms.
With CE# and OE# at a logic low level, raising A9 to
high voltage VID (see DC Characteristics) activates
the operation. Data read from locations 0000H and
0001H represent the manufacturer's code and the
device code, respectively.
The manufacturer and device codes can also be
read via the command register, for instances where
the 28F010 is erased and reprogrammed in the
target system. Following a write of 90H to the
command register, a read from address location
0000H outputs the manufacturer code (89H). A
read from address 0001H outputs the device code
(B4H).
2.2.1.5
Write
Device erasure and programming are accomplished
via the command register, when high voltage is
applied to the VPP pin. The contents of the register
serve as input to the internal state machine. The
state machine outputs dictate the function of the
device.
The command register itself does not occupy an
addressable memory location. The register is a
latch used to store the command, along with
address and data information needed to execute
the command.
The command register is written by bringing WE# to
a logic-low level (VIL), while CE# is low. Addresses
are latched on the falling edge of WE#, while data is
latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.
Refer to AC Characteristics—Write/Erase/Program
Only Operations and the erase/programming
waveforms for specific timing parameters.
2.2.2
COMMAND DEFINITIONS
When low voltage is applied to the VPP pin, the
contents of the command register default to 00H,
enabling read-only operations.
Placing high voltage on the VPP pin enables
read/write operations. Device operations are
selected by writing specific data patterns into the
command register. Table 3 defines these 28F010
register commands.
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28F010
Table 3. Command Definitions
First Bus Cycle
Second Bus Cycle
Command
Bus
Cycles
Req’d
Operation(1) Address(2) Data(3)
Operation(1)
Address(2) Data(3)
Read Memory
1 Write
X 00H
Read Intelligent
Identifier Codes(4)
3
Write
IA 90H Read
IA ID
Set-Up
Erase/Erase(5)
2
Write
X 20H Write
X 20H
Erase Verify(5)
2
Write
EA A0H
Read
X EVD
Set-Up Program/
Program(6)
2
Write
X 40H Write
PA PD
Program Verify(6)
2
Write
X C0H Read
X PVD
Reset(7)
2 Write
X FFH Write
X FFH
NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: 00H for manufacturer code, 01H for device code.
EA = Erase Address: Address of memory location to be read during erase verify.
PA = Program Address: Address of memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
3. ID = Identifier Data: Data read from location IA during device identification (Mfr = 89H, Device = B4H).
EVD = Erase Verify Data: Data read from location EA during erase verify.
PD = Program Data: Data to be programmed at location PA. Data is latched on the rising edge of WE#.
PVD = Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the 28F010 Quick-Erase Algorithm flowchart.
6. Figure 4 illustrates the 28F010 Quick-Pulse Programming Algorithm flowchart.
7. The second bus cycle must be followed by the desired command register write.
2.2.2.1
Read Command
While VPP is high, for erasure and programming,
memory contents can be accessed via the Read
command. The read operation is initiated by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register
contents are altered.
The default contents of the register upon VPP
power-up is 00H. This default value ensures that no
spurious alteration of memory contents occurs
during the VPP power transition. Where the VPP
supply is hardwired to the 28F010, the device
powers-up and remains enabled for reads until the
command register contents are changed. Refer to
the AC Characteristics—Read-Only Operations and
waveforms for specific timing parameters.
2.2.2.2
Intelligent Identifier Command
Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer and device codes must be
accessible while the device resides in the target
system. PROM programmers typically access
signature codes by raising A9 to a high voltage.
However, multiplexing high voltage onto address
lines is not a desired system design practice.
The 28F010 contains an intelligent identifier
operation to supplement traditional PROM-
programming methodology. The operation is
initiated by writing 90H into the command register.
Following the command Write, a read cycle from
address 0000H retrieves the manufacturer code of
89H. A read cycle from address 0001H returns the
device code of B4H. To terminate the operation, it
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28F010
is necessary to write another valid command into
the register.
2.2.2.3
Set-Up Erase/Erase Commands
Set-Up Erase is a command-only operation that
stages the device for electrical erasure of all bytes
in the array. The set-up erase operation is
performed by writing 20H to the command register.
To commence chip-erasure, the Erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
WE# pulse and terminates with the rising edge of
the next WE# pulse (i.e., Erase Verify command).
This two-step sequence of set-up followed by
execution ensures that memory contents are not
accidentally erased. Also, chip-erasure can only
occur when high voltage is applied to the pin. In the
absence of this high voltage, memory contents are
protected against erasure. Refer to AC
Characteristics—Write/Erase/Program Only Oper-
ations and waveforms for specific timing
parameters.
2.2.2.4
Erase Verify Command
The Erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing A0H into the command register. The
address for the byte to be verified must be supplied
as it is latched on the falling edge of the WE# pulse.
The register write terminates the erase operation
with the rising edge of its WE# pulse.
The 28F010 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The Erase Verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer Section
2.2.2.3, Set-Up Erase/Erase Commands.)
Verification then resumes from the address of the
last-verified byte. Once all bytes in the array have
been verified, the erase step is complete. The
device can be programmed. At this
12
point, the verify operation is terminated by writing a
valid command (e.g., Program Set-Up) to the
command register. Figure 5, the 28F010 Quick-
Erase Algorithm flowchart, illustrates how
commands and bus operations are combined to
perform electrical erasure of the 28F010. Refer to
AC Characteristics—Write/Erase/Program Only
Operations and waveforms for specific timing
parameters.
2.2.2.5
Set-Up Program/Program
Commands
Set-up program is a command-only operation that
stages the device for byte programming. Writing
40H into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next WE# pulse causes a transition to an active
programming operation. Addresses are internally
latched on the falling edge of the WE# pulse. Data
is internally latched on the rising edge of the WE#
pulse. The rising edge of WE# also begins the
programming operation. The programming
operation terminates with the next rising edge of
WE#, used to write the Program Verify command.
Refer to AC Characteristics—Write/Erase/Program
Only Operations and Waveforms for specific timing
parameters.
2.2.2.6
Program Verify Command
The 28F010 is programmed on a byte-by-byte
basis. Byte programming may occur sequentially or
at random. Following each programming operation,
the byte just programmed must be verified.
The program verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the
rising edge of its WE# pulse. The program verify
operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F010 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming
then proceeds to the next desired byte location.
Figure 5, the 28F010 Quick-Pulse Programming
Algorithm flowchart, illustrates how commands are
combined with bus operations to perform byte


TE28F010 (Intel)
1024K (128K x 8) CMOS FLASH MEMORY

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28F010
programming. Refer to AC Characteristics
Write/Erase/Program Only Operations and
waveforms for specific timing parameters.
2.2.2.7
Reset Command
A Reset command is provided as a means to safely
abort the Erase or Program command sequences.
Following either Set-Up command (Erase or
Program) with two consecutive writes of FFH will
safely abort the operation. Memory contents will not
be altered. A valid command must then be written
to place the device in the desired state.
2.2.3
EXTENDED ERASE/PROGRAM
CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin
oxide EEPROMs for tunneling can literally tear
apart the oxide at defect regions. To combat this,
some suppliers have implemented redundancy
schemes, reducing cycling failures to insignificant
levels. However, redundancy requires that cell size
be doubled—an expensive solution.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting
improvements in cycling reliability come without
increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge
carrying ability ten-fold. Second, the oxide area per
cell subjected to the tunneling electric field is one-
tenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally,
the peak electric field during erasure is
approximately 2 MV/cm lower than EEPROM. The
lower electric field greatly reduces oxide stress and
the probability of failure.
The 28F010 is capable or 100,000 program/erase
cycles. The device is programmed and erased
using Intel's quick-pulse programming and quick-
erase algorithms. Intel's algorithmic approach uses
a series of operations (pulses), along with byte
verification, to completely and reliably erase and
program the device.
2.2.4
QUICK-PULSE PROGRAMMING
ALGORITHM
The quick-pulse programming algorithm uses
programming operations of 10 µs duration. Each
operation is followed by a byte verification to
determine when the addressed byte has been
successfully programmed. The algorithm allows for
up to 25 programming operations per byte, although
most bytes verify on the first or second operation.
The entire sequence of programming and byte
verification is performed with VPP at high voltage.
Figure 4 illustrates the 28F010 Quick-Pulse
Programming Algorithm flowchart.
2.2.5
QUICK-ERASE ALGORITHM
Intel's quick-erase algorithm yields fast and reliable
electrical erasure of memory contents. The
algorithm employs a closed-loop flow, similar to the
quick-pulse programming algorithm, to simul-
taneously remove charge from all bits in the array.
Erasure begins with a read of memory contents.
The 28F010 is erased when shipped from the
factory. Reading FFH data from the device would
immediately be followed by device programming.
For devices being erased and reprogrammed,
uniform and reliable erasure is ensured by first
programming all bits in the device to their charged
state (Data = 00H). This is accomplished, using the
quick-pulse programming algorithm, in approxi-
mately two seconds.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address 0000H and continues through the array to
the last address, or until data other than FFH is
encountered. With each erase operation, an
increasing number of bytes verify to the erased
state. Erase efficiency may be improved by storing
the address of the last byte verified in a register.
Following the next erase operation, verification
starts at that stored address location. Erasure
typically occurs in one second. Figure 5 illustrates
the 28F010 Quick-Erase Algorithm flowchart.
13


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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
Start
Programming (4)
Apply VPPH (1)
Bus
Operation
Command
Comments
Standby
Wait for VPP Ramp to
VPPH(1)
PLSCNT = 0
Initialize Pulse-Count
Increment
Address
Write Set-Up
Program Cmd
Write Program
Cmd (A/D)
Time Out 10 µs
Write Program
Verify Cmd
Time Out 6 µs
Read Data
from Device
Verify
Data
N
Y
N Last
Address?
Y
Write Read Cmd
N
Inc
PLSCNT
=25?
Y
Write
Write
Set-Up
Program
Data = 40H
Program Valid Address/Data
Standby
Write
Duration of Program
Operation (tWHWH1 )
Program
Verify(2)
Data = C0H; Stops
Program Operations(3)
Stand-by
Read
tWHGL
Read Byte to Verify
Programming
Standby
Compare Data Output to
Data Expected
Write
Read
Data = 00H, Resets the
Register for Read
Operations
Standby
Wait for VPP Ramp to VPPL(1)
Apply VPPL (1)
Apply VPPL (1)
Programming
Completed
Program
Error
0207_04
NOTES:
1. See DC Characteristics for the value of VPPH and VPPL.
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the
register is written with the Read command.
3. Refer to Principles of Operation.
4. CAUTION: The algorithm must be followed to ensure proper and reliable operation of the device.
Figure 4. 28F010 Quick-Pulse Programming Algorithm
14


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28F010
Start Erasure (4)
Y
Data = 00H?
N
Program All
Bytes to 00H
Bus
Operation
Command
Comments
Entire Memory Must = 00H
Before Erasure
Use Quick-Pulse
Programming Algorithm
(Figure 4)
Apply VPPH (1)
ADDR = 00H
PLSCNT = 0
Write Erase
Set-Up Cmd
Write Erase Cmd
Time Out 10 ms
Write Erase
Verify Cmd
Time Out 6 µs
Standby
Wait for VPP Ramp to VPPH (1)
Write
Write
Stand-by
Write
Standby
Initialize Addresses and
Pulse-Count
Set-Up
Erase
Data = 20H
Erase Data = 20H
Erase (2)
Verify
Duration of Erase Operation
(tWHWH2 )
Addr = Byte to Verify;
Data = A0H; Stops Erase
Operation(3)
tWHGL
Read Data
from Device
Data = FFH?
N
Increment Addr
Y
N
Last Address?
Y
Write Read Cmd
N
Inc
PLSCNT =
1000?
Y
Apply VPPL (1)
Apply VPPL (1)
Read
Standby
Read Byte to Verify Erasure
Compare Output to FFH
Increment Pulse-Count
Write
Read
Data = 00H, Resets the
Register for Read Operations
Standby
Wait for VPP Ramp to VPPL (1)
Erasure
Completed
Erase Error
0207_05
NOTES:
1. See DC Characteristics for the value of VPPH and VPPL.
2. Erase Verify is performed only after chip-erasure. A final read/compare may be performed (optional) after the register is
written with the Read command.
3. Refer to Principles of Operation.
4. CAUTION: The algorithm must be followed to ensure proper and reliable operation of the device.
Figure 5. 28F010 Quick-Erase Algorithm
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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
3.0 DESIGN CONSIDERATIONS
3.1 Two-Line Output Control
Flash memories are often used in larger memory
arrays. Intel provides two read control inputs to
accommodate multiple memory connections. Two-
line control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an
address decoder output should drive chip-enable,
while the system’s read signal controls all flash
memories and other parallel memories. This
assures that only enabled memory devices have
active outputs, while deselected devices maintain
the low power standby condition.
3.2 Power Supply Decoupling
Flash memory power-switching characteristics
require careful device decoupling. System
designers are interested in three supply current
(ICC) issues—standby, active, and transient current
peaks produced by falling and rising edges of chip-
enable. The capacitive and inductive loads on the
device outputs determine the magnitudes of these
peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 µF ceramic
capacitor connected between VCC and VSS, and
between VPP and VSS.
Place the high-frequency, low-inherent inductance
capacitors as close as possible to the devices.
Also, for every eight devices, a 4.7 µF electrolytic
capacitor should be placed at the array's power
supply connection, between VCC and VSS. The bulk
capacitor will overcome voltage slumps caused by
printed circuit board trace inductance, and will
supply charge to the smaller capacitors as needed.
3.3 VPP Trace on Printed Circuit
Boards
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the VPP power
supply trace. The VPP pin supplies the memory cell
current for programming. Use similar trace widths
and layout considerations given the VCC power bus.
Adequate VPP supply traces and decoupling will
decrease VPP voltage spikes and overshoots.
3.4 Power-Up/Down Protection
The 28F010 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F010 is
indifferent as to which power supply, VPP or VCC,
powers up first. Power supply sequencing is not
required. Internal circuitry in the 28F010 ensures
that the command register is reset to the read mode
on power-up.
A system designer must guard against active writes
for VCC voltages above VLKO when VPP is active.
Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit
writes. The control register architecture provides an
added level of protection since alteration of memory
contents only occurs after successful completion of
the two-step command sequences.
3.5 28F010 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain
code or data when the system is off. Table 4
illustrates the power dissipated when updating the
28F010.
16


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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
Table 4. 28F010 Typical Update Power Dissipation(4)
Operation
Notes
Power Dissipation (Watt-Seconds)
Array Program/Program Verify
1
0.171
Array Erase/Erase Verify
2
0.136
One Complete Cycle
3
0.478
NOTES:
1. Formula to calculate typical Program/Program Verify Power = [VPP × # Bytes × typical # Prog Pulses (tWHWH1 × IPP2 typical
+ tWHGL × IPP4 typical)] + [VCC × # Bytes × typical # Prog Pulses (tWHWH1 × ICC2 typical + tWHGL × ICC4 typical].
2. Formula to calculate typical Erase/Erase Verify Power = [VPP (VPP3 typical × tERASE typical + IPP5 typical × tWHGL × #
Bytes)] + [VCC (ICC3 typical × tERASE typical + ICC5 typical × tWHGL × # Bytes)].
3. One Complete Cycle = Array Preprogram + Array Erase + Program.
4. “Typicals” are not guaranteed, but based on a limited number of samples from production lots.
17


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1024K (128K x 8) CMOS FLASH MEMORY

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28F010
4.0 ELECTRICAL SPECIFICATIONS
4.1 Absolute Maximum Ratings*
Operating Temperature
During Read ...............................0 °C to +70 °C(1)
During Erase/Program................0 °C to +70 °C(1)
Operating Temperature
During Read ...........................–40 °C to +85 °C(2)
During Erase/Program............–40 °C to +85 °C(2)
Temperature Under Bias............–10 °C to +80 °C(1)
Temperature Under Bias............–50 °C to +95 °C(2)
Storage Temperature.................. –65 °C to +125 °C
Voltage on Any Pin with
Respect to Ground .................. –2.0 V to +7.0 V(3)
Voltage on Pin A9 with
Respect to Ground ............. –2.0 V to +13.5 V(3, 4)
VPP Supply Voltage with
Respect to Ground
During Erase/Program........ –2.0 V to +14.0 V(3, 4)
VCC Supply Voltage with
Respect to Ground .................. –2.0 V to +7.0 V(3)
Output Short Circuit Current..................... 100 mA(5)
NOTICE: This is a production datasheet. The specifications
are subject to change without notice.
*WARNING: Stressing the device beyond the Absolute
Maximum Ratings may cause permanent damage. These
are stress ratings only. Operation beyond the Operating
Conditions is not recommended and extended exposure
beyond the Operating Conditions may affect device
reliability.
NOTES:
1. Operating Temperature is for commercial product as
defined by this specification.
2. Operating Temperature is for extended temperature
products as defined by this specification.
3. Minimum DC input voltage is –0.5 V. During transitions,
inputs may undershoot to –2.0 V for periods less than
20 ns. Maximum DC voltage on output pins is VCC +
0.5 V, which may overshoot to VCC + 2.0 V for periods
less than 20 ns.
4. Maximum DC voltage on A9 or VPP may overshoot to
+14.0 V for periods less than 20 ns.
5. Output shorted for no more than one second. No more
than one output shorted at a time.
6. See AC Testing Input/Output Waveform (Figure 6) and
AC Testing Load Circuit (Figure 7) for testing
characteristics.
4.2 Operating Conditions
Symbol
TA
TA
VCC
VCC
Parameter
Operating Temperature(1)
Operating Temperature(2)
VCC Supply Voltage (10%)(6)
VCC Supply Voltage (5%)(7)
Limits
Min Max
0 70
–40 +85
4.50 5.50
4.75 5.25
Unit
°C
°C
V
V
4.3 Capacitance
TA = 25 °C, f = 1.0 MHz
Symbol
Parameter
CIN Address/Control Capacitance
COUT
Output Capacitance
NOTE:
1. Sampled, not 100% tested.
Notes
1
1
Limits
Min Max
8
12
Unit
pF
pF
Conditions
VIN = 0 V
VOUT = 0 V
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28F010
4.4 DC Characteristics—TTL/NMOS Compatible—Commercial Products
Limits
Symbol
Parameter
Notes Min Typ(3) Max Unit
Test Conditions
ILI Input Leakage Current 1
±1.0
µA VCC = VCC Max
VIN = VCC or VSS
ILO
Output Leakage Current
1
±10 µA VCC = VCC Max
VOUT = VCC or VSS
ICCS
VCC Standby Current
1
0.3 1.0 mA VCC = VCC Max
CE# = VIH
ICC1 VCC Active Read Current 1
10 30 mA VCC = VCC Max, CE# = VIL
f = 6 MHz, IOUT = 0 mA
ICC2 VCC Programming Current 1, 2
1.0 10 mA Programming in Progress
ICC3 VCC Erase Current
1, 2
5.0 15 mA Erasure in Progress
ICC4 VCC Program Verify
Current
1, 2
5.0 15 mA VPP = VPPH
Program Verify in Progress
ICC5 VCC Erase Verify Current 1, 2
5.0 15 mA VPP = VPPH
Erase Verify in Progress
IPPS VPP Leakage Current
1
±10 µA VPP VCC
IPP1 VPP Read Current
or Standby Current
1
90 200 µA VPP > VCC
±10.0
VPP VCC
IPP2 VPP Programming Current 1, 2
8.0 30 mA VPP = VPPH
Programming in Progress
IPP3 VPP Erase Current
1, 2
6.0 30 mA VPP = VPPH
Erasure in Progress
IPP4 VPP Program Verify
Current
1, 2
2.0 5.0 mA VPP = VPPH
Program Verify in Progress
IPP5 VPP Erase Verify Current 1, 2
2.0 5.0 mA VPP = VPPH
Erase Verify in Progress
VIL Input Low Voltage
–0.5 0.8 V
VIH Input High Voltage
2.0 VCC V
+ 0.5
VOL Output Low Voltage
0.45
V VCC = VCC Min
IOL = 5.8 mA
VOH1 Output High Voltage
2.4
V VCC = VCC Min
IOH = –2.5 mA
VID A9 Intelligent Identifier
Voltage
11.50
13.00 V
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28F010
4.4 DC Characteristics—TTL/NMOS Compatible—Commercial Products
(Continued)
Limits
Symbol
Parameter
Notes Min Typ(3) Max Unit
Test Conditions
IID
A9 Intelligent Identifier
1, 2
Current
90 200 µA A9 = VID
VPPL
VPP during Read-Only
Operations
0.00
6.5 V NOTE: Erase/Program are
Inhibited when VPP = VPPL
VPPH
VPP during Read/Write
Operations
11.40
12.60 V
VLKO
VCC Erase/Write Lock
Voltage
2.5
V
NOTES:
Sampled, not 100% tested.
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25 °C. These currents are
valid for all product versions (packages and speeds).
2. Not 100% tested: characterization data available.
3. “Typicals” are not guaranteed, but based on a limited number of samples from production lots.
4.5 DC Characteristics—CMOS Compatible—Commercial Products
Limits
Symbol
Parameter
Notes Min Typ(3) Max Unit
Test Conditions
ILI Input Leakage Current 1
±1.0
µA VCC = VCC Max
VIN = VCC or VSS
ILO
Output Leakage Current
1
±10 µA VCC = VCC Max
VOUT = VCC or VSS
ICCS
VCC Standby Current
1
50 100 µA VCC = VCC Max
CE# = VCC ±0.2 V
ICC1 VCC Active Read Current 1
10 30 mA VCC = VCC Max, CE# = VIL
f = 6 MHz, IOUT = 0 mA
ICC2 VCC Programming Current 1, 2
1.0 10 mA Programming in Progress
ICC3 VCC Erase Current
1, 2
5.0 15 mA Erasure in Progress
ICC4 VCC Program Verify
Current
1, 2
5.0 15 mA VPP = VPPH
Program Verify in Progress
ICC5 VCC Erase Verify Current 1, 2
5.0 15 mA VPP = VPPH
Erase Verify in Progress
IPPS VPP Leakage Current
1
±10 µA VPP VCC
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28F010
4.5 DC Characteristics—CMOS Compatible—Commercial Products (Continued)
Limits
Symbol
Parameter
Notes Min Typ(3) Max Unit
Test Conditions
IPP1 VPP Read Current, ID
Current or Standby
Current
1
90 200 µA VPP > VCC
±10 VPP VCC
IPP2 VPP Programming Current 1, 2
8.0 30 mA VPP > = VPPH
Programming in Progress
IPP3 VPP Erase Current
1, 2
6.0 30 mA VPP = VPPH
Erasure in Progress
IPP4 VPP Program Verify
Current
1, 2
2.0 5.0 mA VPP = VPPH
Program Verify in Progress
IPP5 VPP Erase Verify Current 1, 2
2.0 5.0 mA VPP = VPPH
Erase Verify in Progress
VIL Input Low Voltage
–0.5 0.8 V
VIH Input High Voltage
0.7 VCC V
VCC + 0.5
VOL Output Low Voltage
0.45
V VCC = VCC Min
IOL = 5.8 mA
VOH1 Output High Voltage
0.85
VCC
V VCC = VCC Min
IOH = –2.5 mA
VOH2
VCC
– 0.4
VCC = VCC Min
IOH = –100 µA
VID A9 Intelligent Identifier
Voltage
11.50
13.00 V
IID
A9 Intelligent Identifier
1, 2
Current
90 200 µA A9 = VID
VPPL
VPP during Read-Only
Operations
0.00
6.5 V NOTE: Erase/Programs are
Inhibited when VPP = VPPL
VPPH
VPP during Read/Write
Operations
11.40
12.60 V
VLKO
VCC Erase/Write Lock
Voltage
2.5
V
NOTES:
Refer to Section 4.4.
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28F010
4.6 DC Characteristics—TTL/NMOS Compatible—Extended Temperature
Products
Limits
Symbol
Parameter
Notes Min Typ(3) Max Unit
Test Conditions
ILI Input Leakage Current 1
±1.0
µA VCC = VCC Max
VIN = VCC or VSS
ILO
Output Leakage Current
1
±10 µA VCC = VCC Max
VOUT = VCC or VSS
ICCS
VCC Standby Current
1
0.3 1.0 mA VCC = VCC Max
CE# = VIH
ICC1 VCC Active Read Current 1
10 30 mA VCC = VCC Max, CE# = VIL
f = 6 MHz, IOUT = 0 mA
ICC2 VCC Programming Current 1, 2
1.0 30 mA Programming in Progress
ICC3 VCC Erase Current
1, 2
5.0 30 mA Erasure in Progress
ICC4 VCC Program Verify
Current
1, 2
5.0 30 mA VPP = VPPH
Program Verify in Progress
ICC5 VCC Erase Verify Current 1, 2
5.0 30 mA VPP = VPPH
Erase Verify in Progress
IPPS VPP Leakage Current
1
±10 µA VPP VCC
IPP1 VPP Read Current or
Standby Current
1
90 200 µA VPP > VCC
±10.0
VPP VCC
IPP2 VPP Programming Current 1, 2
8.0 30 mA VPP = VPPH
Programming in Progress
IPP3 VPP Erase Current
1, 2
6.0 30 mA VPP = VPPH
Erasure in Progress
IPP4 VPP Program Verify
Current
1, 2
2.0 5.0 mA VPP = VPPH
Program Verify in Progress
IPP5 VPP Erase Verify Current 1, 2
2.0 5.0 mA VPP = VPPH
Erase Verify in Progress
VIL Input Low Voltage
–0.5 0.8 V
VIH Input High Voltage
2.0 VCC V
+ 0.5
VOL Output Low Voltage
0.45
V VCC = VCC Min
IOL = 5.8 mA
VOH1 Output High Voltage
2.4
V VCC = VCC Min
IOH = –2.5 mA
VID A9 Intelligent Identifier
Voltage
11.50
13.00 V
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28F010
4.6 DC Characteristics—TTL/NMOS Compatible—Extended Temperature
Products (Continued)
Symbol
Parameter
IID A9 Intelligent Identifier
Current
VPPL
VPP during Read-Only
Operations
VPPH
VPP during Read/Write
Operations
VLKO
VCC Erase/Write Lock
Voltage
NOTES:
Refer to Section 4.4.
Limits
Notes Min Typ(3) Max Unit
Test Conditions
1, 2 90 500 µA A9 = VID
0.00
11.40
6.5
12.60
V NOTE: Erase/Program are
Inhibited when VPP = VPPL
V
2.5 V
4.7 DC Characteristics—CMOS Compatible—Extended Temperature Products
Limits
Symbol
Parameter
Notes Min Typ(3) Max Unit
Test Conditions
ILI Input Leakage Current 1
±1.0
µA VCC = VCC Max
VIN = VCC or VSS
ILO
Output Leakage Current
1
±10 µA VCC = VCC Max
VOUT = VCC or VSS
ICCS
VCC Standby Current
1
50 100 µA VCC = VCC Max
CE# = VCC ±0.2 V
ICC1 VCC Active Read Current 1
10 30 mA VCC = VCC Max, CE# = VIL
f = 10 MHz, IOUT = 0 mA
ICC2 VCC Programming Current 1, 2
1.0 10 mA Programming in Progress
ICC3 VCC Erase Current
1, 2
5.0 30 mA Erasure in Progress
ICC4 VCC Program Verify
Current
1, 2
5.0 30 mA VPP = VPPH
Program Verify in Progress
ICC5 VCC Erase Verify Current 1, 2
5.0 30 mA VPP = VPPH
Erase Verify in Progress
IPPS VPP Leakage Current
1
±10 µA VPP VCC
IPP1 VPP Read Current, ID
Current or Standby
Current
1
90 200 µA VPP > VCC
±10 VPP VCC
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28F010
4.7 DC Characteristics—CMOS Compatible—Extended Temperature Products
(Continued)
Limits
Symbol
Parameter
Notes Min Typ(3) Max Unit
Test Conditions
IPP2 VPP Programming Current 1, 2
8.0 30 mA VPP = VPPH
Programming in Progress
IPP3 VPP Erase Current
1, 2
6.0 30 mA VPP = VPPH
Erasure in Progress
IPP4 VPP Program Verify
Current
1, 2
2.0 5.0 mA VPP = VPPH
Program Verify in Progress
IPP5 VPP Erase Verify Current 1, 2
2.0 5.0 mA VPP = VPPH
Erase Verify in Progress
VIL Input Low Voltage
–0.5 0.8 V
VIH Input High Voltage
0.7 VCC + V
VCC 0.5
VOL Output Low Voltage
0.45
V VCC = VCC Min
IOL = 5.8 mA
VOH1 Output High Voltage
0.85
VCC
V VCC = VCC Min
IOH = –2.5 mA
VOH2
VCC
– 0.4
VCC = VCC Min
IOH = –100 µA
VID A9 Intelligent Identifier
Voltage
11.50
13.00 V
IID
A9 Intelligent Identifier
1, 2
Current
90 500 µA A9 = VID
VPPL
VPP during Read-Only
Operations
0.00
6.5 V NOTE: Erase/Programs are
Inhibited when VPP = VPPL
VPPH
VPP during Read/Write
Operations
11.40
12.60 V
VLKO
VCC Erase/Write Lock
Voltage
2.5
V
NOTE:
Refer to Section 4.4.
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28F010
2.4
Input
0.45
2.0
Test Points
0.8
2.0
Output
0.8
0207_06
AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1”
and VOL (0.45 VTTL) for a Logic “0”. Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH
and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 6. Testing Input/Output Waveform(1)
Device
Under Test
1.3V
1N914
RL = 3.3 k
Out
CL = 100 pF
NOTE:
1. Testing characteristics for 28F010-90, 28F010-120, and
28F010-150.
CL Includes Jig Capacitance
0207_07
Figure 7. AC Testing Load Circuit
4.8 AC Characteristics—Read-Only Operations—Commercial and Extended
Temperature Products
Versions
28F010-90(1) 28F010-120(1) 28F010-150(1)
Symbol
Characteristic
Notes Min Max Min Max Min Max Unit
tAVAV/tRC Read Cycle Time
90 120 150 ns
tELQV/tCE CE# Access Time
90 120 150 ns
tAVQV/tACC Address Access Time
90 120 150 ns
tGLQV/tOE OE# Access Time
35 50 55 ns
tELQX/tLZ CE# to Low Z
2, 3 0 0 0 ns
tEHQZ
Chip Disable to Output in
High Z
2
45 55 55 ns
tGLQX/tOLZ OE# to Output in Low Z
2, 3 0
0
0 ns
tGHQZ/tDF Output Disable to Output in
High Z
2
30 30 35 ns
tOH Output Hold from Address, 2, 4 0 0 0 ns
CE#, or OE# Change
tWHGL
Write Recovery Time before
6
6
6 µs
Read
NOTES:
1. See AC Input/Output Waveform and AC Testing Load Circuit for testing characteristics.
2. Sampled, not 100% tested.
3. Guaranteed by design.
4. Whichever occurs first.
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28F010
Figure 8. AC Waveforms for Read Operations
290207-9
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28F010
4.9 AC Characteristics—Write/Erase/Program Only Operations(1)
Commercial and Extended Temperature Products
Versions
28F010-90(2) 28F010-120(2) 28F010-150(2)
Symbol
Characteristic
Notes Min Max Min Max Min Max Unit
tAVAV/tWC
tAVWL/tAS
tWLAX/tAH
Write Cycle Time
Address Set-Up Time
Address Hold Time
90
0
40
3 55
120 150
00
40 40
ns
ns
ns
tDVWH/tDS Data Set-Up Time
40 40 40 ns
55
tWHDX/tDH Data Hold Time
10 10 10 ns
tWHGL
Write Recovery Time before
6
6
6 µs
Read
tGHWL
Read Recovery Time before 4
0
0
0 ns
Write
tELWL/tCS
Chip Enable Set-Up Time
before Write
15 15 15 ns
tWHEH/tCH Chip Enable Hold Time
0 0 0 ns
tWLWH/tWP Write Pulse Width
40 60 60 ns
3 55
tWHWL/tWPH Write Pulse Width High
20 20 20 ns
tWHWH1
Duration of Programming
5 10
10
10
µs
Operation
tWHWH2
Duration of Erase Operation 5
9.5
9.5
9.5
ms
tVPEL
VPP Set-Up Time to Chip
41
1
1 µs
Enable Low
NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read-Only Operations.
2. See AC Input/Output Waveform and AC Testing Load Circuit for testing characteristics.
3. Minimum specification for extended temperature product.
4. Guaranteed by design.
5. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum
specification.
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290207-13
Figure 9. Typical Programming Capability
290207-15
Figure 11. Typical Erase Capability
290207-14
Figure 10. Typical Program Time at 12 V
28
290207-16
Figure 12. Typical Erase Time at 12 V


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Figure 13. AC Waveforms for Programming Operations
290207-10
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Figure 14. AC Waveforms for Erase Operations
290207-11
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