GT28F128W30 (Intel)
Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
28F640W30, 28F320W30, 28F128W30
Datasheet
Product Features
High Performance Read-While-Write/Erase
— Burst Frequency at 40 MHz
— 70 ns Initial Access Speed
— 25 ns Page-Mode Read Speed
— 20 ns Burst-Mode Read Speed
— Burst and Page Mode in All Blocks and
across All Partition Boundaries
— Burst Suspend Feature
— Enhanced Factory Programming:
3.5 µs per Word Program Time
— Programmable WAIT Signal Polarity
Flash Power
— VCC = 1.70 V – 1.90 V
— VCCQ = 2.20 V – 3.30 V
— Standby Current (0.13 µm) = 8 µA (typ.)
— Read Current = 7 mA
(4 word burst, typ.)
Flash Software
— 5 µs/9 µs (typ.) Program/Erase Suspend
Latency Time
— Intel® Flash Data Integrator (FDI) and
Common Flash Interface (CFI) Compatible
Quality and Reliability
— Operating Temperature:
–40 °C to +85 °C
— 100K Minimum Erase Cycles
— 0.13 µm ETOX™ VIII Process
— 0.18 µm ETOX™ VII Process
Flash Architecture
— Multiple 4-Mbit Partitions
— Dual Operation: RWW or RWE
— Parameter Block Size = 4-Kword
— Main block size = 32-Kword
— Top and Bottom Parameter Devices
Flash Security
— 128-bit Protection Register: 64 Unique Device
Identifier Bits; 64 User OTP Protection
Register Bits
— Absolute Write Protection with VPP at Ground
— Program and Erase Lockout during Power
Transitions
— Individual and Instantaneous Block Locking/
Unlocking with Lock-Down
Density and Packaging
— 0.13 µm: 32-, 64-, and 128-Mbit in VF BGA
Package; 64-, 128-Mbit in QUAD+ Package
— 0.18 µm: 32- and 128-Mbit Densities in VF
BGA Package; 64-Mbit Density in µBGA*
Package
— 56 Active Ball Matrix, 0.75 mm Ball-Pitch
— 16-bit Data Bus
The Intel®Wireless Flash Memory (W30) device combines state-of-the-art Intel® Flash
technology to provide the most versatile memory solution for high performance, low power,
board constraint memory applications. The W30 device offers a multi-partition, dual-operation
flash architecture that enables the device to read from one partition while programming or
erasing in another partition. This Read-While-Write or Read-While-Erase capability makes it
possible to achieve higher data throughput rates as compared to single partition devices,
allowing two processors to interleave code execution because program and erase operations can
now occur as background processes.
The W30 device incorporates a new Enhanced Factory Programming (EFP) mode to improve 12
V factory programming performance. This new feature helps eliminate manufacturing
bottlenecks associated with programming high density flash devices. Compare the EFP program
time of 3.5 µs per word to the standard factory program time of 8.0 µs per word and save
significant factory programming time for improved factory efficiency.
Additionally, the W30 device includes block lock-down and programmable WAIT signal
polarity, and is supported by an array of software tools. All these features make this product a
perfect solution for any demanding memory application.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
290702-010
May 2004


GT28F128W30 (Intel)
Wireless Flash Memory

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Wireless Flash Memory (W30) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2004, Intel Corporation.
*Other names and brands may be claimed as the property of others.
Datasheet
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28F320W30, 28F640W30, 28F128W30
Contents
1.0 Introduction ..................................................................................................................9
1.1 Document Purpose................................................................................................9
1.2 Nomenclature ........................................................................................................9
1.3 Conventions ..........................................................................................................9
2.0 Functional Overview ...............................................................................................11
2.1 Overview .............................................................................................................11
2.2 Memory Map and Partitioning .............................................................................12
3.0 Package Information ...............................................................................................15
3.1 W30 – 0.18 mm Lithography ...............................................................................15
3.2 W30 – 0.13 mm Lithography ...............................................................................18
4.0 Ballout and Signal Descriptions ........................................................................20
4.1 Signal Ballout ......................................................................................................20
4.2 Signal Descriptions..............................................................................................22
5.0 Maximum Ratings and Operating Conditions ..............................................23
5.1 Absolute Maximum Ratings.................................................................................23
5.2 Operating Conditions...........................................................................................23
6.0 Electrical Specifications........................................................................................25
6.1 DC Current Characteristics .................................................................................25
6.2 DC Voltage Characteristics .................................................................................26
7.0 AC Characteristics...................................................................................................27
7.1 Read Operations - 0.13 µm Lithography .............................................................27
7.2 Read Operations - 0.18 µm Lithography .............................................................29
7.3 AC Write Characteristics .....................................................................................39
7.4 Erase and Program Times ..................................................................................43
8.0 Power and Reset Specifications ........................................................................44
8.1 Active Power .......................................................................................................44
8.2 Automatic Power Savings (APS).........................................................................44
8.3 Standby Power ....................................................................................................44
8.4 Power-Up/Down Characteristics .........................................................................45
8.4.1 System Reset and RST# ........................................................................45
8.4.2 VCC, VPP, and RST# Transitions ..........................................................45
8.5 Power Supply Decoupling ...................................................................................45
8.6 Reset Specifications............................................................................................46
8.7 AC I/O Test Conditions........................................................................................47
8.8 Device Capacitance ............................................................................................48
9.0 Device Operations ...................................................................................................48
9.1 Bus Operations....................................................................................................48
9.1.1 Read .......................................................................................................48
9.1.2 Burst Suspend........................................................................................49
Datasheet
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Wireless Flash Memory

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28F320W30, 28F640W30, 28F128W30
10.0
11.0
12.0
13.0
14.0
4
9.1.3 Standby .................................................................................................. 50
9.1.4 Reset ...................................................................................................... 50
9.1.5 Write ....................................................................................................... 50
9.2 Device Commands .............................................................................................. 51
9.3 Command Sequencing........................................................................................ 54
Read Operations....................................................................................................... 55
10.1 Read Array .......................................................................................................... 55
10.2 Read Device ID ................................................................................................... 55
10.3 Read Query (CFI)................................................................................................ 56
10.4 Read Status Register .......................................................................................... 56
10.5 Clear Status Register .......................................................................................... 58
Program Operations ............................................................................................... 58
11.1 Word Program ..................................................................................................... 58
11.2 Factory Programming.......................................................................................... 59
11.3 Enhanced Factory Program (EFP) ...................................................................... 60
11.3.1 EFP Requirements and Considerations ................................................. 60
11.3.2 Setup ...................................................................................................... 61
11.3.3 Program ................................................................................................. 61
11.3.4 Verify ...................................................................................................... 61
11.3.5 Exit ......................................................................................................... 62
Program and Erase Operations.......................................................................... 64
12.1
12.2
12.3
Program/Erase Suspend and Resume ............................................................... 64
Block Erase ......................................................................................................... 66
Read-While-Write and Read-While-Erase .......................................................... 68
Security Modes ......................................................................................................... 69
13.1
13.2
13.3
Block Lock Operations ........................................................................................ 69
13.1.1 Lock........................................................................................................ 70
13.1.2 Unlock .................................................................................................... 70
13.1.3 Lock-Down ............................................................................................. 70
13.1.4 Block Lock Status................................................................................... 71
13.1.5 Lock During Erase Suspend .................................................................. 71
13.1.6 Status Register Error Checking.............................................................. 71
13.1.7 WP# Lock-Down Control ........................................................................ 72
Protection Register.............................................................................................. 72
13.2.1 Reading the Protection Register ............................................................ 73
13.2.2 Programing the Protection Register ....................................................... 73
13.2.3 Locking the Protection Register ............................................................. 74
VPP Protection .................................................................................................... 75
Set Read Configuration Register....................................................................... 76
14.1 Read Mode (RCR[15]) ........................................................................................ 78
14.2 First Access Latency Count (RCR[13:11]) .......................................................... 78
14.2.1 Latency Count Settings .......................................................................... 79
14.3 WAIT Signal Polarity (RCR[10]) .......................................................................... 79
14.4 WAIT Signal Function ......................................................................................... 79
14.5 Data Hold (RCR[9]) ............................................................................................. 80
14.6 WAIT Delay (RCR[8]) .......................................................................................... 81
Datasheet


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Wireless Flash Memory

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28F320W30, 28F640W30, 28F128W30
14.7
14.8
14.9
14.10
Burst Sequence (RCR[7])....................................................................................81
Clock Edge (RCR[6])...........................................................................................83
Burst Wrap (RCR[3]) ...........................................................................................83
Burst Length (RCR[2:0])......................................................................................83
Appendix A Write State Machine .............................................................................................84
Appendix B Common Flash Interface ....................................................................................87
Appendix C Ordering Information ...........................................................................................96
Datasheet
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Wireless Flash Memory

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28F320W30, 28F640W30, 28F128W30
Revision History
Date of
Revision
09/19/00
03/14/01
04/05/02
04/24/02
10/20/02
Version
Description
-001
-002
-003
-004
-005
Original Version
28F3208W30 product references removed (product was discontinued)
28F640W30 product added
Revised Table 2, Signal Descriptions (DQ15–0, ADV#, WAIT, S-UB#, S-LB#, VCCQ)
Revised Section 3.1, Bus Operations
Revised Table 5, Command Bus Definitions, Notes 1 and 2
Revised Section 4.2.2, First Latency Count (LC2–0); revised Figure 6, Data Output
with LC Setting at Code 3; added Figure 7, First Access Latency Configuration
Revised Section 4.2.3, WAIT Signal Polarity (WT)
Added Section 4.2.4, WAIT Signal Function
Revised Section 4.2.5, Data Output Configuration (DOC)
Added Figure 8, Data Output Configuration with WAIT Signal Delay
Revised Table 13, Status Register DWS and PWS Description
Revised entire Section 5.0, Program and Erase Voltages
Revised entire Section 5.3, Enhanced Factory Programming (EFP)
Revised entire Section 8.0, Flash Security Modes
Revised entire Section 9.0, Flash Protection Register; added Table 15, Simulta-
neous Operations Allowed with the Protection Register
Revised Section 10.1, Power-Up/Down Characteristics
Revised Section 11.3, DC Characteristics. Changed ICCS,ICCWS, ICCES Specs from
18 µA to 21µA; changed ICCR Spec from 12 mA to 15 mA (burst length = 4)
Added Figure 20, WAIT Signal in Synchronous Non-Read Array Operation Wave-
form
Added Figure 21, WAIT Signal in Asynchronous Page-Mode Read Operation
Waveform
Added Figure 22, WAIT Signal in Asynchronous Single-Word Read Operation
Waveform
Revised Figure 23, Write Waveform
Revised Section 12.4, Reset Operations
Clarified Section 13.2, SRAM Write Operation, Note 2
Revised Section 14.0, Ordering Information
Minor text edits
Deleted SRAM Section
Added 128M DC and AC Specifications
Added Burst Suspend
Added Read While Write Transition Waveforms
Various text edits
Revised Device ID
Revised Write Speed Bin
Various text edits
Added Latency Count Tables
Updated Packing Ball-Out and Dimension
Various text edits
Minor text clarifications
6 Datasheet


GT28F128W30 (Intel)
Wireless Flash Memory

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28F320W30, 28F640W30, 28F128W30
Date of
Revision
01/14/03
03/22/03
11/17/03
05/06/04
05/17/04
Version
-006
-007
-008
-009
-010
Description
Revised Table 20, DC Current Characteristics, ICCS
Revised Table 20, DC Current Characteristics, ICCAPS
Removed Intel Burst order
Minor text edits
Updated Package Drawing and Dimensions
Revised Table 22, Read Operations, tAPA
Added note to table 15, Configuration Register Descriptions
Added note to section 3.1.1, Read
Updated Block Lock Operations (Sect. 7.1 and Fig. 11)
Updated improved AC timings
Added QUAD+ package option, and Appendix D
Minor text edits including new product-naming conventions
Corrected Absolute Maximum Rating for VCCQ (Sect. 10.1, Table 18)
Minor text edits
Restructured the datasheet according to new layout.
Datasheet
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Wireless Flash Memory

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28F320W30, 28F640W30, 28F128W30
8 Datasheet


GT28F128W30 (Intel)
Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
1.0 Introduction
1.1 Document Purpose
This datasheet contains information about the Intel® Wireless Flash Memory (W30) family.
Section 1.0 provides a flash memory overview. Section 2.0 through Section 8.0 describe the
memory functionality. Section 6.0 describes the electrical specifications for extended temperature
product offerings. Packaging specifications and order information can be found in Appendix C and
Appendix C, respectively.
1.2 Nomenclature
Many acronyms that describe product features or usage are defined here:
APS - Automatic Power Savings
BBA - Block Base Address
CFI - Common Flash Interface
CUI - Command User Interface
DU - Do not Use
EFP - Enhanced Factory Programming
FDI - Flash Data Integrator
NC - No Connect
OTP - One-Time Programmable
PBA - Partition Base Address
RCR - Read Configuration Register
RWE - Read-While-Erase
RWW - Read-While-Write
SCSP - Stacked Chip Scale Package
SRD - Status Register Data
VF BGA - Very-thin, Fine-pitch, Ball Grid Array
WSM - Write State Machine
1.3 Conventions
Many abbreviated terms and phrases are used throughout this document:
1.8 V refers to the VCC operating voltage range of 1.7 V – 1.9 V (except where noted).
3.0 V refers to the VCCQ operating voltage range of 2.2 V - 3.3 V.
VPP = 12 V refers to 12 V ± 5%.
Datasheet
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Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
When referring to registers, the term set means the bit is a logical 1, and cleared means the bit
is a logical 0.
The terms pin and signal are often used interchangeably to refer to the external signal
connections on the package. (ball is the term used for BGA).
A word is 2 bytes, or 16 bits.
Signal names are in all CAPS (e.g., WAIT).
Voltage applied to the signal is subscripted (e.g., VPP).
Throughout this document, references are made to top, bottom, parameter, and partition. To clarify
these references, the following conventions have been adopted:
A block is a group of bits (or words) that erase simultaneously with one block erase
instruction.
A main block contains 32 Kwords.
A parameter block contains 4 Kwords.
The Block Base Address (BBA) is the first address of a block.
A partition is a group of blocks that share erase and program circuitry and a common status
register.
The Partition Base Address (PBA) is the first address of a partition. For example, on a 32-
Mbit top-parameter device, partition number 5 has a PBA of 0x140000.
The top partition is located at the highest physical device address. This partition may be a
main partition or a parameter partition.
The bottom partition is located at the lowest physical device address. This partition may be a
main partition or a parameter partition.
A main partition contains only main blocks.
A parameter partition contains a mixture of main blocks and parameter blocks.
A top parameter device (TPD) has the parameter partition at the top of the memory map with
the parameter blocks at the top of that partition. This was formerly referred to as top-boot
device.
A bottom parameter device (BPD) has the parameter partition at the bottom of the memory
map with the parameter blocks at the bottom of that partition. This was formerly referred to as
bottom-boot block flash device.
10 Datasheet


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Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
2.0
2.1
Functional Overview
This section provides an overview of the W30 features and architecture.
Overview
The W30 provides Read-While-Write (RWW) and Read-White-Erase (RWE) capability with high-
performance synchronous and asynchronous reads in package-compatible densities with a 16-bit
data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight
4-Kword parameter blocks are located in the parameter partition at either the top or bottom of the
memory map. The rest of the memory array is grouped into 32-Kword main blocks.
The memory architecture for the W30 consists of multiple 4-Mbit partitions, the exact number
depending on device density. By dividing the memory array into partitions, program or erase
operations can take place simultaneously during read operations. Burst reads can traverse partition
boundaries, but user application code is responsible for ensuring that they don’t extend into a
partition that is actively programming or erasing. Although each partition has burst-read, write, and
erase capabilities, simultaneous operation is limited to write or erase in one partition while other
partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An
erase can be suspended to perform a program or read operation within any block, except that which
is erase-suspended. A program operation nested within a suspended erase can subsequently be
suspended to read yet another memory location.
After device power-up or reset, the W30 defaults to asynchronous read configuration. Writing to
the device’s Read Configuration Register (RCR) enables synchronous burst-mode read operation.
In synchronous mode, the CLK input increments an internal burst address generator. CLK also
synchronizes the flash memory with the host CPU and outputs data on every, or on every other,
valid CLK cycle after an initial latency. A programmable WAIT output signals to the CPU when
data from the flash memory device is ready.
In addition to its improved architecture and interface, the W30 incorporates Enhanced Factory
Programming (EFP), a feature that enables fast programming and low-power designs. The EFP
feature provides the fastest currently-available program performance, which can increase a
factory’s manufacturing throughput.
The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V.
With the 1.8-V option, VCC and VPP can be tied together for a simple, ultra-low-power design. In
addition to voltage flexibility, the dedicated VPP input provides complete data protection when
VPP VPPLK.
A 128-bit protection register enhances the user’s ability to implement new security techniques and
data protection schemes. Unique flash device identification and fraud-, cloning-, or content-
protection schemes are possible through a combination of factory-programmed and user-OTP data
Datasheet
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Intel® Wireless Flash Memory (W30)
cells. Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data. An additional block lock-down capability provides
hardware protection where software commands alone cannot change the block’s protection status.
The device’s Command User Interface (CUI) is the system processor’s link to internal flash
memory operation. A valid command sequence written to the CUI initiates device Write State
Machine (WSM) operation that automatically executes the algorithms, timings, and verifications
necessary to manage flash memory program and erase. An internal status register provides ready/
busy indication results of the operation (success, fail, and so on).
Three power-saving features– Automatic Power Savings (APS), standby, and RST#– can
significantly reduce power consumption. The device automatically enters APS mode following
read cycle completion. Standby mode begins when the system deselects the flash memory by
de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also
resets the part to read-array mode (important for system-level reset), clears internal status registers,
and provides an additional level of flash write protection.
2.2 Memory Map and Partitioning
The W30 is divided into 4-Mbit physical partitions, which allows simultaneous RWW or RWE
operations and allows users to segment code and data areas on 4-Mbit boundaries. The device’s
memory array is asymmetrically blocked, which enables system code and data integration within a
single flash device. Each block can be erased independently in block erase mode. Simultaneous
program and erase operations are not allowed; only one partition at a time can be actively
programming or erasing. See Table 1, “Bottom Parameter Memory Map” on page 13 and Table 2,
“Top Parameter Memory Map” on page 14.
The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit
device has 32 partitions. Each device density contains one parameter partition and several main
partitions. The 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-
Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each.
The bulk of the array is divided into main blocks that can store code or data, and parameter blocks
that allow storage of frequently updated small parameters that are normally stored in EEPROM. By
using software techniques, the word-rewrite functionality of EEPROMs can be emulated.
.
12 Datasheet


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Intel® Wireless Flash Memory (W30)
Table 1. Bottom Parameter Memory Map
Size
(KW)
32
Blk #
32 Mbit
Blk #
64 Mbit
32
32 134 3F8000-3FFFFF
32 71 200000-207FFF
32
70 1F8000-1FFFFF
70 1F8000-1FFFFF
32
39 100000-107FFF
39 100000-107FFF
32
38 0F8000-0FFFFF
38 0F8000-0FFFFF
32
31 0C0000-0C7FFF
31 0C0000-0C7FFF
32
30 0B8000-0BFFFF
30 0B8000-0BFFFF
32
23 080000-087FFF
23 080000-087FFF
32
22 078000-07FFFF
22 078000-07FFFF
32
15 040000-047FFF
15 040000-047FFF
32
14 038000-03FFFF
14 038000-03FFFF
32
8 008000-00FFFF
8 008000-00FFFF
4
7 007000-007FFF
7 007000-007FFF
4
0 000000-000FFF
0 000000-000FFF
Blk #
128 Mbit
262 7F8000-7FFFFF
135 400000-407FFF
134 3F8000-3FFFFF
71 200000-207FFF
70 1F8000-1FFFFF
39 100000-107FFF
38 0F8000-0FFFFF
31 0C0000-0C7FFF
30 0B8000-0BFFFF
23 080000-087FFF
22 078000-07FFFF
15 040000-047FFF
14 038000-03FFFF
8 008000-00FFFF
7 007000-007FFF
0 000000-000FFF
Datasheet
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Intel® Wireless Flash Memory (W30)
Table 2. Top Parameter Memory Map
Size
(KW)
4
Blk #
32 Mbit
70 1FF000-1FFFFF
Blk #
64 Mbit
134 3FF000-3FFFFF
4
63 1F8000-1F8FFF
127 3F8000-3F8FFF
32
62 1F0000-1F7FFF
126 3F0000-3F7FFF
32
56 1C0000-1C7FFF
120 3C0000-3C7FFF
32
55 1B8000-1BFFFF
119 3B8000-3BFFFF
32
48 18000-187FFF
112 380000-387FFF
32
47 178000-17FFFF
111 378000-37FFFF
32
40 140000-147FFF
104 340000-347FFF
32
39 138000-13FFFF
103 338000-33FFFF
32
32 100000-107FFF
96 300000-307FFF
32
31 0F8000-0FFFFF
95 2F8000-2FFFFF
32
0 000000-007FFF
64 200000-207FFF
32 63 1F8000-1FFFFF
32 0 000000-007FFF
32
32
Blk #
128 Mbit
262 7FF000-7FFFFF
255 7F8000-7F8FFF
254 7F0000-7F7FFF
248 7C0000-7C7FFF
247 7B8000-7BFFFF
240 780000-787FFF
239 778000-77FFFF
232 740000-747FFF
231 738000-73FFFF
224 700000-707FFF
223 6F8000-6FFFFF
192 600000-607FFF
191 5F8000-5FFFFF
128 400000-407FFF
127 3F8000-3FFFFF
0 000000-007FFF
14 Datasheet


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Intel® Wireless Flash Memory (W30)
3.0 Package Information
3.1 W30 – 0.18 mm Lithography
Figure 1. 64-Mb µBGA* CSP Package Drawing and Dimensions
Pin # 1
Indicator
D
s1 Pin # 1
Corner
123
A
B
C
D
E
F
G
45
67
8
E
876 54 321
A
B
C
D
E
F
G
e
b
s2
Top View - Silicon backside
Complete Ink Mark Not
Bottom View - Bump side Up
A1
A2 A Seati
Y
Plan
Side
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Width
Package Body Length
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
Symbol
A
A1
A2
b
D
E
[e]
N
Y
S1
S2
Millimeters
Min
0.850
0.150
0.612
0.300
7.600
8.900
1.125
2.150
Nom
0.712
0.350
7.700
9.000
0.750
56
1.225
2.250
Max
1.000
0.812
0.400
7.800
9.100
Notes
Inches
Min
0.0335
0.0059
0.0241
0.0118
0.2992
0.3503
0.100
1.325
2.350
0.0443
0.0846
Nom
Max
0.0394
0.0280
0.0138
0.3031
0.3543
0.0295
56
0.0482
0.0886
0.0320
0.0157
0.3071
0.3583
0.0039
0.0522
0.0925
Datasheet
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Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
Figure 2. 32-Mb VF BGA Package Drawing
Ball A1
Corner
D
12345 678
A
B
C
ED
E
F
G
Top View - Bump Side Down
A1
A2
Side View
Figure 3. 128-Mb VF BGA Package Drawing
Ball A1
Corner
D
1 2 3 4 5 6 7 8 9 10
A
B
C
ED
E
F
G
H
J
Top View - Bump Side
Down
A1
A2
Side View
Ball A1
Corner
S1
8 7 6 5 4 3 21
A
B
C
D
E
F
G
b
Bottom View - Ball Side Up
e
S2
A Seating
Plane
Y
Note: Drawing not to scale
Ball A
S1 Corne
10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
e
G
H
Jb
Bottom View - Ball Side
Up
S2
A Seating
Plane
Y
Note: Drawing not to scal e
16 Datasheet


GT28F128W30 (Intel)
Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
Table 3. 32-Mbit and 128-Mbit VF BGA Package Dimensions
Dimension
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Width 32Mb
Package Body Length32Mb
Package Body Width 128Mb
Package Body Length 128Mb
Pitch
Ball (Lead) Count 32Mb
Ball (Lead) Count 128Mb
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D 32Mb
Corner to Ball A1 Distance Along E 32Mb
Corner to Ball A1 Distance Along D 128Mb
Corner to Ball A1 Distance Along E 128Mb
Symbol
A
A1
A2
b
D
E
D
E
[e]
N
N
Y
S1
S2
S1
S2
Millimeters
Inches
Min Nom Max Min Nom Max
0.850
0.150
0.615
0.325
7.600
8.900
12.400
11.900
-
-
-
-
1.125
2.150
2.775
2.900
-
-
0.665
0.375
7.700
9.000
12.500
12.000
0.750
56
60
-
1.225
2.250
2.875
3.000
1.000
-
0.715
0.425
7.800
9.100
12.600
12.100
-
-
-
0.100
1.325
2.350
2.975
3.1000
0.0335
0.0059
0.0242
0.0128
0.2992
0.3503
0.4882
0.4685
-
-
-
-
0.0443
0.0846
0.1093
0.1142
-
-
0.0262
0.0148
0.3031
0.3543
0.4921
0.4724
0.0295
56
60
-
0.0482
0.0886
0.1132
0.1181
0.0394
-
0.0281
0.0167
0.3071
0.3583
0.4961
0.4764
-
-
-
0.0039
0.0522
0.0925
0.1171
0.1220
Datasheet
17


GT28F128W30 (Intel)
Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
3.2 W30 – 0.13 mm Lithography
Figure 4. 32-, 64- and 128-Mbit VF BGA CSP Package Drawing
Ball A1
Corner
D
Ball A1
Corner
S1
1 23 4 56 7 8
A
B
C
ED
E
F
G
Top View - Bump Side Down
A1
A2
8 7 6 5 4 3 21
A
B
C
D
E
F
G
b
Bottom View- Ball Side Up
e
S2
A
Seating
Plane
Y
Dimension
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Width (32 Mb, 64 Mb)
Package Body Width (128 Mb)
Package Body Length (32 Mb, 64 Mb, 128 Mb)
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D (32 Mb, 64 Mb)
Corner to Ball A1 Distance Along D (128 Mb)
Corner to Ball A1 Distance Along E (32 Mb, 64 Mb,128
Mb)
Symbol
A
A1
A2
b
D
D
E
[e]
N
Y
S1
S1
S2
Millimeters
Inches
Min Nom Max Min Nom Max
-
0.150
-
0.325
-
-
0.665
0.375
1.000
-
-
0.425
-
0.0059
-
0.0128
-
-
0.0262
0.0148
0.0394
-
-
0.0167
7.600 7.700 7.800 0.2992 0.3031 0.3071
10.900 11.000 11.100 0.4291 0.4331 0.4370
8.900 9.000 9.100 0.3504 0.3543 0.3583
- 0.750 -
- 0.0295 -
- 56 -
- 56 -
- - 0.100 - - 0.0039
1.125 1.225 1.325 0.0443 0.0482 0.0522
2.775 2.2875 2.975 0.1093 0.1132 0.1171
2.150 2.250 2.350 0.0846 0.0886 0.0925
18 Datasheet


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Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
Figure 5. 64Mbit and 128Mbit QUAD+ Package Drawing
A1 Index
Mark
12 34 56 7 8
A
B
C
D
E
F
G
H
J
K
L
M
E
A
B
C
D
E
F
D
G
H
J
K
L
M
S1
8 7 6 5 4 3 21
S2
e
b
Top View - Ball Down
A2
A1
Bottom View - Ball Up
A
Y
Drawing not to scale.
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Symbol
A
A1
A2
b
D
E
e
N
Y
S1
S2
Min
0.200
0.325
9.900
7.900
1.100
0.500
Millimeters
Nom Max Notes
1.200
0.860
0.375
10.000
8.000
0.800
88
1.200
0.600
0.425
10.100
8.100
0.100
1.300
0.700
Min
0.0079
0.0128
0.3898
0.3110
0.0433
0.0197
Inches
Nom
0.0339
0.0148
0.3937
0.3150
0.0315
88
0.0472
0.0236
Max
0.0472
0.0167
0.3976
0.3189
0.0039
0.0512
0.0276
Datasheet
19


GT28F128W30 (Intel)
Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
4.0 Ballout and Signal Descriptions
4.1 Signal Ballout
The W30 is available in the 56-ball VF BGA and µBGA Chip Scale Package with 0.75 mm ball
pitch, or the QUAD+ SCSP package. Figure 6 shows the VF BGA and µBGA package ballout.
Figure 7 shows the QUAD+ package ballout.
Figure 6. 56-Ball VF BGA/ µBGA Ballout
12345678
87654321
A
A11
A8 vSS
vCC
vPP
A18
A6
A4
B
A12
A9
A20
CLK
RST# A17
A5
A3
C
A13
A10
A21 ADV# WE# A19
A7 A2
D
A15
E
A14
WAIT
A16
D12 WP#
A22
A1
VCCQ
D15
D6
D4
D2 D1
CE#
A0
F
VSS
D14
D13
D11
D10
D9
D0 OE#
G
D7
VSSQ
D5
vCC
D3
VCCQ
D8
VSSQ
A4
A6 A18
vPP
vCC
VSS
A8
A3
A5 A17
RST# CLK
A20
A9
A2
A7
A19
WE#
ADV#
A21
A10
A1 A22 WP# D12 A16 WAIT A14
A0
CE#
D1
D2 D4 D6
D15
OE# D0 D9
D10
D11
D13
D14
VSSQ
D8 VCCQ
D3
VCC
D5
VSSQ
A
A11
B
A12
C
A13
D
A15
E
VCCQ
F
VSS
G
D7
Top View - Ball Side Down
Complete Ink Mark Not Shown
Bottom View - Ball Side Up
NOTES:
1. On lower density devices, upper address balls can be treated as NC. (i.e., on 32-Mbit density, A22 and A21 are NC).
2. See Appendix C, “Ordering Information” on page 96 for mechanical specifications for the package.
20 Datasheet


GT28F128W30 (Intel)
Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
Figure 7. 88-Ball (80 active balls) QUAD+ Ballout
123 4567 8
A DU DU
DU DU
B
A4 A18 A19 VSS F1-VCC F2-VCC A21 A11
C
A5 R-LB# A23 VSS S-CS2 CLK A22 A12
D
A3
A17
A24
F-VPP,
F-VPEN
R-WE# P1-CS#
A9
A13
E
A2 A7 A25 F-WP# ADV# A20 A10 A15
F
A1
A6 R-UB# F-RST# F-WE# A8
A14 A16
G
A0 D8 D2 D10 D5 D13 WAIT F2-CE#
H
R-OE# D0 D1 D3 D12 D14 D7 F2-OE#
J
S-CS1# F1-OE# D9 D11 D4 D6 D15 VCCQ
K
F1-CE# P2-CS# F3-CE# S-VCC
P-VCC F2-VCC
VCCQ
P-Mode,
P-CRE
L
VSS VSS VCCQ F1-VCC VSS VSS VSS VSS
M DU DU
DU DU
Top View - Ball Side Down
Legend:
SRAM/PSRAM specific
Global
Flash specific
NOTES:
1. On lower density devices, upper address balls can be treated as NC (i.e., on 64-Mb density, A[25:23]are NC)
2. See Appendix C, “Ordering Information” on page 96 for mechanical specifications for the package.
Datasheet
21


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Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
4.2 Signal Descriptions
Table 4 describes the signals.
Table 4. Signal Descriptions
Symbol
A[22:0]
D[15:0]
ADV#
CE#
CLK
OE#
RST#
WAIT
WE#
WP#
VPP
VCC
VCCQ
VSS
VSSQ
DU
NC
Type
Name and Function
Input
Input/
Output
Input
Input
Input
Input
Input
Output
Input
Input
Power/
Input
Power
Power
Power
Power
ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during reads.
Data pins are High-Z when the device or outputs are deselected. Data is internally latched during
writes.
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on the rising edge of ADV#, or the next valid CLK edge with
ADV# low, whichever occurs first.
CHIP ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.
De-asserting CE# deselects the device, places it in standby mode, and tri-states all outputs.
CLOCK: CLK synchronizes the device to the system bus frequency during synchronous reads and
increments an internal address generator. During synchronous read operations, addresses are latched
on ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.
OUTPUT ENABLE: When asserted, OE# enables the device’s output data buffers during a read cycle.
When OE# is deasserted, data outputs are placed in a high-impedance state.
RESET: When low, RST# resets internal automation and inhibits write operations. This provides data
protection during power transitions. de-asserting RST# enables normal operation and places the
device in asynchronous read-array mode.
WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to be
asserted-high or asserted-low based on bit 10 of the Read Configuration Register. WAIT is tri-stated if
CE# is deasserted. WAIT is not gated by OE#.
WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the
rising edge of WE#.
WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See
Section 13.1, “Block Lock Operations” on page 69 for details on block locking.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when VPP VPPLK. Block erase and program at invalid VPP voltages should
not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPP1 min. VPP must remain above VPP1
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V may reduce block cycling capability.
DEVICE POWER SUPPLY: Writes are inhibited at VCC VLKO. Device operations at invalid VCC
voltages should not be attempted.
OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ.
GROUND: Pins for all internal device circuitry must be connected to system ground.
OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied
directly to VSS.
DO NOT USE: Do not use this pin. This pin should not be connected to any power supplies, signals or
other pins and must be floated.
NO CONNECT: No internal connection; can be driven or floated.
22 Datasheet


GT28F128W30 (Intel)
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Intel® Wireless Flash Memory (W30)
5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended,
and extended exposure beyond the “Operating Conditions” may affect device reliability.
Notice: This datasheet contains information on products in the design phase of development. The information
here is subject to change without notice. Do not finalize a design with this information.
Table 5. Absolute Maximum Ratings
Parameter
Note
Maximum Rating
Temperature under Bias
–40 °C to +85 °C
Storage Temperature
–65 °C to +125 °C
Voltage on Any Pin (except VCC, VCCQ, VPP)
VPP Voltage
VCC Voltage
VCCQ Voltage
Output Short Circuit Current
1,2,3
1
1
4
–0.5 V to +3.8 V
–0.2 V to +14 V
–0.2 V to +2.45 V
–0.2 V to +3.8 V
100 mA
NOTES:
1. All specified voltages are relative to VSS. Minimum DC voltage is –0.5 V on input/output pins and
–0.2 V on VCC and VPP pins. During transitions, this level may undershoot to –2.0 V for periods < 20
ns. Maximum DC voltage on input/output pins is VCC +0.5 V which, during transitions, may overshoot
to VCC +2.0 V for periods < 20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.
3. VPP program voltage is normally VPP1. VPP can be 12 V ± 0.6 V for 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks during program/erase.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5.2 Operating Conditions
Table 6. Extended Temperature Operation (Sheet 1 of 2)
Symbol
Parameter1
Note
TA
VCC
VCCQ
VPP1
VPP2
tPPH
Operating Temperature
VCC Supply Voltage
I/O Supply Voltage
VPP Voltage Supply (Logic Level)
Factory Programming VPP
Maximum VPP Hours
VPP = 12 V
3
3
2
2
2
Min
–40
1.7
2.2
0.90
11.4
-
Nom
25
1.8
3.0
1.80
12.0
-
Max
Unit
85 °C
1.90
3.3
1.95
V
12.6
80 Hours
Datasheet
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Intel® Wireless Flash Memory (W30)
Table 6. Extended Temperature Operation (Sheet 2 of 2)
Symbol
Parameter1
Note
Min
Nom
Max
Unit
Block
Erase
Cycles
Main and Parameter
Blocks
Main Blocks
Parameter Blocks
VPP VCC
VPP = 12 V
VPP = 12 V
2 100,000
2-
2-
-
-
-
-
1000
2500
Cycles
NOTES:
1. See Section 6.1, “DC Current Characteristics” on page 25 and Section 6.2, “DC Voltage Characteristics” on
page 26 for specific voltage-range specifications.
2. VPP is normally VPP1. VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks for
extended temperatures and 2500 cycles on parameter blocks at extended temperature.
3. Contact your Intel field representative for VCC/VCCQ operations down to 1.65 V.
4. See the tables in Section 6.0, “Electrical Specifications” on page 25 and in Section 7.0, “AC
Characteristics” on page 27 for operating characteristics
24 Datasheet


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Intel® Wireless Flash Memory (W30)
6.0 Electrical Specifications
6.1 DC Current Characteristics
Table 7. DC Current Characteristics (Sheet 1 of 2)
Sym
Parameter (1)
VCCQ= 3.0 V
Note 32/64 Mbit 128 Mbit
Unit
Test Condition
ILI Input Load
ILO
Output
Leakage
DQ[15:0]
.18 µm
ICCS
.13 µm
ICCS
VCC Standby
.18 µm
ICCAPS
.13 µm
ICCAPS
APS
Asynchronous
Page Mode
f=13 MHz
ICCR
Average
VCC
Read
Synchronous
CLK = 40 MHz
ICCW VCC Program
ICCE VCC Block Erase
ICCWS VCC Program Suspend
ICCES VCC Erase Suspend
IPPS
(IPPWS
,
IPPES)
VPP Standby
VPP Program Suspend
VPP Erase Suspend
IPPR VPP Read
Typ Max Typ Max
VCC = VCCMax
9 - ±2 - ±2 µA VCCQ = VCCQMax
VIN = VCCQ or GND
VCC = VCCMax
- ±10 - ±10 µA VCCQ = VCCQMax
VIN = VCCQ or GND
6 21 6 30
VCC = VCCMax
10
µA
VCCQ = VCCQMax
CE# = VCCQ
8 50 8 70
RST# =VCCQ
6 21 6 30
VCC = VCCMax
VCCQ = VCCQMax
11 µA CE# = VSSQ
8 50 8 70
RST# =VCCQ
All other inputs =VCCQ or VSSQ
2 4 7 4 10 mA 4 Word Read
7 15 7 15 mA Burst length = 4
9 16 9 16 mA Burst length = 8
2 11 19 11 19 mA Burst length =16
VCC = VCCMax
CE# = VIL
OE# = VIH
Inputs = VIH or VIL
12
22
12
22
mA
Burst length =
Continuous
18 40 18 40 mA VPP = VPP1, Program in Progress
3,4,5
8 15 8 15 mA VPP = VPP2, Program in Progress
18 40 18 40 mA VPP = VPP1, Block Erase in Progress
3,4,5
8 15 8 15 mA VPP = VPP2, Block Erase in Progress
6 6 21 6 30 µA CE# = VCC, Program Suspended
6 6 21 6 30 µA CE# = VCC, Erase Suspended
3 0.2 5 0.2 5 µA VPP <VCC
2 15 2 15 µA VPP VCC
Datasheet
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Intel® Wireless Flash Memory (W30)
Table 7. DC Current Characteristics (Sheet 2 of 2)
Sym
Parameter (1)
VCCQ= 3.0 V
Note 32/64 Mbit 128 Mbit
Unit
Test Condition
Typ Max Typ Max
IPPW VPP Program
0.05 0.10 0.05 0.10
VPP = VPP1, Program in Progress
4 mA
8 22 16 37
VPP = VPP2, Program in Progress
IPPE
VPP Erase
0.05 0.10 0.05 0.10
VPP = VPP1, Erase in Progress
4 mA
8 22 8 22
VPP = VPP2, Erase in Progress
NOTES:
1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25°C.
2. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. See ICCRQ specification
for details.
3. Sampled, not 100% tested.
4. VCC read + program current is the sum of VCC read and VCC program currents.
5. VCC read + erase current is the sum of VCC read and VCC erase currents.
6. ICCES is specified with device deselected. If device is read while in erase suspend, current is ICCES plus ICCR.
7. VPP <= VPPLK inhibits erase and program operations. Don’t use VPPL and VPPH outside their valid ranges.
8. VIL can undershoot to –0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less.
9. If VIN>VCC the input load current increases to 10 µA max.
10.ICCS is the average current measured over any 5ms time interval 5µs after a CE# de-assertion.
11.Refer to section Section 8.2, “Automatic Power Savings (APS)” on page 44 for ICCAPS measurement details.
12.TBD values are to be determined pending silicon characterization.
6.2 DC Voltage Characteristics
Table 8. DC Voltage Characteristics
Sym Parameter (1) Note
VCCQ= 3.0 V
32/64 Mbit
128 Mbit
Unit Test Condition
Min Max Min Max
VIL Input Low
VIH Input High
8 0 0.4 0 0.4
VCCQ
– 0.4
VCCQ
VCCQ
– 0.4
VCCQ
V
V
VOL Output Low
VCC = VCCMin
- 0.1 - 0.1 V VCCQ = VCCQMin
IOL = 100 µA
VOH Output High
VCCQ
– 0.1
-
VCCQ
– 0.1
-
VCC = VCCMin
V VCCQ = VCCQMin
IOH = –100 µA
VPPLK VPP Lock-Out
7
-
0.4
-
0.4 V
VLKO
VCC Lock
1.0 - 1.0 - V
VILKOQ VCCQ Lock
0.9 - 0.9 - V
NOTE: For all numbered note references in this table, refer to the notes in Table 7, “DC Current
Characteristics” on page 25.
26 Datasheet


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Intel® Wireless Flash Memory (W30)
7.0 AC Characteristics
7.1 Read Operations - 0.13 µm Lithography
Table 9. Read Operations - 0.13 µm Lithography (Sheet 1 of 2)
# Sym
Parameter 1
32-Mbit
64-Mbit
-70 -85
128-Mbit
-70
Units Notes
Min Max Min Max Min Max
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read Cycle Time
Address to Output Valid
CE# Low to Output Valid
OE# Low to Output Valid
RST# High to Output Valid
CE# Low to Output Low-Z
OE# Low to Output Low-Z
CE# High to Output High-Z
OE# High to Output High-Z
CE# (OE#) High to Output Low-Z
Latching Specifications
R101
R102
R103
R104
R105
R106
R108
tAVVH
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
tAPA
Address Setup to ADV# High
CE# Low to ADV# High
ADV# Low to Output Valid
ADV# Pulse Width Low
ADV# Pulse Width High
Address Hold from ADV# High
Page Address Access Time
Clock Specifications
R200
R201
R202
R203
fCLK
tCLK
tCH/L
tCHCL
CLK Frequency
CLK Period
CLK High or Low Time
CLK Fall or Rise Time
70 - 85 - 70 -
- 70 - 85 - 70
- 70 - 85 - 70
- 30 - 30 - 30
- 150 - 150 - 150
0-0-0-
0-0-0-
- 20 - 20 - 20
- 14 - 14 - 14
0-0-0-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
6
6
3
4
3,4
4
3,4
3,4
10 - 10 - 12 -
10 - 10 - 12 -
- 70
85 - 70
10 - 10 - 12 -
10 - 10 - 12 -
9-9-9-
- 25 - 25 - 25
ns
ns
ns
ns
ns
ns
ns
6
2
- 40 - 33 - 40 MHz
25 - 30 - 25 -
ns
9.5 - 9.5 - 9.5 -
ns
- 3 - 5 - 5 ns
Datasheet
27


GT28F128W30 (Intel)
Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
Table 9. Read Operations - 0.13 µm Lithography (Sheet 2 of 2)
# Sym
Parameter 1
32-Mbit
64-Mbit
-70 -85
128-Mbit
-70
Units Notes
Min Max Min Max Min Max
Synchronous Specifications
R301 tAVCH Address Valid Setup to CLK
9 - 9 - 10 - ns
R302 tVLCH ADV# Low Setup to CLK
10 - 10 - 10 -
ns
R303 tELCH CE# Low Setup to CLK
9 - 9 - 9 - ns
R304 tCHQV CLK to Output Valid
- 20 - 22 - 20 ns
R305 tCHQX Output Hold from CLK
5 - 5 - 5 - ns
R306 tCHAX Address Hold from CLK
10 - 10 - 10 -
ns
R307 tCHTV CLK to WAIT Valid
- 20 - 22 - 22 ns
R308 tELTV CE# Low to WAIT Valid
- 20 - 22 - 22 ns
R309 tEHTZ CE# High to WAIT High-Z
- 25 - 25 - 25 ns
R310 tEHEL CE# Pulse Width High
20 - 20 - 20 -
ns
NOTES:
1. See Figure 22, “AC Input/Output Reference Waveform” on page 47 for timing measurements and maximum
allowable input slew rate.
2. Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied
first.
3. OE# may be delayed by up to tELQV – tGLQV after the falling edge of CE# without impact to tELQV.
4. Sampled, not 100% tested.
5. Applies only to subsequent synchronous reads.
6. During the initial access of a synchronous burst read, data from the first word may begin to be driven onto the data
bus as early as the first clock edge after tAVQV.
2
5
4,5
5
28 Datasheet


GT28F128W30 (Intel)
Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
7.2 Read Operations - 0.18 µm Lithography
Table 10. Read Operations - 0.18 µm Lithography (Sheet 1 of 2)
# Sym
Parameter 1
32-Mbit
64-Mbit
-70 -85
128-Mbit
-90
Units Notes
Min Max Min Max Min Max
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read Cycle Time
Address to Output Valid
CE# Low to Output Valid
OE# Low to Output Valid
RST# High to Output Valid
CE# Low to Output Low-Z
OE# Low to Output Low-Z
CE# High to Output High-Z
OE# High to Output High-Z
CE# (OE#) High to Output Low-Z
Latching Specifications
R101
R102
R103
R104
R105
R106
R108
tAVVH
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
tAPA
Address Setup to ADV# High
CE# Low to ADV# High
ADV# Low to Output Valid
ADV# Pulse Width Low
ADV# Pulse Width High
Address Hold from ADV# High
Page Address Access Time
Clock Specifications
R200
R201
R202
R203
fCLK
tCLK
tCH/L
tCHCL
CLK Frequency
CLK Period
CLK High or Low Time
CLK Fall or Rise Time
70 - 85 - 90 -
- 70 - 85 - 90
- 70 - 85 - 90
- 30 - 30 - 30
- 150 - 150 - 150
0-0-0-
0-0-0-
- 20 - 20 - 20
- 14 - 14
14
0-0-0-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
6
6
3
4
3.4
4
3,4
3,4
10 - 10 - 12 -
10 - 10 - 12 -
- 70 - 85 - 90
10 - 10 - 12 -
10 - 10 - 12 -
9-9-9-
- 25 - 25 - 30
ns
ns
ns
ns
ns
ns
ns
6
2
- 40 - 33 - 33 MHz
25 - 30 - 30 -
ns
9.5 - 9.5 - 9.5 -
ns
-3
5 - 5 ns
Datasheet
29


GT28F128W30 (Intel)
Wireless Flash Memory

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Intel® Wireless Flash Memory (W30)
Table 10. Read Operations - 0.18 µm Lithography (Sheet 2 of 2)
# Sym
Parameter 1
32-Mbit
64-Mbit
-70 -85
128-Mbit
-90
Units Notes
Min Max Min Max Min Max
Synchronous Specifications
R301 tAVCH Address Valid Setup to CLK
9 - 9 - 10 - ns
R302 tVLCH ADV# Low Setup to CLK
10 - 10 - 10 -
ns
R303 tELCH CE# Low Setup to CLK
9 - 9 - 9 - ns
R304 tCHQV CLK to Output Valid
- 20 - 22 - 22 ns
R305 tCHQX Output Hold from CLK
5-5
5 - ns
R306 tCHAX Address Hold from CLK
10 - 10 - 10 -
ns
R307 tCHTV CLK to WAIT Valid
- 20 - 22 - 22 ns
R308 tELTV CE# Low to WAIT Valid
- 20 - 22 - 22 ns
R309 tEHTZ CE# High to WAIT High-Z
- 25 - 25 - 25 ns
R310 tEHEL CE# Pulse Width High
20 - 20 - 20 -
ns
NOTES:
1. See Figure 22, “AC Input/Output Reference Waveform” on page 47 for timing measurements and maximum
allowable input slew rate.
2. Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied
first.
3. OE# may be delayed by up to tELQV– tGLQV after the falling edge of CE# without impact to tELQV.
4. Sampled, not 100% tested.
5. Applies only to subsequent synchronous reads.
6. During the initial access of a synchronous burst read, data from the first word may begin to be driven onto the data
bus as early as the first clock edge after tAVQV.
2
5
4,5
5
30 Datasheet




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