TE28F400BV (Intel)
4-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY

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PRELIMINARY
4-MBIT (256K X 16, 512K X 8)
SmartVoltage BOOT BLOCK FLASH
MEMORY FAMILY
28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B
28F400CE-T/B, 28F004BE-T/B
n Intel SmartVoltage Technology
5V or 12V Program/Erase
2.7V, 3.3V or 5V Read Operation
Increased Programming Throughput
at 12V VPP
n Very High-Performance Read
5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
3V: 110/150/180 ns Max Access
65/90 ns Max. Output Enable Time
2.7V: 120 ns Max Access 65 ns Max.
Output Enable Time
n Low Power Consumption
Max 60 mA Read Current at 5V
Max 30 mA Read Current at
2.7V–3.6V
n x8/x16-Selectable Input/Output Bus
28F400 for High Performance 16- or
32-bit CPUs
n x8-Only Input/Output Architecture
28F004B for Space-Constrained
8-bit Applications
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
n Absolute Hardware-Protection for Boot
Block
n Software EEPROM Emulation with
Parameter Blocks
n Extended Temperature Operation
–40°C to +85°C
n Extended Cycling Capability
100,000 Block Erase Cycles
(Commercial Temperature)
10,000 Block Erase Cycles
(Extended Temperature)
n Automated Word/Byte Program and
Block Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
n Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
n Hardware Data Protection Feature
Write Lockout during Power
Transitions
n Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP: JEDEC ROM
Compatible
48-Lead TSOP
56-Lead TSOP
n Footprint Upgradeable from 2-Mbit and
to 8-Mbit Boot Block Flash Memories
n ETOX™ IV Flash Technology
July 1997
Order Number: 290530-005


TE28F400BV (Intel)
4-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY

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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B, 28F400CE-T/B, 28F004BE-T/B may contain design defects or errors
known as errata which may cause the product to deviate from published specifications. Current characterized errata are
available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intel’s Website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION, 1997
*Third-party brands and names are the property of their respective owners.
CG-041493


TE28F400BV (Intel)
4-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY

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4-MBIT SmartVoltage BOOT BLOCK FAMILY
CONTENTS
PAGE
1.0 PRODUCT FAMILY OVERVIEW .................... 5
1.1 New Features in the SmartVoltage
Products ..................................................... 5
1.2 Main Features.............................................. 5
1.3 Applications ................................................. 7
1.4 Pinouts......................................................... 7
1.5 Pin Descriptions......................................... 11
2.0 PRODUCT DESCRIPTION............................ 13
2.1 Memory Blocking Organization .................. 13
2.1.1 Boot Block........................................... 13
2.1.2 Parameter Blocks................................ 13
2.1.3 Main Blocks......................................... 13
3.0 PRODUCT FAMILY PRINCIPLES OF
OPERATION ................................................ 15
3.1 Bus Operations .......................................... 15
3.2 Read Operations........................................ 15
3.2.1 Read Array.......................................... 15
3.2.2 Intelligent Identifiers ............................ 17
3.3 Write Operations........................................ 17
3.3.1 Command User Interface (CUI)........... 17
3.3.2 Status Register ................................... 20
3.3.3 Program Mode .................................... 21
3.3.4 Erase Mode......................................... 21
3.4 Boot Block Locking .................................... 22
3.4.1 VPP = VIL for Complete Protection ....... 22
3.4.2 WP# = VIL for Boot Block Locking ....... 22
3.4.3 RP# = VHH or WP# = VIH forr Boot Block
Unlocking ........................................... 22
3.4.4 Upgrade Note for 8-Mbit 44-PSOP
Package............................................. 22
PAGE
3.5 Power Consumption...................................26
3.5.1 Active Power .......................................26
3.5.2 Automatic Power Savings (APS) .........26
3.5.3 Standby Power ....................................26
3.5.4 Deep Power-Down Mode.....................26
3.6 Power-Up/Down Operation.........................26
3.6.1 RP# Connected to System Reset ........26
3.6.2 VCC, VPP and RP# Transitions .............27
3.7 Power Supply Decoupling ..........................27
3.7.1 VPP Trace on Printed Circuit Boards....27
4.0 ABSOLUTE MAXIMUM RATINGS................28
5.0 COMMERCIAL OPERATING CONDITIONS .29
5.1 Applying VCC Voltages ...............................29
5.2 DC Characteristics .....................................30
5.3 AC Characteristics .....................................34
6.0 EXTENDED OPERATING CONDITIONS ......44
6.1 Applying VCC Voltages ...............................44
6.2 DC Characteristics .....................................45
6.3 AC Characteristics .....................................51
APENDIX A: Additional Information .................56
APPENDIX B: Additional Information...............57
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4-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY

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4-MBIT SmartVoltage BOOT BLOCK FAMILY
E
Number
-001
-002
-003
-004
-005
REVISION HISTORY
Description
Initial release of datasheet.
Status changed from Product Preview to Preliminary
28F400CV/CE/BE references and information added throughout.
2.7V CE/BE specs added throughout.
The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,
3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.
Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.
Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.
Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.
Sections 5.1, 6.1 changed to “Applying VCC Voltages.” These sections completely
changed to clarify VCC ramp requirements.
IPPD 3.3V Commercial spec changed from 10 to 5 µA.
Capacitance tables added after commercial and extended DC Characteristics tables.
Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.
Test configuration drawings (Fig. 14, 22) consolidated into one, with component
values in table. (Component values also rounded off).
tELFL, tELFH, tAVFL changed from 7 to 5 ns for 3.3V BV-60 commercial and 3.3V
TBV-80 extended, 10 to 5 ns for 3.3V BV-80 and BV-120 commercial.
tWHAX and tEHAX changed from 10 to 0 ns.
tPHWL changed from 1000 ns to 800 ns for 3.3V BV-80, BV-120 commercial.
tPHEL changed from 1000 ns to 800 ns for 3.3V BV-60, BV-80, and BV-120 commercial.
28F400BE row removed from Table 1
Applying VCC voltages (Sections 5.1 and 6.1) rewritten for clarity.
Minor cosmetic changes/edits.
Corrections: Spec typographical error “tQWL” corrected to read “tQVVL.”
Intel386™ EX Microprocessor block diagram updated because latest Intel386 CPU
specs require less glue logic.
Spec tELFL and tELFH changed from 5 ns (max) to 0 ns (min).
New specs tPLPH and tPLQX added from Specification Update document (297595).
Specs tEHQZ and tGHQZ improved on most voltage/speed combinations.
Correction: Appendix A, Ordering information fixed order numbers from TE27F400BVT80
to TE28F400BVT80 and TE27F400BVB80 to TE28F400BVB80.
Updated disclaimer.
4 PRELIMINARY


TE28F400BV (Intel)
4-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY

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4-MBIT SmartVoltage BOOT BLOCK FAMILY
1.0 PRODUCT FAMILY OVERVIEW
This datasheet contains the specifications for the
two branches of products in the SmartVoltage
4-Mbit boot block flash memory family: the -BE/CE
suffix products feature a low VCC operating range
of 2.7V–3.6V; the -BV/CV suffix products offer
3.0V–3.6V operation. Both BE/CE and BV/CV
products also operate at 5V for high-speed access
times. Throughout this datasheet, the 28F400
refers to all x8/x16 4-Mbit products, while
28F004B refers to all x8 4-Mbit boot block
products. Also, the term “2.7V” generally refers to
the full voltage range 2.7V–3.6V. Section 1
provides an overview of the flash memory family
including applications, pinouts and pin
descriptions. Sections 2 and 3 describe the
memory organization and operation for these
products. Finally, Sections 4 and 5 contain the
family’s operating specifications.
1.1 New Features in the
SmartVoltage Products
The SmartVoltage boot block flash memory family
offers identical operation with the BX/BL 12V
program products, except for the differences listed
below. All other functions are equivalent to current
products, including signatures, write commands,
and pinouts.
WP# pin has replaced a DU (Don’t Use) pin.
Connect the WP# pin to control signal or to
VCC or GND (in this case, a logic-level signal
can be placed on DU pin). See Tables 2 and
9 to see how the WP# pin works.
5V program/erase operation has been added.
If switching VPP for write protection, switch to
GND (not 5V) for complete write protection. To
take advantage of 5V write-capability, allow for
connecting 5V to VPP and disconnecting 12V
from VPP line.
Enhanced circuits optimize low VCC
performance, allowing operation down to
VCC = 2.7V (using the BE product).
If you are using BX/BL 12V VPP boot block
products today, you should account for the
differences listed above and also allow for
connecting 5V to VPP and disconnecting 12V from
VPP line, if 5V writes are desired.
1.2 Main Features
Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash industry,
providing two discrete voltage supply pins: VCC for
read operation, and VPP for program and erase
operation. Discrete supply pins allow system
designers to use the optimal voltage levels for
their design. The 28F400BV/CV, 28F004BV,
28F400CE and 28F004BE provide program/erase
capability at 5V or 12V. The 28F400BV/CV and
28F004BV allow reads with VCC at 3.3 ± 0.3V or
5V, while the 28F400CE and 28F004BE allow
reads with VCC at 2.7V–3.6V or 5V. Since many
designs read from the flash memory a large
percentage of the time, read operation using the
2.7V or 3.3V ranges can provide great power
savings. If read performance is an issue, however,
5V VCC provides faster read access times.
Product
Name
28F004BV-T/B
28F400BV-T/B
28F400CV-T/B
28F004BE-T/B
28F400CE-T/B
Table 1. SmartVoltage Provides Total Voltage Flexibility
Bus
Width
2.7V–3.6V
VCC
3.3 ± 0.3V
5V ± 5%
5V ± 10%
VPP
5V ± 10% 12V ± 5%
x8 √ √ √ √
x8 or x16
√√√√
x8 or x16
√√√√
x8
√√√
x8 or x16
√√√
PRELIMINARY
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TE28F400BV (Intel)
4-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY

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For program and erase operations, 5V VPP
operation eliminates the need for in system voltage
converters, while 12V VPP operation provides faster
program and erase for situations where 12V is
available, such as manufacturing or designs where
12V is in-system. For design simplicity, however,
just hook up VCC and VPP to the same 5V ± 10%
source.
The 28F400/28F004B boot block flash memory
family is a high-performance, 4-Mbit (4,194,304 bit)
flash memory family organized as either
256 Kwords of 16 bits each (28F400 only) or
512 Kbytes of 8 bits each (28F400 and 28F004B).
Separately erasable blocks, including a hardware-
lockable boot block (16,384 bytes), two parameter
blocks (8,192 bytes each) and main blocks (one
block of 98,304 bytes and three blocks of 131,072
bytes), define the boot block flash family
architecture. See Figures 7 and 8 for memory
maps. Each block can be independently erased and
programmed 100,000 times at commercial
temperature or 10,000 times at extended
temperature.
The boot block is located at either the top (denoted
by -T suffix) or the bottom (-B suffix) of the address
map in order to accommodate different
microprocessor protocols for boot code location.
The hardware-lockable boot block provides
complete code security for the kernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.4 for details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications,
thereby unburdening the microprocessor or
microcontroller of these tasks. The Status Register
(SR) indicates the status of the WSM and whether it
successfully completed the desired program or
erase operation.
Program and Erase Automation allows program and
erase operations to be executed using an industry-
standard two-write command sequence to the CUI.
Data writes are performed in word (28F400 family)
or byte (28F400 or 28F004B families) increments.
Each byte or word in the flash memory can be
programmed independently of other memory
locations, unlike erases, which erase all locations
within a block simultaneously.
The 4-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
Savings (APS) feature which minimizes system
battery current drain, allowing for very low power
designs. To provide even greater power savings,
the boot block family includes a deep power-down
mode which minimizes power consumption by
turning most of the flash memory’s circuitry off.
This mode is controlled by the RP# pin and its
usage is discussed in Section 3.5, along with other
power consumption issues.
Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during
system reset and power-up/down sequences. For
example, when the flash memory powers-up, it
automatically defaults to the read array mode, but
during a warm system reset, where power
continues uninterrupted to the system components,
the flash memory could remain in a non-read mode,
such as erase. Consequently, the system Reset
signal should be tied to RP# to reset the memory to
normal read mode upon activation of the Reset
signal. See Section 3.6.
The 28F400 provides both byte-wide or word-wide
input/output, which is controlled by the BYTE# pin.
Please see Table 2 and Figure 16 for a detailed
description of BYTE# operations, especially the
usage of the DQ15/A–1 pin.
The 28F400 products are available in a
ROM/EPROM-compatible pinout and housed in the
44-lead PSOP (Plastic Small Outline) package, the
48-lead TSOP (Thin Small Outline, 1.2 mm thick)
package and the 56-lead TSOP as shown in
Figures 4, 5 and 6, respectively. The 28F004
products are available in the 40-lead TSOP
package as shown in Figure 3.
Refer to the DC Characteristics Table, Section 5.2
(commercial temperature) and Section 6.2
(extended temperature), for complete current and
voltage specifications. Refer to the AC
Characteristics Table, Section 5.3 (commercial
temperature) and Section 6.3 (extended
temperature), for read, write and erase performance
specifications.
6 PRELIMINARY


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4-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY

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4-MBIT SmartVoltage BOOT BLOCK FAMILY
1.3 Applications
The 4-Mbit boot block flash memory family
combines high-density, low-power, high-
performance, cost-effective flash memories with
blocking and hardware protection capabilities. Their
flexibility and versatility reduce costs throughout the
product life cycle. Flash memory is ideal for Just-In-
Time production flow, reducing system inventory
and costs, and eliminating component handling
during the production phase.
When your product is in the end-user’s hands, and
updates or feature enhancements become
necessary, flash memory reduces the update costs
by allowing user-performed code changes instead
of costly product returns or technician calls.
The 4-Mbit boot block flash memory family provides
full-function, blocked flash memories suitable for a
wide range of applications. These applications
include extended PC BIOS and ROM-able
applications storage, digital cellular phone program
and data storage, telecommunication boot/firmware,
printer firmware/font storage and various other
embedded applications where program and data
storage are required.
Reprogrammable systems, such as personal
computers, are ideal applications for the 4-Mbit
flash memory products. Increasing software
sophistication greatens the probability that a code
update will be required after the PC is shipped. For
example, the emerging of “plug and play” standard
in desktop and portable PCs enables auto-
configuration of ISA and PCI add-in cards.
However, since the “plug and play” specification
continues to evolve, a flash BIOS provides a cost-
effective capability to update existing PCs. In
addition, the parameter blocks are ideal for storing
the required auto-configuration parameters,
allowing you to integrate the BIOS PROM and
parameter storage EEPROM into a single
component, reducing parts costs while increasing
functionality.
The 4-Mbit flash memory products are also
excellent design solutions for digital cellular phone
and telecommunication switching applications
requiring very low power consumption, high-
performance, high-density storage capability,
modular software designs, and a small form factor
package. The 4-Mbit’s blocking scheme allows for
easy segmentation of the embedded code with
16 Kbytes of hardware-protected boot code, four
main blocks of program code and two parameter
blocks of 8 Kbytes each for frequently updated data
storage and diagnostic messages (e.g., phone
numbers, authorization codes).
Intel’s boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically-blocked
memory map allows the integration of several
memory components into a single flash device. The
boot block provides a secure boot PROM; the
parameter blocks can emulate EEPROM
functionality for parameter store with proper
software techniques; and the main blocks provide
code and data storage with access times fast
enough to execute code in place, decreasing RAM
requirements.
1.4 Pinouts
Intel’s SmartVoltage Boot Block architecture
provides upgrade paths in every package pinout to
the 8-Mbit density. The 28F004B 40-lead TSOP
pinout for space-constrained designs is shown in
Figure 3. The 28F400 44-lead PSOP pinout follows
the industry-standard ROM/EPROM pinout, as
shown in Figure 4. For designs that require x16
operation but have space concerns, refer to the
48-lead pinout in Figure 5. Furthermore, the 28F400
56-lead TSOP pinout shown in Figure 6 provides
density upgrades to future higher density boot block
memories.
Pinouts for the corresponding 2-Mbit and 8-Mbit
components are also provided for convenient
reference. 4-Mbit pinouts are given on the chip
illustration in the center, with 2-Mbit and 8-Mbit
pinouts going outward from the center.
PRELIMINARY
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A[18:1]
CS#
RD#
WR#
i386™ EX CPU
(25 MHz)
D[0:15]
RESET
A[0:17]
CE#
OE#
WE#
28F400BV-60
DQ[0:15]
RP#
RESET
NOTE:
A data bus buffer may be needed for processor speeds above 25 MHz.
Figure 1. 28F400 Interface to Intel386™ EX Microprocessor
0530_01
A[16:18]
A8-A15
80C188EB
ALE
AD0-AD7
ADDRESS
LATCHES
LE
ADDRESS
LATCHES
LE
A0 -A18
28F004-T
UCS#
WR#
RD#
RESIN#
P1.X
System Reset
DQ 0 -DQ 7
CE#
VCC
10K
WE#
OE#
RP#
VCC
VPP
P1.X
WP#
Figure 2. 28F004B Interface to Intel80C188EB 8-Bit Embedded Microprocessor
0530_02
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4-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY

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4-MBIT SmartVoltage BOOT BLOCK FAMILY
28F008B 28F002B
28F002B 28F008B
AA1165
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
A
A
16
15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
NC
A7
A6
A5
A4
A3
A2
A1
A
A
16
15
A 14
A 13
A 12
A 11
A9
A8
WE#
RP#
VPP
WP#
A 18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28F004B
Boot Block
40-Lead TSOP
10 mm x 20 mm
TOP VIEW
40 A17 A17 A17
39 GND GND GND
38 NC NC NC
37 NC NC A19
36 A10 A10 A10
35 DQ7 DQ7 DQ7
34 DQ6 DQ6 DQ6
33 DQ5 DQ5 DQ5
32 DQ4 DQ4 DQ4
31
VCC
VCC
VCC
30
VCC
VCC
VCC
29 NC NC NC
28 DQ3 DQ3 DQ3
27 DQ2 DQ2 DQ2
26 DQ1 DQ1 DQ1
25 DQ0 DQ0 DQ0
24 OE# OE# OE#
23 GND GND GND
22 CE# CE# CE#
21 A 0 A 0 A 0
0530_03
Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications
28F800 28F200
28F200
28F800
VPP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VPP
WP#
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VPP
WP#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RP#
RP#
RP#
43 WE#
WE#
WE#
42 A8
41 A9
40 A10
39 A11
38 A12
PA28F400
37 A13
Boot Block
36 A14
44-Lead PSOP
35 A15
0.525" x 1.110" 34 A16
33 BYTE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
BYTE#
32 GND
GND
GND
TOP VIEW
31 DQ15 /A -1 DQ15 /A -1 DQ15 /A -1
30 DQ7
DQ7
DQ7
29 DQ14
DQ14
DQ14
28 DQ6
DQ6
DQ6
27 DQ13
DQ13
DQ13
26 DQ5
DQ5
DQ5
25 DQ12
DQ12
DQ12
24 DQ4
DQ4
DQ4
23 VCC
VCC
VCC
0530_04
NOTE: Pin 2 is WP# on 2- and 4-Mbit devices but A18 on the 8-Mbit because no other pins were available for the high order
address. Thus, the 8-Mbit in the 44-lead PSOP cannot unlock the boot block without RP# = VHH (12V). To allow upgrades to
the 8 Mbit from 2/2 Mbit in this package, design pin 2 to control WP# at the 2/4 Mbit level and A18 at the 8-Mbit density. See
Section 3.4 for details.
Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards
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28F800
A 15
A 14
A 13
A12
A11
A 10
A9
A8
NC
NC
W E#
RP#
V PP
W P#
NC
A 18
A 17
A7
A6
A5
A4
A3
A2
A1
28F200
A 15
A 14
A 13
A12
A11
A 10
A9
A8
NC
NC
WE#
RP#
V PP
WP#
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
V PP
WP#
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28F400
Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
28F200
48 A16 A16
47 BYTE# BYTE#
46
GND
GND
45 DQ15 /A-1 DQ15 /A-1
44
DQ 7
DQ 7
43
DQ 14
DQ 14
42
DQ 6
DQ 6
41
DQ 13
DQ 13
40
DQ 5
DQ 5
39
DQ 12
DQ 12
38
DQ 4
DQ 4
37
V CC
V CC
36
DQ 11
DQ 11
35
DQ 3
DQ 3
34
DQ 10
DQ 10
33
DQ 2
DQ 2
32
DQ 9
DQ 9
31
DQ 1
DQ 1
30
DQ 8
DQ 8
29
DQ 0
DQ 0
28
OE#
OE#
27
GND
GND
26
CE#
CE#
25 A 0
A0
Figure 5. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation
28F800
A 16
BYTE#
GND
DQ15 /A-1
DQ 7
DQ 14
DQ 6
DQ 13
DQ 5
DQ 12
DQ 4
V CC
DQ 11
DQ 3
DQ 10
DQ 2
DQ 9
DQ 1
DQ 8
DQ 0
OE#
GND
CE#
A0
0530_05
28F200
NC
NC
A 15
A 14
A 13
A 12
A 11
A 10
A9
A8
NC
NC
WE#
RP#
NC
NC
VPP
WP#
NC
NC
A7
A6
A5
A4
A3
A2
A1
NC
28F200
NC
NC
A 15
A 14
A 13
A 12
A 11
A 10
A9
A8
NC
NC
WE#
RP#
NC
NC
VPP
WP#
NC
A 17
A7
A6
A5
A4
A3
A2
A1
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
28F400
56-Lead TSOP
Boot Block
14 mm x 20 mm
TOP VIEW
56 NC
55 A16
NC
A 16
54
BYTE#
BYTE#
53 GND
GND
52 DQ15/A -1 DQ15/A -1
51 DQ7
DQ7
50 DQ14 DQ14
49 DQ6
DQ6
48 DQ13 DQ13
47
46
DQ5
DQ12
DQ5
DQ12
45
44
43
DQ4
VCC
VCC
DQ4
VCC
VCC
42 DQ11 DQ11
41 DQ3
DQ3
40 DQ10 DQ10
39 DQ2
DQ2
38 DQ9
DQ9
37 DQ1
DQ1
36 DQ8
DQ8
35 DQ0
DQ0
34 OE#
OE#
33 GND
32 CE#
31 A 0
30 NC
GND
CE#
A0
NC
29 NC
NC
Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits
0530_06
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1.5 Pin Descriptions
Table 2. 28F400/004 Pin Descriptions
Symbol
A0–A18
A9
Type
INPUT
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle. The 28F400 only has A0– A17 pins, while the 28F004B
has A0– A18.
ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During
this mode, A0 decodes between the manufacturer and device IDs. When BYTE#
is at a logic low, only the lower byte of the signatures are read. DQ15/A–1 is a
don’t care in the signature mode when BYTE# is low.
DQ0–DQ7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, Intelligent Identifier and Status Register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
DQ8–DQ15
CE#
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ15/A–1 becomes the lowest order address for data output on DQ0–DQ7.
The 28F004B does not include these DQ8–DQ15 pins.
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.
OE#
INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during
a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WE# is active low. Addresses and data are latched on the rising edge of the WE#
pulse.
RP#
INPUT RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at VHH, the boot block is unlocked and can be programmed or
erased. This overrides any control from the WP# input.
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Symbol
WP#
BYTE#
VCC
VPP
GND
NC
Type
INPUT
INPUT
Table 2. 28F400/004 Pin Descriptions (Continued)
Name and Function
WRITE PROTECT: Provides a method for unlocking the boot block in a system
without a 12V supply.
When WP# is at logic low, the boot block is locked, preventing program and
erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the Status Register to indicate the operation
failed.
When WP# is at logic high, the boot block is unlocked and can be
programmed or erased.
NOTE: This feature is overridden and the boot block unlocked when RP# is at
VHH. See Section 3.4 for details on write protection.
BYTE# ENABLE: Not available on 28F004B. Controls whether the device
operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pin
must be controlled at CMOS levels to meet the CMOS current specification in the
standby mode.
When BYTE# is at logic low, the byte-wide mode is enabled, where data is
read and programmed on DQ0–DQ7 and DQ15/A–1 becomes the lowest order
address that decodes between the upper and lower byte. DQ8–DQ14 are tri-stated
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is
read and programmed on DQ0–DQ15.
DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3 ± 0.3V, 2.7V–3.6V (BE/CE only)
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5V ± 10% or 12V ± 5% must
be applied to this pin. When VPP < VPPLK all blocks are locked and protected
against Program and Erase commands.
GROUND: For all internal circuitry.
NO CONNECT: Pin may be driven or left floating.
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2.0 PRODUCT DESCRIPTION
2.1 Memory Blocking Organization
This product family features an asymmetrically-
blocked architecture providing system memory
integration. Each erase block can be erased
independently of the others up to 100,000 times for
commercial temperature or up to 10,000 times for
extended temperature. The block sizes have been
chosen to optimize their functionality for common
applications of nonvolatile storage. The combination
of block sizes in the boot block architecture allow
the integration of several memories into a single
chip. For the address locations of the blocks, see
the memory maps in Figures 4 and 5.
2.1.1
ONE 16-KB BOOT BLOCK
The boot block is intended to replace a dedicated
boot PROM in a microprocessor or microcontroller-
based system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address map
to accommodate different microprocessor protocols
for boot code location. This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot block is
controlled using a combination of the VPP, RP#, and
WP# pins, as is detailed in Section 3.4.
2.1.2
TWO 8-KB PARAMETER BLOCKS
The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the byte-
rewrite functionality of EEPROMs can be emulated.
These techniques are detailed in Intel’s application
note, AP-604 Using Intel’s Boot Block Flash
Memory Parameter Blocks to Replace EEPROM.
Each boot block component contains two parameter
blocks of 8 Kbytes (8,192 bytes) each. The
parameter blocks are not write-protectable.
2.1.3
ONE 96-KB + THREE 128-KB
MAIN BLOCKS
After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each 4-Mbit
device contains one 96-Kbyte (98,304 byte) block
and three 128-Kbyte (131,072 byte) blocks. See the
memory maps for each device for more information.
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28F400-T
28F400-B
3FFFFH
3E000H
3DFFFH
3D000H
3CFFFH
3C000H
3BFFFH
30000H
2FFFFH
20000H
1FFFFH
10000H
0FFFFH
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
3FFFFH
30000H
2FFFFH
20000H
1FFFFH
10000H
0FFFFH
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
00000H
00000H
0530_07
NOTE: Address = A[17:0]. In x8 operation, the least significant system address should be connected to A-1. Memory maps are
shown for x16 operation.
Figure 7. Word-Wide x16-Mode Memory Maps
28F004-T
28F004-B
7FFFFH
7C000H
7BFFFH
7A000H
79FFFH
78000H
77FFFH
60000H
5FFFFH
40000H
3FFFFH
20000H
1FFFFH
00000H
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
7FFFFH
60000H
5FFFFH
40000H
3FFFFH
20000H
1FFFFH
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH
00000H
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
NOTE: Address = A[18:0]. These memory maps apply to the 28F004B or the 28F400 in x8 mode.
Figure 8. Byte-Wide x8-Mode Memory Maps
0530_08
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3.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory combines EPROM functionality with
in-circuit electrical write and erase. The boot block
flash family utilizes a Command User Interface
(CUI) and automated algorithms to simplify write
and erase operations. The CUI allows for 100%
TTL-level control inputs, fixed power supplies
during erasure and programming, and maximum
EPROM compatibility.
When VPP < VPPLK, the device will only successfully
execute the following commands: Read Array,
Read Status Register, Clear Status Register and
intelligent identifier mode. The device provides
standard EPROM read, standby and output disable
operations. Manufacturer identification and device
identification data can be accessed through the CUI
or through the standard EPROM A9 high voltage
access (VID) for PROM programming equipment.
The same EPROM read, standby and output
disable functions are available when 5V or 12V is
applied to the VPP pin. In addition, 5V or 12V on
VPP allows write and erase of the device. All
functions associated with altering memory contents:
Program and Erase, Intelligent Identifier Read, and
Read Status are accessed via the CUI.
The internal Write State Machine (WSM) completely
automates program and erase, beginning operation
signaled by the CUI and reporting status through
the Status Register. The CUI handles the WE#
interface to the data and address latches, as well
as system status requests during WSM operation.
3.1 Bus Operations
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles. These bus operations are summarized in
Tables 3 and 4.
3.2 Read Operations
3.2.1
READ ARRAY
When RP# transitions from VIL (reset) to VIH, the
device will be in the read array mode and will
respond to the read control inputs (CE#, address
inputs, and OE#) without any commands being
written to the CUI.
When the device is in the read array mode, five
control signals must be controlled to obtain data at
the outputs.
RP# must be logic high (VIH)
WE# must be logic high (VIH)
BYTE# must be logic high or logic low
CE# must be logic low (VIL)
OE must be logic low (VIL)
In addition, the address of the desired location must
be applied to the address pins. Refer to Figures 15
and 16 for the exact sequence and timing of these
signals.
If the device is not in read array mode, as would be
the case after a program or erase operation, the
Read Mode command (FFH) must be written to the
CUI before reads can take place.
During system design, consideration should be
taken to ensure address and control inputs meet
required input slew rates of <10 ns as defined in
Figures 12 and 13.
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Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH)
Mode
Notes RP# CE# OE# WE# A9
A0 VPP
Read
1,2,3 VIH VIL VIL VIH
X
X
X
Output Disable
VIH VIL VIH VIH
X
X
X
Standby
VIH VIH
X
X
X
X
X
Deep Power-Down 9 VIL X X X X X X
Intelligent Identifier
(Mfr)
4 VIH VIL VIL VIH VID VIL X
Intelligent Identifier
(Device)
4,5 VIH VIL VIL VIH VID VIH
X
Write
6,7,8 VIH VIL VIH VIL
X
X
X
DQ0–15
DOUT
High Z
High Z
High Z
0089 H
See
Table 5
DIN
Mode
Read
Output
Disable
Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Notes RP# CE# OE# WE# A9
A0 A–1 VPP
1,2,3 VIH VIL VIL VIH
X
X
X
X
VIH VIL VIH VIH
X
X
X
X
DQ0–7
DOUT
High Z
DQ8–14
High Z
High Z
Standby
VIH VIH
X
X
X
X
X
X High Z High Z
Deep Power-
9
VIL X
X
X
X
X
X
X High Z High Z
Down
Intelligent
Identifier (Mfr)
4
VIH VIL VIL VIH VID VIL
X
X 89H High Z
Intelligent
Identifier
(Device)
4,5 VIH VIL VIL VIH VID VIH X
X See High Z
Table
5
Write
6,7,8 VIH VIL VIH VIL
X
X
X
X
DIN
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP.
3. See DC Characteristics for VPPLK, VPPH1, VPPH2, VHH, VID voltages.
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A17 = X, A1–A18 = X.
5. See Table 5 for device IDs.
6. Refer to Table 7 for valid DIN during a write operation.
7. Command writes for block erase or word/byte program are only executed when VPP = VPPH1 or VPPH2.
8. To write or erase the boot block, hold RP# at VHH or WP# at VIH. See Section 3.4.
9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
High Z
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3.2.2
INTELLIGENT IDENTIFIERS
To read the manufacturer and device codes, the
device must be in intelligent identifier read mode,
which can be reached using two methods: by
writing the intelligent identifier command (90H) or
by taking the A9 pin to VID. Once in intelligent
identifier read mode, A0 = 0 outputs the manu-
facturer’s identification code and A0 = 1 outputs the
device code. In byte-wide mode, only the lower byte
of the above signatures is read (DQ15/A–1 is a
“don’t care” in this mode). See Table 5 for product
signatures. To return to read array mode, write a
Read Array command (FFH).
Table 5. Intelligent Identifier Table
Product Mfr. ID
Device ID
-T -B
(Top Boot) (Bottom Boot)
28F400 0089 H 4470 H
4471 H
28F004 89 H
78 H
79 H
3.3 Write Operations
3.3.1
COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) is the interface
between the microprocessor and the internal chip
controller. Commands are written to the CUI using
standard microprocessor write timings. The
available commands are Read Array, Read
Intelligent Identifier, Read Status Register, Clear
Status Register, Erase and Program (summarized
in Tables 6 and 7). The three read modes are read
array, intelligent identifier read, and status register
read. For Program or Erase commands, the CUI
informs the Write State Machine (WSM) that a write
or erase has been requested. During the execution
of a Program command, the WSM will control the
programming sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase
suspend. After the WSM has completed its task, it
will set the WSM Status bit to a “1” (ready), which
indicates that the CUI can respond to its full
command set. Note that after the WSM has
returned control to the CUI, the CUI will stay in the
current command state until it receives another
command.
3.3.1.1
Command Function Description
Device operations are selected by writing specific
commands into the CUI. Tables 6 and 7 define the
available commands.
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Table 6. Command Codes and Descriptions
Code Device Mode
Decription
00 Invalid/ Unassigned commands that should not be used. Intel reserves the right to redefine
Reserved these codes for future functions.
FF Read Array Places the device in read array mode, so that array data will be output on the data
pins.
40 Program Sets the CUI into a state such that the next write will latch the Address and Data
Set-Up registers on the rising edge and begin the program algorithm. The device then
defaults to the read status mode, where the device outputs Status Register data
when OE# is enabled. To read the array, issue a Read Array command.
To cancel a program operation after issuing a Program Set-Up command, write all
1’s (FFH for x8, FFFFH for x16) to the CUI. This will return to read status register
mode after a standard program time without modifying array contents. If a program
operation has already been initiated to the WSM this command can not cancel that
operation in progress.
10 Alternate (See 40H/Program Set-Up)
Prog Set-Up
20
Erase
Prepares the CUI for the Erase Confirm command. If the next command is not an
Set-Up Erase Confirm command, then the CUI will set both the Program Status (SR.4) and
Erase Status (SR.5) bits of the Status Register to a “1,” place the device into the
read Status Register state, and wait for another command without modifying array
contents. This can be used to cancel an erase operation after the Erase Setup
command has been issued. If an operation has already been initiated to the WSM
this can not cancel that operation in progress.
D0
Erase
If the previous command was an Erase Set-Up command, then the CUI will latch
Resume/ address and data, and begin erasing the block indicated on the address pins.
Erase
During erase, the device will respond only to the Read Status Register and Erase
Confirm Suspend commands and will output Status Register data when OE# is toggled low.
Status Register data is updated by toggling either OE# or CE# low.
B0
Erase
Valid only while an erase operation is in progress and will be ignored in any other
Suspend circumstance. Issuing this command will begin to suspend erase operation. The
Status Register will indicate when the device reaches erase suspend mode. In this
mode, the CUI will respond only to the Read Array, Read Status Register, and
Erase Resume commands and the WSM will also set the WSM Status bit to a “1”
(ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input control pins except RP#, which will immediately shut down the
WSM and the remainder of the chip, if it is made active. During a suspend
operation, the data and address latches will remain closed, but the address pads
are able to drive the address into the read path. See Section 3.3.4.1.
70 Read Status Puts the device into the read Status Register mode, so that reading the device
Register outputs Status Register data, regardless of the address presented to the device.
The device automatically enters this mode after program or erase has completed.
This is one of the two commands that is executable while the WSM is operating.
See Section 3.3.2.
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Table 6. Command Codes and Descriptions (Continued)
Code Device Mode
Decription
50 Clear Status The WSM can only set the Program Status and Erase Status bits in the Status
Register Register to “1;” it cannot clear them to “0.”
The Status Register operates in this fashion for two reasons. The first is to give the
host CPU the flexibility to read the status bits at any time. Second, when
programming a string of bytes, a single Status Register query after programming
the string may be more efficient, since it will return the accumulated error status of
the entire string. See Section 3.3.2.1.
90 Intelligent Puts the device into the intelligent identifier read mode, so that reading the device
Identifier
will output the manufacturer and device codes. (A0 = 0 for manufacturer,
A0 = 1 for device, all other address inputs are ignored). See Section 3.2.2.
Command
Read Array
Intelligent Identifier
Read Status Register
Clear Status Register
Word/Byte Program
Alternate Word/Byte
Program
Block Erase/Confirm
Erase Suspend
Erase Resume
Table 7. Command Bus Definitions
First Bus Cycle
Note Oper Addr
Data
8 Write X
FFH
1 Write X
90H
2,4 Write
X
70H
3 Write X
50H
Write
PA
40H
6,7 Write
PA
10H
Second Bus Cycle
Oper
Addr
Data
Read
IA
IID
Read X SRD
Write
Write
PA
PA
PD
PD
6,7 Write
BA
20H Write
BA
D0H
5 Write X
B0H
Write
X
D0H
ADDRESS
BA = Block Address
IA = Identifier Address
PA = Program Address
X = Don’t Care
DATA
SRD = Status Register Data
IID = Identifier Data
PD = Program Data
NOTES:
1. Bus operations are defined in Tables 3 and 4.
2. IA = Identifier Address: A0 = 0 for manufacturer code, A0 = 1 for device code.
3. SRD - Data read from Status Register.
4. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and
device codes.
5. BA = Address within the block being erased.
6. PA = Address to be programmed. PD = Data to be programmed at location PA.
7. Either 40H or 10H commands is valid.
8. When writing commands to the device, the upper data bus [DQ8–DQ15] = X (28F400 only) which is either VIL or VIH, to
minimize current draw.
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Table 8. Status Register Bit Definition
WSMS
ESS
ES
DWS
VPPS
R
R
R
76543210
NOTES:
SR.7 =WRITE STATE MACHINE STATUS
1 = Ready
(WSMS)
0 = Busy
Check Write State Machine bit first to determine
Word/Byte program or Block Erase completion,
before checking Program or Erase Status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to
“1.” ESS bit remains set to “1” until an Erase
Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the
max number of erase pulses to the block and is
still unable to verify successful block erasure.
SR.4 = PROGRAM STATUS (DWS)
1 = Error in Byte/Word Program
0 = Successful Byte/Word Program
When this bit is set to “1,” WSM has attempted
but failed to program a byte or word.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP Status bit does not provide continuous
indication of VPP level. The WSM interrogates VPP
level only after the Byte Write or Erase command
sequences have been entered, and informs the
system if VPP has not been switched on. The VPP
Status bit is not guaranteed to report accurate
feedback between VPPLK and VPPH.
SR.2-SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use and should
be masked out when polling the Status Register.
3.3.2
STATUS REGISTER
The device Status Register indicates when a
program or erase operation is complete, and the
success or failure of that operation. To read the
Status Register write the Read Status (70H)
command to the CUI. This causes all subsequent
read operations to output data from the Status
Register until another command is written to the
CUI. To return to reading from the array, issue a
Read Array (FFH) command.
The Status Register bits are output on DQ0–DQ7, in
both byte-wide (x8) or word-wide (x16) mode. In the
word-wide mode the upper byte, DQ8–DQ15,
outputs 00H during a Read Status command. In the
byte-wide mode, DQ8–DQ14 are tri-stated and
DQ15/A–1 retains the low order address function.
Important: The contents of the Status Register
are latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if
Status Register contents change while being read.
CE# or OE# must be toggled with each subsequent
status read, or the Status Register will not indicate
completion of a program or erase operation.
When the WSM is active, the SR.7 register will
indicate the status of the WSM, and will also hold
the bits indicating whether or not the WSM was
successful in performing the desired operation.
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3.3.2.1
Clearing the Status Register
The WSM sets status bits 3 through 7 to “1,” and
clears bits 6 and 7 to “0,” but cannot clear status
bits 3 through 5 to “0.” Bits 3 through 5 can only be
cleared by the controlling CPU through the use of
the Clear Status Register (50H) command, because
these bits indicate various error conditions. By
allowing the system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively programming several bytes
or erasing multiple blocks in sequence) before
reading the Status Register to determine if an error
occurred during that series. Clear the Status
Register before beginning another command or
sequence. Note, again, that a Read Array
command must be issued before data can be read
from the memory or intelligent identifier.
3.3.3
PROGRAM MODE
Programming is executed using a two-write
sequence. The Program Setup command is written
to the CUI followed by a second write which
specifies the address and data to be programmed.
The WSM will execute a sequence of internally
timed events to:
1. Program the desired bits of the addressed
memory word or byte.
2. Verify that the desired bits are sufficiently
programmed.
Programming of the memory results in specific bits
within a byte or word being changed to a “0.”
If the user attempts to program “1”s, there will be no
change of the memory cell content and no error
occurs.
The Status Register indicates programming status:
while the program sequence is executing, bit 7 of
the Status Register is a “0.” The Status Register
can be polled by toggling either CE# or OE#. While
programming, the only valid command is Read
Status Register.
When programming is complete, the Program
Status bits should be checked. If the programming
operation was unsuccessful, bit 4 of the Status
Register is set to a “1” to indicate a Program
Failure. If bit 3 is set to a “1,” then VPP was not
within acceptable limits, and the WSM did not
execute the programming sequence.
The Status Register should be cleared before
attempting the next operation. Any CUI instruction
can follow after programming is completed;
however, reads from the Memory Array or
Intelligent Identifier cannot be accomplished until
the CUI is given the appropriate command.
3.3.4
ERASE MODE
To erase a block, write the Erase Set-Up and Erase
Confirm commands to the CUI, along with the
addresses identifying the block to be erased. These
addresses are latched internally when the Erase
Confirm command is issued. Block erasure results
in all bits within the block being set to “1.” Only one
block can be erased at a time.
The WSM will execute a sequence of internally
timed events to:
1. Program all bits within the block to “0.”
2. Verify that all bits within the block are
sufficiently programmed to “0.”
3. Erase all bits within the block to “1.”
4. Verify that all bits within the block are
sufficiently erased.
While the erase sequence is executing, bit 7 of the
Status Register is a “0.”
When the Status Register indicates that erasure is
complete, check the Erase Status bit to verify that
the erase operation was successful. If the Erase
operation was unsuccessful, bit 5 of the Status
Register will be set to a “1,” indicating an Erase
Failure. If VPP was not within acceptable limits after
the Erase Confirm command is issued, the WSM
will not execute an erase sequence; instead, bit 5 of
the Status Register is set to a “1” to indicate an
Erase Failure, and bit 3 is set to a “1” to identify that
VPP supply voltage was not within acceptable limits.
Clear the Status Register before attempting the
next operation. Any CUI instruction can follow after
erasure is completed; however, reads from the
Memory Array, Status Register, or Intelligent
Identifier cannot be accomplished until the CUI is
given the Read Array command.
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3.3.4.1
Suspending and Resuming Erase
Since an erase operation requires on the order of
seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in
order to read data from another block of the
memory. Once the erase sequence is started,
writing the Erase Suspend command to the CUI
requests that the WSM pause the erase sequence
at a predetermined point in the erase algorithm. The
Status Register will indicate if/when the erase
operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register command.
During erase suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to VIH, which
reduces active current draw.
To resume the erase operation, enable the chip by
taking CE# to VIL, then issuing the Erase Resume
command, which continues the erase sequence to
completion. As with the end of a standard erase
operation, the Status Register must be read,
cleared, and the next instruction issued in order to
continue.
3.4 Boot Block Locking
The boot block family architecture features a
hardware-lockable boot block so that the kernel
code for the system can be kept secure while the
parameter and main blocks are programmed and
erased independently as necessary. Only the boot
block can be locked independently from the other
blocks. The truth table, Table 9, clearly defines the
write protection methods.
3.4.1
VPP = VIL FOR COMPLETE
PROTECTION
For complete write protection of all blocks in the
flash device, the VPP programming voltage can be
held low. When VPP is below VPPLK, any program or
erase operation will result in a error in the Status
Register.
3.4.2
WP# = VIL FOR BOOT BLOCK
LOCKING
When WP# = VIL, the boot block is locked and any
program or erase operation to the boot block will
result in an error in the Status Register. All other
blocks remain unlocked in this condition and can be
programmed or erased normally. Note that this
feature is overridden and the boot block unlocked
when RP# = VHH.
3.4.3
RP# = VHH OR WP# = VIH FOR BOOT
BLOCK UNLOCKING
Two methods can be used to unlock the boot block:
1. WP# = VIH
2. RP# = VHH
If both or either of these two conditions are met, the
boot block will be unlocked and can be
programmed or erased.
3.4.4
UPGRADE NOTE FOR 8-MBIT
44-PSOP PACKAGE
If upgradability to 8M is required, note that the
8-Mbit in the 44-PSOP does not have a WP#
because no pins were available for the 8-Mbit
upgrade address. Thus, in this density-package
combination only, VHH (12V) on RP# is required to
unlock the boot block. Unlocking with a logic-level
signal is not possible. If this functionality is
required, and 12V is not available, consider using
the 48-TSOP package, which has a WP# pin and
can be unlocked with a logic-level signal. All other
density-package combinations have WP# pins.
Table 9. Write Protection Truth Table
VPP RP# WP#
Write Protection
Provided
VIL
VPPLK
X
VIL
X All Blocks Locked
X All Blocks Locked
(Reset)
VPPLK
VPPLK
VPPLK
VHH
VIH
VIH
X All Blocks Unlocked
VIL Boot Block Locked
VIH All Blocks Unlocked
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Start
Write 40H,
Word/Byte Address
Write Word/Byte
Data/Address
Read
Status Register
SR.7 = 1
?
NO
YES
Full Status
Check if Desired
Word/Byte Program
Complete
Bus
Operation
Write
Write
Command
Comments
Setup
Program
Program
Data = 40H
Addr = Word/Byte to Program
Data = Data to Program
Addr = Location to Program
Read
Status Register Data
Toggle CE# or OE#
to Update SRD.
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent word/byte program operations.
SR Full Status Check can be done after each word/byte program,
or after a sequence of word/byte programs.
Write FFH after the last program operation to reset device to
read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus
Operation
Command
Comments
SR.3=
1
0
SR.4 =
0
1
Word/Byte Program
Successful
VPP Range Error
Word/Byte Program
Error
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4
1 = Word/Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State Machine.
SR.4 is only cleared by the Clear Status Register command,
in cases where multiple bytes are programmed before full
status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0530_09
Figure 9. Automated Word/Byte Programming Flowchart
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Start
Write 20H,
Block Address
Write D0H and
Block Address
Read Status
Register
SR.7 =
0
Suspend Erase
Loop
NO
Suspend YES
Erase
1
Full Status
Check if Desired
Bus
Operation
Command
Comments
Write
Erase Setup
Data = 20H
Addr = Within Block to Be Erased
Write
Read
Erase
Confirm
Data = D0H
Addr = Within Block to Be Erased
Status Register Data Toggle CE#
or OE# to Update Status Register
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase, or after a
sequence of block erasures.
Write FFH after the last operation to reset device to read array mode.
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
0
1
SR.4,5 =
0
SR.5 =
0
1
VPP Range Error
Command Sequence
Error
Block Erase Error
Block Erase Successful
Bus
Operation
Command
Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Standby
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.5
1 = Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.5 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erase before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0530_10
Figure 10. Automated Block Erase Flowchart
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Start
Write B0H
Read
Status Register
SR.7 =
0
1
CSR.6 =
0
1
Write FFH
Erase Completed
Bus
Operation
Write
Command
Erase
Suspend
Read
Comments
Data = B0H
Addr = X
Status Register Data Toggle CE#
or OE# to Update SRD
Addr = X
Standby
Standby
Write
Read
Read Array
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.6
1 = Erase Suspended
0 = Erase Completed
Data = FFH
Addr = X
Read array data from block other
than the one being erased.
Write
Erase Resume
Data = D0H
Addr = X
Read Array Data
Done
Reading
NO
YES
Write D0H
Write FFH
Erase Resumed
Read Array Data
Figure 11. Erase Suspend/Resume Flowchart
0530_11
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3.5 Power Consumption
3.5.1
ACTIVE POWER
With CE# at a logic-low level and RP# at a logic-
high level, the device is placed in the active mode.
Refer to the DC Characteristics table for ICC current
values.
3.5.2
AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings (APS) provides low-
power operation during active mode. Power
Reduction Control (PRC) circuitry allows the device
to put itself into a low current state when not being
accessed. After data is read from the memory
array, PRC logic controls the device’s power
consumption by entering the APS mode where
typical ICC current is less than 1 mA. The device
stays in this static state with outputs valid until a
new location is read.
3.5.3
STANDBY POWER
With CE# at a logic-high level (VIH), and the CUI in
read mode, the memory is placed in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
(DQ0–DQ15 or DQ0–DQ7) are placed in a high-
impedance state independent of the status of the
OE# signal. When CE# is at logic-high level during
erase or program operations, the device will
continue to perform the operation and consume
corresponding active power until the operation is
completed.
3.5.4
DEEP POWER-DOWN MODE
The SmartVoltage boot block family supports a low
typical ICC in deep power-down mode, which turns
off all circuits to save power. This mode is activated
by the RP# pin when it is at a logic-low
(GND ± 0.2V). Note: BYTE# pin must be at CMOS
levels to meet the ICCD specification.
During read modes, the RP# pin going low de-
selects the memory and places the output drivers in
a high impedance state. Recovery from the deep
power-down state, requires a minimum access time
of tPHQV (see AC Characteristics table).
During erase or program modes, RP# low will abort
either erase or program operations, but the memory
contents are no longer valid as the data has been
corrupted by the RP# function. As in the read mode
above, all internal circuitry is turned off to achieve
the power savings.
RP# transitions to VIL, or turning power off to the
device will clear the Status Register.
3.6 Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since the
device is indifferent as to which power supply, VPP
or VCC, powers-up first. The CUI is reset to the read
mode after power-up, but the system must drop
CE# low or present a new address to ensure valid
data at the outputs.
A system designer must guard against spurious
writes when VCC voltages are above VLKO and VPP
is active. Since both WE# and CE# must be low for
a command write, driving either signal to VIH will
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled until RP# is brought to
VIH, regardless of the state of its control inputs. By
holding the device in reset (RP# connected to
system PowerGood) during power-up/down, invalid
bus conditions during power-up can be masked,
providing yet another level of memory protection.
3.6.1
RP# CONNECTED TO SYSTEM
RESET
The use of RP# during system reset is important
with automated write/erase devices because the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization would not occur because the flash
memory may be providing status information
instead of array data. Intel’s Flash memories allow
proper CPU initialization following a system reset
by connecting the RP# pin to the same RESET#
signal that resets the system CPU.
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3.6.2
VCC, VPP AND RP# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from deep power-down mode,
or after VCC transitions above VLKO (Lockout
voltage), is read array mode.
After any word/byte write or block erase operation is
complete and even after VPP transitions down to
VPPLK, the CUI must be reset to read array mode
via the Read Array command if accesses to the
flash memory are desired.
Please refer to Intel’s application note AP-617
Additional Flash Data Protection Using VPP, RP#,
and WP#, for a circuit-level discription of how to
implement the protection discussed in Section 3.6.
3.7 Power Supply Decoupling
Flash memory’s power switching characteristics
require careful device decoupling methods. System
designers should consider three supply current
issues:
1. Standby current levels (ICCS)
2. Active current levels (ICCR)
3. Transient peaks produced by falling and rising
edges of CE#.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 µF ceramic
capacitor connected between each VCC and GND,
and between its VPP and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
3.7.1
VPP TRACE ON PRINTED CIRCUIT
BOARDS
Designing for in-system writes to the flash memory
requires special consideration of the VPP power
supply trace by the printed circuit board designer.
The VPP pin supplies the flash memory cells current
for programming and erasing. One should use
similar trace widths and layout considerations given
to the VCC power supply trace. Adequate VPP
supply traces, and decoupling capacitors placed
adjacent to the component, will decrease spikes
and overshoots.
NOTE:
Table headings in Sections 5 and 6 (i.e., BV-60, BV-80, BV-120, TBV-80, TBE-120) refer to the
specific products listed below. See Appendix A for more information on product naming and line items.
Abbreviation
Applicable Product Names
BV-60
E28F004BV-T60, E28F004BV-B60, PA28F400BV-T60, PA28F400BV-B60,
E28F400CV-T60, E28F400CV-B60, E28F400BV-T60, E28F400BV-B60
BV-80
E28F004BV-T80, E28F004BV-B80, PA28F400BV-T80, PA28F400BV-B80,
E28F400CV-T80, E28F400CV-B80, E28F400BV-T80, E28F400BV-B80
BV-120 E28F004BV-T120, E28F004BV-B120, PA28F400BV-T120, PA28F400BV-B120
TBV-80
TE28F004BV-T80, TE28F004BV-B80, TB28F400BV-T80, TB28F400BV-B80,
TE28F400CV-T80, TE28F400CV-B80, TE28F400BV-T80, TE28F400BV-B80
TBE-120 TE28F004BE-T120, TE28F004BE-B120, TE28F400CE-T120, TE28F400CE-B120
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4.0 ABSOLUTE MAXIMUM
RATINGS*
Commercial Operating Temperature
During Read .................................0°C to +70°C
During Block Erase
and Word/Byte Program ...............0°C to +70°C
Temperature Bias.....................–10°C to +80°C
Extended Operating Temperature
During Read .............................–40°C to +85°C
During Block Erase
and Word/Byte Program ...........–40°C to +85°C
Temperature Under Bias ..........–40°C to +85°C
Storage Temperature....................–65°C to +125°C
Voltage on Any Pin
(except VCC, VPP, A9 and RP#)
with Respect to GND..............–2.0V to +7.0V(2)
Voltage on Pin RP# or Pin A9
with Respect to GND......... –2.0V to +13.5V(2,3)
VPP Program Voltage with Respect
to GND during Block Erase
and Word/Byte Program .... –2.0V to +14.0V(2,3)
VCC Supply Voltage
with Respect to GND..............–2.0V to +7.0V(2)
Output Short Circuit Current ................... 100 mA (4)
NOTICE: This datasheet contains preliminary information on
new products in production. Do not finalize a design with
this information. Revised information will be published when
the product is available. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
design.
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.
NOTES:
1. Operating temperature is for commercial product
defined by this specification.
2. Minimum DC voltage is –0.5V on input/output pins.
During transitions, this level may undershoot to –2.0V
for periods
<20 ns. Maximum DC voltage on input/output pins is
VCC + 0.5V which, during transitions, may overshoot to
VCC + 2.0V for periods <20 ns.
3. Maximum DC voltage on VPP may overshoot to +14.0V
for periods <20 ns. Maximum DC voltage on RP# or A9
may overshoot to 13.5V for periods <20 ns.
4. Output shorted for no more than one second. No more
than one output shorted at a time.
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5.0 COMMERCIAL OPERATING CONDITIONS
Symbol
Table 10. Commercial Temperature and VCC Operating Conditions
Parameter
Notes
Min
Max
Units
TA Operating Temperature
0 +70 °C
VCC 3.3V VCC Supply Voltage (± 0.3V)
3.0 3.6 Volts
5V VCC Supply Voltage (10%)
1
4.50
5.50
Volts
5V VCC Supply Voltage (5%)
2
4.75
5.25
Volts
NOTES:
1. 10% VCC specifications apply to the 60 ns, 80 ns and 120 ns product versions in their standard test configuration.
2. 5% VCC specifications apply to the 60 ns version in its high-speed test configuration.
5.1 Applying VCC Voltages
When applying VCC voltage to the device, a delay
may be required before initiating device operation,
depending on the VCC ramp rate. If VCC ramps
slower than 1V/100 µs (0.01 V/µs) then no delay is
required. If VCC ramps faster than 1V/100 µs (0.01
V/µs), then a delay of 2 µs is required before
initiating device operation. RP# = GND is
recommended during power-up to protect against
spurious write signals when VCC is between VLKO
and VCCMIN.
VCC Ramp Rate
Required Timing
1V/100 µs
No delay required.
> 1V/100 µs
A delay time of 2 µs is required before any device operation is initiated, including read
operations, command writes, program operations, and erase operations. This delay is
measured beginning from the time VCC reaches VCCMIN (3.0V for 3.3 ± 0.3V operation;
and 4.5V for 5V operation).
NOTES:
1. These requirements must be strictly followed to guarantee all other read and write specifications.
2. To switch between 3.3V and 5V operation, the system should first transition VCC from the existing voltage range to GND,
and then to the new voltage. Any time the VCC supply drops below VCCMIN, the chip may be reset, aborting any operations
pending or in progress.
3. These guidelines must be followed for any VCC transition from GND.
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5.2 DC Characteristics
Table 11. DC Characteristics (Commercial)
Prod
BV-60
BV-80
BV-120
Sym
Parameter
VCC 3.3 ± 0.3V
5V ± 10% Unit
Test Conditions
Note Typ Max Typ Max
IIL Input Load Current
1
± 1.0
± 1.0
µA VCC = VCC Max
VIN = VCC or GND
ILO Output Leakage Current 1
± 10
± 10
µA VCC = VCC Max
VIN = VCC or GND
ICCS VCC Standby Current
1,3 0.4 1.5 0.8 2.0 mA VCC = VCC Max
CE# = RP# = BYTE# =
WP# = VIH
60 110 50 130 µA VCC = VCC Max
CE# = RP# = VCC ±
0.2V
ICCD VCC Deep Power-Down 1 0.2 8 0.2 8 µA VCC = VCC Max
Current
VIN = VCC or GND
RP# = GND ± 0.2V
ICCR VCC Read Current for 1,5,6 15 30 50 60 mA CMOS INPUTS
Word or Byte
VCC = VCC Max
CE# = GND, OE# = VCC
f = 10 MHz (5V)
5 MHz (3.3V)
IOUT = 0 mA, Inputs =
GND ± 0.2V or VCC
± 0.2V
15 30 55 65 mA TTL INPUTS
VCC = VCC Max
CE# = VIL, OE# = VIH
f = 10 MHz (5V)
5 MHz (3.3V)
IOUT = 0 mA, Inputs =
VIL or VIH
ICCW
VCC Program Current for
Word or Byte
1,4
13
30
30
50
mA VPP = VPPH1 (at 5V)
Program in Progress
10 25 30 45 mA VPP = VPPH2 (at 12V)
Program in Progress
ICCE VCC Erase Current
1,4 13 30 18 35 mA VPP = VPPH1 (at 5V)
Block Erase in Progress
10 25 18 30 mA VPP = VPPH2 (at 12V)
Block Erase in Progress
30 PRELIMINARY




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