JS28F128J3C (Intel)
StrataFlash Memory

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Intel StrataFlash® Memory (J3)
256-Mbit (x8/x16)
Product Features
Datasheet
Performance
Architecture
— 110/115/120/150 ns Initial Access Speed — Multi-Level Cell Technology: High
— 125 ns Initial Access Speed (256 Mbit
density only)
— 25 ns Asynchronous Page mode Reads
— 30 ns Asynchronous Page mode Reads
(256Mbit density only)
— 32-Byte Write Buffer
—6.8 µs per byte effective
programming time
Software
Density at Low Cost
— High-Density Symmetrical 128-Kbyte
Blocks
—256 Mbit (256 Blocks) (0.18µm only)
—128 Mbit (128 Blocks)
64 Mbit (64 Blocks)
—32 Mbit (32 Blocks)
Quality and Reliability
— Operating Temperature:
-40 °C to +85 °C
— Program and Erase suspend support
— 100K Minimum Erase Cycles per Block
— Flash Data Integrator (FDI), Common
Flash Interface (CFI) Compatible
Security
— 128-bit Protection Register
—64-bit Unique Device Identifier
—64-bit User Programmable OTP Cells
— Absolute Protection with VPEN = GND
— Individual Block Locking
— Block Erase/Program Lockout during
Power Transitions
— 0.18 µm ETOX™ VII Process (J3C)
— 0.25 µm ETOX™ VI Process (J3A)
Packaging and Voltage
— 56-Lead TSOP Package
— 64-Ball Intel® Easy BGA Package
— Lead-free packages available
— 48-Ball Intel® VF BGA Package (32 and
64 Mbit) (x16 only)
— VCC = 2.7 V to 3.6 V
— VCCQ = 2.7 V to 3.6 V
Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash® Memory (J3)
device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256-
Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-
per-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed
interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future
devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes
advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components
are ideal for code and data applications where high density and low cost are required. Examples include
networking, telecommunications, digital set top boxes, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from
existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash®
memory (28F640J5 and 28F320J5) devices.
J3 memory components deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density
upgrades and optimized write capabilities of future Intel StrataFlash® memory devices. Manufactured on Intel®
0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device
provides the highest levels of quality and reliability.
Notice: This document contains information on new products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
Order Number: 290667-021
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 3 Volt Intel StrataFlash® Memory may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2005, Intel Corporation. All rights reserved.
Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
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Contents
Contents
1.0 Introduction....................................................................................................................................7
1.1 Nomenclature .......................................................................................................................7
1.2 Conventions..........................................................................................................................7
2.0 Functional Overview .....................................................................................................................8
2.1 Block Diagram ......................................................................................................................9
2.2 Memory Map .......................................................................................................................10
3.0 Package Information ...................................................................................................................11
3.1 56-Lead TSOP Package .....................................................................................................11
3.2 Easy BGA (J3) Package .....................................................................................................12
3.3 VF-BGA (J3) Package ........................................................................................................13
4.0 Ballout and Signal Descriptions ................................................................................................14
4.1 Easy BGA Ballout (32/64/128/256 Mbit) .............................................................................14
4.2 56-Lead TSOP (32/64/128/256 Mbit)..................................................................................15
4.3 VF BGA Ballout (32 and 64 Mbit) .......................................................................................15
4.4 Signal Descriptions .............................................................................................................16
5.0 Maximum Ratings and Operating Conditions...........................................................................18
5.1 Absolute Maximum Ratings ................................................................................................18
5.2 Operating Conditions ..........................................................................................................18
6.0 Electrical Specifications .............................................................................................................19
6.1 DC Current Characteristics .................................................................................................19
6.2 DC Voltage Characteristics.................................................................................................20
7.0 AC Characteristics ......................................................................................................................22
7.1 Read Operations.................................................................................................................22
7.2 Write Operations .................................................................................................................26
7.3 Block Erase, Program, and Lock-Bit Configuration Performance .......................................27
7.4 Reset Operation..................................................................................................................29
7.5 AC Test Conditions.............................................................................................................29
7.6 Capacitance ........................................................................................................................30
8.0 Power and Reset Specifications ................................................................................................31
8.1 Power-Up/Down Characteristics.........................................................................................31
8.2 Power Supply Decoupling...................................................................................................31
8.3 Reset Characteristics..........................................................................................................31
9.0 Bus Operations ............................................................................................................................32
9.1 Bus Operations Overview ...................................................................................................32
9.1.1 Bus Read Operation ..............................................................................................33
9.1.2 Bus Write Operation ..............................................................................................33
9.1.3 Output Disable .......................................................................................................33
9.1.4 Standby..................................................................................................................34
9.1.5 Reset/Power-Down ................................................................................................34
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Contents
9.2 Device Commands ............................................................................................................. 35
10.0 Read Operations.......................................................................................................................... 37
10.1
10.2
10.3
Read Array.......................................................................................................................... 37
10.1.1 Asynchronous Page Mode Read ........................................................................... 37
10.1.2 Enhanced Configuration Register (ECR)............................................................... 38
Read Identifier Codes ......................................................................................................... 39
10.2.1 Read Status Register............................................................................................. 39
Read Query/CFI.................................................................................................................. 41
11.0 Programming Operations ........................................................................................................... 42
11.1
11.2
11.3
11.4
Byte/Word Program ............................................................................................................ 42
Write to Buffer..................................................................................................................... 42
Program Suspend............................................................................................................... 43
Program Resume................................................................................................................ 43
12.0 Erase Operations......................................................................................................................... 44
12.1 Block Erase......................................................................................................................... 44
12.2 Block Erase Suspend ......................................................................................................... 44
12.3 Erase Resume .................................................................................................................... 45
13.0 Security Modes ............................................................................................................................ 46
13.1
13.2
13.3
13.4
Set Block Lock-Bit............................................................................................................... 46
Clear Block Lock-Bits.......................................................................................................... 46
Protection Register Program .............................................................................................. 47
13.3.1 Reading the Protection Register............................................................................ 47
13.3.2 Programming the Protection Register.................................................................... 47
13.3.3 Locking the Protection Register............................................................................. 47
Array Protection .................................................................................................................. 49
14.0 Special Modes.............................................................................................................................. 50
14.1 Set Read Configuration Register Command ...................................................................... 50
14.2 Status (STS) ....................................................................................................................... 50
Appendix A Common Flash Interface.................................................................................................52
Appendix B Flow Charts ......................................................................................................................59
Appendix C Design Considerations ...................................................................................................68
Appendix D Additional Information ....................................................................................................70
Appendix E Ordering Information.......................................................................................................71
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Contents
Revision History
Date of
Revision
07/07/99
08/03/99
09/07/99
12/16/99
03/16/00
06/26/00
2/15/01
04/13/01
Version
Description
-001
-002
-003
-004
-005
-006
-007
-008
Original Version
A0–A2 indicated on block diagram
Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte Mode
currents. Modified RP# on AC Waveform for Write Operations
Changed Block Erase time and tAVWH
Removed all references to 5 V I/O operation
Corrected Ordering Information, Valid Combinations entries
Changed Min program time to 211 µs
Added DU to Lead Descriptions table
Changed Chip Scale Package to Ball Grid Array Package
Changed default read mode to page mode
Removed erase queuing from Figure 10, Block Erase Flowchart
Added Program Max time
Added Erase Max time
Added Max page mode read current
Moved tables to correspond with sections
Fixed typographical errors in ordering information and DC parameter table
Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2
Added recommended resister value for STS pin
Change operation temperature range
Removed note that rp# could go to 14 V
Removed VOL of 0.45 V; Removed VOH of 2.4 V
Updated ICCR Typ values
Added Max lock-bit program and lock times
Added note on max measurements
Updated cover sheet statement of 700 million units to one billion
Corrected Table 10 to show correct maximum program times
Corrected error in Max block program time in section 6.7
Corrected typical erase time in section 6.7
Updated cover page to reflect 100K minimum erase cycles
Updated cover page to reflect 110 ns 32M read speed
Removed Set Read Configuration command from Table 4
Updated Table 8 to reflect reserved bits are 1-7; not 2-7
Updated Table 16 bit 2 definition from R to PSS
Changed VPENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC
Characteristics
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5,
AC Characteristics–Read-Only Operations (1,2)
Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section 6.6, AC
Characteristics–Write Operations
Updated Max. Program Suspend Latency W16 (tWHRH1) from 30 to 75 µs,
Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance
(1,2,3)
Revised Section 7.0, Ordering Information
Datasheet
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Contents
Date of
Revision
07/27/01
10/31/01
03/21/02
Version
-009
-010
-011
Description
Added Figure 4, 3 Volt Intel StrataFlash® Memory VF BGA Package (32 Mbit)
Added Figure 5, 3 Volt Intel StrataFlash® Memory VF BGA Mechanical
Specifications
Updated Operating Temperature Range to Extended (Section 6.1 and Table 22)
Reduced tEHQZ to 35 ns. Reduced tWHEH to 0 ns
Added parameter values for –40 °C operation to Lock-Bit and Suspend Latency
Updated VLKO and VPENLK to 2.2 V
Removed Note #4, Section 6.4 and Section 6.6
Minor text edits
Added notes under lead descriptions for VF BGA Package
Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Characteristics
Removed byte mode read current row un DC characteristics
Added ordering information for VF BGA Package
Minor text edits
Changed datasheet to reflect the best known methods
Updated max value for Clear Block Lock-Bits time
Minor text edits
12/12/02
01/24/03
12/09/03
1/3/04
1/23/04
1/23/04
5/19/04
7/7/04
11/23/04
3/24/05
-012
-013
-014
-015
-016
-016
-018
-019
-020
-021
Added nomenclature for J3C (0.18 µm) devices.
Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128
Mb J3C device. Added “TE” package designator for J3C TSOP package.
Revised Asynchronous Page Read description. Revised Write-to-Buffer flow
chart. Updated timing waveforms. Added 256-Mbit J3C pinout.
Added 256Mbit device timings, device ID, and CFI information. Also corrected
VLKO specification.
Corrected memory block count from 257 to 255.
Memory block count fix.
Restructured the datasheet layout.
Added lead-free part numbers and 8-word page information.
Added Note to DC Voltage Characteristics table; “Speed Bin” to Read Operations
table; Corrected format for AC Waveform for Reset Operation figure; Corrected
“R” and “8W” headings in Enhanced Configuration Register table because they
were transposed; Added 802 and 803 to ordering information and corrected 56-
Lead TSOP combination number.
Corrected ordering information.
6 Datasheet


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1.0
1.1
1.2
256-Mbit J3 (x8/x16)
Introduction
This document describes the Intel StrataFlash® Memory (J3) device. It includes a description of
device features, operations, and specifications.
Nomenclature
AMIN:
AMAX:
Block:
Clear:
CUI:
MLC:
OTP:
PLR:
PR:
PRD
Program:
RFU:
Set:
SR:
SRD:
VPEN:
VPEN:
WSM:
ECR:
XSR:
AMIN = A0 for x8
AMIN = A1 for x16
32 Mbit AMAX = A21
64 Mbit AMAX = A22
128 Mbit AMAX = A23
256 Mbit AMAX = A24
A group of flash cells that share common erase circuitry and erase simultaneously
Indicates a logic zero (0)
Command User Interface
Multi-Level Cell
One Time Programmable
Protection Lock Register
Protection Register
Protection Register Data
To write data to the flash array
Reserved for Future Use
Indicates a logic one (1)
Status Register
Status Register Data
Refers to a signal or package connection name
Refers to timing or voltage levels
Write State Machine
Extended Configuration Register
eXtended Status Register
Conventions
0x:
0b:
k (noun):
M (noun):
Nibble
Byte:
Word:
Kword:
Kb:
KB:
Mb:
MB:
Brackets:
Hexadecimal prefix
Binary prefix
1,000
1,000,000
4 bits
8 bits
16 bits
1,024 words
1,024 bits
1,024 bytes
1,048,576 bits
1,048,576 bytes
Square brackets ([]) will be used to designate group membership or to define a
group of signals with similar function (i.e., A[21:1], SR[4,1] and D[15:0]).
Datasheet
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256-Mbit J3 (x8/x16)
2.0
Functional Overview
The Intel StrataFlash® memory family contains high-density memories organized as 32 Mbytes or
16Mwords (256-Mbit, available on the 0.18µm lithography process only), 16 Mbytes or 8 Mwords
(128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These
devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundred-
twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixty-
four 128-Kbyte erase blocks while the 32-Mbit device contains thirty-two 128-Kbyte erase blocks.
A 128-bit Protection Register has multiple uses, including unique flash device identification.
The device’s optimized architecture and interface dramatically increases read performance by
supporting page-mode reads. This read mode is ideal for non-clock memory systems.
A Common Flash Interface (CFI) permits software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-
compatible software support for the specified flash device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work
with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest
system/device data transfer rates and minimizes device and system-level implementation costs.
A Command User Interface (CUI) serves as the interface between the system processor and
internal operation of the device. A valid command sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase, program, and lock-bit configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second—
independent of other blocks. Each block can be independently erased 100,000 times. Block erase
suspend mode allows system software to suspend block erase to read or program data from any
other block. Similarly, program suspend allows system software to suspend programming (byte/
word program and write-to-buffer operations) to read data or execute code from any other block
that is not being suspended.
Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming
performance. By using the Write Buffer, data is programmed in buffer increments. This feature can
improve system program performance more than 20 times over non-Write Buffer writes.
Blocks are selectively and individually lockable in-system.Individual block locking uses block
lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations.
Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block
Lock-Bits commands).
The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration
operation is finished.
The STS (STATUS) output gives an additional indicator of WSM activity by providing both a
hardware signal of status (versus software polling) and status masking (interrupt masking for
background block erase, for example). Status indication using STS minimizes both CPU overhead
and system power consumption. When configured in level mode (default mode), it acts as a RY/
BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lock-
bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is
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256-Mbit J3 (x8/x16)
suspended (and programming is inactive), program is suspended, or the device is in reset/power-
down mode. Additionally, the configuration command allows the STS signal to be configured to
pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design (see
Table 13, “Chip Enable Truth Table” on page 33) reduces decoder logic typically required for
multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-
chip miniature card or SIMM module.
The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit
mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit
operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A
device block diagram is shown in Figure 4 on page 14.
When the device is disabled (see Table 13 on page 33), with CEx at VIH and RP# at VIH, the
standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which
minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is
required from RP# going high until data outputs are valid. Likewise, the device has a wake time
(tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset
and the Status Register is cleared.
2.1 Block Diagram
Figure 1. 3 Volt Intel StrataFlash® Memory Block Diagram
D[15:0]
VCCQ
A[2:0]
A[MAX:MIN]
Input Buffer
Address
Latch
Address
Counter
Y-Decoder
X-Decoder
Output
Buffer
Input Buffer
Query
Identifier
Register
Status
Register
Data
Comparator
Multiplexer
Y-Gating
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Mbit: One-hundred
twenty-eight
128-Kbyte Blocks
Command
User
Interface
I/O Logic
CE
Logic
VCC
BYTE#
CE0
CE1
CE2
WE#
OE#
RP#
Write State
Machine
Program/Erase
Voltage Switch
STS
VPEN
VCC
GND
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256-Mbit J3 (x8/x16)
2.2 Memory Map
Figure 2. Intel StrataFlash® Memory (J3) Memory Map
A[24-0]: 256 Mbit
A [23-0]:128 Mbit
A [22-0]: 64 Mbit
A [21-0]: 32 Mbit
A[24-1]: 256 Mbit
A [23-1]: 128 Mbit
A [22-1]: 64 Mbit
A [21-1]: 32 Mbit
1FFFFFF
1FE0000
128-Kbyte Block 255
FFFFFF
FF0000
64-Kword Block 255
0FFFFFF
0FE0000
128-Kbyte Block 127
7FFFFF
7F0000
64-Kword Block 127
07FFFFF
07E0000
128-Kbyte Block 63
03FFFFF
03E0000
128-Kbyte Block 31
003FFFF
0020000
001FFFF
0000000
128-Kbyte Block 1
128-Kbyte Block 0
Byte-Wide (x8) Mode
3FFFFF
3F0000
64-Kword Block 63
1FFFFF
1F0000
64-Kword Block 31
01FFFF
010000
00FFFF
000000
64-Kword Block
64-Kword Block
1
0
Word Wide (x16) Mode
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3.0 Package Information
256-Mbit J3 (x8/x16)
3.1 56-Lead TSOP Package
Figure 3. 56-Lead TSOP Package Drawing and Specifications
Pin 1
Z
See Notes 1 and 3
See Note 2
A2
e
E See Detail B
D1
D
See Detail A
Y
A1
Seating
Plane
A
Detail A
C
Detail B
0
L
b
Table 1. 56-Lead TSOP Dimension Table
Millimeters
Package Height
Standoff
Package Body Thickness
Lead Width
Lead Thickness
Package Body Length
Package Body Width
Lead Pitch
Terminal Dimension
Lead Tip Length
Lead Count
Lead Tip Angle
Seating Plane Coplanarity
Lead to Package Offset
Sym
A
A1
A2
b
c
D1
E
e
D
L
N
Y
Z
Min
0.050
0.965
0.100
0.100
18.200
13.800
19.800
0.500
0.150
Nom
0.995
0.150
0.150
18.400
14.000
0.500
20.00
0.600
56
0.250
Max
1.200
1.025
0.200
0.200
18.600
14.200
20.200
0.700
0.100
0.350
Datasheet
Notes
4
4
Min
0.002
0.038
0.004
0.004
0.717
0.543
0.780
0.020
0.006
Inches
Nom
Max
0.047
0.039
0.006
0.006
0.724
0.551
0.0197
0.787
0.024
56
0.010
0.040
0.008
0.008
0.732
0.559
0.795
0.028
0.004
0.014
Notes
4
4
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256-Mbit J3 (x8/x16)
3.2 Easy BGA (J3) Package
Figure 4. Intel StrataFlash® Memory (J3) Easy BGA Mechanical Specifications
Ball A1
Corner
D
Ball A1
Corner
S1
12 3 4 5 6 7 8
A
B
C
D
E
E
F
G
H
Top View - Ball side down
8 7 6 5 4 3 21
A
B
C
D
E
F
G
H
Bottom View - Ball Side Up
S2
b
e
A1
A2
A Seating
Plane
Y
Note: Drawing not to scale
Table 2. Easy BGA Package Dimensions
Millimeters
Inches
Symbol Min
Package Height
A
Ball Height
A1
Package Body Thickness
A2
Ball (Lead) Width
b
Package Body Width (32 Mb, 64 Mb, 128 Mb, 256 Mb) D
Package Body Length (32 Mb, 64 Mb, 128 Mb)
E
Package Body Length (256 Mb)
E
Pitch
[e]
Ball (Lead) Count
N
Seating Plane Coplanarity
Y
Corner to Ball A1 Distance Along D (32/64/128/256 Mb) S1
Corner to Ball A1 Distance Along E (32/64/128 Mb)
S2
Corner to Ball A1 Distance Along E (256 Mb)
S2
0.250
0.330
9.900
12.900
14.900
1.400
2.900
3.900
Nom
0.780
0.430
10.000
13.000
15.000
1.000
64
1.500
3.000
4.000
Max
1.200
0.530
10.100
13.100
15.100
0.100
1.600
3.100
4.100
Notes Min
0.0098
0.0130
1 0.3898
1 0.5079
1 0.5866
1 0.0551
1 0.1142
1 0.1535
Nom
0.0307
0.0169
0.3937
0.5118
0.5906
0.0394
64
0.0591
0.1181
0.1575
Max
0.0472
0.0209
0.3976
0.5157
0.5945
0.0039
0.0630
0.1220
0.1614
NOTES:
1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at;
www.intel.com/design/packtech/index.htm
2. For Packaging Shipping Media information see www.intel.com/design/packtech/index.htm
12 Datasheet


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StrataFlash Memory

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256-Mbit J3 (x8/x16)
3.3 VF-BGA (J3) Package
Figure 5. Intel StrataFlash® Memory (J3) VF BGA Mechanical Specifications
Ball A1
Corner
D
S1
B all A1
C o rn e r
12345 678
A
B
C
ED
E
F
8 7 6 5 4 3 21
A
B
C
D
E
F
b
e
S2
T o p V ie w - B u m p S id e D o w n
A1
A2
S ide V iew
B o tt o m V ie w - B a ll S id e U p
A S e ating
P la n e
Y
N o te : D r a w in g n o t t o s ca le
D im ension s T able
M illim e te rs
In ch es
S y m b o l M in N o m M a x N o te s M in
Pa ckag e H eigh t
A 1.000
Ba ll H e ig h t
A 1 0.150
0.0059
Pa ckag e B o d y T h ickn es s
A 2 0 .6 6 5
Ba ll (Le a d ) W id th
b 0 .3 2 5 0 .3 7 5 0 . 4 2 5
0.0128
D 7 .1 8 6 7 .2 8 6 7 . 3 8 6 1 0 .2 8 2 9
Pa ckag e B o d y Len g th
E 1 0 .75 0 10 . 8 5 0 1 0 .9 5 0 1 0 .4 2 3 2
Pitc h [ e ] 0 .7 5 0
Ba ll (Le a d ) C o u n t
N 48
Se a tin g P la n e C o p la n a r ity
Y 0.100
Co r n e r to B a ll A 1 D is ta n c e A lo n g D
S 1 0 .9 1 8 1 .0 1 8 1 . 1 1 8 1 0 .0 3 6 1
Co r n e r to B a ll A 1 D is ta n c e A lo n g E
S 2 3 .4 5 0 3 .5 5 0 3 . 6 5 0 1 0 .1 3 5 8
N o te : ( 1) P a c k a ge d im e n sio ns a re f o r r e f e re n c e o nly . T h e se d im e n sio ns a re e st im a te s ba s e d o n d ie siz e ,
an d are su bject to ch ang e.
N om
0 .0 26 2
0 .0 14 8
0 .2 86 8
0 .4 27 2
0 .0 29 5
48
0 .0 40 1
0 .1 39 8
M ax
0.0394
0.0167
0.2908
0.4311
0.0039
0.0440
0.1437
NOTES:
1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web
page at; www.intel.com/design/packtech/index.htm
2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page
at; www.intel.com/design/packtech/index.htm
Datasheet
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256-Mbit J3 (x8/x16)
4.0 Ballout and Signal Descriptions
Intel StrataFlash® memory is available in three package types. Each density of the J3C is supported
on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. A 48-ball
VF BGA package is available on 32 and 64 Mbit devices. Figure 6, Figure 7, and Figure 8 show the
pinouts.
4.1 Easy BGA Ballout (32/64/128/256 Mbit)
Figure 6. Intel StrataFlash® Memory Easy BGA Ballout (32/64/128/256 Mbit)
1 23 4 56 78
A
A1 A6 A8 VPEN A13 VCC A18 A22
B
A2 VSS A9 CEO# A14 RFU A19 CE1#
C
A3 A7 A10 A12 A15 RFU A20 A21
D
A4 A5 A11 RP# RFU RFU A16 A17
E
D8 D1 D9 D3 D4 RFU D15 STS
F
BYTE# D0 D10 D11 D12 RFU RFU OE#
G
A23
128M
H
A0
D2 VCCQ D5
D6 D14 WE#
CE2# RFU VCC VSS D13 VSS D7 A24
256M
Easy BGA
Top View- Ball side down
8 765 43 2 1
A
A22 A18 VCC A13 VPEN A8 A6 A1
B
CE1# A19 RFU A14 CEO# A9 VSS A2
C
A21 A20 RFU A15 A12 A10 A7 A3
D
A17 A16 RFU RFU RP# A11 A5 A4
E
STS D15 RFU D4 D3 D9 D1 D8
F
OE# RFU RFU D12 D11 D10 D0 BYTE#
G
WE# D14 D6 D5 VCCQ D2 A0 A23
128M
H
A24
256M
D7 VSS D13 VSS VCC RFU CE2#
Easy BGA
Bottom View- Ball side up
NOTES:
1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC).
2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC).
3. Address A24 is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC).
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4.2 56-Lead TSOP (32/64/128/256 Mbit)
256-Mbit J3 (x8/x16)
Figure 7. Intel StrataFlash® Memory 56-Lead TSOP (32/64/128/256 Mbit)
28F160S3 28F320J5
NC
CE1
NC
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPP
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
NC
CE1
A21
A20
A19
A18
A17
A16
VCC(4)
A15
A14
A13
A12
CE0
VPEN
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
3 Volt Intel
StrataFlash
Memory
32/64/128M
A22(1)
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Highlights pinout changes
3 Volt Intel
StrataFlash® Memory
56-Lead TSOP
Standard Pinout
14 mm x 20 mm
Top View
3 Volt Intel
StrataFlash
Memory
32/64/128M
28F320J5 28F160S3
56
A24(3)
NC
WP#
55
WE#
WE#
WE#
54
OE#
OE#
OE#
53
STS
STS
STS
52
51
50
49
48
DQ15
DQ7
DQ14
DQ6
GND
DQ15
DQ7
DQ14
DQ6
GND
DQ15
DQ7
DQ14
DQ6
GND
47
46
45
44
43
42
DQ13
DQ5
DQ12
DQ4
VCCQ
GND
DQ13
DQ5
DQ12
DQ4
VCCQ
GND
DQ13
DQ5
DQ12
DQ4
VCC
GND
41
40
39
38
37
36
35
34
33
32
31
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
DQ11
DQ3
DDQQ120
VCC(4)
DDQQ19
DQ8
DQ0
A0
BYTE#
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
30
A23(2)
NC
NC
29
CE2
CE2
NC
NOTES:
1. A22 exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this signal is a no-connect (NC).
2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC).
3. A24 exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this signal is a no-connect (NC).
4. VCC = 5 V ± 10% for the 28F640J5/28F320J5.
4.3 VF BGA Ballout (32 and 64 Mbit)
Figure 8. Intel StrataFlash® Memory VF BGA Ballout (32 and 64 Mbit)
12 3 4 5 6 7 8
8 7 6 5 4 3 21
A
A14 A12 A9 VPEN VCC A20
B
A15 A11 WE# RP# A19 A18
C
A16 A13 A10 A22 A21 A7
D
A17 D14 D5 D11 D2 D8
E
VCCQ D15 D6 D12 D3 D9
F
VSS D7 D13 D4 VCC D10
A8
A6
A4
CE#
D0
D1
A5
A3
A2
A1
VSS
OE#
VFBGA6x8
TopView-Ball SideDown
A5
A3
A2
A1
VSS
OE#
A8
A6
A4
CE#
D0
D1
A20
A18
A7
D8
D9
D10
A
VCC VPEN A9 A12 A14
B
A19 RP# WE# A11 A15
C
A21 A22 A10 A13 A16
D
D2 D11 D5 D14 A17
E
D3 D12 D6 D15 VCCQ
F
VCC D4 D13 D7 VSS
VFBGA6x8
BottomView-Ball SideUp
NOTES:
1. CE# is equivalent to CE0, and CE1 and CE2 are internally grounded.
2. A22 exists on the 64 Mb density only. On the 32-Mbit density, this signal is a no-connect (NC).
3. STS not supported in this package.
4. x8 not supported in this package.
Datasheet
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256-Mbit J3 (x8/x16)
4.4 Signal Descriptions
Table 3 describes active signals used.
Table 3. Signal Descriptions (Sheet 1 of 2)
Symbol
A0
A[MAX:1]
D[7:0]
D[15:8]
CE0,
CE1,
CE2
RP#
OE#
WE#
STS
BYTE#
VPEN
VCC
VCCQ
Type
Name and Function
Input
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode.
This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer
is turned off when BYTE# is high).
Input
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle.
32-Mbit: A[21:0]
64-Mbit: A[22:0]
128-Mbit: A[23:0]
256-Mbit: A[24:0]
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs
Input/Output commands during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read
mode. Data is internally latched during write operations.
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Input/Output Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode
Input
CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. When the device is de-selected (see Table 13 on page 33), power reduces to standby
levels.
All timing specifications are the same for these three signals. Device selection occurs with the
first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first
edge of CE0, CE1, or CE2 that disables the device (see Table 13 on page 33).
Input
RESET/ POWER-DOWN: RP#-low resets internal automation and puts the device in power-
down mode. RP#-high enables normal operation. Exit from reset sets the device to read array
mode. When driven low, RP# inhibits write operations which provides data protection during
power transitions.
Input
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
Input
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active
low. Addresses and data are latched on the rising edge of WE#.
Open Drain
Output
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the STATUS signal,
see the Configurations command. STS is to be tied to VCCQ with a pull-up resistor.
Input
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0],
while D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-
high places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the
lowest-order address bit.
Input
Power
Power
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
With VPEN VPENLK, memory contents cannot be altered.
CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when VCC VLKO. Device operation at invalid Vcc voltages should not be attempted.
I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to VCC.
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256-Mbit J3 (x8/x16)
Table 3. Signal Descriptions (Sheet 2 of 2)
Symbol
GND
NC
RFU
Type
Supply
Name and Function
GROUND: Do not float any ground signals.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
RESERVED for FUTURE USE: Balls designated as RFU are reserved by Intel for future device
functionality and enhancement.
Datasheet
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256-Mbit J3 (x8/x16)
5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ratings
This datasheet contains information on new products in production. The specifications are subject
to change without notice. Verify with your local Intel Sales office that you have the latest datasheet
before finalizing a design. Absolute maximum ratings are shown in Table 4.
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
Table 4. Absolute Maximum Ratings
Parameter
Maximum Rating
Temperature under Bias Extended
–40 °C to +85 °C
Storage Temperature
Voltage On Any signal
Output Short Circuit Current
–65 °C to +125 °C
–2.0 V to +5.0 V(1)
100 mA(2)
NOTES:
1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output signals and
–0.2 V on VCC and VPEN signals. During transitions, this level may undershoot to –2.0 V for periods <20
ns. Maximum DC voltage on input/output signals, VCC, and VPEN is VCC +0.5 V which, during transitions,
may overshoot to VCC +2.0 V for periods <20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
5.2 Operating Conditions
Table 5. Temperature and VCC Operating Conditions
Symbol
Parameter
Min Max Unit
TA
VCC
VCCQ
Operating Temperature
VCC1 Supply Voltage (2.7 V3.6 V)
VCCQ Supply Voltage (2.7 V3.6 V)
–40
2.70
2.70
+85
3.60
3.60
°C
V
V
Test Condition
Ambient Temperature
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256-Mbit J3 (x8/x16)
6.0 Electrical Specifications
6.1 DC Current Characteristics
Table 6. DC Current Characteristics (Sheet 1 of 2)
VCCQ
2.7 - 3.6V
VCC
2.7 - 3.6V
Test Conditions
Notes
Symbol
Parameter
Typ Max Unit
ILI
ILO
ICCS
ICCD
ICCR
ICCW
Input and VPEN Load Current
Output Leakage Current
±1
±10
VCC Standby Current
VCC Power-Down Current
50 120
0.71 2
50 120
4-
word
Page
15
24
20
29
VCC Page Mode Read
Current
10 15
8-
word
Page
30
54
VCC Program or Set Lock-
Bit Current
26 46
35 60
40 70
µA
VCC = VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or GND
µA
VCC= VCC Max; VCCQ = VCCQ Max
VIN = VCCQ or GND
CMOS Inputs, VCC = VCC Max,
µA
Device is disabled (see Table 13, “Chip Enable
Truth Table” on page 33),
RP# = VCCQ ± 0.2 V
mA
TTL Inputs, VCC = VCC Max,
Device is disabled (see Table 13), RP# = VIH
µA RP# = GND ± 0.2 V, IOUT (STS) = 0 mA
CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ
Max using standard 4 word page mode reads.
mA
Device is enabled (see Table 13)
f = 5 MHz, IOUT = 0 mA
CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ
Max using standard 4 word page mode reads.
mA
Device is enabled (see Table 13)
f = 33 MHz, IOUT = 0 mA
• CMOS Inputs, VCC = VCC Max, VCCQ =
VCCQ Max using standard 8 word page
mA mode reads.
• Device is enabled (see Table 13)
f = 5 MHz, IOUT = 0 mA
• CMOS Inputs,VCC = VCC Max, VCCQ =
VCCQ Max using standard 8 word page
mode reads.
mA • Device is enabled (see Table 13)
f = 33 MHz, IOUT = 0 mA
• Density: 128-, 64-, and 32- Mbit
• CMOS Inputs,VCC = VCC Max, VCCQ =
VCCQ Max using standard 8 word page
mode reads.
mA • Device is enabled (see Table 13)
f = 33 MHz, IOUT = 0 mA
• Density: 256Mbit
mA CMOS Inputs, VPEN = VCC
mA TTL Inputs, VPEN = VCC
1
1
1,2,3
1,3
1,4
Datasheet
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256-Mbit J3 (x8/x16)
Table 6. DC Current Characteristics (Sheet 2 of 2)
VCCQ
2.7 - 3.6V
VCC
2.7 - 3.6V
Test Conditions
Symbol
Parameter
Typ Max Unit
ICCE
ICCWS
ICCES
VCC Block Erase or Clear
Block Lock-Bits Current
VCC Program Suspend or
Block Erase Suspend
Current
35 70 mA CMOS Inputs, VPEN = VCC
40 80 mA TTL Inputs, VPEN = VCC
10 mA Device is enabled (see Table 13)
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and
speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical
specifications.
2. Includes STS.
3. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.
4. Sampled, not 100% tested.
5. ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend
mode, the device’s current draw is ICCR and ICCWS
Notes
1,4
1,5
6.2 DC Voltage Characteristics
Table 7. DC Voltage Characteristics
Symbol
Parameter
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
VPENLK
VPEN Lockout during Program,
Erase and Lock-Bit Operations
Min
–0.5
2.0
Max
0.8
VCCQ
+ 0.5
0.4
0.85 ×
VCCQ
VCCQ
0.2
0.2
2.2
Unit
V
Test Conditions
V
V
VCCQ = VCCQ Min
IOL = 2 mA
V
VCCQ = VCCQ Min
IOL = 100 µA
V
VCCQ = VCCQ Min
IOH = –2.5 mA
V
VCCQ = VCCQ Min
IOH = –100 µA
V
Notes
2, 6
2,6
1,2
1,2
2,3,4,7
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256-Mbit J3 (x8/x16)
Table 7. DC Voltage Characteristics
Symbol
Parameter
Min Max Unit
Test Conditions
VPENH
VPEN during Block Erase,
Program, or Lock-Bit Operations
2.7
3.6
V
VLKO
VCC Lockout Voltage
2.0
V
NOTES:
1. Includes STS.
2. Sampled, not 100% tested.
3. Block erases, programming, and lock-bit configurations are inhibited when VPEN VPENLK,
and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH
(max).
4. Typically, VPEN is connected to VCC (2.7 V–3.6 V).
5. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and
not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max).
6. Includes all operational modes of the device including standby and power-up sequences.
7. VCC operating condition for standby has to meet typical operationg coditons.
Notes
3,4
5
Datasheet
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256-Mbit J3 (x8/x16)
7.0 AC Characteristics
7.1 Read Operations
Table 8. Read Operations (Sheet 1 of 2)
Asynchronous
Specifications
(All units in ns unless
otherwise noted)
Speed
Bin
-110
VVCCCCQ==22..77VV––33..66VV(3(3))
-115
-120
-125
-150
Notes
# Sym Parameter Density Min Max Min Max Min
32 Mbit 110
R1
tAVAV
Read/Write
Cycle Time
64 Mbit
128 Mbit
115 120
120
256 Mbit
32 Mbit
110
R2
tAVQV
Address to
Output Delay
64 Mbit
128 Mbit
115
256 Mbit
32 Mbit
110
R3
tELQV
CEX to Output
Delay
64 Mbit
128 Mbit
115
256 Mbit
OE# to Non-
R4 tGLQV Array Output
Delay
50 50
32 Mbit
150
R5
tPHQV
RP# High to
Output Delay
64 Mbit
128 Mbit
180
256 Mbit
R6 tELQX CEX to Output in Low Z
0
0
0
R7 tGLQX OE# to Output in Low Z
0
0
0
R8
tEHQZ
CEX High to Output in High
Z
35
35
R9
tGHQZ
OE# High to Output in High
Z
15
15
Output Hold from Address,
R10 tOH
CEX, or OE# Change,
0
0
0
Whichever Occurs First
R11
tELFL/
tELFH
CEX Low to BYTE# High or
Low
10
10
Max
120
120
120
120
50
180
210
35
15
10
Min Max Min Max
150
125
150
125
150
125
50 50
210
210
00
00
35 35
15 15
00
10 10
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2,4
1,2
1,2
1,2
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
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256-Mbit J3 (x8/x16)
Table 8. Read Operations (Sheet 2 of 2)
Asynchronous
Specifications
(All units in ns unless
otherwise noted)
Speed
Bin
-110
VVCCCCQ==22.7.7VV––33.6.6VV(3(3))
-115
-120
-125
-150
Notes
# Sym Parameter Density Min Max Min Max Min Max Min Max Min Max
R12
tFLQV/
tFHQV
BYTE# to Output Delay
1000
1000
1000
R13 tFLQZ BYTE# to Output in High Z
1000
1000
1000
R14 tEHEL CEx High to CEx Low
0
0
0
R15 tAPA Page Address Access Time
25
25
25
R16 tGLQV OE# to Array Output Delay
25
25
25
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is
defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew
rate.
2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that
enables the device (see Table 13) without impact on tELQV.
3. See Figure 15, “Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6
V” on page 29 and Figure 16, “Transient Equivalent Testing Load Circuit” on
page 30 for testing characteristics.
4. When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to
Status Register reads, query reads, or device identifier reads.
5. Sampled, not 100% tested.
6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2
(tAVQV).
1000
1000
1000
1000
00
30 25
25 25
1,2
1,2,5
1,2,5
5, 6
4
Figure 9. Single Word Asynchronous Read Waveform
Address [A]
CEx [E]
OE# [G]
WE# [W]
Data [D/Q]
BYT E# [F]
RP# [P]
R2
R3
R7
R6
R11
R4
R16
R12
R5
R1
R13
R8
R9
R10
Datasheet
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JS28F128J3C (Intel)
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256-Mbit J3 (x8/x16)
0606_16
NOTES:
1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the
first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
2. When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e.: Status
Register reads, query reads, or device identifier reads).
Figure 10. 4-Word Page Mode Read Waveform
A[MAX:3] [A]
A[2:1] [A]
CEx [E]
OE# [G]
WE# [W]
D[15:0] [Q]
RP# [P]
R2
00
R3
R4
R1
01 10 11
R6
R7
R5
R10
R15
12
R8
R10
R9
34
NOTE: CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at
the first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
24 Datasheet


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256-Mbit J3 (x8/x16)
Figure 11. 8-word Asynchronous Page Mode Read
A[MAX:4] [A]
A[3:1] [A]
CEx [E]
OE# [G]
WE# [W]
D[15:0] [Q]
RP# [P]
BYTE#
R2
R3
R4
R1
R6
R7
R5
R10
R15
12
R10
R8
R9
68
NOTES:
1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the
first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
2. In this diagram, BYTE# is asserted high.
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256-Mbit J3 (x8/x16)
7.2 Write Operations
Table 9. Write Operations
# Symbol
Versions
Parameter
Valid for All
Speeds
Min Max
Unit Notes
W1 tPHWL (tPHEL)
RP# High Recovery to WE# (CEX) Going Low
1
µs
W2 tELWL (tWLEL)
CEX (WE#) Low to WE# (CEX) Going Low
0
ns
W3 tWP
Write Pulse Width
70 ns
W4 tDVWH (tDVEH)
Data Setup to WE# (CEX) Going High
50 ns
W5 tAVWH (tAVEH)
Address Setup to WE# (CEX) Going High
55
ns
W6 tWHEH (tEHWH)
CEX (WE#) Hold from WE# (CEX) High
0
ns
W7 tWHDX (tEHDX)
Data Hold from WE# (CEX) High
0 ns
W8 tWHAX (tEHAX)
Address Hold from WE# (CEX) High
0 ns
W9 tWPH
Write Pulse Width High
30 ns
W11 tVPWH (tVPEH)
VPEN Setup to WE# (CEX) Going High
0 ns
W12 tWHGL (tEHGL)
Write Recovery before Read
35 ns
W13 tWHRL (tEHRL)
WE# (CEX) High to STS Going Low
500 ns
W15 tQVVL
VPEN Hold from Valid SRD, STS Going High
0
ns
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1,
or CE2 that disables the device (see Table 13).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics–Read-Only Operations.
2. A write operation can be initiated and terminated with either CEX or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going
high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
5. Refer to Table 14 for valid AIN and DIN for block erase, program, or lock-bit configuration.
6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE#
going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY# default mode.
9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success
(SR[1,3,4:5] = 0).
1,2,3
1,2,4
1,2,4
1,2,5
1,2,5
1,2,
1,2,
1,2,
1,2,6
1,2,3
1,2,7
1,2,8
1,2,3,8,9
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256-Mbit J3 (x8/x16)
7.3 Block Erase, Program, and Lock-Bit Configuration
Performance
Table 10. Configuration Performance
# Sym
Parameter
Typ Max(8) Unit
Notes
W16
Write Buffer Byte Program Time
(Time to Program 32 bytes/16 words)
218 654
µs
W16
tWHQV3
tEHQV3
Byte Program Time (Using Word/Byte Program Command)
210
630
µs
Block Program Time (Using Write to Buffer Command)
0.8 2.4 sec
W16
tWHQV4
tEHQV4
Block Erase Time
1.0 5.0 sec
W16
tWHQV5
tEHQV5
Set Lock-Bit Time
64 75/85 µs
W16
tWHQV6
tEHQV6
Clear Block Lock-Bits Time
0.5 0.70/1.4 sec
W16
tWHRH1
tEHRH1
Program Suspend Latency Time to Read
25 75/90 µs
W16
tWHRH
tEHRH
Erase Suspend Latency Time to Read
26 35/40 µs
NOTES:
1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are
not set. Subject to change based on device characterization.
2. These performance numbers are valid for all speed versions.
3. Sampled but not 100% tested.
4. Excludes system-level overhead.
5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
6. Effective per-byte program time (tWHQV1, tEHQV1) is 6.8 µs/byte (typical).
7. Effective per-word program time (tWHQV2, tEHQV2) is 13.6 µs/word (typical).
8. Max values are measured at worst case temperature and VCC corner after 100k cycles (except as
noted).
9. Max values are expressed at -25 °C/-40 °C.
10.Max values are expressed at 25 °C/-40 °C.
1,2,3,4,5,6,7
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4,9
1,2,3,4,10
1,2,3,9
1,2,3,9
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256-Mbit J3 (x8/x16)
Figure 12. Asynchronous Write Waveform
ADDRESS [A]
W5
CEx (WE#) [E (W)]
WE# (CEx) [W (E)]
OE# [G]
DATA [D/Q]
W2
W3
W4
D
ST S[R]
RP# [P]
VPEN [V]
W1
W11
W8
W6
W9
W7
W13
Figure 13. Asynchronous Write to Read Waveform
Address [A]
W5
CE# [E]
WE# [W]
W2 W3
OE# [G]
Data [D/Q]
RST#/ RP# [P]
VPEN [V]
W1
W4
D
W11
W8
W6
W12
W7
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256-Mbit J3 (x8/x16)
7.4 Reset Operation
Figure 14. AC Waveform for Reset Operation
VIH
STS (R)
VIL
RP# (P) VIH
VIL
P1
P2
NOTE: STS is shown in its default mode (RY/BY#).
Table 11. Reset Specifications
# Sym
Parameter
Min Max Unit Notes
P1 tPLPH
RP# Pulse Low Time
(If RP# is tied to VCC, this specification is not
applicable)
35
µs
P2 tPHRH
RP# High to Reset during Block Erase, Program, or
Lock-Bit Configuration
100 ns
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not
executing then the minimum required RP# Pulse Low Time is 100 ns.
3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until
outputs are valid.
1,2
1,3
7.5 AC Test Conditions
Figure 15. Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6 V
VCCQ
Input VCCQ/2
0.0
Test Points
VCCQ/2 Output
NOTE: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and
output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
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256-Mbit J3 (x8/x16)
Figure 16. Transient Equivalent Testing Load Circuit
1.3V
1N914
Device
Under Test
RL = 3.3 k
Out
CL
NOTE: CL Includes Jig Capacitance.
Test Configuration
VCCQ = VCC = 2.7 V3.6 V
CL (pF)
30
7.6
Capacitance
TA = +25 °C, f = 1 MHz
Symbol
Parameter(1)
CIN Input Capacitance
COUT
Output Capacitance
NOTES:
1. Sampled, not 100% tested.
Type
6
8
Max
8
12
Unit
pF
pF
Condition
VIN = 0.0 V
VOUT = 0.0 V
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