MCF5485 (Freescale Semiconductor)
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Freescale Semiconductor
Data Sheet
Document Number: MCF5485EC
Rev. 4, 12/2007
MCF548x ColdFire®
Microprocessor
Supports MCF5480, MCF5481,
MCF5482, MCF5483, MCF5484, and
MCF5485
MCF548x
TEPBGA–388
27 mm x 27 mm
Features list:
• ColdFire V4e Core
– Limited superscalar V4 ColdFire processor core
– Up to 200MHz peak internal core frequency (308 MIPS
[Dhrystone 2.1] @ 200 MHz)
– Harvard architecture
– 32-Kbyte instruction cache
– 32-Kbyte data cache
– Memory Management Unit (MMU)
– Separate, 32-entry, fully-associative instruction and
data translation lookahead buffers
– Floating point unit (FPU)
– Double-precision conforms to IEE-754 standard
– Eight floating point registers
• Internal master bus (XLB) arbiter
– High performance split address and data transactions
– Support for various parking modes
• 32-bit double data rate (DDR) synchronous DRAM
(SDRAM) controller
– 66–133 MHz operation
– Supports DDR and SDR DRAM
– Built-in initialization and refresh
– Up to four chip selects enabling up to one GB of external
memory
• Version 2.2 peripheral component interconnect (PCI) bus
– 32-bit target and initiator operation
– Support for up to five external PCI masters
– 33–66 MHz operation with PCI bus to XLB divider
ratios of 1:1, 1:2, and 1:4
• Flexible multi-function external bus (FlexBus)
– Provides a glueless interface to boot flash/ROM,
SRAM, and peripheral devices
– Up to six chip selects
– 33 – 66 MHz operation
• Communications I/O subsystem
– Intelligent 16 channel DMA controller
– Up to two 10/100 Mbps fast Ethernet controllers (FECs)
each with separate 2-Kbyte receive and transmit FIFOs
– Universal serial bus (USB) version 2.0 device controller
– Support for one control and six programmable
endpoints, interrupt, bulk, or isochronous
– 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte
of endpoint descriptor RAM
– Integrated physical layer interface
– Up to four programmable serial controllers (PSCs) each
with separate 512-byte receive and transmit FIFOs for
UART, USART, modem, codec, and IrDA 1.1 interfaces
– I2C peripheral interface
– Two FlexCAN controller area network 2.0B controllers
each with 16 message buffers
– DMA Serial Peripheral Interface (DSPI)
• Optional Cryptography accelerator module
– Execution units for:
– DES/3DES block cipher
– AES block cipher
– RC4 stream cipher
– MD5/SHA-1/SHA-256/HMAC hashing
– Random Number Generator
• 32-Kbyte system SRAM
– Arbitration mechanism shares bandwidth between
internal bus masters
• System integration unit (SIU)
– Interrupt controller
– Watchdog timer
– Two 32-bit slice timers alarm and interrupt generation
– Up to four 32-bit general-purpose timers, compare, and
PWM capability
– GPIO ports multiplexed with peripheral pins
• Debug and test features
– ColdFire background debug mode (BDM) port
– JTAG/ IEEE 1149.1 test access port
• PLL and clock generator
– 30 to 66.67 MHz input frequency range
• Operating Voltages
– 1.5V internal logic
– 2.5V DDR SDRAM bus I/O
– 3.3V PCI, FlexBus, and all other I/O
• Estimated power consumption
– Less than 1.5W (388 PBGA)
© Freescale Semiconductor, Inc., 2007. All rights reserved.


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Table of Contents
1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .6
4.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.2 Supply Voltage Sequencing and Separation Cautions . .6
4.3 General USB Layout Guidelines . . . . . . . . . . . . . . . . . . .8
4.4 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5 Output Driver Capability and Loading. . . . . . . . . . . . . . . . . . .10
6 PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .12
8 FlexBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
8.1 FlexBus AC Timing Characteristics. . . . . . . . . . . . . . . .13
9 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
9.1 SDR SDRAM AC Timing Characteristics . . . . . . . . . . .15
9.2 DDR SDRAM AC Timing Characteristics . . . . . . . . . . .18
10 PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
11 Fast Ethernet AC Timing Specifications . . . . . . . . . . . . . . . . .22
11.1 MII/7-WIRE Interface Timing Specs . . . . . . . . . . . . . . .22
11.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . .23
11.3 MII Async Inputs Signal Timing (CRS, COL) . . . . . . . .24
11.4 MII Serial Management Channel Timing (MDIO,MDC).24
12 General Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . .25
13 I2C Input/Output Timing Specifications. . . . . . . . . . . . . . . . . .25
14 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . .26
15 DSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . .29
16 Timer Module AC Timing Specifications . . . . . . . . . . . . . . . . .29
17 Case Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
18 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
List of Figures
Figure 1. MCF548X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. System PLL VDD Power Filter . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Supply Voltage Sequencing and Separation Cautions . 7
Figure 4. Preferred VBUS Connections . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Alternate VBUS Connections . . . . . . . . . . . . . . . . . . . . 8
Figure 6. USB VDD Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. USBRBIAS Connection. . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Input Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 11
Figure 9. CLKIN, Internal Bus, and Core Clock Ratios . . . . . . . 11
Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12.FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13.SDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.SDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15.DDR Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 18
Figure 16.DDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17.DDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18.PCI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19.MII Receive Signal Timing Diagram. . . . . . . . . . . . . . 23
Figure 20.MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 23
Figure 21.MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . 24
Figure 22.MII Serial Management Channel TIming Diagram. . . 24
Figure 23.I2C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 26
Figure 24.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 25.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . 27
Figure 26.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . 27
Figure 27.TRST Timing Debug AC Timing Specifications . . . . . 27
Figure 28.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . . 28
Figure 29.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . . 28
Figure 30.DSPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 31.388-pin BGA Case Outline. . . . . . . . . . . . . . . . . . . . . 31
List of Tables
Table 1. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . 5
Table 5. USB Filter Circuit Values . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. I/O Driver Capability . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Clock Timing Specifications. . . . . . . . . . . . . . . . . . . . . 11
Table 8. MCF548x Divide Ratio Encodings. . . . . . . . . . . . . . . . 11
Table 9. Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . 12
Table 10.FlexBus AC Timing Specifications. . . . . . . . . . . . . . . . 13
Table 11.SDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 16
Table 12.DDR Clock Crossover Specifications . . . . . . . . . . . . . 18
Table 13.DDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 18
Table 14.PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 21
Table 15.MII Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . 23
Table 16.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 23
Table 17.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 24
Table 18.MII Serial Management Channel Signal Timing . . . . . 24
Table 19.General AC Timing Specifications . . . . . . . . . . . . . . . . 25
Table 20.I2C Input Timing Specifications between
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21. I2C Output Timing Specifications between
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 26
Table 23.Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 28
Table 24.DSPI Modules AC Timing Specifications. . . . . . . . . . . 29
Table 25.Timer Module AC Timing Specifications . . . . . . . . . . . 29
MCF548x ColdFire® Microprocessor, Rev. 4
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ColdFire V4e Core
FPU, MMU
EMAC
32K D-cache
32K I-Cache
Interrupt
Controller
Watchdog
Timer
Slice
Timers x 2
GP
Timers x 4
PLL
DDR SDRAM
Interface
XL Bus
Arbiter
XL
Bus
Master/Slave
Interface
Cryptography
Accelerator***
Memory
Controller
32K System
SRAM
XL Bus
Read/Write
FlexBus
Interface
FlexBus
Controller
PCI 2.2
Controller
FlexCAN
x2
DSPI
Multi-Channel DMA
Master Bus Interface & FIFOs
CommBus
PCI Interface
& FIFOs
I2C
PSC x 4
FEC1
FEC2**
USB 2.0
DEVICE*
Perpheral Communications I/O Interface & Ports
USB 2.0
PHY*
Figure 1. MCF548X Block Diagram
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Maximum Ratings
1 Maximum Ratings
Table 1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of
these ranges may cause erratic behavior or damage to the processor.
Table 1. Absolute Maximum Ratings
Rating
External (I/O pads) supply voltage (3.3-V power pins)
Internal logic supply voltage
Memory (I/O pads) supply voltage (2.5-V power pins)
PLL supply voltage
Internal logic supply voltage, input voltage level
Storage temperature range
Symbol
EVDD
IVDD
SD VDD
PLL VDD
Vin
Tstg
Value
–0.3 to +4.0
–0.5 to +2.0
–0.3 to +4.0 SDR Memory
–0.3 to +2.8 DDR Memory
–0.5 to +2.0
–0.5 to +3.6
–55 to +150
Units
V
V
V
V
V
oC
2 Thermal Characteristics
2.1 Operating Temperatures
Table 2 lists junction and ambient operating temperatures.
Table 2. Operating Temperatures
Characteristic
Symbol
Value
Units
Maximum operating junction temperature
Tj 105 oC
Maximum operating ambient temperature
TAmax
<851
oC
Minimum operating ambient temperature
TAmin –40 oC
1 This published maximum operating ambient temperature should be used only as a system design guideline. All device
operating parameters are guaranteed only when the junction temperature lies within the specified range.
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DC Electrical Specifications
2.2 Thermal Resistance
Table 3 lists thermal resistance values.
Table 3. Thermal Resistance
Characteristic
Symbol
Value
Unit
324 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p)
convection
θJMA
20–221,2
°C/W
388 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p)
convection
θJMA
191,2
°C/W
Junction to ambient (@200 ft/min)
Four layer board (2s2p)
θJMA
161,2
°C/W
Junction to board
θJB 113 °C/W
Junction to case
θJC 74 °C/W
Junction to top of package
Natural convection Ψjt 21,5 °C/W
1 θJA and Ψjt parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction
temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device
junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt
parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
2 Per JEDEC JESD51-6 with the board horizontal.
3 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
3 DC Electrical Specifications
Table 4 lists DC electrical operating temperatures. This table is based on an operating voltage of EVDD = 3.3 VDC ± 0.3 VDC
and IVDD of 1.5 ± 0.07 VDC.
Table 4. DC Electrical Specifications
Characteristic
Symbol
External (I/O pads) operation voltage range
EVDD
Memory (I/O pads) operation voltage range (DDR Memory)
Internal logic operation voltage range1
PLL Analog operation voltage range1
SD VDD
IVDD
PLL VDD
USB oscillator operation voltage range
USB_OSVDD
USB digital logic operation voltage range
USBVDD
USB PHY operation voltage range
USB_PHYVDD
USB oscillator analog operation voltage range
USB_OSCAVDD
Min
3.0
2.30
1.43
1.43
3.0
3.0
3.0
1.43
Max Units
3.6 V
2.70 V
1.58 V
1.58 V
3.6 V
3.6 V
3.6 V
1.58 V
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Hardware Design Considerations
Table 4. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max Units
USB PLL operation voltage range
Input high voltage SSTL 3.3V/2.5V2
Input low voltage SSTL 3.3V/2.5V2
USB_PLLVDD
VIH
VIL
1.43
VREF + 0.3
VSS - 0.3
1.58
SD VDD + 0.3
VREF - 0.3
V
V
V
Input high voltage 3.3V I/O pins
VIH
0.7 x EVDD
EVDD + 0.3
V
Input low voltage 3.3V I/O pins
VIL
VSS - 0.3
0.35 x EVDD
V
Output high voltage IOH = 8 mA, 16 mA,24 mA
Output low voltage IOL = 8 mA, 16 mA,24 mA5
Capacitance 3, Vin = 0 V, f = 1 MHz
VOH 2.4
—V
VOL — 0.5 V
CIN
TBD
pF
Input leakage current
Iin –1.0 1.0 μA
1 IVDD and PLL VDD should be at the same voltage. PLL VDD should have a filtered input. Please see Figure 2 for an
example circuit. There are three PLL VDD inputs. A filter circuit should used on each PLL VDD input.
2 This specification is guaranteed by design and is not 100% tested.
3 Capacitance CIN is periodically sampled rather than 100% tested.
4 Hardware Design Considerations
4.1 PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in
Figure 2 should be connected between the board VDD and the PLL VDD pins. The resistor and capacitors should be placed as
close to the dedicated PLL VDD pin as possible.
Board VDD
10 Ω
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 2. System PLL VDD Power Filter
4.2 Supply Voltage Sequencing and Separation Cautions
Figure 3 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SD VDD), PLL VDD (PLL VDD), and Core VDD
(IVDD).
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Hardware Design Considerations
3.3V
2.5V
1.5V
1
Supplies Stable
EVDD, SD VDD (3.3V)
SD VDD (2.5V)
IVDD, PLL VDD
2
0
NOTES:
Time
1. IVDD should not exceed EVDD or SD VDD by more than 0.4V
at any time, including power-up.
2. Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to
0.9V, then separate for completion of ramps.
3. Input voltage must not be greater than the supply voltage (EVDD, SD VDD,
IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up.
4. Use 1 microsecond or slower rise time for all supplies.
Figure 3. Supply Voltage Sequencing and Separation Cautions
The relationship between SD VDD and EVDD is non-critical during power-up and power-down sequences. SD VDD (2.5V or
3.3V) and EVDD are specified relative to IVDD.
4.2.1 Power Up Sequence
If EVDD/SD VDD are powered up with the IVDD at 0V, the sense circuits in the I/O pads cause all pad output drivers connected
to the EVDD/SD VDD to be in a high impedance state. There is no limit to how long after EVDD/SD VDD powers up before IVDD
must power up. IVDD should not lead the EVDD, SD VDD, or PLL VDD by more than 0.4V during power ramp up or there is
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond
to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1 microsecond or slower rise time for all supplies.
2. IVDD/PLL VDD and EVDD/SD VDD should track up to 0.9V, then separate for the completion of ramps with EVDD/SD
VDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
4.2.2 Power Down Sequence
If IVDDPLL VDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IVDD and PLL VDD power down before EVDD or SD VDD must power down. IVDD should
not lag EVDD, SD VDD, or PLL VDD going low by more than 0.4V during power down or there is undesired high current in the
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IVDD/PLL VDD to 0V
2. Drop EVDD/SD VDD supplies
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Hardware Design Considerations
4.3 General USB Layout Guidelines
4.3.1 USB D+ and D- High-Speed Traces
1. High speed clock and the USBD+ and USBD- differential pair should be routed first.
2. Route USBD+ and USBD- signals on the top layer of the board.
3. The trace width and spacing of the USBD+ and USBD- signals should be such that the differential impedance is 90Ω.
4. Route traces over continuous planes (power and ground)—they should not pass over any power/ground plane slots or
anti-etch. When placing connectors, make sure the ground plane clear-outs around each pin have ground continuity
between all pins.
5. Maintain the parallelism (skew matched) between USBD+ and USBD-. These traces should be the same overall length.
6. Do not route USBD+ and USBD- traces under oscillators or parallel to clock traces and/or data buses. Minimize the
lengths of high speed signals that run parallel to the USBD+ and USBD- pair. Maintain a minimum 50mil spacing to
clock signals.
7. Keep USBD+ and USBD- traces as short as possible.
8. Route USBD+, USBD-, and USBVBUS signals with a minimum amount of vias and corners. Use 45° turns.
9. Stubs should be avoided as much as possible. If they cannot be avoided, stubs should be no greater than 200mils.
4.3.2 USB VBUS Traces
Connecting the USBVBUS pin directly to the 5V VBUS signal from the USB connector can cause long-term reliability
problems in the ESD network of the processor. Therefore, use of an external voltage divider for VBUS is recommended.
Figure 4 and Figure 5 depict possible connections for VBUS. Point A, marked in each figure, is where a 5V version of VBUS
should connect. Point B, marked in each figure, is where a 3.3V version of VBUS should connect to the USBVBUS pin on the
device.
(5V)
A 8.2k
(3.3V)
B
MCF548x
50k
20k 50k
Figure 4. Preferred VBUS Connections
(5V)
A 50k
(3.3V)
B
MCF548x
50k
50k
Figure 5. Alternate VBUS Connections
4.3.3 USB Receptacle Connections
It is recommended to connect the shield and the ground pin of the B USB receptacle for upstream ports to the board ground
plane. The ground pin of the A USB receptacles for downstream ports should also be connected to the board ground plane, but
industry practice varies widely on the connection of the shield of the A USB receptacles to other system grounds. Take
precautions for control of ground loops between hosts and self-powered USB devices through the cable shield.
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Hardware Design Considerations
4.4 USB Power Filtering
To minimize noise, an external filter is required for each of the USB power pins. The filter shown in Figure 6 should be
connected between the board EVDD or IVDD and each of the USB VDD pins.
• The resistor and capacitors should be placed as close to the dedicated USB VDD pin as possible.
• A separate filter circuit should be included for each USB VDD pin, a total of five circuits.
• All traces should be as low impedance as possible, especially ground pins to the ground plane.
• The filter for USB_PHYVDD to VSS should be connected to the power and ground planes, respectively, not fingers
of the planes.
• In addition to keeping the filter components for the USB_PLLVDD as close as practical to the body of the processor
as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital
switching noise onto the portion of that supply between the filter and the processor.
• The capacitors for C2 in the table below should be rated X5R or better due to temperature performance.
Board EVDD/IVDD
R1
USB VDD Pin
C1 C2
GND
Figure 6. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
Table 5 lists the resistor values and supply voltages to be used in the circuit for each of the USB VDD pins.
Table 5. USB Filter Circuit Values
USB VDD Pin
USBVDD
(Bias generator supply)
USB_PHYVDD
(Main transceiver supply)
USB_PLLVDD
(PLL supply)
USB_OSCVDD
(Oscillator supply)
USB_OSCAVDD
(Oscillator analog supply)
Nominal Voltage
3.3V
3.3V
1.5V
3.3V
1.5V
R1 (Ω)
10
0
10
0
0
C1 (μF)
10
10
1
10
10
C2 (μF)
0.1
0.1
0.1
0.1
0.1
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Output Driver Capability and Loading
4.4.1 Bias Resistor
The USBRBIAS resistor should be placed as close to the dedicated USB 2.0 pins as possible. The tolerance should be ±1%.
USBRBIAS
9.1kΩ
Figure 7. USBRBIAS Connection
5 Output Driver Capability and Loading
Table 6 lists values for drive capability and output loading.
Table 6. I/O Driver Capability1
Signal
Drive
Output
Capability Load (CL)
SDRAMC (SDADDR[12:0], SDDATA[31:0], RAS, CAS, SDDM[3:0],
SDWE, SDBA[1:0]
24 mA
15 pF
SDRAMC DQS and clocks (SDDQS[3:0], SDRDQS, SDCLK[1:0],
SDCLK[1:0], SDCKE)
24 mA
15 pF
SDRAMC chip selects (SDCS[3:0])
24 mA
15 pF
FlexBus (AD[31:0], FBCS[5:0], ALE, R/W, BE/BWE[3:0], OE)
16 mA
30 pF
FEC (EnMDIO, EnMDC, EnTXEN, EnTXD[3:0], EnTXER
8 mA
15 pF
Timer (TOUT[3:0])
8 mA
50 pF
FlexCAN (CANTX)
8 mA
30 pF
DACK[1:0]
8 mA
30 pF
PSC (PSCnTXD[3:0], PSCnRTS/PSCnFSYNC,
8 mA
30 pF
DSPI (DSPISOUT, DSPICS0/SS, DSPICS[2:3], DSPICS5/PCSS)
24 mA
50 pF
PCI (PCIAD[31:0], PCIBG[4:1], PCIBG0/PCIREQOUT, PCIDEVSEL,
PCICXBE[3:0], PCIFRM, PCIPERR, PCIRESET, PCISERR, PCISTOP,
PCIPAR, PCITRDY, PCIIRDY
16 mA
50 pF
I2C (SCL, SDA)
8 mA
50 pF
BDM (PSTCLK, PSTDDATA[7:0], DSO/TDO,
8 mA
25 pF
RSTO
8 mA
50 pF
1 The device’s pads have balanced sink and source current. The drive capability is the same as
the sink capability.
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6 PLL Timing Specifications
The specifications in Table 7 are for the CLKIN pin.
Table 7. Clock Timing Specifications
Num
Characteristic
Min Max
C1 Cycle time
C2 Rise time (20% of Vdd to 80% of vdd)
C3 Fall time (80% of Vdd to 20% of Vdd)
C4 Duty cycle (at 50% of Vdd)
20
40
40
2
2
60
PLL Timing Specifications
Units
ns
ns
ns
%
C1
CLKIN
C4 C4
C2
C3
Figure 8. Input Clock Timing Diagram
Table 8 shows the supported PLL encodings.
Table 8. MCF548x Divide Ratio Encodings
AD[12:8]1
Clock
Ratio
CLKIN—PCI and FlexBus
Frequency Range (MHz)
Internal XLB, SDRAM Bus,
and PSTCLK Frequency
Range (MHz)
Core Frequency Range
(MHz)
00011
00101
1:2
1:2
41.67–50.0
25.0–41.67
83.33–100
50.0–83.332
166.66–200
100.0–166.66
01111
1:4
25.0
100
200
1 All other values of AD[12:8] are reserved.
2 DDR memories typically have a minimum speed of 83 MHz. Some vendors specifiy down to 75 MHz. Check with the
memory component specifications to verify.
Figure 9 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.
CLKIN
Internal Clock
Core Clock
2x
25.0 50.0
50.0
100.0
2x
100.0
200.0
4x
25.0
100.0
2x
200.0
25 40 50 60 70
CLKIN (MHz)
30 40 50 60 70 80 90 100 60 70 80 90 100110120130140150160170180190200
Internal Clock (MHz)
Core Clock (MHz)
Figure 9. CLKIN, Internal Bus, and Core Clock Ratios
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Reset Timing Specifications
7 Reset Timing Specifications
Table 9 lists specifications for the reset timing parameters shown in Figure 10
Table 9. Reset Timing Specifications
Num
Characteristic
50 MHz CLKIN
Min Max
Units
R11 Valid to CLKIN (setup)
8—
ns
R2
CLKIN to invalid (hold)
1.0 —
ns
R3
RSTI to invalid (hold)
1.0 —
ns
RSTI pulse duration
5 — CLKIN cycles
1 RSTI and FlexBus data lines are synchronized internally. Setup and hold
times must be met only if recognition on a particular clock is required.
Figure 10 shows reset timing for the values in Table 9.
CLKIN
R1
RSTI
Mode Select
FlexBus
R1
R2
R3
NOTE:
Mode selects are registered on the rising clock edge before
the cycle in which RSTI is recognized as being negated.
Figure 10. Reset Timing
8 FlexBus
A multi-function external bus interface called FlexBus is provided on the MCF5482 with basic functionality to interface to
slave-only devices up to a maximum bus frequency of 66 MHz. It can be directly connected to asynchronous or synchronous
devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no
additional circuitry. For asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has six
general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be dedicated to boot ROM access and can be programmed
to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM / flash
memories.
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FlexBus
8.1 FlexBus AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.
Table 10. FlexBus AC Timing Specifications
Num
Characteristic
Min Max
Unit Notes
Frequency of Operation
25 50
Mhz
1
FB1 Clock Period (CLKIN)
20 40
ns
2
FB2 Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0], —
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
7.0
ns
3
FB3 Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
1
ns 3, 4
FB4 Data Input Setup
3.5 —
ns
FB5 Data Input Hold
0—
ns
FB6 Transfer Acknowledge (TA) Input Setup
4—
ns
FB7 Transfer Acknowledge (TA) Input Hold
0—
ns
FB8 Address Output Valid (PCIAD[31:0])
— 7.0
ns
5
FB9 Address Output Hold (PCIAD[31:0])
0—
ns
5
1 The frequency of operation is the same as the PCI frequency of operation. The MCF548X supports a single
external reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI.
2 Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
3 Timing for chip selects only applies to the FBCS[5:0] signals. Please see Section 9.2, “DDR SDRAM AC Timing
Characteristics” for SDCS[3:0] timing.
4 The FlexBus supports programming an extension of the address hold. Please consult the MCF548X
specification manual for more information.
5 These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address
signals.
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FlexBus
CLKIN
AD[X:0]
AD[31:Y]
R/W
ALE
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
FB1
FB2
A[31:Y]
A[X:0]
FB5
DATA
FB3
FB4
TSIZ[1:0]
FB7
FB6
Figure 11. FlexBus Read Timing
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CLKIN
AD[X:0]
AD[31:Y]
FB1
FB2
A[31:Y]
A[X:0]
DATA
FB3
FB3
SDRAM Bus
R/W
ALE
TSIZ[1:0]
TSIZ[1:0]
FBCSn, BE/BWEn
OE
TA
FB7
FB6
Figure 12. FlexBus Write Timing
9 SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time. The SDRAM controller uses SSTL2 and SSTL3
I/O drivers. Both SSTL drive modes are programmable for Class I or Class II drive strength.
9.1 SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SDR_DQS on read cycles. The MCF548x SDRAM controller is a
DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must be supplied to the MCF548x
for each data beat of an SDR read. The MCF548x accomplishes this by asserting a signal called SDR_DQS during read cycles.
Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal
and its usage.
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SDRAM Bus
Table 11. SDR Timing Specifications
Symbol
Characteristic
Min Max Unit Notes
SD1
SD2
SD3
SD4
SD5
Frequency of Operation
Clock Period (tCK)
Clock Skew (tSK)
Pulse Width High (tCKH)
Pulse Width Low (tCKL)
Address, CKE, CAS, RAS, WE, BA, CS - Output Valid (tCMV)
0
7.52
0.45
0.45
133 Mhz
12 ns
TBD
0.55 SDCLK
0.55 SDCLK
0.5 × SDCLK + ns
1.0ns
1
2
3
4
SD6
SD7
SD8
SD9
SD10
Address, CKE, CAS, RAS, WE, BA, CS - Output Hold (tCMH)
2.0
ns
SDRDQS Output Valid (tDQSOV)
Self timed
ns
SDDQS[3:0] input setup relative to SDCLK (tDQSIS)
0.25 × SDCLK 0.40 × SDCLK ns
SDDQS[3:0] input hold relative to SDCLK (tDQSIH)
Does not apply. 0.5 SDCLK fixed width.
Data Input Setup relative to SDCLK (reference only) (tDIS) 0.25 × SDCLK
ns
5
6
7
8
SD11
SD12
Data Input Hold relative to SDCLK (reference only) (tDIH)
Data and Data Mask Output Valid (tDV)
1.0 ns
0.75 × SDCLK
+0.500ns
ns
SD13 Data and Data Mask Output Hold (tDH)
1.5 ns
1 The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external reference
clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at the same
frequency as the internal bus clock. Please see the PLL chapter of the MCF548X Reference Manual for more information on
setting the SDRAM clock rate.
2 SDCLK is one SDRAM clock in (ns).
3 Pulse width high plus pulse width low cannot exceed min and max clock period.
4 Pulse width high plus pulse width low cannot exceed min and max clock period.
5 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
6 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
7 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.
8 Because a read cycle in SDR mode uses the DQS circuit within the MCF548X, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup
spec is provided as guidance.
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SDRAM Bus
SDCLK0
SDCLK1
SDCSn,SDWE,
RAS, CAS
SDADDR,
SDBA[1:0]
SDDM
SDDATA
SD2 SD1
SD3
SD2 SD4
SD6
CMD
SD5
ROW
COL
SD12
WD1
Figure 13. SDR Write Timing
SD13
WD2
WD3
WD4
SD2 SD1
SDCLK0
SD2
SDCLK1
SD6
SDCSn,SDWE,
RAS, CAS
CMD
SD5
SDADDR,
SDBA[1:0]
ROW
COL
tDQS
3/4 MCLK
Reference
SDDM
SD7
SDRQS (Measured at Output Pin)
Board Delay
SD9
SDDQS (Measured at Input Pin)
Delayed
SDCLK
Board Delay
SDDATA
form
Memories
WD1
NOTE: Data driven from memories relative
to delayed memory clock.
SD11
Figure 14. SDR Read Timing
SD10
WD2
SD8
WD3
WD4
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SDRAM Bus
9.2 DDR SDRAM AC Timing Characteristics
When using the DDR SDRAM controller, the following timing numbers must be followed to properly latch or drive data onto
the memory bus. All timing numbers are relative to the four DQS byte lanes.
Table 12shows the DDR clock crossover specifications.
Table 12. DDR Clock Crossover Specifications
Symbol
Characteristic
Min Max Unit
VMP Clock output mid-point voltage
1.05 1.45 V
VOUT Clock output voltage level
–0.3 SD_VDD + 0.3 V
VID Clock output differential voltage (peak to peak swing)
VIX Clock crossing point voltage1
0.7 SD_VDD + 0.6 V
1.05 1.45 V
1 The clock crossover voltage is only guaranteed when using the highest drive strength option for the SDCLK[1:0]
and SDCLK[1:0] signals.
SDCLK
SDCLK
Figure 15. DDR Clock Timing Diagram
VIX
VMP
VIX
VID
Table 13. DDR Timing Specifications
Symbol
Characteristic
Min Max Unit Notes
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
Frequency of Operation
501 133 MHz
Clock Period (tCK)
Pulse Width High (tCKH)
Pulse Width Low (tCKL)
Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output
Valid (tCMV)
Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output Hold
(tCMH)
Write Command to first DQS Latching Transition (tDQSS)
Data and Data Mask Output Setup (DQ−>DQS) Relative to
DQS (DDR Write Mode) (tQS)
Data and Data Mask Output Hold (DQS−>DQ) Relative to DQS
(DDR Write Mode) (tQH)
Input Data Skew Relative to DQS (Input Setup) (tIS)
Input Data Hold Relative to DQS (tIH)
7.52
0.45
0.45
2.0
1.0
1.0
0.25 × SDCLK
+ 0.5ns
12
0.55
0.55
0.5 × SDCLK
+ 1.0 ns
1.25
1
ns
SDCLK
SDCLK
ns
ns
SDCLK
ns
ns
ns
ns
2
3
4
5
6
7
8
9
10
11
DD11 DQS falling edge to SDCLK rising (output setup time) (tDSS)
DD12 DQS falling edge from SDCLK rising (output hold time) (tDSH)
0.5
0.5
— ns
— ns
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SDRAM Bus
Table 13. DDR Timing Specifications (continued)
Symbol
Characteristic
Min Max Unit Notes
DD13 DQS input read preamble width (tRPRE)
0.9 1.1 SDCLK
DD14 DQS input read postamble width (tRPST)
0.4 0.6 SDCLK
DD15 DQS output write preamble width (tWPRE)
0.25 — SDCLK
DD16 DQS output write postamble width (tWPST)
0.4 0.6 SDCLK
1 DDR memories typically have a minimum speed specification of 83 MHz. Check memory component specifications to verify.
2 The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at
the same frequency as the internal bus clock. Please see the reset configuration signals description in the “Signal
Descriptions” chapter within the MCF548x Reference Manual.
3 SDCLK is one memory clock in (ns).
4 Pulse width high plus pulse width low cannot exceed max clock period.
5 Pulse width high plus pulse width low cannot exceed max clock period.
6 Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process,
temperature, and voltage variations.
7 This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
8 The first data beat is valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data
beats is valid for each subsequent SDDQS edge.
9 This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
10 Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing
or other factors).
11 Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data
line becomes invalid.
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SDRAM Bus
SDCLK0
SDCLK1
DD1
DD2
DD3
SDCLK0
SDCLK1
SDCSn,SDWE,
RAS, CAS
SDADDR,
SDBA[1:0]
SDDM
SDDQS
SDDATA
CMD
DD4
ROW
DD5
DD6
COL
DD7
DD8
DD7
WD1 WD2 WD3 WD4
Figure 16. DDR Write Timing
DD8
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SDCLK0
SDCLK1
DD1
DD2
DD3
PCI Bus
SDCLK0
SDCLK1
SDCSn,SDWE,
RAS, CAS
SDADDR,
SDBA[1:0]
SDDQS
SDDATA
SDDQS
SDDATA
CMD
DD4
ROW
DD5
COL
CL=2
CL=2.5
DQS Read
Preamble
DD10
DD9 DQS Read
Postamble
WD1 WD2 WD3 WD4
DQS Read
DQS Read
Preamble
Postamble
WD1 WD2 WD3 WD4
Figure 17. DDR Read Timing
10 PCI Bus
The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please
refer to the PCI 2.2 spec for a more detailed timing analysis.
Table 14. PCI Timing Specifications
Num
Characteristic
Frequency of Operation
P1 Clock Period (tCK)
P2 Address, Data, and Command (33< PCI 50 Mhz)—Input Setup (tIS)
P3 Address, Data, and Command (0 < PCI 33 Mhz)—Input Setup (tIS)
P4 Address, Data, and Command (33–50 Mhz)—Output Valid (tDV)
P5 Address, Data, and Command (0–33 Mhz) - Output Valid (tDV)
P6 PCI signals (0–50 Mhz) - Output Hold (tDH)
Min
25
20
3.0
7.0
0
Max
50
40
6.0
11.0
Unit
MHz
ns
ns
ns
ns
ns
ns
Notes
1
2
3
4
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Fast Ethernet AC Timing Specifications
Table 14. PCI Timing Specifications (continued)
Num
Characteristic
Min Max Unit Notes
P7 PCI signals (0–50 Mhz) - Input Hold (tIH)
P8 PCI REQ/GNT (33 < PCI 50Mhz) - Output valid (tDV)
0 — ns
— 6 ns
5
6
P9 PCI REQ/GNT (0 < PCI 33Mhz) - Output valid (tDV)
— 12 ns
P10 PCI REQ/GNT (33 < PCI 50Mhz) - Input Setup (tIS)
— 5 ns
P11 PCI REQ (0 < PCI 33Mhz) - Input Setup (tIS)
12 — ns
P12 PCI GNT (0 < PCI 33Mhz) - Input Setup (tIS)
10 — ns
1 Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x
Reference Manual. Also specific guidelines may need to be followed when operating the system PLL below certain
frequencies.
2 Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
3 All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals.
4 PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it
is not required or guaranteed.
5 PCI 2.2 spec requires zero input hold.
6 These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec.
CLKIN
Output
Valid/Hold
Input
Setup/Hold
P1
P4 P6
Output Valid
P2
Input Valid
P7
Figure 18. PCI Timing
11 Fast Ethernet AC Timing Specifications
11.1 MII/7-WIRE Interface Timing Specs
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the EMAC_10_100 I/O signals.
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices. If this
interface is to be used with a specific transceiver device the timing specs may be altered to match that specific transceiver.
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Fast Ethernet AC Timing Specifications
Table 15. MII Receive Signal Timing
Num
Characteristic
M1 RXD[3:0], RXDV, RXER to RXCLK setup
M2 RXCLK to RXD[3:0], RXDV, RXER hold
M3 RXCLK pulse width high
M4 RXCLK pulse width low
Min
5
5
35%
35%
Max
65%
65%
Unit
ns
ns
RXCLK period
RXCLK period
M3
RXCLK (Input)
M1 M4
RXD[3:0] (Inputs)
RXDV,
RXER
M2
Figure 19. MII Receive Signal Timing Diagram
11.2 MII Transmit Signal Timing
Table 16. MII Transmit Signal Timing
Num
Characteristic
M5 TXCLK to TXD[3:0], TXEN, TXER invalid
M6 TXCLK to TXD[3:0], TXEN, TXER valid
M7 TXCLK pulse width high
M8 TXCLK pulse width low
Min
0
35%
35%
Max
25
65%
65%
Unit
ns
ns
TXCLK period
TXCLK period
M7
TXCLK (Input)
M5 M8
TXD[3:0] (Outputs)
TXEN,
TXER
M6
Figure 20. MII Transmit Signal Timing Diagram
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Fast Ethernet AC Timing Specifications
11.3 MII Async Inputs Signal Timing (CRS, COL)
Table 17. MII Transmit Signal Timing
Num
M9
Characteristic
CRS, COL minimum pulse width
Min Max
1.5 —
Unit
TX_CLK period
CRS, COL
M9
Figure 21. MII Async Inputs Timing Diagram
11.4 MII Serial Management Channel Timing (MDIO,MDC)
Table 18. MII Serial Management Channel Signal Timing
Num
M10
M11
M12
M13
M14
M15
Characteristic
MDC falling edge to MDIO output invalid
(min prop delay)
MDC falling edge to MDIO output valid
(max prop delay)
MDIO (input) to MDC rising edge setup
MDIO (input) to MDC rising edge hold
MDC pulse width high
MDC pulse width low
Min
0
10
0
40%
40%
Max Unit
— ns
25 ns
60%
60%
ns
ns
MDC period
MDC period
M14 M15
MDC (Output)
M10
MDIO (Output)
M12 M11
MDIO (Input)
M13
Figure 22. MII Serial Management Channel TIming Diagram
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General Timing Specifications
12 General Timing Specifications
Table 19 lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts.
Table 19. General AC Timing Specifications
Name
Characteristic
G1 CLKIN high to signal output valid
G2 CLKIN high to signal invalid (output hold)
G3 Signal input pulse width
Min Max Unit
— 2 PSTCLK
0 — ns
2 — PSTCLK
13 I2C Input/Output Timing Specifications
Table 20 lists specifications for the I2C input timing parameters shown in Figure 23.
Table 20. I2C Input Timing Specifications between SCL and SDA
Num
Characteristic
Min Max
Units
I1 Start condition hold time
2
I2 Clock low period
8
I3 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
I4 Data hold time
0
I5 SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
I6 Clock high time
4
I7 Data setup time
0
I8 Start condition setup time (for repeated start condition only) 2
I9 Stop condition setup time
2
— Bus clocks
— Bus clocks
1 mS
— ns
1 mS
— Bus clocks
— ns
— Bus clocks
— Bus clocks
Table 21 lists specifications for the I2C output timing parameters shown in Figure 23.
Table 21. I2C Output Timing Specifications between SCL and SDA
Num
I11
I2 1
I3 2
I4 1
I5 3
I6 1
I7 1
I8 1
I9 1
Characteristic
Start condition hold time
Clock low period
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
Data setup time
Start condition setup time (for repeated start
condition only)
Stop condition setup time
Min Max
Units
6 — Bus clocks
10 — Bus clocks
——
µS
7 — Bus clocks
—3
ns
10 — Bus clocks
2 — Bus clocks
20 — Bus clocks
10 — Bus clocks
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JTAG and Boundary Scan Timing
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 21. The
I2C interface is designed to scale the actual data transition time to move it to the middle of the
SCL low period. The actual position is affected by the prescale and division values programmed
into the IFDR; however, the numbers given in Table 21 are minimum values.
2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively
drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance
and pull-up resistor values.
3 Specified at a nominal 50-pF load.
Figure 23 shows timing for the values in Table 20 and Table 21.
I2
I6 I5
SCL
I1 I7
I4 I8
SDA
Figure 23. I2C Input/Output Timings
I3
I9
14 JTAG and Boundary Scan Timing
Table 22. JTAG and Boundary Scan Timing
Num
Characteristics1
Symbol Min
J1 TCLK Frequency of Operation
fJCYC
DC
J2 TCLK Cycle Period
tJCYC
2
J3 TCLK Clock Pulse Width
tJCW
15.15
J4 TCLK Rise and Fall Times
tJCRF
0.0
J5 Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
5.0
J6 Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
24.0
J7 TCLK Low to Boundary Scan Output Data Valid
tBSDV
0.0
J8 TCLK Low to Boundary Scan Output High Z
tBSDZ
0.0
J9 TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
5.0
J10 TMS, TDI Input Data Hold Time after TCLK Rise
tTAPBHT
10.0
J11 TCLK Low to TDO Data Valid
tTDODV
0.0
J12 TCLK Low to TDO High Z
tTDODZ
0.0
J13 TRST Assert Time
tTRSTAT
100.0
J14 TRST Setup Time (Negation) to TCLK High
tTRSTST
10.0
1 MTMOD is expected to be a static signal. Hence, it is not associated with any timing
Max
10
3.0
15.0
15.0
20.0
15.0
Unit
MHz
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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JTAG and Boundary Scan Timing
TCLK (Input)
J2
J3
J3
VIH
VIL
J4 J4
Figure 24. Test Clock Input Timing
TCLK
Data Inputs
Data Outputs
Data Outputs
Data Outputs
VIL
7
8
VIH
56
Input Data Valid
Output Data Valid
7
Output Data Valid
Figure 25. Boundary Scan (JTAG) Timing
TCLK
TDI, TMS, BKPT
TDO
TDO
TDO
VIL
11
12
VIH
9 10
Input Data Valid
Output Data Valid
11
Output Data Valid
Figure 26. Test Access Port Timing
TCLK
TRST
14
13
Figure 27. TRST Timing Debug AC Timing Specifications
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JTAG and Boundary Scan Timing
Table 23 lists specifications for the debug AC timing parameters shown in Figure 29.
Table 23. Debug AC Timing Specifications
Num
Characteristic
50 MHz
Min Max
Units
D1 PSTDDATA to PSTCLK setup
4.5 —
ns
D2 PSTCLK to PSTDDATA hold
4.5 —
ns
D3 DSI-to-DSCLK setup
D4 1 DSCLK-to-DSO hold
1 — PSTCLKs
4 — PSTCLKs
D5 DSCLK cycle time
5 — PSTCLKs
1 DSCLK and DSI are synchronized internally. D4 is measured from the
synchronized DSCLK input relative to the rising edge of CLKOUT.
Figure 28 shows real-time trace timing for the values in Table 23.
PSTCLK
D1 D2
PSTDDATA[7:0]
Figure 28. Real-Time Trace AC Timing
Figure 29 shows BDM serial port AC timing for the values in Table 23.
DSCLK
DSI
D3
DSO
D5
Current
D4
Past
Figure 29. BDM Serial Port AC Timing
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DSPI Electrical Specifications
15 DSPI Electrical Specifications
Table 24 lists DSPI timings.
Table 24. DSPI Modules AC Timing Specifications
Name
Characteristic
DS1 DSPI_CS[3:0] to DSPI_CLK
DS2 DSPI_CLK high to DSPI_DOUT valid.
DS3 DSPI_CLK high to DSPI_DOUT invalid. (Output hold)
DS4 DSPI_DIN to DSPI_CLK (Input setup)
DS5 DSPI_DIN to DSPI_CLK (Input hold)
Min
1 × tck
2
10
10
Max
510 × tck
12
Unit
ns
ns
ns
ns
ns
The values in Table 24 correspond to Figure 30.
DSPI_CS[3:0]
DSPI_CLK
DSPI_DOUT
DSPI_DIN
DS1
DS2
DS3 DS4 DS5
Figure 30. DSPI Timing
16 Timer Module AC Timing Specifications
Table 25 lists timer module AC timings.
Table 25. Timer Module AC Timing Specifications
Name
Characteristic
T1 TIN0 / TIN1 / TIN2 / TIN3 cycle time
T2 TIN0 / TIN1 / TIN2 / TIN3 pulse width
0–50 MHz
Min Max
3—
1—
Unit
PSTCLK
PSTCLK
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Case Drawing
17 Case Drawing
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