PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Intel® PXA250 and PXA210
Application Processors
Developer’s Manual
February 2002
Order Number: 278522-001


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The PXA250 and PXA210 application processors may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled
platforms may require licenses from various entities, including Intel Corporation.
This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the
license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a
commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this
document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may
be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2002
AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic,
DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740,
IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel
NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation,
Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer
logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare,
RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In,
TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other names and brands may be claimed as the property of others.
ii PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
Contents
1 Introduction...................................................................................................................................1-1
1.1 Intel® XScale™ Core Features .........................................................................................1-1
1.2 System Integration Features..............................................................................................1-2
1.2.1 Memory Controller ................................................................................................1-2
1.2.2 Clocks and Power Controllers...............................................................................1-2
1.2.3 Universal Serial Bus (USB) Client.........................................................................1-3
1.2.4 DMA Controller (DMAC) .......................................................................................1-3
1.2.5 LCD Controller ......................................................................................................1-3
1.2.6 AC97 Controller ....................................................................................................1-3
1.2.7 Inter-IC Sound (I2S) Controller .............................................................................1-3
1.2.8 Multimedia Card (MMC) Controller .......................................................................1-3
1.2.9 Fast Infrared (FIR) Communication Port...............................................................1-4
1.2.10 Synchronous Serial Protocol Controller (SSPC)...................................................1-4
1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................1-4
1.2.12 GPIO .....................................................................................................................1-4
1.2.13 UARTs ..................................................................................................................1-4
1.2.14 Real-Time Clock (RTC).........................................................................................1-5
1.2.15 OS Timers.............................................................................................................1-5
1.2.16 Pulse-Width Modulator (PWM) .............................................................................1-5
1.2.17 Interrupt Control ....................................................................................................1-5
2 System Architecture .....................................................................................................................2-1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
Overview ............................................................................................................................2-1
Package Types ..................................................................................................................2-2
Intel® XScale™ Microarchitecture Implementation Options..............................................2-2
2.3.1 Coprocessor 7 Register 4 - PSFS Bit ...................................................................2-3
2.3.2 Coprocessor 14 Registers 0-3 - Performance Monitoring.....................................2-3
2.3.3 Coprocessor 14 Register 6 and 7- Clock and Power Management......................2-3
2.3.4 Coprocessor 15 Register 0 - ID Register Definition ..............................................2-4
2.3.5 Coprocessor 15 Register 1 - P-Bit ........................................................................2-6
I/O Ordering .......................................................................................................................2-6
Semaphores ......................................................................................................................2-6
Interrupts............................................................................................................................2-7
Reset .................................................................................................................................2-7
Internal Registers...............................................................................................................2-8
Selecting Peripherals vs. General Purpose I/O .................................................................2-9
Power on Reset and Boot Operation .................................................................................2-9
Power Management...........................................................................................................2-9
Pin List .............................................................................................................................2-10
Processor Options ...........................................................................................................2-26
Memory Map ....................................................................................................................2-27
Register Address Summary .............................................................................................2-30
3 Clocks and Power Manager .........................................................................................................3-1
3.1 Clock Manager Introduction...............................................................................................3-1
3.2 Power Manager Introduction..............................................................................................3-2
iii PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
3.3 Clock Manager...................................................................................................................3-2
3.3.1 32.768 kHz Oscillator............................................................................................3-4
3.3.2 3.6864 MHz Oscillator ..........................................................................................3-4
3.3.3 Core Phase Locked Loop .....................................................................................3-4
3.3.4 95.85 MHz Peripheral Phase Locked Loop ..........................................................3-5
3.3.5 147.46 MHz Peripheral Phase Locked Loop ........................................................3-6
3.3.6 Clock Gating .........................................................................................................3-6
3.4 Resets and Power Modes..................................................................................................3-6
3.4.1 Hardware Reset....................................................................................................3-7
3.4.2 Watchdog Reset ...................................................................................................3-7
3.4.3 GPIO Reset ..........................................................................................................3-8
3.4.4 Run Mode .............................................................................................................3-9
3.4.5 Turbo Mode ..........................................................................................................3-9
3.4.6 Idle Mode ............................................................................................................3-10
3.4.7 Frequency Change Sequence ............................................................................3-12
3.4.8 Sleep Mode.........................................................................................................3-14
3.4.9 Power Mode Summary .......................................................................................3-18
3.5 Power Manager Registers ...............................................................................................3-20
3.5.1 Power Manager Control Register .......................................................................3-21
3.5.2 Power Manager General Configuration Register................................................3-22
3.5.3 Power Manager Wake-Up Enable Register........................................................3-23
3.5.4 Power Manager Rising-Edge Detect Enable Register........................................3-24
3.5.5 Power Manager Falling-Edge Detect Enable Register .......................................3-25
3.5.6 Power Manager GPIO Edge Detect Status Register ..........................................3-26
3.5.7 Power Manager Sleep Status Register...............................................................3-27
3.5.8 Power Manager Scratch Pad Register ...............................................................3-28
3.5.9 Power Manager GPIO Sleep State Registers.....................................................3-29
3.5.10 Reset Controller Status Register ........................................................................3-30
3.5.11 Power Manager Register Locations....................................................................3-31
3.6 Clocks Manager Registers...............................................................................................3-32
3.6.1 Core Clock Configuration Register .....................................................................3-32
3.6.2 Clock Enable Register ........................................................................................3-34
3.6.3 Oscillator Configuration Register ........................................................................3-36
3.6.4 Clocks Manager Register Locations ...................................................................3-36
3.7 Coprocessor 14: Clock and Power Management ............................................................3-37
3.7.1 CCLKCFG Register (CP14 Register 6) ..............................................................3-37
3.7.2 PWRMODE Register (CP14 Register 7) ............................................................3-38
3.8 External Hardware Considerations ..................................................................................3-38
3.8.1 Power Supply Sequencing..................................................................................3-38
3.8.2 Power-On-Reset Considerations ........................................................................3-38
3.8.3 Power Supply Connectivity .................................................................................3-39
3.8.4 Driving the Crystal Pins from an External Clock Source.....................................3-39
3.8.5 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator...............3-39
4 System Integration Unit ................................................................................................................4-1
4.1 General-Purpose I/O..........................................................................................................4-1
4.1.1 GPIO Operation ....................................................................................................4-1
4.1.2 GPIO Alternate Functions.....................................................................................4-2
4.1.3 GPIO Register Definitions.....................................................................................4-6
4.1.4 GPIO Register Locations ....................................................................................4-21
iv PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
4.2 Interrupt Controller ...........................................................................................................4-22
4.2.1 Interrupt Controller Operation .............................................................................4-22
4.2.2 Interrupt Controller Register Definitions..............................................................4-23
4.2.3 Interrupt Controller Register Locations ...............................................................4-30
4.3 Real-Time Clock ..............................................................................................................4-30
4.3.1 Real-Time Clock Operation.................................................................................4-30
4.3.2 RTC Register Definitions ....................................................................................4-31
4.3.3 Trim Procedure ...................................................................................................4-34
4.3.4 Real-Time Clock Register Locations...................................................................4-37
4.4 Operating System (OS) Timer .........................................................................................4-37
4.4.1 Watchdog Timer Operation.................................................................................4-37
4.4.2 OS Timer Register Definitions ............................................................................4-38
4.4.3 OS Timer Register Locations..............................................................................4-41
4.5 Pulse Width Modulator.....................................................................................................4-42
4.5.1 Pulse Width Modulator Operation .......................................................................4-42
4.5.2 Register Descriptions..........................................................................................4-44
4.5.3 Pulse Width Modulator Output Wave Example...................................................4-47
4.5.4 Register Summary ..............................................................................................4-48
5 DMA Controller .............................................................................................................................5-1
5.1 DMA Description ................................................................................................................5-1
5.1.1 DMAC Channels ...................................................................................................5-2
5.1.2 Signal Descriptions ...............................................................................................5-3
5.1.3 DMA Channel Priority Scheme .............................................................................5-4
5.1.4 DMA Descriptors...................................................................................................5-6
5.1.5 Channel States .....................................................................................................5-9
5.1.6 Read and Write Order...........................................................................................5-9
5.1.7 Byte Transfer Order ..............................................................................................5-9
5.1.8 Trailing Bytes ......................................................................................................5-10
5.2 Transferring Data .............................................................................................................5-11
5.2.1 Servicing Internal Peripherals .............................................................................5-11
5.2.2 Quick Reference for DMA Programming ............................................................5-13
5.2.3 Servicing Companion Chips and External Peripherals .......................................5-14
5.2.4 Memory-to-Memory Moves .................................................................................5-16
5.3 DMAC Registers ..............................................................................................................5-17
5.3.1 DMA Interrupt Register .......................................................................................5-17
5.3.2 DMA Channel Control/Status Register ...............................................................5-17
5.3.3 DMA Request to Channel Map Registers ...........................................................5-20
5.3.4 DMA Descriptor Address Registers ....................................................................5-20
5.3.5 DMA Source Address Registers .........................................................................5-21
5.3.6 DMA Target Address Registers ..........................................................................5-22
5.3.7 DMA Command Registers ..................................................................................5-23
5.4 Examples .........................................................................................................................5-26
5.5 DMAC Registers ..............................................................................................................5-28
6 Memory Controller ........................................................................................................................6-1
6.1 Overview............................................................................................................................6-1
6.2 Functional Description .......................................................................................................6-2
6.2.1 SDRAM Interface Overview ..................................................................................6-2
6.2.2 Static Memory Interface / Variable Latency I/O Interface .....................................6-3
v PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.2.3 16-Bit PC Card / Compact Flash Interface ...........................................................6-4
Memory System Examples ................................................................................................6-4
Memory Accesses .............................................................................................................6-7
6.4.1 Reads and Writes .................................................................................................6-8
6.4.2 Aborts and Nonexistent Memory ..........................................................................6-8
Memory Configuration Registers .......................................................................................6-8
Synchronous DRAM Memory Interface .............................................................................6-9
6.6.1 SDRAM MDCNFG Register..................................................................................6-9
6.6.2 SDRAM Mode Register Set Configuration Register ...........................................6-13
6.6.3 SDRAM MDREFR Register ................................................................................6-14
6.6.4 Fixed-Delay or Return-Clock Data Latching .......................................................6-18
6.6.5 SDRAM Memory Options ...................................................................................6-18
6.6.6 SDRAM Command Overview .............................................................................6-27
6.6.7 SDRAM Waveforms............................................................................................6-29
Synchronous Static Memory Interface.............................................................................6-31
6.7.1 Synchronous Static Memory Configuration Register ..........................................6-31
6.7.2 Synchronous Static Memory Mode Register Set Configuration Register ...........6-37
6.7.3 Synchronous Static Memory Timing Diagrams...................................................6-39
6.7.4 Non-SDRAM Timing SXMEM Operation ............................................................6-39
Asynchronous Static Memory ..........................................................................................6-42
6.8.1 Static Memory Interface......................................................................................6-42
6.8.2 Asynchronous Static Memory Control Registers (MSC2-0)................................6-43
6.8.3 ROM Interface ....................................................................................................6-47
6.8.4 SRAM Interface Overview ..................................................................................6-50
6.8.5 Variable Latency I/O (VLIO) Interface Overview.................................................6-52
6.8.6 FLASH Memory Interface ...................................................................................6-55
16-Bit PC Card/Compact Flash Interface ........................................................................6-56
6.9.1 Expansion Memory Timing Configuration Register ............................................6-57
6.9.2 Expansion Memory Configuration Register (MECR) ..........................................6-60
6.9.3 16-Bit PC Card Overview....................................................................................6-60
6.9.4 External Logic for 16-Bit PC Card Implementation .............................................6-63
6.9.5 Expansion Card Interface Timing Diagrams and Parameters ............................6-66
Companion Chip Interface ...............................................................................................6-67
6.10.1 Alternate Bus Master Mode ................................................................................6-69
Options and Settings for Boot Memory............................................................................6-71
6.11.1 Alternate Booting ................................................................................................6-71
6.11.2 Boot Time Defaults .............................................................................................6-71
6.11.3 Memory Interface Reset and Initialization...........................................................6-75
Hardware, Watchdog, or Sleep Reset Operation ............................................................6-76
GPIO Reset Procedure....................................................................................................6-77
7 LCD Controller..............................................................................................................................7-1
7.1 Overview............................................................................................................................7-1
7.1.1 Features................................................................................................................7-2
7.1.2 Pin Descriptions....................................................................................................7-4
7.2 LCD Controller Operation ..................................................................................................7-4
7.2.1 Enabling the Controller .........................................................................................7-4
7.2.2 Disabling the Controller ........................................................................................7-5
7.2.3 Resetting the Controller ........................................................................................7-5
7.3 Detailed Module Descriptions ............................................................................................7-5
vi PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
7.3.1 Input FIFOs ...........................................................................................................7-6
7.3.2 Lookup Palette ......................................................................................................7-6
7.3.3 Temporal Modulated Energy Distribution (TMED) Dithering.................................7-6
7.3.4 Output FIFOs ........................................................................................................7-8
7.3.5 LCD Controller Pin Usage ....................................................................................7-8
7.3.6 DMA ......................................................................................................................7-9
7.4 LCD External Palette and Frame Buffers ........................................................................7-10
7.4.1 External Palette Buffer ........................................................................................7-10
7.4.2 External Frame Buffer.........................................................................................7-11
7.5 Functional Timing ............................................................................................................7-15
7.6 Register Descriptions.......................................................................................................7-18
7.6.1 LCD Controller Control Register 0 (LCCR0) .......................................................7-19
7.6.2 LCD Controller Control Register 1 (LCCR1) .......................................................7-27
7.6.3 LCD Controller Control Register 2 (LCCR2) .......................................................7-29
7.6.4 LCD Controller Control Register 3 (LCCR3) .......................................................7-32
7.6.5 LCD Controller DMA ...........................................................................................7-36
7.6.6 LCD DMA Frame Branch Registers (FBRx) .......................................................7-41
7.6.7 LCD Controller Status Register (LCSR)..............................................................7-42
7.6.8 LCD Controller Interrupt ID Register (LIIDR) ......................................................7-45
7.6.9 TMED RGB Seed Register .................................................................................7-46
7.6.10 TMED Control Register (TCR) ............................................................................7-47
7.6.11 LCD Controller Register Summary .....................................................................7-49
8 Synchronous Serial Port Controller ..............................................................................................8-1
8.1 Overview............................................................................................................................8-1
8.2 Signal Description..............................................................................................................8-1
8.2.1 External Interface to Synchronous Serial Peripherals ..........................................8-1
8.3 Functional Description .......................................................................................................8-2
8.3.1 Data Transfer ........................................................................................................8-2
8.4 Data Formats .....................................................................................................................8-2
8.4.1 Serial Data Formats for Transfer to/from Peripherals ...........................................8-2
8.4.2 Parallel Data Formats for FIFO Storage ...............................................................8-6
8.5 FIFO Operation and Data Transfers ..................................................................................8-7
8.5.1 Using Programmed I/O Data Transfers ................................................................8-7
8.5.2 Using DMA Data Transfers ...................................................................................8-7
8.6 Baud-Rate Generation.......................................................................................................8-7
8.7 SSP Serial Port Registers..................................................................................................8-8
8.7.1 SSP Control Register 0 (SSCR0) .........................................................................8-8
8.7.2 SSP Control Register 1 (SSCR1) .......................................................................8-11
8.7.3 SSP Data Register (SSDR) ................................................................................8-15
8.7.4 SSP Status Register (SSSR) ..............................................................................8-15
8.7.5 SSP Register Address Map ................................................................................8-18
9 I2C Bus Interface Unit...................................................................................................................9-1
9.1 Overview............................................................................................................................9-1
9.2 Signal Description..............................................................................................................9-1
9.3 Functional Description .......................................................................................................9-2
9.3.1 Operational Blocks................................................................................................9-3
9.3.2 I2C Bus Interface Modes .....................................................................................9-4
9.3.3 Start and Stop Bus States ....................................................................................9-4
vii PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
9.4 I2C Bus Operation .............................................................................................................9-7
9.4.1 Serial Clock Line (SCL) Generation......................................................................9-7
9.4.2 Data and Addressing Management ......................................................................9-7
9.4.3 I2C Acknowledge..................................................................................................9-9
9.4.4 Arbitration .............................................................................................................9-9
9.4.5 Master Operations ..............................................................................................9-12
9.4.6 Slave Operations ................................................................................................9-15
9.4.7 General Call Address..........................................................................................9-16
9.5 Slave Mode Programming Examples ..............................................................................9-18
9.5.1 Initialize Unit .......................................................................................................9-18
9.5.2 Write n Bytes as a Slave.....................................................................................9-18
9.5.3 Read n Bytes as a Slave ....................................................................................9-18
9.6 Master Programming Examples ......................................................................................9-19
9.6.1 Initialize Unit .......................................................................................................9-19
9.6.2 Write 1 Byte as a Master ....................................................................................9-19
9.6.3 Read 1 Byte as a Master ....................................................................................9-20
9.6.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master..............................9-20
9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort ..................................9-21
9.7 Glitch Suppression Logic .................................................................................................9-21
9.8 Reset Conditions .............................................................................................................9-21
9.9 Register Definitions..........................................................................................................9-22
9.9.1 I2C Bus Monitor Register- IBMR ........................................................................9-22
9.9.2 I2C Data Buffer Register- IDBR..........................................................................9-22
9.9.3 I2C Control Register- ICR...................................................................................9-23
9.9.4 I2C Status Register.............................................................................................9-26
9.9.5 I2C Slave Address Register- ISAR .....................................................................9-28
10 UARTs ........................................................................................................................................10-1
10.1
10.2
10.3
10.4
10.5
Feature List......................................................................................................................10-1
Overview .......................................................................................................................... 10-2
10.2.1 Full Function UART ............................................................................................10-2
10.2.2 Bluetooth UART..................................................................................................10-2
10.2.3 Standard UART ..................................................................................................10-2
10.2.4 Compatibility with 16550.....................................................................................10-2
Signal Descriptions ..........................................................................................................10-3
UART Operational Description ........................................................................................10-4
10.4.1 Reset ..................................................................................................................10-5
10.4.2 Internal Register Descriptions.............................................................................10-5
10.4.3 FIFO Interrupt Mode Operation ........................................................................10-21
10.4.4 FIFO Polled Mode Operation............................................................................10-22
10.4.5 DMA Requests..................................................................................................10-22
10.4.6 Slow Infrared Asynchronous Interface..............................................................10-23
Register Summary .........................................................................................................10-26
10.5.1 UART Register Differences ..............................................................................10-28
11 Fast Infrared Communication Port..............................................................................................11-1
11.1 Signal Description............................................................................................................11-1
11.2 FICP Operation................................................................................................................11-1
11.2.1 4PPM Modulation ...............................................................................................11-2
11.2.2 Frame Format .....................................................................................................11-3
viii PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
11.3
11.4
11.2.3 Address Field ......................................................................................................11-4
11.2.4 Control Field .......................................................................................................11-4
11.2.5 Data Field ...........................................................................................................11-4
11.2.6 CRC Field ...........................................................................................................11-4
11.2.7 Baud Rate Generation ........................................................................................11-5
11.2.8 Receive Operation ..............................................................................................11-5
11.2.9 Transmit Operation .............................................................................................11-6
11.2.10 Transmit and Receive FIFOs ..............................................................................11-7
11.2.11 Trailing or Error Bytes in the Receive FIFO ........................................................11-7
FICP Register Definitions ................................................................................................11-8
11.3.1 FICP Control Register 0......................................................................................11-8
11.3.2 FICP Control Register 1....................................................................................11-11
11.3.3 FICP Control Register 2....................................................................................11-12
11.3.4 FICP Data Register...........................................................................................11-13
11.3.5 FICP Status Register 0 .....................................................................................11-14
11.3.6 FICP Status Register 1 .....................................................................................11-16
FICP Register Locations ................................................................................................11-17
12 USB Device Controller................................................................................................................12-1
12.1
12.2
12.3
12.4
12.5
12.6
USB Overview .................................................................................................................12-1
Device Configuration .......................................................................................................12-2
USB Protocol ...................................................................................................................12-2
12.3.1 Signalling Levels .................................................................................................12-3
12.3.2 Bit Encoding........................................................................................................12-3
12.3.3 Field Formats ......................................................................................................12-4
12.3.4 Packet Formats...................................................................................................12-5
12.3.5 Transaction Formats ...........................................................................................12-6
12.3.6 UDC Device Requests ........................................................................................12-8
12.3.7 Configuration ......................................................................................................12-9
UDC Hardware Connection ...........................................................................................12-10
12.4.1 Self-Powered Device ........................................................................................12-10
12.4.2 Bus-Powered Devices ......................................................................................12-11
UDC Operation ..............................................................................................................12-11
12.5.1 Case 1: EP0 Control Read ...............................................................................12-12
12.5.2 Case 2: EP0 Control Read with a Premature Status Stage..............................12-12
12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage............12-13
12.5.4 Case 4: EP0 No Data Command ......................................................................12-14
12.5.5 Case 5: EP1 Data Transmit (BULK-IN).............................................................12-15
12.5.6 Case 6: EP2 Data Receive (BULK-OUT)..........................................................12-16
12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)...........................................12-17
12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)........................................12-18
12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN) .................................................12-20
12.5.10 Case 10: RESET Interrupt ................................................................................12-20
12.5.11 Case 11: SUSPEND Interrupt...........................................................................12-20
12.5.12 Case 12: RESUME Interrupt.............................................................................12-21
UDC Register Definitions ...............................................................................................12-21
12.6.1 UDC Control Register .......................................................................................12-21
12.6.2 UDC Endpoint 0 Control/Status Register (UDCCS0)........................................12-23
12.6.3 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 1, 6, or 11....12-25
12.6.4 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 2, 7, or 12....12-28
ix PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
12.6.5 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 3, 8, or 13....12-30
12.6.6 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 4, 9, or 14....12-32
12.6.7 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 5, 10, or 15..12-34
12.6.8 UDC Interrupt Control Register 0 (UICR0) .......................................................12-37
12.6.9 UDC Interrupt Control Register 1 (UICR1) .......................................................12-38
12.6.10 UDC Status/Interrupt Register 0 (USIR0) .........................................................12-39
12.6.11 UDC Status/Interrupt Register 1 (USIR1) .........................................................12-40
12.6.12 UDC Frame Number High Register (UFNHR) ..................................................12-42
12.6.13 UDC Frame Number Low Register (UFNLR) ...................................................12-44
12.6.14 UDC Byte Count Register x (UBCRx), Where x is 2, 4, 7, 9, 12, or 14. ...........12-45
12.6.15 UDC Endpoint 0 Data Register (UDDR0) .........................................................12-45
12.6.16 UDC Data Register x (UDDRx), Where x is 1, 6, or 11 ....................................12-46
12.6.17 UDC Data Register x (UDDRx), Where x is 2, 7, or 12 ....................................12-47
12.6.18 UDC Data Register x (UDDRx), Where x is 3, 8, or 13 ....................................12-47
12.6.19 UDC Data Register x (UDDRx), Where x is 4, 9, or 14 ....................................12-48
12.6.20 UDC Data Register x (UDDRx), Where x is 5, 10, or 15 ..................................12-48
12.6.21 UDC Register Locations ...................................................................................12-49
13 AC97 Controller Unit...................................................................................................................13-1
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Overview .......................................................................................................................... 13-1
Feature List......................................................................................................................13-1
Signal Description............................................................................................................13-2
13.3.1 Signal Configuration Steps .................................................................................13-2
13.3.2 Example AC-link .................................................................................................13-2
AC-link Digital Serial Interface Protocol...........................................................................13-3
13.4.1 AC-link Audio Output Frame (SDATA_OUT)......................................................13-4
13.4.2 AC-link Audio Input Frame (SDATA_IN).............................................................13-8
AC-link Low Power Mode ..............................................................................................13-12
13.5.1 Powering Down the AC-link ..............................................................................13-12
13.5.2 Waking up the AC-link ......................................................................................13-13
ACUNIT Operation.........................................................................................................13-14
13.6.1 Initialization .......................................................................................................13-15
13.6.2 Trailing bytes ....................................................................................................13-16
13.6.3 Operational Flow for Accessing Codec Registers ............................................13-16
Clocks and Sampling Frequencies ................................................................................13-16
Functional Description ...................................................................................................13-17
13.8.1 FIFOs................................................................................................................13-17
13.8.2 Interrupts...........................................................................................................13-18
13.8.3 Registers...........................................................................................................13-18
14 Inter Integrated-circuit Sound (I2S) Controller............................................................................14-1
14.1
14.2
14.3
Overview .......................................................................................................................... 14-1
Signal Descriptions ..........................................................................................................14-2
Controller Operation ........................................................................................................14-3
14.3.1 Initialization .........................................................................................................14-3
14.3.2 Disabling and Enabling Audio Replay.................................................................14-4
14.3.3 Disabling and Enabling Audio Record ................................................................14-4
14.3.4 Transmit FIFO Errors..........................................................................................14-5
14.3.5 Receive FIFO Errors...........................................................................................14-5
14.3.6 Trailing Bytes ......................................................................................................14-5
x PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
14.4
14.5
14.6
14.7
Serial Audio Clocks and Sampling Frequencies ..............................................................14-5
Data Formats ...................................................................................................................14-6
14.5.1 FIFO and Memory Format ..................................................................................14-6
14.5.2 I2S and MSB-Justified Serial Audio Formats......................................................14-6
Registers..........................................................................................................................14-8
14.6.1 Serial Audio Controller Global Control Register (SACR0) ..................................14-8
14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1) ..............14-11
14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)................14-12
14.6.4 Serial Audio Clock Divider Register (SADIV)....................................................14-13
14.6.5 Serial Audio Interrupt Clear Register (SAICR)..................................................14-14
14.6.6 Serial Audio Interrupt Mask Register (SAIMR) .................................................14-15
14.6.7 Serial Audio Data Register (SADR) ..................................................................14-15
14.6.8 Controller: Register Memory Map .....................................................................14-16
Interrupts........................................................................................................................14-17
15 MultiMediaCard Controller ..........................................................................................................15-1
15.1
15.2
15.3
15.4
15.5
Overview ..........................................................................................................................15-1
MMC Controller Functional Description ...........................................................................15-4
15.2.1 Signal Description ...............................................................................................15-5
15.2.2 MMC Controller Reset ........................................................................................15-5
15.2.3 Card Initialization Sequence ...............................................................................15-5
15.2.4 MMC and SPI Modes..........................................................................................15-5
15.2.5 Error Detection....................................................................................................15-7
15.2.6 Interrupts.............................................................................................................15-7
15.2.7 Clock Control ......................................................................................................15-7
15.2.8 Data FIFOs .........................................................................................................15-8
Card Communication Protocol .......................................................................................15-11
15.3.1 Basic, No Data, Command and Response Sequence ......................................15-11
15.3.2 Data Transfer ....................................................................................................15-12
15.3.3 Busy Sequence.................................................................................................15-15
15.3.4 SPI Functionality ...............................................................................................15-16
MultiMediaCard Controller Operation ............................................................................15-16
15.4.1 Start and Stop Clock .........................................................................................15-16
15.4.2 Initialize .............................................................................................................15-16
15.4.3 Enabling SPI Mode ...........................................................................................15-16
15.4.4 No Data Command and Response Sequence..................................................15-17
15.4.5 Erase ................................................................................................................15-17
15.4.6 Single Data Block Write ....................................................................................15-17
15.4.7 Single Block Read ............................................................................................15-18
15.4.8 Multiple Block Write ..........................................................................................15-19
15.4.9 Multiple Block Read ..........................................................................................15-19
15.4.10 Stream Write .....................................................................................................15-20
15.4.11 Stream Read.....................................................................................................15-21
MMC Controller Registers .............................................................................................15-22
15.5.1 MMC_STRPCL Register...................................................................................15-23
15.5.2 MMC_STAT Register........................................................................................15-24
15.5.3 MMC_CLKRT Register .....................................................................................15-26
15.5.4 MMC_SPI Register ...........................................................................................15-27
15.5.5 MMC_CMDAT Register ....................................................................................15-28
15.5.6 MMC_RESTO Register.....................................................................................15-29
xi PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
15.5.7 MMC_RDTO Register.......................................................................................15-29
15.5.8 MMC_BLKLEN Register ...................................................................................15-30
15.5.9 MMC_NOB Register .........................................................................................15-30
15.5.10 MMC_PRTBUF Register ..................................................................................15-31
15.5.11 MMC_I_MASK Register....................................................................................15-31
15.5.12 MMC_I_REG Register ......................................................................................15-32
15.5.13 MMC_CMD Register.........................................................................................15-34
15.5.14 MMC_ARGH Register ......................................................................................15-36
15.5.15 MMC_ARGL Register .......................................................................................15-36
15.5.16 MMC_RES FIFO (read only) ............................................................................15-37
15.5.17 MMC_RXFIFO FIFO (read only).......................................................................15-37
15.5.18 MMC_TXFIFO FIFO .........................................................................................15-38
Figures
2-1 Block Diagram ...........................................................................................................................2-2
2-2 Memory Map (Part One) — From 0x8000 0000 to 0xFFFF FFFF...........................................2-28
2-3 Memory Map (Part Two) — From 0x0000 0000 to 0x7FFF FFFF ...........................................2-29
3-1
4-1
4-2
4-3
4-4
5-1
5-2
5-3
5-4
5-5
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
Clocks Manager Block Diagram ................................................................................................3-3
General-Purpose I/O Block Diagram .........................................................................................4-2
Interrupt Controller Block Diagram ..........................................................................................4-23
PWMn Block Diagram .............................................................................................................4-43
Basic Pulse Width Waveform ..................................................................................................4-47
DMAC Block Diagram................................................................................................................5-2
DREQ timing requirements........................................................................................................5-3
No-Descriptor Fetch Mode Channel State.................................................................................5-7
Descriptor Fetch Mode Channel State ......................................................................................5-8
Little Endian Transfers.............................................................................................................5-10
General Memory Interface Configuration ..................................................................................6-2
SDRAM Memory System Example............................................................................................6-5
Asynchronous Static Memory System Example ........................................................................6-6
External to Internal Address Mapping Options ........................................................................6-19
Basic SDRAM Timing Parameters ..........................................................................................6-29
SDRAM 4-Beat Read/ 4-Beat Write To Different Partitions.....................................................6-30
SDRAM 4-Beat Write / 4-Write Same Bank, Same Row .........................................................6-30
SMROM Read Timing Diagram Half-Memory Clock Frequency, ............................................6-39
Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode) ..........................6-41
MSC0/1/2 Register Bitmap ......................................................................................................6-43
32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram(MSC0:RDF = 4, MSC0:RDN = 1,
MSC0:RRR = 1).......................................................................................................................6-48
Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash(MSC0:RDF = 4, MSC0:RDN = 1,
MSC0:RRR = 0).......................................................................................................................6-49
32-Bit Non-burst ROM, SRAM, or Flash Read Timing Diagram - Four Data Beats(MSC0:RDF =
4, MSC0:RRR = 1)...................................................................................................................6-50
32-Bit SRAM Write Timing Diagram (4-beat Burst)(MSC0:RDF = 2, MSC0:RRR = 1) ...........6-51
32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat) (MSC0:RDF
= 2, MSC0:RDN = 2, MSC0:RRR = 1) 6-53
32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variable Wait Cycles Per Beat)......6-54
Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes) .................................................6-56
MCMEM1 Register Bitmap ......................................................................................................6-57
xii PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-14
7-13
7-15
7-16
7-17
8-1
8-2
8-3
8-4
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
10-1
MCATT1 Register Bitmap........................................................................................................6-57
MCIO1 Register Bitmap...........................................................................................................6-58
16-Bit PC Card Memory Map...................................................................................................6-61
Expansion Card External Logic for a One-Socket Configuration.............................................6-64
Expansion Card External Logic for a Two-Socket Configuration.............................................6-65
16-Bit PC Card Memory or I/O 16-Bit (Half-word) Access.......................................................6-66
16-Bit PC Card I/O 16-Bit Access to 8-Bit Device ...................................................................6-67
Alternate Bus Master Mode .....................................................................................................6-68
Variable Latency IO .................................................................................................................6-68
Asynchronous Boot Time Configurations and Register Defaults.............................................6-73
SMROM Boot Time Configurations and Register Defaults......................................................6-74
SMROM Boot Time Configurations and Register Defaults (Continued) ..................................6-75
LCD Controller Block Diagram...................................................................................................7-3
Temporal Dithering Concept - Single Color ...............................................................................7-6
Compare Range for TMED ........................................................................................................7-7
TMED Block Diagram ...............................................................................................................7-8
Palette Buffer Format...............................................................................................................7-11
1 Bit Per Pixel Data Memory Organization ..............................................................................7-11
2 Bits Per Pixel Data Memory Organization ............................................................................7-12
4 Bits Per Pixel Data Memory Organization ............................................................................7-12
8 Bits Per Pixel Data Memory Organization ............................................................................7-12
16 Bits Per Pixel Data Memory Organization - Passive Mode.................................................7-13
16 Bits Per Pixel Data Memory Organization - Active Mode ...................................................7-13
Passive Mode Start-of-Frame Timing ......................................................................................7-15
Passive Mode Pixel Clock and Data Pin Timing......................................................................7-16
Passive Mode End-of-Frame Timing .......................................................................................7-16
Active Mode Timing .................................................................................................................7-17
Active Mode Pixel Clock and Data Pin Timing.........................................................................7-18
LCD Data-Pin Pixel Ordering...................................................................................................7-26
Texas Instruments’ Synchronous Serial Frame* Format ...........................................................8-4
Motorola SPI* Frame Format.....................................................................................................8-5
National Microwire* Frame Format ............................................................................................8-6
Motorola SPI* Frame Formats for SPO and SPH Programming .............................................8-13
I2C Bus Configuration Example ................................................................................................9-2
Start and Stop Conditions..........................................................................................................9-5
START and STOP Conditions ...................................................................................................9-6
Data Format of First Byte in Master Transaction .......................................................................9-8
Acknowledge on the I2C Bus.....................................................................................................9-9
Clock Synchronization During the Arbitration Procedure.........................................................9-10
Arbitration Procedure of Two Masters .....................................................................................9-11
Master-Receiver Read from Slave-Transmitter .......................................................................9-14
Master-Receiver Read from Slave-Transmitter / Repeated Start / Master-Transmitter Write to
Slave-Receiver ........................................................................................................................9-14
A Complete Data Transfer .......................................................................................................9-14
Master-Transmitter Write to Slave-Receiver............................................................................9-16
Master-Receiver Read to Slave-Transmitter ...........................................................................9-16
Master-Receiver Read to Slave-Transmitter, Repeated START, Master-Transmitter Write to
Slave-Receiver ........................................................................................................................9-16
General Call Address...............................................................................................................9-17
Example UART Data Frame ....................................................................................................10-4
xiii PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
10-2
10-3
10-4
11-1
11-2
11-3
12-4
12-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
14-1
14-2
14-3
15-1
15-2
15-3
15-4
15-5
15-6
Example NRZ Bit Encoding – (0b0100 1011 ...........................................................................10-5
IR Transmit and Receive Example ........................................................................................10-25
XMODE example...................................................................................................................10-26
4PPM Modulation Encodings ..................................................................................................11-2
4PPM Modulation Example .....................................................................................................11-3
Frame Format for IrDA Transmission (4.0 Mbps) ....................................................................11-3
NRZI Bit Encoding Example ....................................................................................................12-4
Self-Powered Device .............................................................................................................12-10
Data Transfer Through the AC-link..........................................................................................13-3
AC97 Standard Bidirectional Audio Frame..............................................................................13-4
AC-link Audio Output Frame....................................................................................................13-5
Start of Audio Output Frame....................................................................................................13-5
AC97 Input Frame ...................................................................................................................13-9
Start of an Audio Input Frame .................................................................................................13-9
AC-link Powerdown Timing ...................................................................................................13-12
SDATA_IN Wake Up Signaling .............................................................................................13-13
PCM Transmit and Receive Operation..................................................................................13-27
Mic-in Receive-Only Operation..............................................................................................13-29
Modem Transmit and Receive Operation ..............................................................................13-32
I2S Data Formats (16 bits) ......................................................................................................14-7
MSB-Justified Data Formats (16 bits)......................................................................................14-7
Transmit and Receive FIFO Accesses Through the SADR...................................................14-16
MMC System Interaction .........................................................................................................15-1
MMC Mode Operation Without Data Token ............................................................................15-3
MMC Mode Operation With Data Token .................................................................................15-3
SPI Mode Operation Without Data Token ...............................................................................15-3
SPI Mode Read Operation ......................................................................................................15-4
SPI Mode Write Operation.......................................................................................................15-4
Tables
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
3-1
3-2
3-3
3-4
3-5
3-6
3-7
CPU Core Fault Register Bitmap and Bit Definitions (Read-only) .............................................2-3
ID Register Bitmap and Bit Definitions (Read-only)...................................................................2-5
PXA250 ID Values .....................................................................................................................2-5
PXA210 ID Values .....................................................................................................................2-6
Effect of Each Type of Reset on Internal Register State ...........................................................2-8
Application Processor Pin Types ............................................................................................. 2-10
Pin & Signal Descriptions for the PXA250 Application Processor ...........................................2-10
Pin Description Notes ..............................................................................................................2-18
Pin & Signal Descriptions for the PXA210 Application Processor ...........................................2-19
Pin Description Notes ..............................................................................................................2-26
Signals Not Supported for the PXA210 Application Processor ...............................................2-26
Register Address Summary.....................................................................................................2-30
Core PLL Output Frequencies for 3.6864 MHz Crystal .............................................................3-5
95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ..................................3-5
147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ................................3-6
Power Mode Entry Sequence Table .......................................................................................3-18
Power Mode Exit Sequence Table .........................................................................................3-19
Power and Clock Supply Sources and States During Power Modes .....................................3-20
Power Manager Control Register ............................................................................................3-21
xiv PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
PCFR Register Bitmap and Bit Definitions ..............................................................................3-22
PWER Register Bitmap and Bit Definitions .............................................................................3-23
PRER Register Bitmap and Bit Definitions ..............................................................................3-24
PFER Register Bitmap and Bit Definitions...............................................................................3-25
PEDR Register Bitmap and Bit Definitions ..............................................................................3-26
PSSR Register Bitmap and Bit Definitions ..............................................................................3-27
PSPR Register Bitmap and Bit Definitions ..............................................................................3-28
PGSR0 Register Bitmap and Bit Definitions ............................................................................3-29
PGSR1 Register Bitmap and Bit Definitions ............................................................................3-29
PGSR2 Register Bitmap and Bit Definitions ............................................................................3-30
RCSR Register Bitmap and Bit Definitions ..............................................................................3-31
Power Manager Register Locations.........................................................................................3-31
CCCR Register Bitmap and Bit Definitions..............................................................................3-33
CKEN Register Bitmap and Bit Definitions ..............................................................................3-34
OSCC Register Bitmap and Bit Definitions..............................................................................3-36
Clocks Manager Register Locations ........................................................................................3-36
Coprocessor 14 Clock and Power Management Summary.....................................................3-37
CCLKCFG Register Bitmap and Bit Definitions .......................................................................3-37
PWRMODE Register Bitmap and Bit Definitions .....................................................................3-38
GPIO Alternate Functions..........................................................................................................4-3
GPIO Register Definitions..........................................................................................................4-6
GPLR0 Register Bitmap ............................................................................................................4-7
GPLR1 Register Bitmap ............................................................................................................4-8
GPLR2 Register Bitmap ............................................................................................................4-8
GPDR0 Register Bitmap............................................................................................................4-9
GPDR1 Register Bitmap............................................................................................................4-9
GPDR2 Register Bitmap............................................................................................................4-9
GPSR0 Register Bitmap ..........................................................................................................4-10
GPSR1 Register Bitmap ..........................................................................................................4-10
GPSR2 Register Bitmap ..........................................................................................................4-11
GPCR0 Register Bitmap..........................................................................................................4-11
GPCR1 Register Bitmap..........................................................................................................4-11
GPCR2 Register Bitmap..........................................................................................................4-12
GRER0 Register Bitmap..........................................................................................................4-13
GRER1 Register Bitmap..........................................................................................................4-13
GRER2 Register Bitmap..........................................................................................................4-13
GFER0 Register Bitmap ..........................................................................................................4-14
GFER1 Register Bitmap ..........................................................................................................4-14
GFER2 Register Bitmap ..........................................................................................................4-14
GEDR0 Register Bitmap..........................................................................................................4-15
GEDR1 Register Bitmap..........................................................................................................4-16
GEDR2 Register Bitmap..........................................................................................................4-16
GAFR0_L Register Bitmap ......................................................................................................4-17
GAFR0_U Register Bitmap......................................................................................................4-18
GAFR1_L Register Bitmap ......................................................................................................4-18
GAFR1_U Register Bitmap......................................................................................................4-19
GAFR2_L Register Bitmap ......................................................................................................4-19
GAFR2_U Register Bitmap......................................................................................................4-20
GPIO Register Addresses .......................................................................................................4-21
ICMR Register Bitmap .............................................................................................................4-24
xv PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
4-46
4-47
4-48
4-49
4-50
4-51
4-52
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
ICLR Register Bitmap..............................................................................................................4-24
ICCR Register Bitmap .............................................................................................................4-25
ICIP Register Bitmap ...............................................................................................................4-26
ICFP Register Bitmap..............................................................................................................4-26
ICPR Register Bitmap .............................................................................................................4-27
List of First–Level Interrupts ....................................................................................................4-29
Interrupt Controller Register Addresses ..................................................................................4-30
RTTR Register Bitmap ............................................................................................................4-32
RTAR Register Bitmap ............................................................................................................4-32
RCNR Register Bitmap............................................................................................................4-33
RTSR Register Bitmap ............................................................................................................4-34
RTC Register Addresses .........................................................................................................4-37
OSMR[x] Register Bitmap .......................................................................................................4-38
OIER Register Bitmap .............................................................................................................4-39
OWER Register Bitmap ...........................................................................................................4-39
OSCR Register Bitmap............................................................................................................4-40
OS Timer Register Locations ..................................................................................................4-41
PWM_CTRLn Register Bitmap ................................................................................................4-45
PWM_DUTYn Register Bitmap ...............................................................................................4-46
PWM_PERVALn Register Bitmap ...........................................................................................4-47
PWM Register Locations .........................................................................................................4-48
DMAC Signal List ......................................................................................................................5-3
Channel Priority (if all channels are running concurrently) ........................................................5-5
Channel Priority .........................................................................................................................5-5
Priority Schemes Examples.......................................................................................................5-5
DMA Quick Reference for Internal Peripherals .......................................................................5-13
DINT Register Bitmap and Bit Definitions................................................................................5-17
DMA Channel Control/Status Register Bitmap and Bit Definitions ..........................................5-18
DRCMRx Registers Bitmap Bit Definitions ..............................................................................5-20
DMA Descriptor Address Register Bit Definitions....................................................................5-21
DSADRx Register Bitmap Bit Definitions.................................................................................5-22
DTADRx Register Bitmap Bit Definitions .................................................................................5-23
DCMDx Register Bitmap and Bit Definitions ...........................................................................5-24
DMA Controller Registers ........................................................................................................5-28
Device Transactions ..................................................................................................................6-7
Memory Interface Control Registers ..........................................................................................6-9
MDCNFG Register Bitmap and Bit Definitions ........................................................................6-10
MDMRS Register Bitmap ........................................................................................................6-13
MDREFR Register Bitmap.......................................................................................................6-15
Sample SDRAM Memory Size Options ...................................................................................6-18
External to Internal Address Mapping for Normal Bank Addressing .......................................6-20
External to Internal Address Mapping for SA-1111 Addressing ..............................................6-22
Pin Mapping to SDRAM Devices with Normal Bank Addressing.............................................6-24
Pin Mapping to SDRAM Devices with SA1111 Addressing.....................................................6-26
SDRAM Command Encoding ..................................................................................................6-28
SDRAM Mode Register Opcode Table....................................................................................6-28
SXCNFG Register Bitmap .......................................................................................................6-31
SXCNFG Register Bitmap .......................................................................................................6-36
Synchronous Static Memory External to Internal Address Mapping Options ..........................6-36
SXMRS Register Bitmap .........................................................................................................6-38
xvi PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
6-17
6-18
6-20
6-19
6-21
6-22
6-23
6-25
6-24
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
8-1
8-2
8-3
8-4
8-5
8-6
8-7
9-1
9-2
9-3
Read Configuration Register Programming Values.................................................................6-40
Frequency Code Configuration Values Based on Clock Speed ..............................................6-40
16-Bit Bus Write Access ..........................................................................................................6-43
32-Bit Bus Write Access ..........................................................................................................6-43
MSC0/1/2 Register Bit Definitions ...........................................................................................6-44
Asynchronous Static Memory and Variable Latency I/O Capabilities......................................6-47
MCMEMx Register Bitmap ......................................................................................................6-57
MCIOx Register Bitmap ...........................................................................................................6-58
MCATTx Register Bitmap ........................................................................................................6-58
Card Interface Command Assertion Code Table.....................................................................6-59
MECR Configuration Register Bitmap .....................................................................................6-60
Common Memory Space Write Commands ............................................................................6-62
Common Memory Space Read Commands ............................................................................6-62
Attribute Memory Space Write Commands .............................................................................6-62
Attribute Memory Space Read Commands .............................................................................6-62
16-Bit I/O Space Write Commands (nIOIS16 = 0)...................................................................6-62
16-Bit I/O Space Read Commands (nIOIS16 = 0)...................................................................6-62
8-Bit I/O Space Write Commands (nIOIS16 = 1) .....................................................................6-62
8-Bit I/O Space Read Commands (nIOIS16 = 1).....................................................................6-63
BOOT_SEL Definitions ............................................................................................................6-71
BOOT_DEF Register Bitmap...................................................................................................6-72
Valid Boot Configurations Based on Processor Type..............................................................6-72
Memory Controller Pin Reset Values.......................................................................................6-75
Pin Descriptions.........................................................................................................................7-4
LCD Controller Control Register 0 ...........................................................................................7-19
Frame Buffer/Palette Output to LCD Data Pins in Active Mode ..............................................7-23
LCD Controller Data Pin Utilization..........................................................................................7-25
LCD Controller Control Register 1 ...........................................................................................7-27
LCD Controller Control Register 2 ...........................................................................................7-30
LCD Controller Control Register 3 ...........................................................................................7-32
LCD DMA Frame Descriptor Address Registers .....................................................................7-37
LCD DMA Frame Source Address Registers ..........................................................................7-38
LCD Frame ID Registers .........................................................................................................7-38
LCD DMA Command Registers...............................................................................................7-39
LCD DMA Frame Branch Registers (FBRx) ............................................................................7-41
LCD Controller Status Register ...............................................................................................7-42
LCD Controller Interrupt ID Register........................................................................................7-46
TMED RGB Seed Register ......................................................................................................7-46
TMED Control Register............................................................................................................7-47
LCD Controller Register Locations ..........................................................................................7-49
External Interface to Codec .......................................................................................................8-1
SSP Control Register 0 (SSCR0) Bitmap and Bit Definitions ....................................................8-9
SSP Control Register 1 (SSCR1) Bitmap and Definitions .......................................................8-11
TFT and RFT Values for DMA Servicing .................................................................................8-15
SSP Data Register (SSDR) Bitmap and Definitions ................................................................8-15
SSP Status Register (SSSR) Bitmap and Bit Definitions.........................................................8-16
SSP Register Address Map .....................................................................................................8-18
MMC Signal Description ............................................................................................................9-1
I2C Bus Definitions ...................................................................................................................9-2
Modes of Operation ...................................................................................................................9-4
xvii PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
10-21
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
12-9
12-10
12-11
12-12
12-13
12-14
12-15
12-16
12-17
12-18
12-19
START and STOP Bit Definitions ..............................................................................................9-5
Master Transactions ................................................................................................................9-12
Slave Transactions ..................................................................................................................9-15
General Call Address Second Byte Definitions .......................................................................9-17
I2C Register Addresses...........................................................................................................9-22
I2C Bus Monitor Register - IBMR ...........................................................................................9-22
I2C Data Buffer Register - IDBR.............................................................................................9-23
I2C Control Register - ICR......................................................................................................9-23
I2C Status Register - ISR .......................................................................................................9-26
I2C Slave Address Register - ISAR ........................................................................................9-28
UART Signal Descriptions .......................................................................................................10-3
UART Register Addresses as Offsets of a Base .....................................................................10-6
Receive Buffer Register...........................................................................................................10-6
Transmit Holding Register .......................................................................................................10-7
Divisor Latch Low Register ......................................................................................................10-8
Divisor Latch High Register .....................................................................................................10-8
Interrupt Enable Register.........................................................................................................10-9
Interrupt Conditions ...............................................................................................................10-10
Interrupt Identification Register..............................................................................................10-10
Interrupt Identification Register Decode ................................................................................10-11
FIFO Control Register ...........................................................................................................10-12
Line Control Register .............................................................................................................10-14
Line Status Register ..............................................................................................................10-15
Modem Control Register........................................................................................................10-18
Modem Status Register .........................................................................................................10-20
Scratch Pad Register – SPR .................................................................................................10-21
Infrared Selection Register ....................................................................................................10-24
FFUART Register Addresses ................................................................................................10-26
BTUART Register Locations .................................................................................................10-27
STUART Register Locations .................................................................................................10-27
Flow Control Registers in BTUART and STUART.................................................................10-28
FICP Signal Description ..........................................................................................................11-1
Fast Infrared Communication Port Control Register 0.............................................................11-9
Fast Infrared Communication Port Control Register 1...........................................................11-11
Fast Infrared Communication Port Control Register 2...........................................................11-12
Fast Infrared Communication Port Data Register..................................................................11-13
Fast Infrared Communication Port Status Register 0 ............................................................11-14
Fast Infrared Communication Port Status Register 1 ............................................................11-16
FICP Control, Data, and Status Register Locations ..............................................................11-17
Endpoint Configuration ............................................................................................................12-2
USB States ..............................................................................................................................12-3
IN, OUT, and SETUP Token Packet Format ...........................................................................12-5
SOF Token Packet Format ......................................................................................................12-5
Data Packet Format.................................................................................................................12-6
Handshake Packet Format ......................................................................................................12-6
Bulk Transaction Formats........................................................................................................12-7
Isochronous Transaction Formats ...........................................................................................12-7
Control Transaction Formats ...................................................................................................12-7
Interrupt Transaction Formats .................................................................................................12-8
Host Device Request Summary ..............................................................................................12-9
xviii PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
12-20
12-21
12-22
12-23
12-24
12-25
12-26
12-27
12-28
12-29
12-30
12-31
12-32
12-33
12-34
12-35
12-36
12-37
12-38
12-39
12-40
13-41
13-42
13-43
13-44
13-45
13-46
13-47
13-48
13-49
13-50
13-51
13-52
13-53
13-54
13-55
13-56
13-57
13-58
13-59
13-60
13-61
13-62
13-63
13-64
14-1
14-2
14-3
14-4
14-5
UDC Control Register ............................................................................................................12-23
UDC Endpoint 0 Control Status Register...............................................................................12-25
UDC Endpoint x Control Status Register, Where x is 1, 6 or 11............................................12-27
UDC Endpoint x Control Status Register, Where x is 2, 7, or 12...........................................12-29
UDC Endpoint x Control Status Register, Where x is 3, 8, or 13...........................................12-32
UDC Endpoint x Control Status Register, Where x is 4, 9, or 14...........................................12-34
UDC Endpoint x Control Status Register, Where x is 5, 10, or 15.........................................12-36
UDC Interrupt Control Register 0...........................................................................................12-37
UDC Interrupt Control Register 1...........................................................................................12-38
UDC Status / Interrupt Register 0 ..........................................................................................12-40
UDC Status / Interrupt Register 1 ..........................................................................................12-42
UDC Frame Number High Register .......................................................................................12-43
UDC Frame Number Low Register........................................................................................12-44
UDC Byte Count Register x, Where x is 2, 4, 7, 9, 12, or 14.................................................12-45
UDC Endpoint 0 Data Register..............................................................................................12-46
UDC Endpoint x Data Register, Where x is 1, 6, or 11..........................................................12-46
UDC Endpoint x Data Register, Where x is 2, 7, or 12..........................................................12-47
UDC Endpoint x Data Register, where x is 3, 8, or 13...........................................................12-47
UDC Endpoint x Data Register, Where x is 4, 9, or 14..........................................................12-48
UDC Endpoint x Data Register, Where x is 5, 10, or 15........................................................12-48
UDC Control, Data, and Status Register Locations...............................................................12-49
External Interface to Codecs ...................................................................................................13-2
Supported Data Stream Formats.............................................................................................13-3
Slot 1 Bit Definitions.................................................................................................................13-7
Slot 2 Bit Definitions.................................................................................................................13-7
Input Slot 1 Bit Definitions......................................................................................................13-10
Input Slot 2 Bit Definitions......................................................................................................13-11
Register Mapping Summary ..................................................................................................13-19
Global Control Register .........................................................................................................13-20
Global Status Register...........................................................................................................13-22
PCM-Out Control Register.....................................................................................................13-24
PCM-In Control Register (PICR)............................................................................................13-24
PCM-Out Status Register ......................................................................................................13-25
PCM_In Status Register ........................................................................................................13-25
Codec Access Register .........................................................................................................13-26
PCM Data Register................................................................................................................13-26
Mic-In Control Register ..........................................................................................................13-27
Mic-In Status Register ...........................................................................................................13-28
Mic-In Data Register ..............................................................................................................13-28
Modem-Out Control Register.................................................................................................13-29
Modem-In Control Register....................................................................................................13-30
Modem-Out Status Register ..................................................................................................13-30
Modem-In Status Register .....................................................................................................13-31
Modem Data Register............................................................................................................13-31
Address Mapping for Codec Registers ..................................................................................13-33
External Interface to CODEC...................................................................................................14-2
Supported Sampling Frequencies ...........................................................................................14-6
SACR0 Bit Descriptions...........................................................................................................14-9
FIFO Write/Read table...........................................................................................................14-10
TFTH and RFTH Values for DMA Servicing ..........................................................................14-10
xix PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
14-6
14-7
14-8
14-9
14-10
14-11
14-12
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
15-18
15-19
15-20
15-21
15-22
15-23
15-24
SACR1 Bit Descriptions.........................................................................................................14-11
SASR0 Bit Descriptions .........................................................................................................14-12
SADIV Bit Descriptions ..........................................................................................................14-14
SAICR Bit Descriptions..........................................................................................................14-14
SAIMR Bit Descriptions .........................................................................................................14-15
SADR Bit Descriptions...........................................................................................................14-15
Register Memory Map ...........................................................................................................14-17
Command Token Format.........................................................................................................15-2
MMC Data Token Format ........................................................................................................15-2
SPI Data Token Format...........................................................................................................15-2
MMC Signal Description ..........................................................................................................15-5
MMC Controller Registers .....................................................................................................15-22
MMC_STRPCL Register .......................................................................................................15-23
MMC_STAT Register ............................................................................................................15-24
MMC_CLK Register...............................................................................................................15-26
MMC_SPI Register ................................................................................................................15-27
MMC_CMDAT Register .........................................................................................................15-28
MMC_RESTO Register .........................................................................................................15-29
MMC_RDTO Register ...........................................................................................................15-29
MMC_BLKLEN Register ........................................................................................................15-30
MMC_NOB Register ..............................................................................................................15-30
MMC_PRTBUF Register .......................................................................................................15-31
MMC_I_MASK Register ........................................................................................................15-31
MMC_I_REG Register ...........................................................................................................15-33
MMC_CMD Register .............................................................................................................15-34
Command Index Values ........................................................................................................15-34
MMC_ARGH Register ...........................................................................................................15-36
MMC_ARGL Register ............................................................................................................15-36
MMC_RES, FIFO Entry .........................................................................................................15-37
MMC_RXFIFO, FIFO Entry ...................................................................................................15-37
MMC_TXFIFO, FIFO Entry....................................................................................................15-38
xx PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Revision History
Date
February 2002
November 2001
December 2001
Revision
Public Release 1.0
1.5
1.5
Description
Released to the public
Released for publication
VLIO operation changed
Contents
PXA250 and PXA210 Application Processors Developer’s Manual
xxi


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Contents
xxii PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Introduction
1
This document applies to both the Intel® PXA250 and the PXA210 application processors. They
are Application Specific Standard Products (ASSP) that provide industry-leading MIPS/mW
performance for Handheld Computing Applications. Each application processor is a highly
integrated system on a chip and includes a high-performance low-power Intel® XScale™ Core
with a variety of different system peripherals.
The PXA250 application processor is a 17x17mm 256-pin PBGA package configuration for high
performance. The 17x17mm package has a 32-bit memory data bus and the full assortment of
peripherals.
The PXA210 is a 13x13mm 255 pin T-PBGA package for a smaller form factor. The 13x13mm
package has a 16-bit memory data bus and some reduction in available peripherals.
Note: See section Section 2.13, “Processor Options” on page 2-26 for a list of the features supported by
the PXA250 application processor, but not by the PXA210.
Throughout the other chapters in this document, the phrase “application processor” applies to both
the PXA250 and PXA210 application processors, unless otherwise noted.
1.1
Intel® XScale™ Core Features
The Intel XScale Core provides the following features:
ARM™ Version 5TE ISA compliant.
— ARM Thumb Instruction Support
— ARM DSP Enhanced Instructions
Low power consumption and high performance
Intel Media Processing Technology
— Enhanced 16-bit Multiply
— 40-bit Accumulator
32-KByte Instruction Cache
32-KByte Data Cache
2-KByte Mini Data Cache
2-KByte Mini Instruction Cache
Instruction and Data Memory Management Units
Branch Target Buffer
Debug Capability via JTAG Port
Refer to the Intel XScale Core Developer’s Manual for more details.
PXA250 and PXA210 Application Processors Developer’s Manual
1-1


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Introduction
1.2 System Integration Features
The application processor integrates the Intel XScale Core with the following peripheral set:
Memory Controller
Clock and Power Controllers
Universal Serial Bus Client
DMA Controller
LCD Controller
AC97
I2S
MultiMediaCard
FIR Communication
Synchronous Serial Protocol Port
I2C
General Purpose I/O pins
UARTs
Real-Time Clock
OS Timers
Pulse Width Modulation
Interrupt Control
1.2.1 Memory Controller
The Memory Controller provides glueless control signals with programmable timing for a wide
assortment of memory-chip types and organizations. It supports up to four SDRAM partitions; six
static chip selects for SRAM, SSRAM, Flash, ROM, SROM, and companion chips; support for two
PCMCIA or Compact Flash slots
Note: The PXA210 application processor does not support PCMCIA, Compact Flash, or variable-latency I/O.
1.2.2
Clocks and Power Controllers
The application processor functional blocks are driven by clocks that are derived from a 3.6864-
MHz crystal and an optional 32.768-kHz crystal.
The 3.6864-MHz crystal drives a core Phase Locked Loop (PLL) and a Peripheral PLL. The PLLs
produce selected clock frequencies to run particular functional blocks.
The 32.768-kHz crystal provides an optional clock source that must be selected after a hard reset.
This clock drives the Real Time Clock, Power Management Controller, and Interrupt Controller.
The 32.768-kHz crystal is on a separate power island to provide an active clock while the
application processor is in Sleep Mode.
1-2 PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Introduction
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7
1.2.8
Power Management controls the transition between the Turbo/Run, Idle, and Sleep operating
modes.
Universal Serial Bus (USB) Client
The USB Client Module is based on the Universal Serial Bus Specification, Revision 1.1. It
supports up to sixteen endpoints and it provides an internally generated 48-MHz clock. The USB
Device Controller provides FIFOs with DMA access to or from memory.
DMA Controller (DMAC)
The DMAC provides sixteen prioritized channels to service transfer requests from internal
peripherals and up to two data transfer requests from external companion chips. The DMAC is
descriptor-based to allow command chaining and looping constructs.
The DMAC operates in Flow-Through Mode when performing peripheral-to-memory, memory-to-
peripheral, and memory-to-memory transfers. The DMAC is compatible with peripherals that use
word, half-word, or byte data sizes.
LCD Controller
The LCD Controller supports both passive (DSTN) and active (TFT) flat-panel displays with a
maximum supported resolution of 800x600x16-bit/pixel. An internal 256 entry palette expands 1,
2, 4, or 8-bit encoded pixels. Non-encoded 16-bit pixels bypass the palette.
Two dedicated DMA channels allow the LCD Controller to support single- and dual-panel
displays. Passive monochrome mode supports up to 256 gray-scale levels and passive color mode
supports up to 64K colors. Active color mode supports up to 64K colors.
AC97 Controller
The AC97 Controller supports AC97 Revision 2.0 CODECs. These CODECs can operate at
sample rates up to 48 KHz. The controller provides independent 16-bit channels for Stereo PCM
In, Stereo PCM Out, Modem In, Modem Out, and mono Microphone In. Each channel includes a
FIFO that supports DMA access to memory.
Inter-IC Sound (I2S) Controller
The I2S Controller provides a serial link to standard I2S CODECs for digital stereo sound. It
supports both the Normal-I2S and MSB-Justified I2S formats, and provides four signals for
connection to an I2S CODEC. I2S Controller signals are multiplexed with AC97 Controller pins.
The controller includes FIFOs that support DMA access to memory.
Multimedia Card (MMC) Controller
The MMC Controller provides a serial interface to standard memory cards. The controller supports
up to two cards in either MMC or SPI modes with serial data transfers up to 20 Mbps. The MMC
controller has FIFOs that support DMA access to and from memory.
PXA250 and PXA210 Application Processors Developer’s Manual
1-3


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Introduction
1.2.9
Fast Infrared (FIR) Communication Port
The FIR Communication Port is based on the 4-Mbps Infrared Data Association (IrDA)
Specification. It operates at half-duplex and has FIFOs with DMA access to memory. The FIR
Communication Port uses the STUART’s transmit and receive pins to directly connect to external
IrDA LED transceivers.
1.2.10
1.2.11
Synchronous Serial Protocol Controller (SSPC)
The SSP Port provides a full-duplex synchronous serial interface that operates at bit rates from
7.2 kHz to 1.84 MHz. It supports National Semiconductor’s Microwire*, Texas Instruments’
Synchronous Serial Protocol*, and Motorola’s Serial Peripheral Interface*. The SSPC has FIFOs
with DMA access to memory.
Inter-Integrated Circuit (I2C) Bus Interface Unit
The I2C Bus Interface Unit provides a general purpose 2-pin serial communication port.The
interface uses one pin for data and address and a second pin for clocking.
1.2.12
GPIO
Each GPIO pin can be individually programmed as an output or an input. Inputs can cause
interrupts on rising or falling edges. Primary GPIO pins are not shared with peripherals while
secondary GPIO pins have alternate functions which can be mapped to the peripherals.
1.2.13 UARTs
The application processor provides three Universal Asynchronous Receiver/Transmitters. Each
UART can be used as a slow infrared (SIR) transmitter/receiver based on the Infrared Data
Association Serial Infrared (SIR) Physical Layer Link Specification.
1.2.13.1
Full Function UART (FFUART)
The FFUART baud rate is programmable up to 230 Kbps. The FFUART provides a complete set of
modem control pins: nCTS, nRTS, nDSR, nDTR, nRI, and nDCD. It has FIFOs with DMA access
to or from memory.
Note: See Table 2-11, “Signals Not Supported for the PXA210 Application Processor” for a list of the
signals that are not supported for the PXA210.
1.2.13.2
Bluetooth UART (BTUART)
The BTUART baud rate is programmable up to 921 Kbps. The BTUART provides a partial set of
modem control pins: nCTS and nRTS. Other modem control pins can be implemented via GPIOs.
The BTUART has FIFOs with DMA access to or from memory.
1-4 PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Introduction
1.2.13.3
Standard UART (STUART)
The STUART baud rate is programmable up to 230 Kbps. The STUART does not provide any
modem control pins. The modem control pins can be implemented via GPIOs. The STUART has
FIFOs with DMA access to or from memory.
The STUART’s transmit and receive pins are multiplexed with the Fast Infrared Communication
Port.
1.2.14
Real-Time Clock (RTC)
The Real-Time Clock can be clocked from either crystal. A system with a 32.768-KHz crystal
consumes less power during Sleep versus a system using only the 3.6864-MHz crystal. This crystal
can be removed to save system cost. The RTC provides a constant frequency output with a
programmable alarm register. This alarm register can be used to wake up the application processor
from Sleep mode.
1.2.15
OS Timers
The OS Timers can be used to provide a 3.68-MHz reference counter with four match registers.
These registers can be configured to cause interrupts when equal to the reference counter. One
match register can be used to cause a watchdog reset.
1.2.16
Pulse-Width Modulator (PWM)
The PWM has two independent outputs that can be programmed to drive two GPIOs. The
frequency and duty cycle are independently programmable. For example, one GPIO can control
LCD contrast and the other LCD brightness.
1.2.17
Interrupt Control
The Interrupt Controller directs the application processor interrupts into the core’s IRQ and FIQ
inputs. The Mask Register enables or disables individual interrupt sources.
PXA250 and PXA210 Application Processors Developer’s Manual
1-5


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

Introduction
1-6 PXA250 and PXA210 Application Processors Developer’s Manual


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

System Architecture
2
2.1
Overview
The PXA250 and PXA210 application processors are an integrated system-on-a-chip
microprocessor for high performance, low power portable handheld and handset devices. It
incorporates the Intel® XScale™ microarchitecture with on-the-fly frequency scaling and
sophisticated power management to provide industry leading MIPs/mW performance. The
application processor is ARM Version 5TE instruction set compliant (excluding floating point
instructions) and follows the ARM programmer’s model.
The application processor memory interface supports a variety of memory types to allow design
flexibility. Support for the connection of two companion chips permits a glueless interface to
external devices. An integrated LCD display controller provides support for displays up to
800x600 pixels, and permits 1-, 2-, 4-, and 8-bit grayscale and 8- or 16-bit color pixels. A
256 entry/512 byte palette RAM provides flexibility in color mapping.
A set of serial devices and general system resources provide computational and connectivity
capability for a variety of applications. Refer to Figure 2-1, “Block Diagram” on page 2-2 for an
overview of the microprocessor system architecture.
PXA250 and PXA210 Application Processors Developer’s Manual
2-1


PXA250 (Intel)
Application Processors

No Preview Available !

Click to Download PDF File for PC

System Architecture
Figure 2-1. Block Diagram
2.2
2.3
RTC
OS Timer
PWM(2)
Int.
Controller
Clocks &
Power Man.
I2S
I2C
AC97
UART1
UART2
Slow IrDA
Fast IrDA
SSP
USB
Client
MMC
Color or
Grayscale
LCD
Controller
Memory
Controller
System Bus
Megacell
Core
3.6864
MHz
Osc
32.768
KHz
Osc
Variable
Latency I/O
Control
PCMCIA
& CF
Control
Dynamic
Memory
Control
Static
Memory
Control
ASIC
XCVR
Socket 0
Socket 1
SDRAM/
SMROM
4 banks
ROM/
Flash/
SRAM
4 banks
A8651-01
Package Types
The PXA250 application processor is available in a 17x17 mm PBGA package and the PXA210
application processor is available in a 13x13 mm T-PBGA package that only supports a 16-bit data
bus. The software used to access the application processor can detect the processor that is being
used. For a list of pins that are not available in the PXA210 application processor, refer to
Table 2-11 on page 2-26.
Intel® XScaleMicroarchitecture Implementation
Options
The application processor incorporates the Intel® XScale™ microarchitecture which is described
in a separate document. This core contains implementation options which an Application Specific
Standard Product (ASSP) may elect to implement or omit. This section describes these options.
2-2 PXA250 and PXA210 Application Processors Developer’s Manual




PXA250.pdf
Click to Download PDF File