M02050-15 (MA-COM)
3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Applications
• 2.5 Gbps STM-16/OC-48 SDH/SONET
• 1.06, 2.12 and 4.24 Gbps Fibre Channel
• 1.25 Gbps Ethernet
• 2.67 Gbps SDH/SONET with FEC
Features
• Operates with a 3.3 or 5V supply
• 4 mV typical input sensitivity at 2.5 Gbps
• PECL outputs
• Rate Selection for 1.25 Gbps operation
• Average Receive power monitor output (RSSIAVG)
• Peak-to-peak Receive power monitor output (RSSIPP)
• On-chip DC offset cancellation circuit
• Low power (< 180 mW at 3.3V)
• Programmable CML Output Amplitude Level
• Output Jam Function
• 16 pin 3x3 QFN package
The M02050-15 is an integrated high-gain limiting amplifier. The M02050-15 features PECL outputs and is intended
for use in applications to 2.5 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02050-15
can operate with a 3.3V or 5V supply.
Rate select is supported for SFP applications and/or to achieve optimum sensitivity at data rates 1.25 Gbps.
When rate select is high, optimum sensitivity is achieved at 2.5 Gbps.
The M02050-15 also includes two analog RSSI outputs proportional to either the average or peak to peak input sig-
nal and a programmable signal-level detector allowing the user to set thresholds at which the logic outputs are
enabled.
Other available solutions: M02049-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
M02040-15 3.3/5V Limiting Amplifier for Applications to 2.125 Gbps (PECL outputs)
M02043-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
1.25 Gbps and 4.25 Gbps SFP reference designs available on MACOM’s website.
Typical Applications Diagram
+3.3 V
Photodiode
RATESELControl RATE SEL
IREF
12.1 kΩ
AC-Coupled
to TIA
DINP
MT02I0A13
VTT
Biasing
Limiting
Amplifier
MON
DINN
Jam
optional
Output
Buffer
PECLP
PECLN
Clock Data
Recovery
Unit
Offset cancel
RxAVGIN
RSSIAVG
REXT
Level
Shift
Level
Detect
Threshold
Setting
Circuit
Comparator
Regulator
STSET
RST
VCC3 VCC
RSSIPP
AC or DC Coupled
(as described in
Applications Information)
LOS
1
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Ordering Information
Part Number
Package
M02050-15 *
M02050-15 in QFN16 package
M02050-15EVM
Evaluation board with M02050-15
* The letter “G” designator after the part number indicates that the device is RoHS-compliant.
Operating Temperature
–40 °C to 85 °C
–40 °C to 85 °C
Revision History
Revision
Level
V5P
D (V4P)
Preliminary
Preliminary
Date
May 2015
April 2005
Description
Updated logos and page layout. No content changes.
Separated the M02049 and M02050 data sheets. New document number for the M02049 is 02049-
15-DSH-002-D.
Update the following DC specifications: ICC, RINDIFF and VOH. Update the following ac specifications:
VIN(MIN), vn, VLOS, HYS, DJ, RJ, tr/tf, TLOS_ON, and TLOS_OFF. Update RST and RSSI values for this
revision of the part.
M02050 Typical Eye Diagram
M02050-15 Pin Configuration
16 13
10 mVPP differential input
2.5 Gbps
150 mV/div
80 ps/div
GND
VCC
PECLN
PECLP
1
4
Center Pad
Connect to GND
58
12 RxAvgIN
GND
DINN
9 DINP
2
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M02050-15 (MA-COM)
3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
1.0 Product Specification
1.1 Absolute Maximum Ratings
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged. Reli-
able operation at these extremes for any length of time is not implied.
NOTE:
The package bottom must be adequately grounded to ensure correct
thermal and electrical performance, and it is recommended that vias
are inserted through to a lower ground plane.
Table 1-1. Absolute Maximum Ratings
Symbol
Parameter
VCC
TSTG
PECLP, PECLN
I(PECLP), I(PECLN)
|DINP - DINN|
DINP, DINN
STSET
JAM
LOS
Rate_Sel
IREF
I(RSSIAVG)
RSSIPP
I(LOS)
Power supply voltage (VCC-GND)
Storage temperature
PECL Output pins voltage
PECL Output pins maximum continuous current (delivered to load)
Data input pins differential voltage
Data input pins voltage meeting |DINP - DINN| requirement
Signal detect threshold setting pin voltage
Output enable pin voltage
Status Output pins voltage
Rate Select input pin voltage
Current into Reference input
Current into RSSIavg input
RSSIPP pin voltage
Current into Loss of Signal pin
Rating
-0.5 to +5.75V
-65 to +150
VCC - 2 to VCC + 0.4
30
0.80
GND to VCC3 + 0.4
GND to VCC + 0.4
GND to VCC + 0.4
GND to VCC + 0.4
GND to VCC + 0.4
+0 to -120
+0 to -3
GND to +3.6
+1500 to -100
Units
V
°C
V
mA
V
V
V
V
V
V
µA
mA
V
µA
3
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
1.2 Recommended Operating Conditions
Table 1-2. Recommended Operating Conditions
Parameter
Power supply: (VCC-GND) (apply no potential to VCC3) or
(VCC3-GND) (connect VCC to same potential as VCC3)
Junction temperature
Operating ambient
Rating
+5V ± 7.5% or +3.3V
± 7.5%
-40 to +110
-40 to +85
Units
V
°C
°C
1.3 DC Characteristics
VCC = +3.3V ± 7.5% or +5V ± 7.5%, TA = -40°C to +85°C, unless otherwise noted.
Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-3. DC Characteristics
Symbol
Parameter
Conditions
Min
ICC Supply Current
Includes PECL load
VOUTLpecl PECL Output Low Voltage Single ended; 50 Ω load to VCC-2V
(PECLP, PECLN)
VCC-1.81
VOUTHpecl PECL Output High Voltage Single ended; 50Ω load to VCC-2V
(PECLP, PECLN)
VCC-1.025
RINDIFF Differential Input Resistance
Measured between DINP and DINN
90
VOH LOS Output High Voltage
External 4.7-10 kΩ pull up to VCC
2.75
VOL LOS Output Low Voltage
External 4.7-10 kΩ pull up to VCC
0
VIH Logic Input High Voltage
JAM, RATESEL
2.7
VIL Logic Input Low Voltage
JAM, RATESEL
Notes:
1. RATESEL high (high bandwidth operation). Typical supply current decreases by 1.5 mA in low rate mode.
Typ
54 (1)
VCC-1.71
VCC-0.952
115
VCC
Max
TBD
VCC-1.62
VCC-0.88
135
0.4
VCC
0.8
Units
mA
V
V
Ω
V
V
V
V
4
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
1.4 AC Characteristics
VCC = +3.3V ± 7.5% or +5V ± 7.5%, TA = -40°C to +85°C, input bit rate = 2.5 Gbps 223-1 PRBS high rate
mode (RATESEL = High) unless otherwise noted.
Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-4. AC Characteristics
Symbol
Parameter
Conditions
VIN(MIN)) Differential Input Sensitivity
VI(MAX) Input Overload
1.25 Gbps, BER < 10-12, low rate mode
(RATESEL = low)
2.5 Gbps, BER < 10-12
BER < 10-12, differential input 2.5 Gbps
BER < 10-12, single-ended input, 2.5 Gbps
vn RMS Input Referred Noise
RATESEL = high
VLOS Loss of Signal Programmable Range Differential inputs
HYS Signal Detect Hysteresis
electrical; across LOS programmable range
RSSIpp
Peak-to-peak received signal strength Differential input signal range
indicator range
RSSIavg
BWLF
Average received signal strength ± 15% accuracy
indicator range
± 20% accuracy
Small-Signal –3dB Low Frequency Excluding AC coupling capacitors
Cutoff
DJ Deterministic Jitter (includes DCD) K28.5 pattern at 2.5 Gbps, 10 mVPP input
RJ Random Jitter
10 mVPP input
tr / tf Data Output Rise and Fall Times
20% to 80%; outputs terminated into 50 Ω;
10 mVPP input
RATESEL = High
RATESEL = Low
TRATESEL Rate select assert / deassert time
Time from when rate select is asserted high or low until
amplifier is performing at selected bandwidth
TLOS_ON
Time from LOS state until LOS output LOS assert time after 1 VPP input signal is turned off;
is asserted
signal detect level set to 10 mV
TLOS_OFF
Time from non-LOS state until LOS is LOS deassert time after input crosses signal detect
deasserted
level; signal detect set to 10 mV with applied input
signal of 20 mVPP
Min
1200
600
5
2
4
5
0.5
2.3
2.3
Typ Max Units
2 – mV
4 7 mV
– – mV
– – mV
280 – μVRMS
– 75 mV
3.5 5.5
dB
– 100 mV
– 500 μA
– 2 mA
25 – kHz
– 25 ps
4.7 – psRMS
ps
90 110
150 200
– 10
μs
– 80 μs
– 80 μs
5
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Figure 1-1. Data Input Requirements
Differential Input
DINP
DINN
Single-ended Input
DINP or DINN
Unused Input
Note:
2 - 600 mV For single-ended input connections.
When connecting to the used input with AC-
coupling, the unused input should be AC-
coupled through 50 Ω to the supply voltage of
the TIA;
4 - 1200 mV When connecting to the used input with DC-
coupling, the unused input should be DC-
coupled through 50 Ω to a voltage equal to
the common mode level of the used input.
4 - 600 mV
6
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
1.5 Typical Eye Diagrams
Figure 1-2. M02050 1.25 Gbps in Low Rate Mode Figure 1-3. M02050 2.5 Gbps High Rate Mode
10 mVPP differential input
1.25 Gbps
160 mV/div
140 ps/div
10 mVPP differential input
2.5 Gbps
150 mV/div
80 ps/div
7
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
2.0 Pin Definitions
Preliminary - Rev V5P
Table 2-1.
QFN Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Pin Descriptions
Name
Function
GND Ground.
VCC
PECLN
Power supply. Connect to either +5V or +3.3V.
Inverting PECL data output.
PECLP
Non-inverting PECL data output.
IREF
STSET
VCC3
RATESEL
Internal reference current. Must be connected to ground through a 12.1 kΩ 1% resistor.
Loss of signal threshold setting input. Connect a 1% resistor between this pin and VCC3 to set loss of signal threshold.
Power supply input for 3.3V applications or the output of the internally regulated 3.3V voltage when VCC = 5V. Connect
directly to supply for 3.3V applications (internal regulator not in use). Do not connect to power supply if VCC = 5V.
Rate select. When low or floating, the device is in low-rate mode (data rates 1.25 Gbps) and has reduced bandwidth.
When high, the device is in full-rate mode with full bandwidth. Internal 80 kΩ resistor to ground. Drive with a current
limited source as described in Section 4.1.4.
DINP
DINN
GND
Non-inverting data input. Internally terminated with 50 Ω to VTT.
Inverting data input. Internally terminated with 50 Ω to VTT.
Ground.
RxAVGIN
Average power monitor input. Connect to monitor output of TIAs that produce a current (sink) mirror replica of the
photodiode current. Leave floating if not used.
JAM Output disable. When high, data outputs are disabled (with non-inverting output held high and inverting output held
low). Connect to LOS output to disable outputs with loss of signal. Outputs are enabled when JAM is low or floating.
Internal 150 kΩ resistor to ground.
LOS
RSSIAVG
Loss of signal output. Goes high when input signal falls below threshold set by STSET. Open collector TTL with internal
80 kΩ pull-up resistor to VCC.
Receiver average input power monitor. Provides a current source mirror of the current at RxAVGIN. Connect a resistor
to ground to set the full scale voltage to the desired level at maximum average input power.
RSSIPP
Receiver peak-to-peak input voltage monitor. Provides a DC voltage (ground referenced) proportional to the peak-to-
peak input voltage swing.
Center Pad Ground. Must be connected to ground for proper operation.
8
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Figure 2-1. M02050-15 Pinout - 16 Pin (3 x 3 mm) QFN Top View
Preliminary - Rev V5P
GND
VCC
PECLN
PECLP
1
4
16 13
Center Pad
Connect to GND
58
12 RxAvgIN
GND
DINN
9 DINP
9
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
3.0 Functional Description
3.1 Overview
The M02050-15 is an integrated high-gain limiting amplifier. The M2050 features PECL outputs and is intended for
use in applications to 2.5 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02050-15
can operate with a 3.3V or 5V supply.
Rate select is supported for SFP applications and/or to achieve optimum sensitivity at data rates 1.25 Gbps.
When rate select is high, optimum sensitivity is achieved at 2.5 Gbps.
The M02050-15 also includes two analog RSSI outputs proportional to either the average or peak to peak input sig-
nal and a programmable signal-level detector allowing the user to set thresholds at which the logic outputs are
enabled.
Figure 3-1. Block Diagram Example
RATESEL
IREF
VTT Biasing
DINP
DINN
Limiting
Amplifier
Jam
Output
Buffer
RxAVGIN
RSSIAVG
Level
Shift
Offset cancel
Level
Detect
Comparator
Threshold
Setting
Circuit
Regulator
STSET
VCC3 VCC
PECLP
PECLN
RSSIPP
LOS
10
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
3.2 Features
• Operates with a 3.3 or 5V supply
• 4 mV typical input sensitivity at 2.5 Gbps
• PECL outputs
• Rate Selection for 1.25 Gbps operation
• Average Receive power monitor output (RSSIAVG)
• Peak-to-peak Receive power monitor output (RSSIPP)
• On-chip DC offset cancellation circuit
• Low power (< 180 mW at 3.3V)
• Programmable CML Output Amplitude Level
• Output Jam Function
• 16 pin 3x3 QFN package
3.3 General Description
The M02050-15 is a high-gain limiting amplifier for applications up to 2.5 Gbps, and incorporates a limiting ampli-
fier, an input signal level detection circuit and also a fully integrated DC-offset cancellation loop that does not
require any external components. The M02050-15 features PECL data outputs.
The M02050-15 provides the user with the flexibility to set the signal detect threshold. Optional output buffer dis-
able (squelch/jam) can be implemented using the JAM input.
3.3.1
Inputs
The data inputs are internally connected to VTT via 50 Ω resistors, and generally need to be AC coupled. Referring
to Figure 3-2, the nominal VTT voltage is 2.85V because of the internal resistor divider to VCC3, which means this is
the DC potential on the data inputs. See the applications information section for further details on choosing the AC-
coupling capacitor.
11
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3.3/5V Limiting Amplifier

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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Figure 3-2. CML Data Inputs
VTT
DINP
VCC3
50 Ω
50 Ω
Preliminary - Rev V5P
1.3 kΩ
8.3 kΩ
DINN
3.3.2
DC Offset Compensation
The M02050-15 contains an internal DC autozero circuit that can remove the effect of DC offsets without using
external components. This circuit is configured such that the feedback is effective only at frequencies well below
the lowest frequency of interest. The low frequency cut off is typically 25 kHz.
12
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
3.3.3
PECL Outputs
The M02050-15 features 100k/300k PECL compliant outputs as shown in Figure 3-3. The outputs may be termi-
nated using any standard AC or DC-coupling PECL termination technique. AC-coupling is used in applications
where the average DC content of the data is zero e.g. SONET. The advantage of this approach is lower power con-
sumption, no susceptibility to DC drive and compatibility with non-PECL interfaces.
Figure 3-3. PECL Data Outputs
VCC
DOUTP
DOUTN
50 Ω 50 Ω
VCC - 2V
3.3.4
Loss of Signal (LOS)
The M02050-15 features input signal level detection over an extended range. Using an external resistor, RST,
between pin STSET and VCC3 (Figure 3-5) the user can program the input signal threshold. The signal detect status
is indicated on the LOS output pin shown in Figure 3-4. The LOS signal is active when the signal is below the
threshold value. The signal detection circuitry has the equivalent of 3.5 dB (typical) electrical hysteresis.
13
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Figure 3-4. LOS Output
VCC
80 kΩ
LOS
Preliminary - Rev V5P
RST establishes a threshold voltage at the STSET pin as shown in Figure 3-5. Internally, the input signal level is
monitored by the Level Detector (which also outputs the RSSIPP voltage). As described in the RSSIPP section, this
voltage is proportional to the input signal peak to peak value. The voltage at STSET is internally compared to the
signal level from the Level Detector. When the Level Detect voltage is less than V(STSET), LOS is asserted and will
stay asserted until the input signal level increases by a predefined amount of hysteresis. When the input level
increases by more than this hysteresis above V(STSET), LOS is deasserted. See the applications information sec-
tion for the selection of RST.
Note that STSET can be left open if the loss of signal detector function is not required. In this case LOS would be
low.
Figure 3-5. STset Input
VCC3
VCC
RST
STSET
VSTSET
14
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
3.3.5
Peak to Peak Received Signal Strength Indicator (RSSIPP)
The RSSIPP output voltage is logarithmically proportional to the peak to peak level of the input signal. It is not nec-
essary to connect an external capacitor to this output. Internally, the RSSI voltage is compared with a user select-
able reference to determine loss of signal as described in the previous section.
Figure 3-6. RSSIPP Output
VCC
RSSIPP
4
I(RSSIPP)
15
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Figure 3-7. Typical RSSIPP Transfer Function
275
250
225
200
175
150
125
100
75
50
25
0
0
25 50 75 100 125 150 175 200
Differential Input Level (mVPP)
16
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Figure 3-8. Typical RSSIPP Transfer Function (Low Input Level)
225
200
175
150
125
100
75
50
25
0
0
5 10 15 20 25 30 35 40 45 50
Differential Input Level (mVPP)
17
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Figure 3-9. Typical RSSIPP Transfer Function (Log Scale)
275
250
225
200
175
150
125
100
75
50
25
0
1
10
Differential Input Level (mVPP)
100
3.3.6
JAM Function
When asserted, the active high power down (JAM) pin forces the outputs to a logic “one” state. This ensures that
no data is propagated through the system. The loss of signal detection circuit can be used to automatically force
the data outputs to a high state when the input signal falls below the threshold. The function is normally used to
allow data to propagate only when the signal is above the user's bit-error-rate requirement. It therefore inhibits the
data outputs toggling due to noise when there is no signal present (“squelch”).
In order to implement this function, LOS should be connected to the JAM pin shown in Figure 3-10, thus forcing the
data outputs to a logic “one” state when the signal falls below the threshold.
18
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Figure 3-10. JAM and RATESEL Input
VCC
Preliminary - Rev V5P
JAM or
RATESEL
R1
R2
RR12
=
=
55 k
100
Ω for JAM, 30 kΩ
kΩ for JAM, 50 k
ΩforfoRrARTAETSEESLEL
3.3.7
Average Received Signal Strength Indicator (RSSIAVG)
The RSSIAVG output current is a mirrored version of the RxAVGIN current from compatible TIAs. It sources rather
than sinks the current making it compatible with DDMI type interfaces.
Figure 3-11. RSSIAVG Output
VCC
RxAVGIN
RSSIAVG
(From TIA)
REXT
19
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
3.3.8
Voltage Regulation
The M02050-15 contains an on-chip voltage regulator to allow both 5V and 3.3V operation. When used at 5V, the
on-chip regulator is enabled and the digital inputs and outputs are compatible with TTL 5V logic levels.
20
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
4.0 Applications Information
4.1 Applications
• 2.5 Gbps STM-16/OC-48 SDH/SONET
• 1.06, 2.12 and 4.24 Gbps Fibre Channel
• 1.25 Gbps Ethernet
• 2.67 Gbps SDH/SONET with FEC
Figure 4-1. Typical Applications Diagram
Preliminary - Rev V5P
+3.3 V
Photodiode
RATESELControl RATE SEL
IREF
12.1 kΩ
AC-Coupled
to TIA
DINP
MT02I0A13
VTT
Biasing
Limiting
Amplifier
MON
DINN
Jam
Output
Buffer
RxAVGIN
RSSIAVG
REXT
Level
Shift
Offset cancel
Level
Detect
Comparator
Threshold
Setting
Circuit
Regulator
STSET
RST
VCC3 VCC
optional
PECLP
PECLN
RSSIPP
LOS
Clock Data
Recovery
Unit
AC or DC Coupled
(as described in
Applications Information)
21
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3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
4.1.1
Reference Current Generation
The M02050-15 contains an accurate on-chip bias circuit that requires an external 12.1 kΩ 1% resistor, RREF, from
pin IREF to ground to define an on-chip reference current.
Figure 4-2. Reference Current Generation
VCC
+
-
IREF
RREF
12.1 kΩ
4.1.2
Connecting VCC and VCC3
For 5V operation, the VCC pin is connected to an appropriate 5V ± 7.5% supply. No potential should be applied to
the VCC3 pin. The only connection to VCC3 should be RST as shown in Figure 3-5.
When VCC = 5V all logic outputs and the data outputs are 5V compatible while the CML data inputs are still refer-
enced to 3.3V from the internal regulator (see Figure 3-2). For low power operation, VCC and VCC3 should be con-
nected to an appropriate 3.3V ± 7.5% supply. In this case all I/Os are 3.3V compatible.
4.1.3
Choosing an Input AC-Coupling Capacitor
When AC-coupling the input the coupling capacitor should be of sufficient value to pass the lowest frequencies of
interest, bearing in mind the number of consecutive identical bits, and the input resistance of the part. For SONET
data, a good rule of thumb is to chose a coupling capacitor that has a cut-off frequency less than 1/(10,000) of the
input data rate. For example, for 2.5 Gbps data, the coupling capacitor should be chosen as:
fCUTOFF (2.5x109 / 10x103) = 250x103
The -3 dB cutoff frequency of the low pass filter at the 50 Ω input is found as:
f3dB = 1/ (2 * π * 50 Ω * CAC)
so solving for C where f3dB = fCUTOFF
CAC = 1/ (2 * π * 50 Ω * fCUTOFF)
EQ.1
22 and in this case the minimum capacitor is 12 nF.
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
For Ethernet or Fibre Channel, there are less consecutive bits in the data, and the recommended cut-off frequency
is 1/(1,000) of the input data rate. This results in a minimum capacitor of 1.5 nF for 2.125 Gbps Fibre Channel.
Multirate applications down to 155 Mbps
In this case, the input coupling capacitor needs to be large enough to pass 15 kHz (155x106/10,000) which results
in a capacitor value of 0.2 μF. However, because this low pass frequency is close to the 25 kHz low pass frequency
of the internal DC servo loop, it is preferable to use a larger input coupling capacitor such as 1 μF which provides
an input cutoff frequency of 3.1 kHz. This separates the two poles sufficiently to allow them to be considered inde-
pendent. This capacitor should also have a 10 nF capacitor in parallel to pass the higher frequency data (in the
multirate application) without distortion.
In all cases, a high quality coupling capacitor should be used as to pass the high frequency content of the input
data stream.
4.1.4
Using Rate Selection
Because of the performance of PECL outputs, the M02050-15 should not be used at data rates above 2.5 Gbps.
When the RATESEL pin (shown in Figure 3-10) is driven high, the M02050-15 bandwidth is set to its maximum
which allows the M02050-15 to operate at data rates up to 2.5 Gbps. Because of the nature of the ESD structure
on this pin, if it is driven by a device with IOL or IOH > 2 mA then a 1 kΩ to 10 kΩ resistor should be used in series
with the RATESEL pin. If rate selection is not used and the part is configured for high bandwidth only, the RATESEL
pin should be connected to VCC using a 1 kΩ to 10 kΩ resistor. When operating at data rates 1.25 Gbps, then
RATESEL should be left floating (do not tie low). This enables low-rate mode which reduces the bandwidth (and
thus the noise level) of the part.
4.1.5
Using RSSIAVG
As shown in the typical applications circuit (Figure 4-1), when interfacing to a TIA that features a “MON” output
such as the M02013 or M02016, the M02050-15 can reference the current sunk into the TIA “MON” output and pro-
duce a proportional current at the M02050-15 RSSIAVG output. The current is sourced into resistor REXT to ground
creating a voltage suitable for DDMI applications. REXT should be chosen as:
REXT = 1/(maximum current into RSSIAVG)
EQ.2
This keeps the voltage at RSSIAVG between 0 and 1 V.
4.1.6
Setting the Signal Detect Level
Using Figure 4-3, the value for RST is chosen to set the LOS threshold at the desired value. The resulting hystere-
sis is also shown in Figure 4-3.
From Figure 4-3, it is apparent that small variations in RST cause significant variation in the LOS threshold level,
particularly for low input signal levels. This is because of the logarithmic relationship between the RSSI voltage and
the input signal level. It is recommended that a 1% resistor be used for RST and that allowance is provided for LOS
variation, particularly when the LOS threshold is near the sensitivity limit of the M02050-15.
23
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3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Example RST resistor values are given in Table 4-1.
Table 4-1. LOS Assert Levels for Various RST Resistor Values
VIN (mV pp) differential
RST (kΩ)
5.0 7.50
10.3 6.98
19.4 6.49
32.6 6.04
45.8 5.76
Figure 4-3. Loss of Signal Characteristic (Extended Range)
100
Conditions:
90
2.5 Gbps, 231 - 1
80
Vcc = 3.3V, Temp = 25C
70
60
De-assert
50
Optical Hysteresis
40
30 = 10*log10(De-assert/Assert)
20
10 Assert
0
5.5 5.7 5.9 6.1 6.3 6.5 6.7 6.9 7.1 7.3 7.5 7.7 7.9
RST (kΩ)
24
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Figure 4-4. Loss of Signal Characteristic (Low Input Signal)
30
Conditions:
25 2.5 Gbps, 231 - 1
De-assert
20
Vcc = 3.3V, Temp = 25C
Optical Hysteresis
15 = 10*log10(De-assert/Assert)
10
Assert
5
0
6.5 6.7 6.9 7.1 7.3 7.5 7.7 7.9
RST (kΩ)
25
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Figure 4-5. Loss of Signal Characteristic (High Input Level)
100
90
80
70
60
50
40
30
20
5.5
Conditions:
2.5 Gbps, 231 - 1
Vcc = 3.3V, Temp = 25C
De-assert Optical Hysteresis
= 10*log10(De-assert/Assert)
Assert
5.7 5.9 6.1 6.3 6.5
RST (kΩ)
4.1.7
PECLP and PECLN Termination
The outputs of the M02050-15 are PECL compatible and any standard AC or DC-coupling termination technique
can be used. Figure 4-6 and Figure 4-7 illustrate typical AC and DC terminations.
AC-coupling is used in applications where the average DC content of the data is zero e.g. SONET. The advantage
of this approach is lower power consumption, no susceptibility to DC drift and compatibility with non-PECL inter-
faces. Figure 4-6 shows the circuit configuration and Table 4-2 lists the resistor values. If using transmission lines
other than 50 Ω, the shunt terminating resistance ZT should equal twice the impedance of the transmission line
(ZO).
DC-coupling can be used when driving PECL interfaces and has the advantage of a reduced component count. A
Thevenin termination is used at the receive end to give a 50 Ω load and the correct DC bias. Figure 4-7 shows the
circuit configuration and Table 4-2 the resistor values.
Alternatively, if available, terminating to VCC - 2V as shown in Figure 4-8 has the advantage that the resistance
value is the same for 3.3 V and 5 V operation and it also has performance advantages at high data rates.
26
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Table 4-2.
Supply
5V
3.3V
PECL Termination Resistor Values
Output
Impedance
RPULL-DOWN
50 Ω
270 Ω
50 Ω
150 Ω
ZT
100 Ω
100 Ω
RTA / RTB
2.7 kΩ / 7.8 kΩ
2.7 kΩ / 4.3 kΩ
Figure 4-6. AC-Coupled PECL Termination
VCC
PECLP
0.1µF
Zo
M02050
PECLN
0.1µF
Zo
RPULL-DOWN
VCC
RTA RTA
ZT PECL
RTB RTB
RT / RB
82 Ω / 130 Ω
130 Ω / 82 Ω
Figure 4-7. DC-Coupled PECL Termination
VCC
PECLP Zo
M02050
PECLN Zo
VCC
RT RT
10 nF
PECL
RB RB
27
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3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
Figure 4-8. Alternative PECL Termination
VCC
PECLP Zo
M02050
PECLN Zo
VCC
PECL
50 Ω 50 Ω
VCC - 2V
10 nF
28
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
5.0 Package Specification
Figure 5-1. Package Information
Preliminary - Rev V5P
Note: View is for a 12 pin package. All dimensions in the
tables apply for the 16 pin package
16
4
4
1.35 1.50 1.65
1.35 1.50 1.65
29
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M02050-15
3.3/5V Limiting Amplifier for Aplications to 2.5 Gbps
Preliminary - Rev V5P
M/A-COM Technology Solutions Inc. All rights reserved.
Information in this document is provided in connection with M/A-COM Technology Solutions Inc ("MACOM")
products. These materials are provided by MACOM as a service to its customers and may be used for
informational purposes only. Except as provided in MACOM's Terms and Conditions of Sale for such products or
in any separate agreement related to this document, MACOM assumes no liability whatsoever. MACOM assumes
no responsibility for errors or omissions in these materials. MACOM may make changes to specifications and
product descriptions at any time, without notice. MACOM makes no commitment to update the information and
shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its
specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document.
THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR
IMPLIED, RELATING TO SALE AND/OR USE OF MACOM PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL
DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
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MATERIALS. MACOM SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS,
WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
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MACOM for any damages resulting from such improper use or sale.
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