H0700KC17Y (IXYS)
Fast Symmetrical Gate Turn-Off Thyristor

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Date:- 28 September, 2012
Data Sheet Issue:- 2
Fast Symmetrical Gate Turn-Off Thyristor
Type H0700KC14# to H0700KC17#
Absolute Maximum Ratings
VDRM
VRSM
VRRM
VRSM
VOLTAGE RATINGS
Repetitive peak off-state voltage, (note 1)
Non-repetitive peak off-state voltage, (note 1)
Repetitive peak reverse voltage
Non-repetitive peak reverse voltage
MAXIMUM
LIMITS
1400-1700
1500-1800
100-1360
100-1360
UNITS
V
V
V
V
ITGQ
Ls
IT(AVM)
IT(RMS)
ITSM
ITSM2
I2t
di/dtcr
PFGM
PRGM
IFGM
VRGM
toff
ton
Tj
Tstg
RATINGS
Peak turn-off current, (note 2)
Snubber loop inductance, ITM=ITGQ, (note 2)
Mean on-state current, Tsink=55°C (note 3)
Nominal RMS on-state current, 25°C (note 3)
Peak non-repetitive surge current tp=10ms
Peak non-repetitive surge current, (Note 4)
I2t capacity for fusing tp=10ms
Critical rate of rise of on-state current, (note 5)
Peak forward gate power
Peak reverse gate power
Peak forward gate current
Peak reverse gate voltage (note 6).
Minimum permissible off-time, ITM=ITGQ, (note 2)
Minimum permissible on-time
Operating temperature range
Storage temperature range
Notes:-
1) VGK=-2Volts.
2) Tj=125°C, VD=80%VDM, VDM<VDRM, diGQ/dt=40A/µs, CS=1.5µF.
3) Double-side cooled, single phase; 50Hz, 180° half-sinewave.
4) Half-sinewave, tp=2ms
5) For di/dt>1000A/µs, consult factory.
6) May exceed this value during turn-off avalanche period.
MAXIMUM
LIMITS
700
0.3
360
700
4
7.2
80×103
1000
160
5
100
18
45
20
-40 to +125
-40 to +150
UNITS
A
µH
A
A
kA
kA
A2s
A/µs
W
kW
A
V
µs
µs
°C
°C
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 1 of 15
September, 2012


H0700KC17Y (IXYS)
Fast Symmetrical Gate Turn-Off Thyristor

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Characteristics
Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
Parameter
VTM Maximum peak on-state voltage
IL Latching current
IH Holding current.
dv/dtcr Critical rate of rise of off-state voltage
IDM Peak off state current
IRM Peak reverse current
IGKM Peak negative gate leakage current
VGT Gate trigger voltage
IGT Gate trigger current
td Delay time
tgt Turn-on time
tf Fall time
tgq Turn-off time
Igq Turn-off gate current
Qgq Turn-off gate charge
ttail Tail time
tgw Gate off-time (see note 3).
RthJK Thermal resistance junction to sink
F Mounting force
Wt Weight
MIN
-
-
-
800
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80
-
-
-
4.5
-
TYP MAX TEST CONDITIONS
2.4 2.75 IG=1.5A, IT=700A
5 - Tj=25°C
5 - Tj=25°C
- - VD=80%VDRM, VGR=-2V
- 30 Rated VDRM, VGR=-2V
- 40 Rated VRRM
- 200 VGR=-16V
0.9 - Tj=-40°C
0.8 - Tj=25°C
VD=25V, RL=25m
0.7 - Tj=125°C
2.5 6 Tj=-40°C
0.4 1.5 Tj=25°C
VD=25V, RL=25m
20 200 Tj=125°C
VD=50%VDRM, ITGQ=700A, IGM=30A, diG/dt=15A/µs
0.5 -
Tj=25°C, di/dt=300A/µs, (10%IGM to 90%VD)
3 5 Conditions as for td, (10%IGM to 10%VD)
VD=50%VDRM, ITGQ=700A, CS=1.5µF,
0.5 -
diGQ/dt=40A/µs, VGR=-16V, (90%ITGQ to 10%ITGQ)
5 6.5 Conditions as for tf, (10%IGQ to 10%ITGQ)
190 - Conditions as for tf
580 700 Conditions as for tf
25 35 Conditions as for tf, (10%ITGQ to ITGQ<1A)
- - Conditions as for tf
- 0.063 Double side cooled
- 0.21 Cathode side cooled
- 0.09 Anode side cooled
- 9.0 (see note 2)
120 -
UNITS
V
A
A
V/µs
mA
mA
mA
V
V
V
A
A
mA
µs
µs
µs
µs
A
µC
µs
µs
K/W
K/W
K/W
kN
g
Notes:-
1) Unless otherwise indicated Tj=125oC.
2) For other clamping forces, consult factory.
3) The gate off-time is the period during which the gate circuit is
required to remain low impedance to allow for the passage
of tail current.
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 2 of 15
September, 2012


H0700KC17Y (IXYS)
Fast Symmetrical Gate Turn-Off Thyristor

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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
Notes on ratings and characteristics.
1. Maximum Ratings.
1.1 Off-state voltage ratings.
Unless otherwise indicated, all off-state voltage ratings are given for gate conditions as diagram 1. For
other gate conditions see the curves of figure 5. It should be noted that VDRM is the repeatable peak
voltage which may be applied to the device and does not relate to a DC operating condition. While not
given in the ratings, VDC should ideally be limited to 60% VDRM in this product.
Diagram 1.
1.2 Reverse voltage rating.
All devices in this series have a minimum VRRM of 100 Volts. If specified at the time of order, a VRRM up to
80%VDRM is available.
1.3 Peak turn-off current.
The figure given in maximum ratings is the highest value for normal operation of the device under
conditions given in note 2 of ratings. For other combinations of ITGQ, VD and Cs see the curves of figures
15 & 16. The curves are effective over the normal operating range of the device and assume a snubber
circuit equivalent to that given in diagram 2. If a more complex snubber, such as an Underland circuit, is
employed then the equivalent CS should be used and Ls<0.3µH must be ensured for the curves to be
applied.
Ls
Ds R
Cs
Diagram 2.
1.4 R.M.S and average current.
Measured as for standard thyristor conditions, double side cooled, single phase, 50Hz, 180° half-
sinewave. These are included as a guide to compare the alternative types of GTO thyristors available,
values can not be applied to practical applications, as they do not include switching losses.
1.5 Surge rating and I2t.
Ratings are for half-sinewave, peak value against duration is given in the curve of figure 4.
1.6 Snubber loop inductance.
Use of GTO thyristors with snubber loop inductance, Ls<0.3µH implies no dangerous Vs voltages (see
diagrams 2 & 3) can be applied, provided the other conditions given in note 1.3 are enforced.
Alternatively Vs should be limited to 600 Volts to avoid possible device failure.
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 3 of 15
September, 2012


H0700KC17Y (IXYS)
Fast Symmetrical Gate Turn-Off Thyristor

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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
1.7 Critical rate of rise of on-state current
The value given is the maximum repetitive rating, but does not imply any specific operating condition. The
high turn-on losses associated with limit di/dt would not allow for practical duty cycle at this maximum
condition. For special pulse applications, such as crowbars and pulse power supplies, a much higher di/dt
is possible. Where the device is required to operate with infrequent high current pulses, with natural
commutation (i.e. not gate turn-off), then di/dt>5kA/µs is possible. For this type of operation individual
specific evaluation is required.
1.8 Gate ratings
The absolute conditions above which the gate may be damaged. It is permitted to allow VGK(AV) during
turn-off (see diagram 10) to exceed VRGM which is the implied DC condition.
1.9 Minimum permissible off time.
This time relates specifically to re-firing of device (see also note on gate-off time 2.7). The value given in
the ratings applies only to operating conditions of ratings note 2. For other operating conditions see the
curves of figure 18.
1.10 Minimum permissible on-time.
Figure is given for minimum time to allow complete conduction of all the GTO thyristor islands. Where a
simple snubber, of the form given in diagram 1. (or any other non-energy recovery type which discharges
through the GTO at turn-on) the actual minimum on-time will usually be fixed by the snubber circuit time
constant, which must be allowed to fully discharge before the GTO thyristor is turned off. If the anode
circuit has di/dt<10A/µs then the minimum on-time should be increased, the actual value will depend
upon the di/dt and operating conditions (each case needs to be assessed on an individual basis).
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 4 of 15
September, 2012


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Fast Symmetrical Gate Turn-Off Thyristor

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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
2 Characteristics
2.1 Instantaneous on-state voltage
Measured using a 500µs square pulse, see also the curves of figure 2 for other values of ITM.
2.2 Latching and holding current
These are considered to be approximately equal and only the latching current is measured, type test only
as outlined below. The test circuit and wave diagrams are given in diagram 4. The anode current is
monitored on an oscilloscope while VD is increased, until the current is seen to flow during the un-gated
period between the end of IG and the application of reverse gate voltage. Test frequency is 100Hz with
IGM & IG as for td of characteristic data.
IG
IGM
100µs
Gate current
100µs
16V
Anode current
R1
Unlatched
unlatched condition
CT
Gate-drive
DUT
C1 Vs
Latched
Anode current
Latched condition
Diagram 4, Latching test circuit and waveforms.
2.3 Critical dv/dt
The gate conditions are the same as for 1.1, this characteristic is for off-state only and does not relate to
dv/dt at turn-off. The measurement, type test only, is conducted using the exponential ramp method as
shown in diagram 5. It should be noted that GTO thyristors have a poor static dv/dt capability if the gate is
open circuit or RGK is high impedance. Typical values: - dv/dt<30V/µs for RGK>10.
Diagram 5, Definition of dV/dt.
2.4 Off-state leakage.
For IDRM & IRRM see notes 1.1 & 1.2 for gate leakage IGK, the off-state gate circuit is required to sink this
leakage and still maintain minimum of –2 Volts. See diagram 6.
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Diagram 6.
Page 5 of 15
September, 2012


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Fast Symmetrical Gate Turn-Off Thyristor

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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
2.5 Gate trigger characteristics.
These are measured by slowly ramping up the gate current and monitoring the transition of anode
current and voltage (see diagram 7). Maximum and typical data of gate trigger current, for the full junction
temperature range, is given in the curves of figure 6. Only typical figures are given for gate trigger
voltage, however, the curves of figure 1 give the range of gate forward characteristics, for the full
allowable junction temperature range. The curves of figures 1 & 6 should be used in conjunction, when
considering forward gate drive circuit requirement. The gate drive requirements should always be
calculated for lowest junction temperature start-up condition.
Feedback
R1
Current-
sence
CT
Gate-drive
DUT
0.9VAK
C1 Vs
0.1IA
Not to scale
Anode current
Gate current
IGT Anode-Cathode
Voltage
Diagram 7, Gate trigger circuit and waveforms.
2.6 Turn-on characteristics
The basic circuit used for turn-on tests is given in diagram 8. The test is initiated by establishing a
circulating current in Tx, resulting in VD appearing across Cc/Lc. When the test device is fired Cc/Lc
discharges through DUT and commutates Tx off, as pulse from Cc/Lc decays the constant current source
continues to supply a fixed current to DUT. Changing value of Cc & Lc allows adjustment of ITM and di/dt
respectively, VD and i are also adjustable.
Cc Lc
R1
i Tx D
CT
Gate-drive
DUT
Cd Vd
Diagram 8, Turn-on test circuit of FT40.
The definitions of turn-on parameters used in the characteristic data are given in diagram 9. The gate
circuit conditions IGM & IG are fully adjustable, IGM duration 10µs.
diG/dt
IG
IGM
td tr
di/dt
VD
tgt
VD=VDM
ITM
Eon integral
period
Diagram 9, Turn-on wave-diagrams.
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 6 of 15
September, 2012


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Fast Symmetrical Gate Turn-Off Thyristor

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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
In addition to the turn-on time figures given in the characteristics data, the curves of figure 9 give the
relationship of tgt to di/dt and IGM. The data in the curves of figures 7 & 8, gives the turn-on losses both
with and without snubber discharge, a snubber of the form given in diagram 2 is assumed. Only typical
losses are given due to the large number of variables which effect Eon. It is unlikely that all negative
aspects would appear in any one application, so typical figures can be considered as worst case. Where
the turn-on loss is higher than the figure given it will in most cases be compensated by reduced turn-off
losses, as variations in processing inversely effect many parameters. For a worst case device, which
would also have the lowest turn-off losses, Eon would be 1.5x values given in the curves of figures 7 & 8.
Turn-on losses are measured over the integral period specified below:-
10 µs
Eon = iv.dt
0
The turn-on loss can be sub-divided into two component parts, firstly that associated with tgt and secondly
the contribution of the voltage tail. For this series of devices tgt contributes 50% and the voltage tail 50%
(These figures are approximate and are influenced by several second order effects). The loss during tgt is
greatly affected by gate current and as with turn-on time (figure 9), it can be reduced by increasing IGM.
The turn-on loss associated with the voltage tail is not effected by the gate conditions and can only be
reduced by limiting di/dt, where appropriate a turn-on snubber should be used. In applications where the
snubber is discharged through the GTO thyristor at turn-on, selection of discharge resistor will effect Eon.
The curves of figure 8 are given for a snubber as shown in diagram 2, with R=5, this is the lowest
recommended value giving the highest Eon, higher values will reduce Eon.
2.7 Turn-off characteristics
The basic circuit used for the turn-off test is given in diagram 10. Prior to the negative gate pulse being
applied constant current, equivalent to ITGQ, is established in the DUT. The switch Sx is opened just before
DUT is gated off with a reverse gate pulse as specified in the characteristic/data curves. After the period
tgt voltage rises across the DUT, dv/dt being limited by the snubber circuit. Voltage will continue to rise
across DUT until Dc turns-on at a voltage set by the active clamp Cc, the voltage will be held at this value
until energy stored in Lx is depleted, after which it will fall to VDC .The value of Lx is selected to give
required VD Over the full tail time period. The overshoot voltage VDM is derived from Lc and forward
voltage characteristic of DC, typically VDM=1.2VD to 1.5VD depending on test settings. The gate is held
reverse biased through a low impedance circuit until the tail current is fully extinguished.
Lc
Dc
Sx RL
Lx Rs
CT Ds
Vd
i DX
Cs Cd
Gate- DUT
drive
Cc
Vc
RCD snubber
Diagram 10, Turn-off test circuit.
The definitions of turn-off parameters used in the characteristic data are given in diagram 11.
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 7 of 15
September, 2012


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Fast Symmetrical Gate Turn-Off Thyristor

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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
tgq
tf
0.9
VDM
ITGQ
0.1
IGQ
QGQ
VD
0.1
VG(AV)
VGQ
VGR
tgw
Diagram 11, Turn-off parameter definitions.
In addition to the turn-off figures given in characteristic data, the curves of figures 10, 11 & 12 give the
relationship of IGQ QGQ and tgq to turn-off current (ITGQ) and diGQ/dt. Only typical values of IGQ are given due
to a great dependence upon the gate circuit impedance, which is a function of gate drive design not the
device. The tgq is also, to a lesser extent, affected by circuit impedance and as such the maximum figures
given in data assume a good low impedance circuit design. The curves of figures 17 & 18 give the tail
time and minimum off time to re-fire device as a function of turn-off current. The minimum off time to re-
fire the device is distinct from tgw, the gate off time given in characteristics. The GTO thyristor may be
safely re-triggered when a small amount of tail current is still flowing. In contrast, the gate circuit must
remain low impedance until the tail current has fallen to zero or below a level which the higher impedance
VGR circuit can sink without being pulled down below –2 Volts. If the gate circuit is to be switched to a
higher impedance before the tail current has reached zero then the requirements of diagram 12 must be
applied.
i tail
R
(VGR - itail R)>2V
Diagram 12.
VGR
The figure tgw, as given in the characteristic data, is the maximum time required for the tail current to
decay to zero. The figure is applicable under all normal operating conditions for the device; provided
suitable gate drive is employed. At lower turn-off current, or with special gate drive considerations, this
time may be reduced (each case needs to be considered individually).Typical turn-off losses are given in
the curves of figures 13 & 14, the integration period for the losses is nominally taken to the end of the
tail time (Itail<1A) i.e. :-
tgt +ttail
Eoff = iv.dt.
0
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 8 of 15
September, 2012


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Fast Symmetrical Gate Turn-Off Thyristor

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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
The curves of figure 13 give the turn-off energy for a fixed VD with a VDM=120%VD, whereas the curves of
figure 14 give the turn-off energy with a fixed value of VDM and VD=50%VDRM. The curves are for energy
against turn-off current/snubber capacitance with a correction for voltage inset as an additional graph
(snubber equivalent to diagram 2 is assumed). From these curves a typical value of turn-off energy for
any combination of ITGQ/Cs and VD or VDM can be derived. Only typical data is included, to allow for the
trade-off with on-state voltage (VTM) which is a feature of these devices, see diagram 13. When
calculating losses in an application, the use of a maximum VTM and typical Eoff will (under normal
operating frequencies) give a more realistic value. The lowest VTM device of this type would have a
maximum turn-off energy of 1.5x the figure given in the curves of figures 13 & 14.
Trade-off between VTM & Eoff
E off
Diagram 13.
VTM
2.8 Safe turn-off periphery
The necessity to control dv/dt at tun-off for the GTO thyristor implies a trade-off between ITGQ/VDM/Cs. This
information is given in the curves of figures 15 & 16. The information in these curves should be
considered as maximum limits and not implied operating conditions, some margin of 'safety' is advised
with the conditions of the curves reserved for occasional excursions. It should be noted that these curves
are derived at maximum junction temperature, however, they may be applied across the full operating
temperature range of the device provided additional precautions are taken. At very low temperature,
(below –10°C) the fall-time of device becomes very rapid and can give rise to very high turn-off voltage
spikes, as such it is advisable to reduce snubber loop inductance to <0.2µH to minimise this effect.
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 9 of 15
September, 2012


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Fast Symmetrical Gate Turn-Off Thyristor

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Curves
Figure 1 – Forward gate characteristics
1000
H0700KC14#-17#
Issue 2
For Tj= -40oC to +125oC
Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
Figure 2 - On-state characteristics of Limit device
10000
H0700KC14#-17#
Issue 2
100
Minimum
Maximum
10
1000
100
Tj=125oC
Tj=25oC
1
0 0.5 1 1.5
Instantaneous forward gate voltage, VFG (V)
Figure 3 - Maximum surge and I2t Ratings
100000
H0700KC14#-17#
Issue 2
Tj (initial) = 125°C
2
10
0
1234
Instantaneous on-state voltage, VT (V)
5
I2t: VRRM 10V
I2t: 60% VRRM
1.00E+06
10000
1.00E+05
1000
1
3 5 10
Duration of surge (ms)
ITSM: 60% VRRM
ITSM: VRRM 10V
1
5 10
50 100
Duration of surge (cycles @ 50Hz)
1.00E+04
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 10 of 15
September, 2012


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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
Figure 4 – Transient thermal impedance
1
H0700KC14#-17#
Issue 2
Figure 5 – Typical forward blocking voltage Vs.
external gate-cathode resistance
1.2
H0700KC14#-17#
Issue 2
CATHODE
1
0.1
ANODE
0.8
DOUBLE-SIDE
0.6
Tj=25oC
Tj=100oC
0.01
0.001
0.001
0.01
0.1 1
TIME, (S)
Figure 6 – Gate trigger current
10
H0700KC14#-17#
Issue 2
0.4
0.2
RGK
Tj=125oC
10 100
0
1 10 100 1000
EXTERNAL GATE-CATHODE RESISTANCE, RGK (OHMS)
Figure 7 – Typical turn-on energy per pulse
(excluding snubber discharge)
30
H0700KC14#-17#
Issue 2
VD=0.5VDRM
IGM=30A, diG/dt=15A/µs
25 Tj=25oC
di/dt=500A/µs
1 20 di/dt=300A/µs
MAXIMUM
0.1
TYPICAL
0.01
-50
-25 0
25 50 75 100 125 150
JUNCTION TEMPERATURE, Tj(°C)
15
di/dt=100A/µs
10
5
0
0 300 600 900 1200
TURN-ON CURRENT, ITM (A)
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
Figure 8 – Typical turn-on energy per pulse
(including snubber discharge)
200
H0700KC14#-17#
Issue 2
VD=0.5VDRM
IGM=30A, diG/dt=15A/µs
Cs=1.5µF, Rs=5W
Tj=25oC
150
di/dt=500A/µs
di/dt=300A/µs
di/dt=100A/µs
100
Figure 9 – Maximum turn-on time
5
H0700KC14#-17#
Issue 2
VD=0.5VDRM, ITGQ=600A
tr of IGM 2µs
Tj=25oC
4
3
IGM=30A
IGM=40A
IGM=50A
2
50
1
0
0 300 600 900 1200
TURN-ON CURRENT, ITM(A)
Figure 10 – Typical peak turn-off gate current
250
H0700KC14#-17#
Issue 2
VD=0.8VDRM
Tj=125oC
diGQ/dt=50A/µs
diGQ/dt=40A/µs
200
diGQ/dt=30A/µs
0
10 100 1000
RATE OF RISE OF ON-STATE CURRENT, di/dt (A/ µs)
Figure 11 – Maximum gate turn-off charge
1.2
H0700KC14#-17#
Issue 2
VD=0.8VDRM
Tj=125oC
1
diGQ/dt=20A/µs
diGQ/dt=30A/µs
0.8 diGQ/dt=40A/µs
diGQ/dt=50A/µs
150 0.6
0.4
100
QGQ
0.2
50
0
200 400 600 800
TURN-OFF CURRENT, IT (A)
1000
0
0 200 400 600 800 1000
TURN-OFF CURRENT, ITGQ (A)
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
Figure 12 – Maximum turn-off time
12
H0700KC14#-17#
Issue 2
VD=0.8VDR
Tj=125o
diGQ/dt=20A/µs
8 diGQ/dt=30A/µs
Figure 13 – Turn-off energy per pulse
0.4
H0700KC14#-17#
Issue 2
VD=800V, VDM=1.2VD
diGQ/dt=40A/µs
Ls0.3µH
Tj=125oC
CS=3µF
CS=2µF
CS=1.5µF
CS=1µF
0.3 CS=0.5µF
VDM
VD
diGQ/dt=40A/µs
diGQ/dt=50A/µ
0.2
For other values
of VD scale Eoff.
Note:VDMVDRM
42
0.1 1
0
200 800 1400
VD
0
0 200 400 600 800 1000
TURN-OFF CURRENT, ITGQ (A)
Figure 14 – Typical turn-off energy per pulse
0.5
H0700KC14#-17#
Issue 2
VDM=1200V, VD=0.5VDRM
diGQ/dt=40A/µs
Ls0.3µH
0.4 Tj=125oC
Cs=1µF Cs=1.5µF Cs=2µF Cs=3µF
Cs=0.5µF
Note: VDMVDRM
0.3 VDM
VD
0
0 200 400 600 800 1000
TURN-OFF CURRENT, ITGQ (A)
Figure 15 – Maximum permissible turn-off current
3
H0700KC14#-17#
Issue 2
diGQ/dt=40A/µs
Ls0.3µH
2.5 Tj=125oC
VD=0.8VDRM
VD=0.65VDRM
VD0.5VDRM
VDM1.2VD
VD
2
1.5
0.2
For other values of VDM scale Eoff
1.5
1
0.1
1
0.5
600
1200
1800
VDM
0.5
0
0 200 400 600 800 1000
TURN-OFF CURRENT, ITGQ (A)
0
0 200 400 600 800 1000
TURN-OFF CURRENT, ITGQ (A)
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 13 of 15
September, 2012


H0700KC17Y (IXYS)
Fast Symmetrical Gate Turn-Off Thyristor

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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
Figure 16 – Maximum turn-off current
1000
Cs=3µF
VDM1.2VD
VD
Cs=2.2µF
800
Figure 17 – Maximum tail time
40
H0700KC14#-17#
Issue 2
VD=0.8VDRM
Tj=125oC
Cs=1.5µF
Cs=1µF
600
35
Cs=0.5µF
400
200
0
0
diGQ/dt=40A/µs
Ls0.3µH
Tj=125oC
H0700KC14#-17#
Issue 2
0.2 0.4 0.6 0.8
TURN-OFF VOLTAGE AS THE RATIO VD/VDRM
1
Figure 18 – Minimum off-time to re-fire device
60
H0700KC14#-17#
Issue 2
VD=0.8VDRM
Tj=125oC
50
30
25
0
200 400 600 800
TURN-OFF CURRENT, ITGQ (A)
1000
diGQ/dt=20A/µs
diGQ/dt=30A/µs
diGQ/dt=50A/µs
40
30
0
200 400 600
TURN-OFF CURRENT, ITGQ (A)
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 14 of 15
800 1000
September, 2012


H0700KC17Y (IXYS)
Fast Symmetrical Gate Turn-Off Thyristor

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Fast Symmetrical Gate Turn-Off Thyristor type H0700KC14# to H0700KC17#
Outline Drawing & Ordering Information
101A287
ORDERING INFORMATION
(Please quote 10 digit code as below)
H0700
KC
♦♦
#
Fixed
Type Code
Fixed
Outline Code
Fixed Voltage Code
VDRM/100
14-17
VRRM Code as % of VDRM
D=80, Y=100V VRRM
Typical order code: H0700KC17D – 1700V VDRM, VRRM=80%VDRM (1360V), 16.5mm clamp height capsule.
IXYS Semiconductor GmbH
Edisonstraße 15
D-68623 Lampertheim
Tel: +49 6206 503-0
Fax: +49 6206 503-627
E-mail: marcom@ixys.de
IXYS Corporation
1590 Buckeye Drive
Milpitas CA 95035-7418
Tel: +1 (408) 457 9000
Fax: +1 (408) 496 0670
E-mail: sales@ixys.net
www.ixysuk.com
www.ixys.com
IXYS UK Westcode Ltd
Langley Park Way, Langley Park,
Chippenham, Wiltshire, SN15 1GE.
Tel: +44 (0)1249 444524
Fax: +44 (0)1249 659448
E-mail: sales@ixysuk.com
IXYS Long Beach
IXYS Long Beach, Inc
2500 Mira Mar Ave, Long Beach
CA 90815
Tel: +1 (562) 296 6584
Fax: +1 (562) 296 6585
E-mail: service@ixyslongbeach.com
The information contained herein is confidential and is protected by Copyright. The information may not be used or disclosed
except with the written permission of and in the manner permitted by the proprietors IXYS UK Westcode Ltd.
In the interest of product improvement, IXYS UK Westcode reserves the right to change specifications at any time without prior
notice.
Devices with a suffix code (2-letter, 3-letter or letter/digit/letter combination) added to their generic code are not necessarily subject
to the conditions and limits contained in this report.
© IXYS UK Westcode Ltd.
Data Sheet. Type H0700KC14# to H0700KC17# Issue 2
Page 15 of 15
September, 2012




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