M0519LD3AE (nuvoton)
32-BIT MICROCONTROLLER

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M0519
ARM® Cortex® -M0
32-bit Microcontroller
NuMicro® Family
M0519 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Nov. 02, 2016
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M0519
Table of Contents
1 GENERAL DESCRIPTION .......................................................................6
2 FEATURES .........................................................................................7
3 ABBREVIATIONS ................................................................................ 10
4 PARTS INFORMATION LIST AND PIN CONFIGURATION .............................. 12
4.1 NuMicro® M0519 Selection Guide..................................................................12
4.2 Pin Configuration......................................................................................13
4.3 Pin Description ........................................................................................16
5 BLOCK DIAGRAM ............................................................................... 23
6 FUNCTIONAL DESCRIPTION................................................................. 24
6.1 ARM® Cortex® -M0 Core..............................................................................24
6.2 System Manager ......................................................................................26
6.3 Clock Controller .......................................................................................35
6.4 Flash Memory Controller (FMC) ....................................................................38
6.5 General Purpose I/O (GPIO) ........................................................................39
6.6 Timer Controller (TIMER)............................................................................40
6.7 Basic PWM Generator and Capture Timer (BPWM) ............................................41
6.8 Enhanced PWM Generator (EPWM) ..............................................................42
6.9 Enhanced Input Capture Timer (ECAP)...........................................................43
6.10 Watchdog Timer (WDT)..............................................................................44
6.11 Window Watchdog Timer (WWDT) ................................................................45
6.12 Universal Asynchronous Receiver Transmitter (UART) ........................................46
6.13 I2C Serial Interface Controller (I²C) ................................................................47
6.14 Serial Peripheral Interface (SPI)....................................................................48
6.15 Hardware Divider (HDIV) ............................................................................49
6.16 Enhanced Analog-to-Digital Converter (EADC)..................................................50
6.17 Analog Comparator (ACMP) ........................................................................51
6.18 OP Amplifier (OPA)...................................................................................52
7 ELECTRICAL CHARACTERISTICS .......................................................... 53
7.1 Absolute Maximum Ratings .........................................................................53
7.2 DC Electrical Characteristics........................................................................54
7.3 AC Electrical Characteristics ........................................................................58
7.4 Analog Characteristics ...............................................................................60
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M0519
7.5 Flash DC Electrical Characteristics ................................................................64
8 PACKAGE DIMENSIONS ...................................................................... 65
8.1 LQFP 100V (14x14x1.4 mm footprint 2.0mm) ...................................................65
8.2 LQFP 64S (7x7x1.4 mm footprint 2.0 mm) .......................................................66
8.3 LQFP 48L (7x7x1.4mm footprint 2.0mm) .........................................................67
9 REVISION HISTORY ............................................................................ 68
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M0519
List of Figures
Figure 4-1 NuMicro® M0519 Selection Code........................................................................ 12
Figure 4-2 NuMicro® M0519VxxAE Series LQFP-100 Pin Diagram ..................................... 13
Figure 4-3 NuMicro® M0519SxxAE Series LQFP-64 Pin Diagram ....................................... 14
Figure 4-4 NuMicro® M0519LxxAE Series LQFP-48 Pin Diagram........................................ 15
Figure 5-1 NuMicro® M0519 Series Block Diagram.............................................................. 23
Figure 6-1 Functional Controller Diagram ............................................................................ 24
Figure 6-2 NuMicro® M0519 Series Power Distribution Diagram.......................................... 27
Figure 6-3 Clock Generator Block Diagram ......................................................................... 36
Figure 6-4 Clock Generator Global View Diagram ............................................................... 37
Figure 71 Typical Crystal Application Circuit ...................................................................... 58
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M0519
List of Tables
Table 6-1 Address Space Assignments for On-Chip Controllers .......................................... 29
Table 6-2 Exception Model .................................................................................................. 32
Table 6-3 System Interrupt Map Vector Table...................................................................... 33
Table 6-4 Vector Table ........................................................................................................ 34
Table 6-5 Clock Stable Count Value Table .......................................................................... 35
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M0519
1 GENERAL DESCRIPTION
The NuMicro® M0519 Series 32-bit microcontroller is embedded with the newest ARM® Cortex® -
M0 core at a cost equivalent to traditional 8-bit microcontroller for industrial control and
applications which need high performance.
The NuMicro® M0519 Series embedded with the Cortex® -M0 core runs up to 72 MHz and
supports a variety of industrial control and applications which need high CPU performance. The
NuMicro® M0519 Series provides 128K/64K bytes embedded flash, 4 Kbytes data flash, 8 Kbytes
flash for the ISP, and 16K bytes embedded SRAM. This MCU includes advanced PWM function
and input capture timer which are specially designed for motor driving application. It is also
equipped with plenty of peripheral devices, such as Timers, Watchdog Timer, UART, SPI, I2C,
PWM Timer, GPIO, 12-bit ADC, Low Voltage Detector and Brown-out detector. These useful
functions make the NuMicro® M0519 Series powerful for a wide range of applications.
In addition, the NuMicro® M0519 Series is equipped with ISP (In-System Programming), ICP (In-
Circuit Programming) functions and IAP (In-Application Programming) which allow user to update
the program memory without removing the chip from the actual end product.
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M0519
2 FEATURES
Core
ARM® Cortex® -M0 core running up to 72 MHz
One 24-bit system timer
Supports Low Power Sleep mode by WFI instructions
Single-cycle 32-bit hardware multiplier
Supports programmable 4 level priorities of Nested Vectored Interrupt Controller
(NVIC)
Supports Serial Wire Debug (SWD) support with two watchpoints and four breakpoints
Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V
Memory
128K/64K bytes Flash for program memory (APROM)
4KB Flash for data memory (Data Flash)
8KB Flash for loader (LDROM)
Supports In-system program (ISP) and In-application program (IAP) application code
update
Supports 2-wired ICP update through SWD/ICE interface
Supports fast parallel programming mode by external programmer
16K bytes embedded SRAM
Clock Control
Built-in 22.1184 MHz internal high speed RC oscillator (HIRC) for system operation
(variation < 2% at -40˚C ~ +105˚C)
Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-
up operation
Built-in 4~24 MHz external high speed crystal oscillator (HXT) for precise timing
operation
Supports one PLL up to 72 MHz for high performance system operation, sourced from
HIRC and HXT
Supports clock output
Hardware divider
Supports signed 32-bit dividend, 16-bit divisor operation
GPIO port
Four I/O modes:
TTL/Schmitt trigger input selectable
Bit control available
I/O pin configured as interrupt source with edge/level trigger setting
Supports high driver and high sink current I/O (up to 16 mA at 5V)
INT0 and INT1 pins with individual interrupt vectors
Supports up to 82/51/38 GPIOs for LQFP100/64/48 respectively
Timers
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
Provides One-shot, Periodic, Toggle and Continuous Counting operation modes
Supports event counting function to count the event from external pin
Watchdog Timer
Supports multiple clock sources from LIRC(default selection) and HCLK/2048
8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source)
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Time-out reset delay period time can be selected
Window Watchdog Timer
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M0519
Supports multiple clock sources from HCLK/2048 (default selection) and LIRC
Window set by 6-bit counter with 11-bit prescale
Able to wake up from Power-down or Idle mode
Basic PWM
1 unit of 16-bit basic PWM, up to 2ch output
Alternative function as input capture timer
Enhanced PWM
2 units of 16-bit enhanced PWM, up to 6ch output with dead-zone control, brake and
polarity control for motor drive
Default tri-state during any reset
Enhanced Input Capture
Up to 2 units of 24-bit input capture
Each unit has 3 inputs: ECAPx_IC0, ECAPx_IC1 and ECAPx_IC2
UART
SPI
Up to two 16550 compatible UART devices
Programmable baud-rate generator
Buffered receiving and transmitting, each with 16 bytes FIFO
Supports flow control (TX, RX, CTS and RTS)
Supports IrDA(SIR) function
Supports RS-485
I2C
Up to three sets of SPI device
Supports SPI master/slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Supports Byte Suspend mode in 32-bit transmission
Master/Slave up to 1 Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters
Programmable clocks allow versatile rate control
Multiple address recognition (four slave address with mask option)
ADC
Two A/D converters
Each ADC with up to 8 channel, 12-bit resolution with 10-bit accuracy
16 result registers
Sampling rate up to 800ksps
Two operating modes:
Single Sampling mode: Only one specified channel can be sampled at one time.
Simultaneous Sampling mode: Allowing two ADC channels to be sampled
simultaneously.
Two converting result digital comparators
Conversion start by software, external pins, or linked with Timer 0~3 or PWM module
Up to three Analog Comparators
Up to two OPA (operational amplifier)
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Brown-out detector
4 levels: 4.4V/3.7V/2.7V/2.2V
Optional brown-out interrupt or reset
Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V
Low Voltage Reset
96-bit unique ID
Operating Temperature: -40~105
Develop tools: parallel writer or In-Circuit Programming (ICP) writer
Packages:
All Green package (RoHS)
LQFP 100/64/48-pin
M0519
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3 ABBREVIATIONS
Acronym
Description
ACMP
Analog Comparator Controller
ADC
Analog-to-Digital Converter
AES
Advanced Encryption Standard
APB
Advanced Peripheral Bus
AHB
Advanced High-Performance Bus
BOD
Brown-out Detection
CAN
Controller Area Network
DAP
Debug Access Port
DES
Data Encryption Standard
EBI External Bus Interface
EPWM
Enhanced Pulse Width Modulation
FIFO
First In, First Out
FMC
Flash Memory Controller
FPU
Floating-point Unit
GPIO
General-Purpose Input/Output
HCLK
The Clock of Advanced High-Performance Bus
HIRC
22.1184 MHz Internal High Speed RC Oscillator
HXT
4~24 MHz External High Speed Crystal Oscillator
IAP In Application Programming
ICP In Circuit Programming
ISP In System Programming
LDO
Low Dropout Regulator
LIN Local Interconnect Network
LIRC
10 kHz internal low speed RC oscillator (LIRC)
MPU
Memory Protection Unit
NVIC
Nested Vectored Interrupt Controller
PCLK
The Clock of Advanced Peripheral Bus
PDMA
Peripheral Direct Memory Access
PLL Phase-Locked Loop
PWM
Pulse Width Modulation
QEI Quadrature Encoder Interface
SDIO
Secure Digital Input/Output
SPI Serial Peripheral Interface
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SPS
TDES
TMR
UART
UCID
USB
WDT
WWDT
Samples per Second
Triple Data Encryption Standard
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
Watchdog Timer
Window Watchdog Timer
M0519
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4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® M0519 Selection Guide
4.1.1 NuMicro® M0519 Selection Guide
Connectivity
M0519
M0519LD3AE 64 16
4
8 38 4 2 1 1 2 -
x2,
6 2 2 v LQFP48
16-ch
M0519LE3AE 128 16 Config. 8 38 4 2 1 1 2 -
x2,
6 2 2 v LQFP48
16-ch
M0519SD3AE 64 16
4
8 51 4 2 2 1 2 -
x2,
10 2 2 v LQFP64
16-ch
M0519SE3AE 128 16 Config. 8 51 4 2 2 1 2 -
x2,
10 2 2 v LQFP64
16-ch
M0519VE3AE 128 16 Config. 8 82 4 2 3 1 2 6
x2,
14 2 3 v LQFP100
16-ch
4.1.2 NuMicro® M0519 Naming Rule
M0519 - X X X X E
CPU core
ARM Cortex M0
Temperature
E: - 40 ~ +105
Package Type
L: LQFP 48 (7x7)
S: LQFP 64 (7x7)
V: LQFP 100 (14x14)
Flash ROM
D: 64 KB Flash ROM
E: 128 KB Flash ROM
Version
A: Version
SRAM Size
3: 16KB SRAM
Figure 4-1 NuMicro® M0519 Selection Code
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4.2 Pin Configuration
4.2.1 LQFP 100-pin
M0519
ADC1_CH7/P7.7
ADC1_CH6/P7.6
ACMP2_P/ADC1_CH5/P7.5
ACMP2_N/ADC1_CH4/P7.4
ADC1_CH3/P7.3
ADC1_CH2/P7.2
ADC1_CH1/P7.1
ADC1_CH0/P7.0
ACMP0_P/P8.4
ACMP0_N/P8.3
OP1_O/P9.0
OP1_N/P9.1
OP1_P/P9.2
VDD
VSS
P8.5
EPWM1_BRAKE1/P9.3
nRESET
XT1_OUT
XT1_IN
ICE_DAT
ICE_CLK
SPI1_CLK/P9.4
SPI1_MISO/P9.5
SPI1_MOSI/P9.6
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
M0519VxxAE
LQFP 100-pin
50 P5.2/SPI2_MISO/ACMP1_O
49 P2.0/SPI2_MOSI/ACMP2_O
48 P2.1/ECAP0_IC2
47 P2.2/ECAP0_IC1
46 P2.3/ECAP0_IC0
45 P0.4/EPWM0_CH4
44 P0.5/EPWM0_CH5
43 P0.6/EPWM0_BRAKE1
42 P0.7/STADC
41 P2.4
40 P2.5
39 P2.6/SPI0_SS/UART1_nCTS
38 P2.7/SPI0_CLK/UART1_nRTS
37 P5.1/SPI0_MISO/UART0_nCTS/I2C_SDA
36 P5.0/SPI0_MOSI/UART0_nRTS/I2C_SCL
35 VSS
34 VDD
33 P4.7/TM3
32 P3.1/UART0_TXD/ACMP0_O
31 P3.0/UART0_RXD/CLKO
30 P1.0/EPWM1_CH0
29 P1.1/EPWM1_CH1
28 P4.6/TM2
27 P3.3/INT1
26 P4.3
Figure 4-2 NuMicro® M0519VxxAE Series LQFP-100 Pin Diagram
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4.2.2 LQFP 64-pin
M0519
ADC1_CH7/P7.7
ADC1_CH6/P7.6
ACMP2_P/ADC1_CH5/P7.5
ACMP2_N/ADC1_CH4/P7.4
ADC1_CH3/P7.3
ADC1_CH2/P7.2
ADC1_CH1/P7.1
ADC1_CH0/P7.0
OP1_O/P9.0
OP1_N/P9.1
OP1_P/P9.2
nRESET
XT1_OUT
XT1_IN
ICE_DAT
ICE_CLK
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
M0519SxxAE
LQFP 64-pin
32 P5.2/SPI2_MISO/ACMP1_O
31 P2.0/SPI2_MOSI/ACMP2_O
30 P0.4/EPWM0_CH4
29 P0.5/EPWM0_CH5
28 P2.4
27 P2.5
26 P2.6/SPI0_SS/UART1_nCTS
25 P2.7/SPI0_CLK/UART1_nRTS
24 P5.1/SPI0_MISO/UART0_nCTS/I2C_SDA
23 P5.0/SPI0_MOSI/UART0_nRTS/I2C_SCL
22 VSS
21 VDD
20 P3.1/UART0_TXD
19 P3.0/UART0_RXD/CLKO
18 P1.0/EPWM1_CH0
17 P1.1/EPWM1_CH1
Figure 4-3 NuMicro® M0519SxxAE Series LQFP-64 Pin Diagram
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4.2.3 LQFP 48-pin
M0519
ADC1_CH7/P7.7
ADC1_CH6/P7.6
ACMP2_P/ADC1_CH5/P7.5
ACMP2_N/ADC1_CH4/P7.4
ADC1_CH3/P7.3
ADC1_CH2/P7.2
ADC1_CH1/P7.1
ADC1_CH0/P7.0
OP1_O/P9.0
OP1_N/P9.1
OP1_P/P9.2
nRESET
37
38
39
40
41
42
43
44
45
46
47
48
M0519LxxAE
LQFP 48-pin
24 P6.7/ADC0_CH7
23 P0.7/STADC
22 P2.6/SPI0_SS/UART1_nCTS
21 P2.7/SPI0_CLK/UART1_nRTS
20 P5.1/SPI0_MISO/UART0_nCTS/I2C_SDA
19 P5.0/SPI0_MOSI/UART0_nRTS/I2C_SCL
18 P3.1/UART0_TXD/ACMP0_O
17 P3.0/UART0_RXD/CLKO
16 P1.5/EPWM1_CH5
15 P1.4/EPWM1_CH4
14 P1.3/EPWM1_CH3
13 P1.2/EPWM1_CH2
Figure 4-4 NuMicro® M0519LxxAE Series LQFP-48 Pin Diagram
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M0519
4.3 Pin Description
Pin Number
100- pin 64-pin 48-pin
Pin Name
10
6
34
61
21
89
7 VDD
11
7
35
60
22
90
8 VSS
9 5 6 LDO_CAP
1 - - PVSS
74 47 36 AVDD
73 46 35 AVSS
75 48
- VREF
93 60 48 nRESET
94 61
95 62
96 63
97 64
57 -
56 -
55 -
4 XT1_OUT
3 XT1_IN
2 ICE_DAT
1 ICE_CLK
P0.0
- PWM0_CH0
ECAP1_IC0
P0.1
- PWM0_CH1
ECAP1_IC1
P0.2
-
PWM0_CH2
Pin
Type[1]
Description
P POWER SUPPLY: Supply voltage Digital VDD for operation.
P GROUND: Digital Ground potential.
LDO: LDO output pin
P
Note: It needs to be connected with a 1uF capacitor.
P PLL GROUND: PLL Ground potential.
AP Power supply for internal analog circuit
AP Ground Pin for analog circuit
Voltage reference input for ADC
AP
Note: It needs to be connected with a 1uF capacitor.
RESET: nRESET pin is a Schmitt trigger input pin for hardware device
I reset. A Low” on this pin for 768 clock counter of Internal RC 22.1184
MHz while the system clock is running will reset the device. nRESET
(ST) pin has an internal pull-up resistor allowing power-on reset by simply
connecting an external capacitor to GND.
O
CRYSTAL OUT: This is the output pin from the internal inverting
amplifier. It emits the inverted signal of XT1_IN.
I CRYSTAL IN: This is the input pin to the internal inverting amplifier.
The system clock is from external crystal or resonator when FOSC[1:0]
(ST) (CONFIG3[1:0]) are both logic 1 by default.
I/O Serial Wired Debugger Data pin
I Serial Wired Debugger Clock pin
I/O General purpose digital I/O pin
O PWM0 output of PWM Unit 0
I Input 0 of Enhanced Input Capture Unit 1
I/O General purpose digital I/O pin
O PWM1 output of PWM Unit 0
I Input 1 of Enhanced Input Capture Unit 1
I/O General purpose digital I/O pin
O PWM2 output of PWM Unit 0
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Pin Number
100- pin 64-pin 48-pin
Pin Name
ECAP1_IC2
P0.3
54 -
- PWM0_CH3
STADC
Pin
Type[1]
Description
I Input 2 of Enhanced Input Capture Unit 1
I/O General purpose digital I/O pin
O PWM3 output of PWM Unit 0
I ADC external trigger input
45 30
P0.4
-
PWM0_CH4
I/O General purpose digital I/O pin
O PWM4 output of PWM Unit 0
44 29
P0.5
-
PWM0_CH5
I/O General purpose digital I/O pin
O PWM5 output of PWM Unit 0
43 -
P0.6
I/O General purpose digital I/O pin
-
PWM0_BRAKE1 I Brake input pin 1 of PWM Unit 0
P0.7
42 - 23
STADC
I/O General purpose digital I/O pin
I ADC external trigger input
30 18
P1.0
-
PWM1_CH0
I/O General purpose digital I/O pin
O PWM0 output of PWM Unit 1
29 17
P1.1
-
PWM1_CH1
I/O General purpose digital I/O pin
O PWM1 output of PWM Unit 1
P1.2
20 16 13
PWM1_CH2
I/O General purpose digital I/O pin
O PWM2 output of PWM Unit 1
P1.3
19 15 14
PWM1_CH3
I/O General purpose digital I/O pin
O PWM3 output of PWM Unit 1
P1.4
18 14 15
PWM1_CH4
I/O General purpose digital I/O pin
O PWM4 output of PWM Unit 1
P1.5
17 13 16
PWM1_CH5
I/O General purpose digital I/O pin
O PWM5 output of PWM Unit 1
16 12
P1.6
I/O General purpose digital I/O pin
-
PWM0_BRAKE0 I Brake input pin 0 of PWM Unit 0
P1.7
I/O General purpose digital I/O pin
845
PWM1_BRAKE0 I Brake input pin0 of PWM Unit 1
P2.0
I/O General purpose digital I/O pin
49 31
- SPI2_MOSI
I/O SPI2 MOSI (Master Out, Slave In) pin
ACMP2_O
AO Analog comparator 2 output pin
48 -
P2.1
-
ECAP0_IC2
I/O General purpose digital I/O pin
I Input 2 of Enhanced Input Capture Unit 0
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Pin Number
100- pin 64-pin 48-pin
Pin Name
47 -
P2.2
-
ECAP0_IC1
46 -
P2.3
-
ECAP0_IC0
41 28
- P2.4
40 27
- P2.5
P2.6
39 26 22 SPI0_SS
UART1_nCTS
P2.7
38 25 21 SPI0_CLK
UART1_nRTS
P3.0
31 19 17
UART0_RXD
P3.1
32 20 18 UART0_TXD
ACMP0_O
P3.2
73 -
INT0
27 -
P3.3
-
INT1
P3.4
6 2 - TM0
I2C0_SDA
P3.5
5 1 - TM1
I2C0_SCL
4 - - P3.6
3 - - P3.7
23 -
P4.0
-
ECAP1_IC0
24 -
P4.1
-
ECAP1_IC1
Pin
Type[1]
Description
I/O General purpose digital I/O pin
I Input 1 of Enhanced Input Capture Unit 0
I/O General purpose digital I/O pin
I Input 0 of Enhanced Input Capture Unit 0
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O SPI0 slave select pin
I UART1 CTS pin
I/O General purpose digital I/O pin
I/O SPI0 serial clock pin
O UART1 RTS pin
I/O General purpose digital I/O pin
I Data Receiver input pin for UART0
I/O General purpose digital I/O pin
O Data transmitter output pin for UART0
AO Analog comparator 0 output
I/O General purpose digital I/O pin
I External Interrupt 0 input pin
I/O General purpose digital I/O pin
I External Interrupt 1 input pin
I/O General purpose digital I/O pin
I/O Timer0 external clock
I/O I2C0 data input/output pin
I/O General purpose digital I/O pin
I/O Timer1 external clock
I/O I2C0 clock output pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I Input 0 of Enhanced Input Capture Unit 1
I/O General purpose digital I/O pin
I Input 1 of Enhanced Input Capture Unit 1
Nov. 02, 2016
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Pin Number
100- pin 64-pin 48-pin
Pin Name
25 -
P4.2
-
ECAP1_IC2
26 -
- P4.3
21 -
- P4.4
22 -
- P4.5
28 -
P4.6
-
TM2
33 -
P4.7
-
TM3
P5.0
36 23 19 SPI0_MOSI
UART0_nRTS
P5.1
37 24 20 SPI0_MISO
UART0_nCTS
50 32
51 33
P5.2
- SPI2_MISO
ACMP1_O
P5.3
-
SPI2_CLK
52 34
P5.4
-
SPI2_SS
53 -
P5.5
-
CLKO
P5.6
15 11 12
PWM2_CH0
P5.7
14 10 11
PWM2_CH1
P6.0
69 42 31
ADC0_CH0
P6.1
68 41 30
ADC0_CH1
67 40 29 P6.2
Pin
Type[1]
Description
I/O General purpose digital I/O pin
I Input 2 of Enhanced Input Capture Unit 1
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O General purpose digital I/O pin
I/O Timer2 external clock
I/O General purpose digital I/O pin
I/O Timer3 external clock
I/O General purpose digital I/O pin
I/O SPI0 MOSI (Master Out, Slave In) pin
O UART0 RTS pin
I/O General purpose digital I/O pin
I/O SPI0 MISO (Master In, Slave Out) pin
I UART0 CTS pin
I/O General purpose digital I/O pin
I/O SPI2 MISO (Master In, Slave Out) pin
AO Analog comparator 1 output pin
I/O General purpose digital I/O pin
I/O SPI2 serial clock pin
I/O General purpose digital I/O pin
I/O SPI2 slave select pin
I/O General purpose digital I/O pin
O Frequency Divider output pin
I/O General purpose digital I/O pin
I/O PWM0 output of PWM unit 2
I/O General purpose digital I/O pin
I/O PWM1 output of PWM unit 2
I/O General purpose digital I/O pin
AI ADC analog input 0 for sample-and-hold A
I/O General purpose digital I/O pin
AI ADC analog input 1 for sample-and-hold A
I/O General purpose digital I/O pin
Nov. 02, 2016
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Pin Number
100- pin 64-pin 48-pin
Pin Name
ADC0_CH2
P6.3
66 39 28
ADC0_CH3
P6.4
65 38 27 ADC0_CH4
ACMP1_N
P6.5
64 37 26 ADC0_CH5
ACMP1_P
P6.6
63 36 25
ADC0_CH6
P6.7
62 35 24
ADC0_CH7
P7.0
83 56 44
ADC1_CH0
P7.1
82 55 43
ADC1_CH1
P7.2
81 54 42
ADC1_CH2
P7.3
80 53 41
ADC1_CH3
P7.4
79 52 40 ADC1_CH4
ACMP2_N
P7.5
78 51 39 ADC1_CH5
ACMP2_P
P7.6
77 50 38
ADC1_CH6
P7.7
76 49 37
ADC1_CH7
P8.0
72 45 34
OP0_P
Pin
Type[1]
Description
AI ADC analog input 2 for sample-and-hold A
I/O General purpose digital I/O pin
AI ADC analog input 3 for sample-and-hold A
I/O General purpose digital I/O pin
AI ADC analog input 4 for sample-and-hold A
AI Analog comparator 1 negative input
I/O General purpose digital I/O pin
AI ADC analog input 5 for sample-and-hold A
AI Analog comparator 1 positive input
I/O General purpose digital I/O pin
AI ADC analog input 6 for sample-and-hold A
I/O General purpose digital I/O pin
AI ADC analog input 7 for sample-and-hold A
I/O General purpose digital I/O pin
AI ADC analog input 0 for sample-and-hold B
I/O General purpose digital I/O pin
AI ADC analog input 1 for sample-and-hold B
I/O General purpose digital I/O pin
AI ADC analog input 2 for sample-and-hold B
I/O General purpose digital I/O pin
AI ADC analog input 3 for sample-and-hold B
I/O General purpose digital I/O pin
AI ADC analog input 4 for sample-and-hold B
AI Analog comparator 2 negative input
I/O General purpose digital I/O pin
AI ADC analog input 5 for sample-and-hold B
AI Analog comparator 2 positive input
I/O General purpose digital I/O pin
AI ADC analog input 6 for sample-and-hold B
I/O General purpose digital I/O pin
AI ADC analog input 7 for sample-and-hold B
I/O General purpose digital I/O pin
AI OP Amplifier 0 positive input
Nov. 02, 2016
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Pin Number
100- pin 64-pin 48-pin
Pin Name
Pin
Type[1]
Description
P8.1
71 44 33
OP0_N
I/O General purpose digital I/O pin
AI OP Amplifier 0 negative input
P8.2
70 43 32
OP0_O
I/O General purpose digital I/O pin
AO OP Amplifier 0 output
85 -
P8.3
-
ACMP0_N
I/O General purpose digital I/O pin
AI Analog comparator negative input pin
84 -
P8.4
-
ACMP0_P
I/O General purpose digital I/O pin
AI Analog comparator positive input pin
91 -
- P8.5
I/O General purpose digital I/O pin
59 -
- P8.6
I/O General purpose digital I/O pin
58 -
P8.7
-
ACMP0_O
I/O General purpose digital I/O pin
O Analog comparator output pin
P9.0
86 57 45
OP1_O
I/O General purpose digital I/O pin
AO OP Amplifier 1 output
P9.1
87 58 46
OP1_N
I/O General purpose digital I/O pin
AI OP Amplifier 1 negative input
P9.2
88 59 47
OP1_P
I/O General purpose digital I/O pin
AI OP Amplifier 1 positive input
92 -
P9.3
I/O General purpose digital I/O pin
-
PWM1_BRAKE1 I Brake input pin 1 of PWM Unit 1
98 -
P9.4
-
SPI1_CLK
I/O General purpose digital I/O pin
I/O SPI1 serial clock pin
99 -
P9.5
-
SPI1_MISO
I/O General purpose digital I/O pin
I/O SPI1 MISO (Master In, Slave Out) pin
100 -
P9.6
-
SPI1_MOSI
I/O General purpose digital I/O pin
I/O SPI1 MOSI (Master Out, Slave In) pin
P9.7
2- -
SPI1_SS
I/O General purpose digital I/O pin
I/O SPI1 slave select pin
PA.0
I/O General purpose digital I/O pin
13 9 10 UART1_TXD O Data transmitter output pin for UART1
I2C0_SDA
I/O I2C0 data input/output pin
12 8
PA.1
9
UART1_RXD
I/O General purpose digital I/O pin
I Data Receiver input pin for UART1
Nov. 02, 2016
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Pin Number
100- pin 64-pin 48-pin
Pin Name
Pin
Type[1]
Description
I2C0_SCL
I/O I2C0 clock output pin
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power
M0519
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M0519
5 BLOCK DIAGRAM
ARM®
Cortex® -M0
72 MHz
Memory
APROM 128/64 KB
LDROM 8 KB
Data Flash 4 KB
SRAM 16 KB
AHB Bus
Timer / PWM
32-bit
Timer x 4
EPWM
Timer x 12
Watchdog
Timers
ICAP
Timer x 2
BPWM Timer x 2
Analog Interface
2 sets of 12-bit
ADC x 8
Operating Amp. x 2
Comparators x 3
Bridge
APB Bus
Power Control
LDO
Power-on Reset
LVR
Brown-out Detection
Clock Control
PLL
HS Osc.
22.1184 MHz
HS Ext. Crystal
Osc. 4~24 MHz
LS Osc.
10 kHz
GPIO
General Purpose I/O
Reset Pin
External Interrupt
Connectivity
UART x 2
SPI x 3
I²C
Figure 5-1 NuMicro® M0519 Series Block Diagram
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M0519
6 FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6-1 shows the functional controller of processor.
CortexTM-M0 Components
CortexTM-M0 processor
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
CortexTM-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Bus Matrix
AHB-Lite
Interface
Debug
Breakpoint
and
Watchpoint
Unit
Debugger
Interface
Debug
Access
Port
(DAP)
Serial Wire or
JTAG Debug Port
Figure 6-1 Functional Controller Diagram
The implemented device provides the following components and features:
A low gate count processor:
- ARMv6-M Thumb® instruction set
- Thumb-2 technology
- ARMv6-M compliant 24-bit SysTick timer
- A 32-bit hardware multiplier
- System interface supported with little-endian data accesses
- Ability to have deterministic, fixed-latency, interrupt handling
- Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
- C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
- Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
NVIC:
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M0519
- 32 external interrupt inputs, each with four levels of priority
- Dedicated Non-maskable Interrupt (NMI) input
- Supports for both level-sensitive and pulse-sensitive interrupt lines
- Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support
- Four hardware breakpoints
- Two watchpoints
- Program Counter Sampling Register (PCSR) for non-intrusive code profiling
- Single step and vector catch capabilities
Bus interfaces:
- Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
- Single 32-bit slave port that supports the DAP (Debug Access Port)
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M0519
6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Resets
System Power Distribution
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Hardware Reset
Power-on Reset (POR)
Low level on the Reset pin (nRESET)
Watchdog Time-out Reset (WDT)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD)
Software Reset
SYS Reset - SYSRESETREQ (AIRCR[2])
Cortex® -M0 Core One-shot Reset - CPU_RST (IPRSTC1[1])
Chip One-shot Reset - CHIP_RST (IPRSTC1[0])
Power-on Reset or CHIP_RST (IPRST1[0]) reset the whole chip including all peripherals,
external crystal circuit and BS (ISPCON[1]) bit.
SYSRESETREQ (AIRCR[2]) reset the whole chip including all peripherals, but does not reset
external crystal circuit and BS (ISPCON[1]) bit.
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M0519
6.2.3 System Power Distribution
In this chip, the power distribution is divided into two segments.
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the I/O pins and internal
regulator which provides a fixed 1.8V power for digital operation.
The output of internal voltage regulators, LDO_CAP, requires an external capacitor which should
be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level
of the digital power (VDD).
AVDD
AVSS
XT1_IN
XT1_OUT
12-bit
SAR-ADC
Analog
Comparator
OPA
Brown-
out
Detector
Low
Voltage
Reset
Temperature
Seneor
FLASH
Digital Logic
Internal
22.1184 MHz & 10 kHz
Oscillator
4~24MHz
Crystal
PLL
POR18
POR50
1.8V
LDO
IO cell
LDO_CAP
1uF
GPIO
Figure 6-2 NuMicro® M0519 Series Power Distribution Diagram
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M0519
6.2.4 System Memory Map
The NuMicro® M0519 Series provides 4G-byte addressing space. The memory locations assigned
to each on-chip controllers are shown in Table 6-1. The detailed register definition, memory
space, and programming detailed will be described in the following sections for each on-chip
peripheral. The NuMicro® M0519 Series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 0x0001_FFFF
FLASH_BA
FLASH Memory Space (128 KB)
0x2000_0000 0x2000_3FFF
SRAM_BA
SRAM Memory Space (16 KB)
AHB Controllers Space (0x5000_0000 0x501F_FFFF)
0x5000_0000 0x5000_01FF
GCR_BA
System Global Control Registers
0x5000_0200 0x5000_02FF
CLK_BA
Clock Control Registers
0x5000_0300 0x5000_03FF
INT_BA
Interrupt Multiplexer Control Registers
0x5000_4000 0x5000_7FFF
GPIO_BA
GPIO Control Registers
0x5000_C000 0x5000_FFFF
FMC_BA
Flash Memory Control Registers
0x5001_4000 0x5001_7FFF
HDIV_BA
Hardware Divider Register
APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 0x4000_7FFF
WDT_BA
Watchdog Timer Control Registers
0x4000_4100 0x4000_7FFF
WWDT_BA
Window Watchdog Timer Control Registers
0x4001_0000 0x4001_3FFF
0x4002_0000 0x4002_3FFF
TMR01_BA
I2C0_BA
Timer0/Timer1 Control Registers
I2C0 Interface Control Registers
0x4003_0000 0x4003_3FFF
SPI0_BA
SPI0 with master/slave function Control Registers
0x4003_4000 0x4003_7FFF
SPI1_BA
SPI1 with master/slave function Control Registers
0x4004_0000 0x4004_3FFF
BPWM0_BA
Basic PWM0 Control Registers
0x4005_0000 0x4005_3FFF
UART0_BA
UART0 Control Registers
0x400D_0000 0x400D_3FFF
ACMP_BA
Analog Comparator Control Registers
0x400E_0000 0x400E_3FFF
EADC_BA
Enhanced Analog-Digital-Converter (EADC) Control Registers
0x400F_0000 0x400F_3FFF
OPA_BA
Operation Amplifier Control Registers
APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF)
0x4011_0000 0x4011_3FFF
TMR23_BA
Timer2/Timer3 Control Registers
0x4013_0000 0x4013_3FFF
SPI2_BA
SPI2 with master/slave function Control Registers
0x4015_0000 0x4015_3FFF
UART1_BA
UART1 Control Registers
Reserved
Reserved
Reserved
0x4019_0000 0x4019_3FFF
EPWM0_BA
Enhanced PWM0 Control Registers
0x4019_4000 0x4019_7FFF
EPWM1_BA
Enhanced PWM1 Control Registers
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Address Space
Token
Controllers
0x401B_0000 0x401B_3FFF
ECAP0_BA
Enhanced Input Capture 0 Control Registers
0x401B_4000 0x401B_7FFF
ECAP1_BA
Enhanced Input Capture 1 Control Registers
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 0xE000_E01F
SYST_BA
System Timer Control Registers
0xE000_E100 0xE000_E4EF
NVIC_BA
External Interrupt Controller Control Registers
0xE000_ED00 0xE000_ED3F
SCS_BA
System Control Registers
Table 6-1 Address Space Assignments for On-Chip Controllers
M0519
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6.2.5 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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