C8051F542 (Silicon Laboratories)
Mixed Signal ISP Flash MCU Family

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Analog Peripherals
- 12-Bit ADC
Up to 200 ksps
Up to 25 external single-ended inputs
VREF from on-chip VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- Two Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 19 mA at 50 MHz;
Typical stop mode current: 1 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
C8051F54x
Mixed Signal ISP Flash MCU Family
Memory
- 1280 bytes internal data RAM (256 + 1024 XRAM)
- 16 or 8 kB Flash; In-system programmable in
512-byte Sectors
Digital Peripherals
- 25 or 18 Port I/O; All 5 V tolerant
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy master LIN
operation
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 32-Pin QFP/QFN (C8051F540/1/4/5)
- 24-Pin QFN (C8051F542/3/6/7)
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
TEMP
SENSOR
X ADC
Voltage VREG
Comparators 0-1 VREF
DIGITAL I/O
UART 0
SMBus
SPI
PCA
Timers 0-3
LIN
Ports 0-3
Crossbar
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
1 kB XRAM
POR WDT
Rev. 1.1 4/11
Copyright © 2011 by Silicon Laboratories
C8051F540/1/2/3/4/5/6/7


C8051F542 (Silicon Laboratories)
Mixed Signal ISP Flash MCU Family

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C8051F54x
Table of Contents
1. System Overview ..................................................................................................... 13
2. Ordering Information ............................................................................................... 16
3. Pin Definitions.......................................................................................................... 18
4. Package Specifications ........................................................................................... 23
4.1. QFP-32 Package Specifications........................................................................ 23
4.2. QFN-32 Package Specifications........................................................................ 25
4.3. QFN-24 Package Specifications........................................................................ 27
5. 12-Bit ADC (ADC0) ................................................................................................... 29
5.1. Modes of Operation ........................................................................................... 30
5.2. Output Code Formatting .................................................................................... 34
5.3. Selectable Gain ................................................................................................. 35
5.4. Programmable Window Detector....................................................................... 43
6. Electrical Characteristics ........................................................................................ 47
6.1. Absolute Maximum Specifications..................................................................... 47
6.2. Electrical Characteristics ................................................................................... 48
6.1. ADC0 Analog Multiplexer .................................................................................. 58
6.2. Temperature Sensor.......................................................................................... 60
7. Voltage Reference.................................................................................................... 61
8. Comparators............................................................................................................. 63
8.1. Comparator Multiplexer ..................................................................................... 69
9. Voltage Regulator (REG0) ....................................................................................... 72
10. CIP-51 Microcontroller........................................................................................... 74
10.1. Performance .................................................................................................... 74
10.2. Instruction Set.................................................................................................. 76
10.3. CIP-51 Register Descriptions .......................................................................... 80
10.4. Serial Number Special Function Registers (SFRs) ......................................... 84
11. Memory Organization ............................................................................................ 85
11.1. Program Memory............................................................................................. 85
11.2. Data Memory ................................................................................................... 86
11.3. External RAM .................................................................................................. 87
12. Special Function Registers................................................................................... 89
12.1. SFR Paging ..................................................................................................... 89
12.2. Interrupts and SFR Paging .............................................................................. 89
12.3. SFR Page Stack Example ............................................................................... 91
13. Interrupts .............................................................................................................. 105
13.1. MCU Interrupt Sources and Vectors.............................................................. 105
13.2. Interrupt Register Descriptions ...................................................................... 108
13.3. External Interrupts INT0 and INT1..................................................................115
14. Flash Memory....................................................................................................... 117
14.1. Programming the Flash Memory ................................................................... 117
14.2. Non-volatile Data Storage ............................................................................. 119
14.3. Security Options ............................................................................................ 119
14.4. Flash Write and Erase Guidelines ................................................................. 121
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15. Power Management Modes................................................................................. 126
15.1. Idle Mode....................................................................................................... 126
15.2. Stop Mode ..................................................................................................... 127
15.3. Suspend Mode .............................................................................................. 127
16. Reset Sources ...................................................................................................... 129
16.1. Power-On Reset ............................................................................................ 130
16.2. Power-Fail Reset/VDD Monitor ..................................................................... 130
16.3. External Reset ............................................................................................... 132
16.4. Missing Clock Detector Reset ....................................................................... 132
16.5. Comparator0 Reset ....................................................................................... 133
16.6. PCA Watchdog Timer Reset ......................................................................... 133
16.7. Flash Error Reset .......................................................................................... 133
16.8. Software Reset .............................................................................................. 133
17. Oscillators and Clock Selection ......................................................................... 135
17.1. System Clock Selection................................................................................. 135
17.2. Programmable Internal Oscillator .................................................................. 137
17.3. Clock Multiplier .............................................................................................. 140
17.4. External Oscillator Drive Circuit..................................................................... 142
18. Port Input/Output ................................................................................................. 147
18.1. Port I/O Modes of Operation.......................................................................... 148
18.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 149
18.3. Priority Crossbar Decoder ............................................................................. 150
18.4. Port I/O Initialization ...................................................................................... 152
18.5. Port Match ..................................................................................................... 157
18.6. Special Function Registers for Accessing and Configuring Port I/O ............. 161
19. Local Interconnect Network (LIN)....................................................................... 170
19.1. Software Interface with the LIN Controller..................................................... 171
19.2. LIN Interface Setup and Operation................................................................ 171
19.3. LIN Master Mode Operation .......................................................................... 174
19.4. LIN Slave Mode Operation ............................................................................ 175
19.5. Sleep Mode and Wake-Up ............................................................................ 176
19.6. Error Detection and Handling ........................................................................ 176
19.7. LIN Registers................................................................................................. 177
20. SMBus................................................................................................................... 187
20.1. Supporting Documents .................................................................................. 188
20.2. SMBus Configuration..................................................................................... 188
20.3. SMBus Operation .......................................................................................... 188
20.4. Using the SMBus........................................................................................... 190
20.5. SMBus Transfer Modes................................................................................. 197
20.6. SMBus Status Decoding................................................................................ 201
21. UART0 ................................................................................................................... 205
21.1. Baud Rate Generator .................................................................................... 205
21.2. Data Format................................................................................................... 207
21.3. Configuration and Operation ......................................................................... 208
22. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 214
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22.1. Signal Descriptions........................................................................................ 215
22.2. SPI0 Master Mode Operation ........................................................................ 216
22.3. SPI0 Slave Mode Operation .......................................................................... 218
22.4. SPI0 Interrupt Sources .................................................................................. 218
22.5. Serial Clock Phase and Polarity .................................................................... 219
22.6. SPI Special Function Registers ..................................................................... 220
23. Timers ................................................................................................................... 227
23.1. Timer 0 and Timer 1 ...................................................................................... 229
23.2. Timer 2 .......................................................................................................... 237
23.3. Timer 3 .......................................................................................................... 243
24. Programmable Counter Array............................................................................. 249
24.1. PCA Counter/Timer ....................................................................................... 250
24.2. PCA0 Interrupt Sources................................................................................. 251
24.3. Capture/Compare Modules ........................................................................... 252
24.4. Watchdog Timer Mode .................................................................................. 260
24.5. Register Descriptions for PCA0..................................................................... 263
25. C2 Interface .......................................................................................................... 269
25.1. C2 Interface Registers................................................................................... 269
25.2. C2 Pin Sharing .............................................................................................. 272
Rev. 1.1
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List of Figures
Figure 1.1. C8051F540/1/4/5 Block Diagram .......................................................... 14
Figure 1.2. C8051F542/3/6/7 Block Diagram .......................................................... 15
Figure 3.1. QFP-32 Pinout Diagram (Top View) ...................................................... 20
Figure 3.2. QFN-32 Pinout Diagram (Top View) ..................................................... 21
Figure 3.3. QFN-24 Pinout Diagram (Top View) ..................................................... 22
Figure 4.1. QFP-32 Package Drawing ..................................................................... 23
Figure 4.2. QFP-32 Landing Diagram ..................................................................... 24
Figure 4.3. QFN-32 Package Drawing .................................................................... 25
Figure 4.4. QFN-32 Landing Diagram ..................................................................... 26
Figure 4.5. QFN-24 Package Drawing .................................................................... 27
Figure 4.6. QFN-24 Landing Diagram ..................................................................... 28
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 29
Figure 5.2. ADC0 Tracking Modes .......................................................................... 31
Figure 5.3. 12-Bit ADC Tracking Mode Example ..................................................... 32
Figure 5.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4 ............. 33
Figure 5.5. ADC0 Equivalent Input Circuit ............................................................... 35
Figure 5.6. ADC Window Compare Example: Right-Justified Data ......................... 46
Figure 5.7. ADC Window Compare Example: Left-Justified Data ........................... 46
Figure 6.1. Minimum VDD Monitor Threshold vs. System Clock Frequency ........... 50
Figure 6.2. ADC0 Multiplexer Block Diagram .......................................................... 58
Figure 6.3. Temperature Sensor Transfer Function ................................................ 60
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 61
Figure 8.1. Comparator Functional Block Diagram ................................................. 63
Figure 8.2. Comparator Hysteresis Plot .................................................................. 64
Figure 8.3. Comparator Input Multiplexer Block Diagram ........................................ 69
Figure 9.1. External Capacitors for Voltage Regulator Input/Output—
Regulator Enabled ............................................................................................. 72
Figure 9.2. External Capacitors for Voltage Regulator Input/Output—Regulator Dis-
abled ............................................................................................................... 73
Figure 10.1. CIP-51 Block Diagram ......................................................................... 75
Figure 11.1. C8051F54x Memory Map .................................................................... 85
Figure 11.2. Flash Program Memory Map ............................................................... 86
Figure 12.1. SFR Page Stack .................................................................................. 90
Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SMB0ADR . 91
Figure 12.3. SFR Page Stack After SPI0 Interrupt Occurs ...................................... 92
Figure 12.4. SFR Page Stack Upon PCA Interrupt Occurring During a SPI0 ISR .. 93
Figure 12.5. SFR Page Stack Upon Return From PCA Interrupt ............................ 94
Figure 12.6. SFR Page Stack Upon Return From SPI0 Interrupt ............................ 95
Figure 14.1. Flash Program Memory Map ............................................................. 119
Figure 16.1. Reset Sources ................................................................................... 129
Figure 16.2. Power-On and VDD Monitor Reset Timing ....................................... 130
Figure 17.1. Oscillator Options .............................................................................. 135
Figure 17.2. Example Clock Multiplier Output ....................................................... 140
Rev. 1.1
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Figure 17.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 145
Figure 18.1. Port I/O Functional Block Diagram .................................................... 147
Figure 18.2. Port I/O Cell Block Diagram .............................................................. 148
Figure 18.3. Peripheral Availability on Port I/O Pins .............................................. 151
Figure 18.4. Crossbar Priority Decoder in Example Configuration ........................ 152
Figure 19.1. LIN Block Diagram ............................................................................ 170
Figure 20.1. SMBus Block Diagram ...................................................................... 187
Figure 20.2. Typical SMBus Configuration ............................................................ 188
Figure 20.3. SMBus Transaction ........................................................................... 189
Figure 20.4. Typical SMBus SCL Generation ........................................................ 191
Figure 20.5. Typical Master Write Sequence ........................................................ 198
Figure 20.6. Typical Master Read Sequence ........................................................ 199
Figure 20.7. Typical Slave Write Sequence .......................................................... 200
Figure 20.8. Typical Slave Read Sequence .......................................................... 201
Figure 21.1. UART0 Block Diagram ...................................................................... 205
Figure 21.2. UART0 Timing Without Parity or Extra Bit ......................................... 207
Figure 21.3. UART0 Timing With Parity ................................................................ 207
Figure 21.4. UART0 Timing With Extra Bit ............................................................ 207
Figure 21.5. Typical UART Interconnect Diagram ................................................. 208
Figure 21.6. UART Multi-Processor Mode Interconnect Diagram ......................... 209
Figure 22.1. SPI Block Diagram ............................................................................ 214
Figure 22.2. Multiple-Master Mode Connection Diagram ...................................... 217
Figure 22.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
217
Figure 22.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
217
Figure 22.5. Master Mode Data/Clock Timing ....................................................... 219
Figure 22.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 220
Figure 22.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 220
Figure 22.8. SPI Master Timing (CKPHA = 0) ....................................................... 224
Figure 22.9. SPI Master Timing (CKPHA = 1) ....................................................... 224
Figure 22.10. SPI Slave Timing (CKPHA = 0) ....................................................... 225
Figure 22.11. SPI Slave Timing (CKPHA = 1) ....................................................... 225
Figure 23.1. T0 Mode 0 Block Diagram ................................................................. 230
Figure 23.2. T0 Mode 2 Block Diagram ................................................................. 231
Figure 23.3. T0 Mode 3 Block Diagram ................................................................. 232
Figure 23.4. Timer 2 16-Bit Mode Block Diagram ................................................. 237
Figure 23.5. Timer 2 8-Bit Mode Block Diagram ................................................... 238
Figure 23.6. Timer 2 External Oscillator Capture Mode Block Diagram ................ 239
Figure 23.7. Timer 3 16-Bit Mode Block Diagram ................................................. 243
Figure 23.8. Timer 3 8-Bit Mode Block Diagram ................................................... 244
Figure 23.9. Timer 3 External Oscillator Capture Mode Block Diagram ................ 245
Figure 24.1. PCA Block Diagram ........................................................................... 249
Figure 24.2. PCA Counter/Timer Block Diagram ................................................... 251
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Figure 24.3. PCA Interrupt Block Diagram ............................................................ 252
Figure 24.4. PCA Capture Mode Diagram ............................................................. 254
Figure 24.5. PCA Software Timer Mode Diagram ................................................. 255
Figure 24.6. PCA High-Speed Output Mode Diagram ........................................... 256
Figure 24.7. PCA Frequency Output Mode ........................................................... 257
Figure 24.8. PCA 8-Bit PWM Mode Diagram ........................................................ 258
Figure 24.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 259
Figure 24.10. PCA 16-Bit PWM Mode ................................................................... 260
Figure 24.11. PCA Module 2 with Watchdog Timer Enabled ................................ 261
Figure 25.1. Typical C2 Pin Sharing ...................................................................... 272
Rev. 1.1
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List of Tables
Table 2.1. Product Selection Guide ......................................................................... 17
Table 3.1. Pin Definitions for the C8051F54x .......................................................... 18
Table 4.1. QFP-32 Package Dimensions ................................................................ 23
Table 4.2. QFP-32 Landing Diagram Dimensions ................................................... 24
Table 4.3. QFN-32 Package Dimensions ................................................................ 25
Table 4.4. QFN-32 Landing Diagram Dimensions ................................................... 26
Table 4.5. QFN-24 Package Dimensions ................................................................ 27
Table 4.6. QFN-24 Landing Diagram Dimensions ................................................... 28
Table 6.1. Absolute Maximum Ratings .................................................................... 47
Table 6.2. Global Electrical Characteristics ............................................................. 48
Table 6.3. Port I/O DC Electrical Characteristics ..................................................... 51
Table 6.4. Reset Electrical Characteristics .............................................................. 52
Table 6.5. Flash Electrical Characteristics .............................................................. 52
Table 6.6. Internal High-Frequency Oscillator Electrical Characteristics ................. 53
Table 6.7. Clock Multiplier Electrical Specifications ................................................ 54
Table 6.8. Voltage Regulator Electrical Characteristics .......................................... 54
Table 6.9. ADC0 Electrical Characteristics .............................................................. 55
Table 6.10. Temperature Sensor Electrical Characteristics .................................... 56
Table 6.11. Voltage Reference Electrical Characteristics ....................................... 56
Table 6.12. Comparator 0 and Comparator 1 Electrical Characteristics ................. 57
Table 10.1. CIP-51 Instruction Set Summary .......................................................... 77
Table 12.1. Special Function Register (SFR) Memory Map for
Pages 0x0 and 0xF ............................................................................. 100
Table 12.2. Special Function Registers ................................................................. 101
Table 13.1. Interrupt Summary .............................................................................. 107
Table 14.1. Flash Security Summary .................................................................... 120
Table 18.1. Port I/O Assignment for Analog Functions ......................................... 149
Table 18.2. Port I/O Assignment for Digital Functions ........................................... 149
Table 18.3. Port I/O Assignment for External Digital Event Capture Functions .... 150
Table 19.1. Baud Rate Calculation Variable Ranges ............................................ 171
Table 19.2. Manual Baud Rate Parameters Examples ......................................... 173
Table 19.3. Autobaud Parameters Examples ........................................................ 174
Table 19.4. LIN Registers* (Indirectly Addressable) .............................................. 179
Table 20.1. SMBus Clock Source Selection .......................................................... 191
Table 20.2. Minimum SDA Setup and Hold Times ................................................ 192
Table 20.3. Sources for Hardware Changes to SMB0CN ..................................... 196
Table 20.4. SMBus Status Decoding ..................................................................... 202
Table 21.1. Baud Rate Generator Settings for Standard Baud Rates ................... 206
Table 22.1. SPI Slave Timing Parameters ............................................................ 226
Table 24.1. PCA Timebase Input Options ............................................................. 250
Table 24.2. PCA0CPM and PCA0PWM Bit Settings for
PCA Capture/Compare Modules ........................................................ 253
Table 24.3. Watchdog Timer Timeout Intervals1 ................................................... 262
Rev. 1.1
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List of Registers
SFR Definition 5.4. ADC0CF: ADC0 Configuration ...................................................... 40
SFR Definition 5.5. ADC0H: ADC0 Data Word MSB .................................................... 41
SFR Definition 5.6. ADC0L: ADC0 Data Word LSB ...................................................... 41
SFR Definition 5.7. ADC0CN: ADC0 Control ................................................................ 42
SFR Definition 5.8. ADC0TK: ADC0 Tracking Mode Select ......................................... 43
SFR Definition 5.9. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 44
SFR Definition 5.10. ADC0GTL: ADC0 Greater-Than Data Low Byte .......................... 44
SFR Definition 5.11. ADC0LTH: ADC0 Less-Than Data High Byte .............................. 45
SFR Definition 5.12. ADC0LTL: ADC0 Less-Than Data Low Byte ............................... 45
SFR Definition 6.3. ADC0MX: ADC0 Channel Select ................................................... 59
SFR Definition 7.1. REF0CN: Reference Control ......................................................... 62
SFR Definition 8.1. CPT0CN: Comparator0 Control ..................................................... 65
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection ....................................... 66
SFR Definition 8.3. CPT1CN: Comparator1 Control ..................................................... 67
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection ....................................... 68
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection ........................................ 70
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection ........................................ 71
SFR Definition 9.1. REG0CN: Regulator Control .......................................................... 73
SFR Definition 10.1. DPL: Data Pointer Low Byte ........................................................ 81
SFR Definition 10.2. DPH: Data Pointer High Byte ....................................................... 81
SFR Definition 10.3. SP: Stack Pointer ......................................................................... 82
SFR Definition 10.4. ACC: Accumulator ....................................................................... 82
SFR Definition 10.5. B: B Register ................................................................................ 82
SFR Definition 10.6. PSW: Program Status Word ........................................................ 83
SFR Definition 10.7. SNn: Serial Number n .................................................................. 84
SFR Definition 11.1. EMI0CN: External Memory Interface Control .............................. 88
SFR Definition 12.1. SFR0CN: SFR Page Control ....................................................... 96
SFR Definition 12.2. SFRPAGE: SFR Page ................................................................. 97
SFR Definition 12.3. SFRNEXT: SFR Next .................................................................. 98
SFR Definition 12.4. SFRLAST: SFR Last .................................................................... 99
SFR Definition 13.1. IE: Interrupt Enable .................................................................... 109
SFR Definition 13.2. IP: Interrupt Priority .................................................................... 110
SFR Definition 13.3. EIE1: Extended Interrupt Enable 1 ............................................ 111
SFR Definition 13.4. EIP1: Extended Interrupt Priority 1 ............................................ 112
SFR Definition 13.5. EIE2: Extended Interrupt Enable 2 ............................................ 113
SFR Definition 13.6. EIP2: Extended Interrupt Priority Enabled 2 .............................. 114
SFR Definition 13.7. IT01CF: INT0/INT1 Configuration .............................................. 116
SFR Definition 14.1. PSCTL: Program Store R/W Control ......................................... 122
SFR Definition 14.2. FLKEY: Flash Lock and Key ...................................................... 123
SFR Definition 14.3. FLSCL: Flash Scale ................................................................... 124
SFR Definition 14.4. CCH0CN: Cache Control ........................................................... 125
SFR Definition 14.5. ONESHOT: Flash Oneshot Period ............................................ 125
SFR Definition 15.1. PCON: Power Control ................................................................ 128
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SFR Definition 16.1. VDM0CN: VDD Monitor Control ................................................ 132
SFR Definition 16.2. RSTSRC: Reset Source ............................................................ 134
SFR Definition 17.1. CLKSEL: Clock Select ............................................................... 136
SFR Definition 17.2. OSCICN: Internal Oscillator Control .......................................... 138
SFR Definition 17.3. OSCICRS: Internal Oscillator Coarse Calibration ...................... 139
SFR Definition 17.4. OSCIFIN: Internal Oscillator Fine Calibration ............................ 139
SFR Definition 17.5. CLKMUL: Clock Multiplier .......................................................... 141
SFR Definition 17.6. OSCXCN: External Oscillator Control ........................................ 143
SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0 .......................................... 154
SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1 .......................................... 155
SFR Definition 18.3. XBR2: Port I/O Crossbar Register 1 .......................................... 156
SFR Definition 18.4. P0MASK: Port 0 Mask Register ................................................. 157
SFR Definition 18.5. P0MAT: Port 0 Match Register .................................................. 157
SFR Definition 18.6. P1MASK: Port 1 Mask Register ................................................. 158
SFR Definition 18.7. P1MAT: Port 1 Match Register .................................................. 158
SFR Definition 18.8. P2MASK: Port 2 Mask Register ................................................. 159
SFR Definition 18.9. P2MAT: Port 2 Match Register .................................................. 159
SFR Definition 18.10. P3MASK: Port 3 Mask Register ............................................... 160
SFR Definition 18.11. P3MAT: Port 3 Match Register ................................................ 160
SFR Definition 18.12. P0: Port 0 ................................................................................. 161
SFR Definition 18.13. P0MDIN: Port 0 Input Mode ..................................................... 162
SFR Definition 18.14. P0MDOUT: Port 0 Output Mode .............................................. 162
SFR Definition 18.15. P0SKIP: Port 0 Skip ................................................................. 163
SFR Definition 18.16. P1: Port 1 ................................................................................. 163
SFR Definition 18.17. P1MDIN: Port 1 Input Mode ..................................................... 164
SFR Definition 18.18. P1MDOUT: Port 1 Output Mode .............................................. 164
SFR Definition 18.19. P1SKIP: Port 1 Skip ................................................................. 165
SFR Definition 18.20. P2: Port 2 ................................................................................. 165
SFR Definition 18.21. P2MDIN: Port 2 Input Mode ..................................................... 166
SFR Definition 18.22. P2MDOUT: Port 2 Output Mode .............................................. 166
SFR Definition 18.23. P2SKIP: Port 2 Skip ................................................................. 167
SFR Definition 18.24. P3: Port 3 ................................................................................. 167
SFR Definition 18.25. P3MDIN: Port 3 Input Mode ..................................................... 168
SFR Definition 18.26. P3MDOUT: Port 3 Output Mode .............................................. 168
SFR Definition 18.27. P3SKIP: Port 3Skip .................................................................. 169
SFR Definition 19.1. LIN0ADR: LIN0 Indirect Address Register ................................. 177
SFR Definition 19.2. LIN0DAT: LIN0 Indirect Data Register ....................................... 177
SFR Definition 19.3. LIN0CF: LIN0 Control Mode Register ........................................ 178
SFR Definition 20.1. SMB0CF: SMBus Clock/Configuration ...................................... 193
SFR Definition 20.2. SMB0CN: SMBus Control .......................................................... 195
SFR Definition 20.3. SMB0DAT: SMBus Data ............................................................ 197
SFR Definition 21.1. SCON0: Serial Port 0 Control .................................................... 210
SFR Definition 21.2. SMOD0: Serial Port 0 Control .................................................... 211
SFR Definition 21.3. SBUF0: Serial (UART0) Port Data Buffer .................................. 212
SFR Definition 21.4. SBCON0: UART0 Baud Rate Generator Control ...................... 212
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SFR Definition 21.6. SBRLL0: UART0 Baud Rate Generator Reload Low Byte ........ 213
SFR Definition 21.5. SBRLH0: UART0 Baud Rate Generator Reload High Byte ....... 213
SFR Definition 22.1. SPI0CFG: SPI0 Configuration ................................................... 221
SFR Definition 22.2. SPI0CN: SPI0 Control ............................................................... 222
SFR Definition 22.3. SPI0CKR: SPI0 Clock Rate ....................................................... 223
SFR Definition 22.4. SPI0DAT: SPI0 Data ................................................................. 223
SFR Definition 23.1. CKCON: Clock Control .............................................................. 228
SFR Definition 23.2. TCON: Timer Control ................................................................. 233
SFR Definition 23.3. TMOD: Timer Mode ................................................................... 234
SFR Definition 23.4. TL0: Timer 0 Low Byte ............................................................... 235
SFR Definition 23.5. TL1: Timer 1 Low Byte ............................................................... 235
SFR Definition 23.6. TH0: Timer 0 High Byte ............................................................. 236
SFR Definition 23.7. TH1: Timer 1 High Byte ............................................................. 236
SFR Definition 23.8. TMR2CN: Timer 2 Control ......................................................... 240
SFR Definition 23.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 241
SFR Definition 23.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 241
SFR Definition 23.11. TMR2L: Timer 2 Low Byte ....................................................... 242
SFR Definition 23.12. TMR2H Timer 2 High Byte ....................................................... 242
SFR Definition 23.13. TMR3CN: Timer 3 Control ....................................................... 246
SFR Definition 23.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 247
SFR Definition 23.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 247
SFR Definition 23.16. TMR3L: Timer 3 Low Byte ....................................................... 248
SFR Definition 23.17. TMR3H Timer 3 High Byte ....................................................... 248
SFR Definition 24.1. PCA0CN: PCA Control .............................................................. 263
SFR Definition 24.2. PCA0MD: PCA Mode ................................................................ 264
SFR Definition 24.3. PCA0PWM: PCA PWM Configuration ....................................... 265
SFR Definition 24.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 266
SFR Definition 24.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 267
SFR Definition 24.6. PCA0H: PCA Counter/Timer High Byte ..................................... 267
SFR Definition 24.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 268
SFR Definition 24.8. PCA0CPHn: PCA Capture Module High Byte ........................... 268
Rev. 1.1
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C8051F54x
1. System Overview
C8051F54x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are
listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
LIN 2.1 peripheral (fully backwards compatible, master and slave modes) (C8051F540/2/4/6)
True 12-bit 200 ksps 32-channel single-ended ADC with analog multiplexer
Precision programmable 24 MHz internal oscillator that is within ±0.5% across the temperature range
and for VDD voltages greater than or equal to the on-chip voltage regulator minimum output at the low
setting. The oscillator is within +1.0% for VDD voltages below this minimum output setting.
On-chip Clock Multiplier to reach up to 50 MHz
16 kB (C8051F540/1/2/3) or 8 kB (C8051F544/5/6/7) of on-chip Flash memory
1280 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer
function
On-chip Voltage Regulator
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
On-chip Voltage Comparator
25 or 18 Port I/O (5 V push-pull)
With on-chip Voltage Regulator, Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the
C8051F54x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be repro-
grammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051
firmware. User software has complete control of all peripherals, and may individually shut down any or all
peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins.
The devices are specified for 1.8 V to 5.25 V operation over the automotive temperature range (–40 to
+125 °C). The C8051F540/1/4/5 devices are available in 32-pin QFP and QFN packages and the
C8051F542/3/6/7 devices are available in 32-pin QFN packages. All package options are lead-free and
RoHS compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 and
Figure 1.2.
Rev. 1.1
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C8051F54x
C2CK/RST
VREGIN
VDD
GND
VDDA
GNDA
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
CIP-51 8051 Controller
Core (50 MHz)
16 kB Flash Program
Memory
256 Byte RAM
1 kB XRAM
Voltage Regulator
(LDO)
System Clock Setup
XTAL1 XTAL2
Internal Oscillator
(±0.5%)
External Oscillator
Clock Multiplier
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
SPI
I2C
Priority
Crossbar
Decoder
Crossbar Control
Analog Peripherals
Voltage
Reference VREF
VDD
VREF
12-bit
200ksps
ADC
A
M
U
X
VDD
VREF
P0 – P3
Temp
Sensor
GND
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Driver
CP0, CP0A +
Comparator 0 -
CP1, CP1A +
-
Comparator 1
Figure 1.1. C8051F540/1/4/5 Block Diagram
VIO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
14 Rev. 1.1


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C8051F54x
C2CK/RST
VREGIN
VDD
GND
GNDA
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
CIP-51 8051 Controller
Core (50 MHz)
16 kB Flash Program
Memory
256 Byte RAM
1 kB XRAM
Voltage Regulator
(LDO)
System Clock Setup
XTAL1 XTAL2
Internal Oscillator
(±0.5%)
External Oscillator
Clock Multiplier
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
SPI
I2C
Priority
Crossbar
Decoder
Crossbar Control
Analog Peripherals
Voltage
Reference VREF
VDD
VREF
12-bit
200ksps
ADC
A
M
U
X
VDD
VREF
P0 – P2
Temp
Sensor
GND
CP0, CP0A +
Comparator 0 -
CP1, CP1A +
Comparator 1 -
Figure 1.2. C8051F542/3/6/7 Block Diagram
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
VIO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1/C2D
Rev. 1.1
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C8051F54x
2. Ordering Information
The following features are common to all devices in this family:
50 MHz system clock and 50 MIPS throughput (peak)
1280 bytes of RAM (256 internal bytes and 1024 XRAM bytes)
Internal 24 MHz oscillator
SMBus / I2C, Enhanced SPI, Enhanced UART
Four Timers
Six Programmable Counter Array channels
Internal Voltage Regulator
12-bit, 200 ksps ADC, Internal Voltage Reference and Temperature Sensor
Two Analog Comparators
Table 2.1 shows the features that differentiate the devices in this family.
Rev. 1.1
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C8051F54x
Table 2.1. Product Selection Guide
C8051F540-IQ
C8051F540-IM
C8051F541-IQ
C8051F541-IM
C8051F542-IM
C8051F543-IM
C8051F544-IQ
C8051F544-IM
C8051F545-IQ
C8051F545-IM
C8051F546-IM
C8051F547-IM
16 25 QFP32
16 25 QFN32
16 — 25 QFP32
16 — 25 QFN32
16 18 QFN24
16 — 18 QFN24
8 25 QFP32
8 25 QFN32
8 25 QFP32
8 — 25 QFN32
8 18 QFN24
8 18 QFN24
Note: The suffix of the part number indicates the device rating and the package. All devices are RoHS compliant.
All of these devices are also available in an automotive version. For the automotive version, the -I in the
ordering part number is replaced with -A. For example, the automotive version of the C8051F540-IM is the
C8051F540-AM.
The -AM and -AQ devices receive full automotive quality production status, including AEC-Q100 qualifica-
tion, registration with International Material Data System (IMDS) and Part Production Approval Process
(PPAP) documentation. PPAP documentation is available at www.silabs.com with a registered and NDA
approved user account. The -AM and -AQ devices enable high volume automotive OEM applications with
their enhanced testing and processing. Please contact Silicon Labs sales for more information regarding
–AM and -AQ devices for your automotive project.
17 Rev. 1.1


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C8051F54x
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F54x
Name
Pin
Pin
‘F540/1/4/5 ‘F542/3/6/7
Type
Description
VDD
GND
VDDA
(32-pin)
4
6
5
GNDA
VREGIN
VIO
RST/
7
3
2
10
C2CK
P2.1/
(24-pin)
3 Digital Supply Voltage. Must be connected.
4 Digital Ground. Must be connected.
— Analog Supply Voltage. Must be connected. Connected
internally to VDD on the 24-pin packages.
5 Analog Ground. Must be connected.
2 Voltage Regulator Input
1 Port I/O Supply Voltage. Must be connected.
8 D I/O Device Reset. Open-drain output of internal POR or
VDD Monitor.
D I/O Clock signal for the C2 Debug Interface.
7 D I/O or A In Port 2.1. See SFR Definition 18.20 for a description.
C2D
P3.0/
9
D I/O Bi-directional data signal for the C2 Debug Interface.
— D I/O or A In Port 3.0. See SFR Definition 18.24 for a description.
C2D
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
8
1
32
31
30
29
28
27
26
25
24
D I/O Bi-directional data signal for the C2 Debug Interface.
6 D I/O or A In Port 0.0. See SFR Definition 18.12 for a description.
24 D I/O or A In Port 0.1
23 D I/O or A In Port 0.2
22 D I/O or A In Port 0.3
21 D I/O or A In Port 0.4
20 D I/O or A In Port 0.5
19 D I/O or A In Port 0.6
18 D I/O or A In Port 0.7
17 D I/O or A In Port 1.0. See SFR Definition 18.16 for a description.
16 D I/O or A In Port 1.1.
15 D I/O or A In Port 1.2.
Rev. 1.1
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C8051F54x
Table 3.1. Pin Definitions for the C8051F54x (Continued)
Name
Pin
Pin
‘F540/1/4/5 ‘F542/3/6/7
Type
Description
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
(32-pin)
23
22
21
20
19
18
17
16
15
14
13
12
11
(24-pin)
14 D I/O or A In Port 1.3.
13 D I/O or A In Port 1.4.
12 D I/O or A In Port 1.5.
11 D I/O or A In Port 1.6.
10 D I/O or A In Port 1.7.
9 D I/O or A In Port 2.0. See SFR Definition 18.20 for a description.
— D I/O or A In Port 2.1.
— D I/O or A In Port 2.2.
— D I/O or A In Port 2.3.
— D I/O or A In Port 2.4.
— D I/O or A In Port 2.5.
— D I/O or A In Port 2.6.
— D I/O or A In Port 2.7.
19 Rev. 1.1


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C8051F54x
P0.1 / CNVSTR 1
VIO 2
VREGIN 3
VDD 4
VDDA 5
GND 6
GNDA 7
P0.0 / VREF 8
C8051F540-IQ
C8051F541-IQ
C8051F544-IQ
C8051F545-IQ
Top View
24 P1.2
23 P1.3
22 P1.4
21 P1.5
20 P1.6
19 P1.7
18 P2.0
17 P2.1
Figure 3.1. QFP-32 Pinout Diagram (Top View)
Rev. 1.1
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C8051F54x
P0.1 / CNVSTR
VIO
VREGIN
VDD
VDDA
GND
GNDA
P0.0 / VREF
1
2
3
4
5
6
7
8
C8051F540-IM
C8051F541-IM
C8051F544-IM
C8051F545-IM
Top View
GND
24 P1.2
23 P1.3
22 P1.4
21 P1.5
20 P1.6
19 P1.7
18 P2.0
17 P2.1
Figure 3.2. QFN-32 Pinout Diagram (Top View)
21 Rev. 1.1


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C8051F54x
VIO 1
VREGIN 2
VDD 3
GND 4
GNDA 5
P0.0/VREF 6
C8051F542-IM
C8051F543-IM
C8051F546-IM
C8051F547-IM
Top View
GND
18 P0.7/CAN0 RX
17 P1.0
16 P1.1
15 P1.2
14 P1.3
13 P1.4
Figure 3.3. QFN-24 Pinout Diagram (Top View)
Rev. 1.1
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4. Package Specifications
4.1. QFP-32 Package Specifications
C8051F54x
Figure 4.1. QFP-32 Package Drawing
Table 4.1. QFP-32 Package Dimensions
Dimension Min Typ Max
Dimension Min Typ Max
A — — 1.60
A1 0.05 — 0.15
A2 1.35 1.40 1.45
b 0.30 0.37 0.45
c 0.09 — 0.20
D 9.00 BSC.
D1 7.00 BSC.
e 0.80 BSC.
E 9.00 BSC.
E1 7.00 BSC.
L 0.45 0.60 0.75
aaa 0.20
bbb 0.20
ccc 0.10
ddd 0.20
θ 0° 3.5° 7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
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C8051F54x
Figure 4.2. QFP-32 Landing Diagram
Table 4.2. QFP-32 Landing Diagram Dimensions
Dimension
C1
Min
8.40
Max Dimension
8.50 X1
C2 8.40 8.50
Y1
E 0.80 BSC
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Min
0.40
1.25
Max
0.50
1.35
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
24 Rev. 1.1


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4.2. QFN-32 Package Specifications
C8051F54x
Figure 4.3. QFN-32 Package Drawing
Table 4.3. QFN-32 Package Dimensions
Dimension Min Typ Max
Dimension Min Typ Max
A 0.80 0.9 1.00
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 5.00 BSC.
D2 3.20 3.30 3.40
e 0.50 BSC.
E 5.00 BSC.
E2 3.20 3.30 3.40
L 0.30 0.40 0.50
L1 0.00 — 0.15
aaa — — 0.15
bbb — — 0.15
ddd — — 0.05
eee — — 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
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C8051F54x
Figure 4.4. QFN-32 Landing Diagram
Table 4.4. QFN-32 Landing Diagram Dimensions
Dimension
C1
C2
e
X1
Min Max
4.80 4.90
4.80 4.90
0.50 BSC
0.20 0.30
Dimension
X2
Y1
Y2
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Min
3.20
0.75
3.20
Max
3.40
0.85
3.40
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 3x3 array of 1.0 mm openings on a 1.20 mm pitch should be used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
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4.3. QFN-24 Package Specifications
C8051F54x
Figure 4.5. QFN-24 Package Drawing
Table 4.5. QFN-24 Package Dimensions
Dimension Min Typ Max
Dimension Min Typ Max
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 4.00 BSC
D2 2.55 2.70 2.80
e 0.50 BSC
E 4.00 BSC
E2 2.55 2.70 2.80
L 0.30 0.40 0.50
L1 0.00
0.15
aaa 0.15
bbb 0.10
ddd 0.05
eee 0.08
Z 0.24
Y 0.18
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD, except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
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C8051F54x
Figure 4.6. QFN-24 Landing Diagram
Table 4.6. QFN-24 Landing Diagram Dimensions
Dimension
Min
Max Dimension
C1 3.90 4.00
C2 3.90 4.00
X2
Y1
E 0.50 BSC Y2
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Min
2.70
0.65
2.70
Max
2.80
0.75
2.80
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center ground
pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
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C8051F54x
5. 12-Bit ADC (ADC0)
The ADC0 on the C8051F54x consists of an analog multiplexer (AMUX0) with 25/18 total input selections
and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, pro-
grammable window detector, programmable attenuation (1:2), and hardware accumulator. The ADC0 sub-
system has a special Burst Mode which can automatically enable ADC0, capture and accumulate
samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0, data
conversion modes, and window detector are all configurable under software control via the Special Func-
tion Registers shows in Figure 5.1. ADC0 inputs are single-ended and may be configured to measure
P0.0-P3.7, the Temperature Sensor output, VDD, or GND with respect to GND. The voltage reference for
ADC0 is selected as described in Section “6.2. Temperature Sensor” on page 60. ADC0 is enabled when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
ADC0MX
ADC0TK
ADC0CN
P2.2-P2.7, P3.0 available
on 32-pin packages
P0.0
P0.7
P1.0
P1.7
P2.0
28-to-1
AMUX0
Start
Conversion
SYSCLK
Burst Mode
Logic
Burst Mode
Oscillator
25 MHz Max
Selectable
Gain
P2.7
P3.0
VDD
Temp Sensor
GND
ADC0GNH ADC0GNL ADC0GNA
VDD
12-Bit
SAR
ADC
Start
Conversion
00
01
10
11
AD0BUSY (W)
Timer 1 Overflow
CNVSTR Input
Timer 2 Overflow
Accumulator
ADC0LTH ADC0LTL
AD0WINT
Window
Compare
32 Logic
ADC0CF
ADC0GTH ADC0GTL
Figure 5.1. ADC0 Functional Block Diagram
Rev. 1.1
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C8051F54x
5.1. Modes of Operation
In a typical system, ADC0 is configured using the following steps:
1. If a gain adjustment is required, refer to Section “5.3. Selectable Gain” on page 35.
2. Choose the start of conversion source.
3. Choose Normal Mode or Burst Mode operation.
4. If Burst Mode, choose the ADC0 Idle Power State and set the Power-Up Time.
5. Choose the tracking mode. Note that Pre-Tracking Mode can only be used with Normal Mode.
6. Calculate the required settling time and set the post convert-start tracking time using the AD0TK bits.
7. Choose the repeat count.
8. Choose the output word justification (Right-Justified or Left-Justified).
9. Enable or disable the End of Conversion and Window Comparator Interrupts.
5.1.1. Starting a Conversion
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM10) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
Writing a 1 to the AD0BUSY bit of register ADC0CN
A rising edge on the CNVSTR input signal (pin P0.1)
A Timer 1 overflow (i.e., timed continuous conversions)
A Timer 2 overflow (i.e., timed continuous conversions)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand.” During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 overflows are used as the conversion source, Low Byte overflows are
used if Timer2 is in 8-bit mode; High byte overflows are used if Timer 2 is in 16-bit mode. See Section
“23. Timers” on page 227 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.1. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.1 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.1, set to 1 Bit1 in register P0SKIP. See Section “18. Port
Input/Output” on page 147 for details on Port I/O configuration.
5.1.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accu-
rate. ADC0 has three tracking modes: Pre-Tracking, Post-Tracking, and Dual-Tracking. Pre-Tracking Mode
provides the minimum delay between the convert start signal and end of conversion by tracking continu-
ously before the convert start signal. This mode requires software management in order to meet minimum
tracking requirements. In Post-Tracking Mode, a programmable tracking time starts after the convert start
signal and is managed by hardware. Dual-Tracking Mode maximizes tracking time by tracking before and
after the convert start signal. Figure 5.2 shows examples of the three tracking modes.
Pre-Tracking Mode is selected when AD0TM is set to 10b. Conversions are started immediately following
the convert start signal. ADC0 is tracking continuously when not performing a conversion. Software must
allow at least the minimum tracking time between each end of conversion and the next convert start signal.
The minimum tracking time must also be met prior to the first convert start signal after ADC0 is enabled.
30 Rev. 1.1




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