CDM5364A (GE)
CMOS 8192-Word by 8-Bit LSI Static ROMS

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Read-Only Memories (ROMs)
CDM5364, CDM5364A
A7 24 Voo
A6 23 A8
A5 3
22 A9
A4 4
21 AI2
A3 20 CEtCE
A2 6
19 AID
AI 7
AD 8
18 All
17 C7
QO 9
16 Q6
QI 10
Q2 II
15 Q5
14 Q4
Vss 12
13 Q3
92CS - 33698
CDM5364
TERMINAL ASSIGNMENT
CMOS 8192-Word by 8-Bit
LSI Static ROMS
Features:
• Asynchronous operation
• Fast access time - 250 ns max.
• Low standby and operating power:
ISBY2 = 2 p.A typical (CDM5364)
loos = 2 p.A typical (CDM5364A)
IOPER2 = 10 mA max. at teye = 1 p.s
= 30 mA max. at teye = 250 ns
• Automatic power down
• TTL input and output compatible
• 24-pin JEDEC standard pin out:
Pin compatible with Motorola
MCM68764 and MCM68766
EPROMs
• Choice of pin 20 function:
Mask-programmable CE
(CDM5364)
Mask-programmable CS
(CDM5364A)
The RCA CDM5364 and CDM5364A are 65,536-bit mask-
programmable CMOS Read Only Memories organized as
8192 eight-bit words. They are characterized by fast access
time and low-power dissipation, and are designed to be
used with a wide variety of general purpose microprocessor
systems, including RCA-CDP1800-and CDP6805-series
systems. The CDM5364 and CDM5364A differ in the function
for pin 20.
The CDM5364 provides a chip enable input at pin 20, which
gates the address buffers and output drivers, providing a
low power standby mode.
The CDM5364A has a chip select input at pin 20. As a chip
select input, pin 20 controls only the output drivers providing
fast output enable time. The polarities of the chip enable
and the chip select inputs are user mask-programmable.
Both the CDM5364 and CDM5364A provide automatic
power-down and data hold while the address inputs are
stable.
The CDM5364 and CDM5364A are supplied in 24-lead
hermetic, dual-in-line side-brazed ceramic packages (0
suffix), and in 24-lead du-al-ln-Iine plastic packages (E
suffix) .
A7 24 voo
A6 23 A8
A5 22 A9
A4 4
A3 5
21 AI2
20 CStCS
A2 6
19 AID
AI 18 All
AD 17 Q7
QO 9
16 Q6
QI 10
Q2 II
15 Q5
14 Q4
Vss 12
13 Q3
TOP VIEW
92CS ~ 36697
CDM5364A
TERMINAL ASSIGNMENT
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to V•• terminal) ..................................................................•• -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ...........•..•........••.•...•....•.••..•.........•••••..........•. ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +eO°C (PACKAGE TYPE E) .............................................................. 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) .................................. Derate Linearly at 8 mW/oC to 300 mW
=For T. -55 to +100°C (PACKAGE TYPE D) ............................................................. 500 mW
ForT. = +100 to 125°C (PACKAGE TYPE D) .......•...........••••.••...... Derate Linearly at 8 mWrC to 300 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ••.•.......••.••••••......•••••••.•• 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE 0 .••.•.•..•...........................•.......••...•...........•••••••.......... -55 to +125°C
PACKAGE TYPE E .••..........••............••.•.•..........••...•.•.....•••.••.••........••••.•• -40 to +85°C
STORAGE-TEMPERATURE RANGE (T...) ............................................................. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 in. (1.59 ± 0.79 mm) from case for 10 s maximum ..............•..............•.•.... +265°C
File Number 1467
____________________________________________________________ 709


CDM5364A (GE)
CMOS 8192-Word by 8-Bit LSI Static ROMS

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Read-Only Memories (ROMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDM5364, CDM5364A
=RECOMMENDED OPERATl-NG CONDITIONS at TA ·40 to +85·C
For maximum reliability, nominal operating conditions should be selected 10 that operation II alwaYI within the
following rangel:
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
LIMITS
CDM5364, CDM5384A
Min.
Max.
46
Vss voo
UNITS
V
AI2----j
I
I
I
I
I
I
I
A3 --f-....,
A2 --1--1
AI --f--I
.Ia.n:.
o".c..
C
...In
In
8
""
AO-~--'-~~~-l--l--l-+-____~
65,~36 BIT
ROM
CELL ARRAY
IAI
r+voDD'
II
CS~IBI
isD~U6!1\....!
IAI
*CE
I BI
CDM~364
* CEICDM5364)AND CSICDM5364A)
ARE ",ASK'PROGRAMMABLE AS:
~~~\¥\A~kGH OR ACTIVE-LOW OR
ACTIVITY
DETECTOR
IAUTO POWER)
DOWN
00 01
02 03
Fig. 1 - Functional block diagram.
04 05
06
92CM-!6702
07
710 ______________________________________________________________


CDM5364A (GE)
CMOS 8192-Word by 8-Bit LSI Static ROMS

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Read-Only Memories (ROMs)
CDM5364, CDM5364A
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo = 5 V ± 10%, Except as noted
CHARACTERISTIC
CONDITIONS
LIMITS
CDM5364
- UNITS
Min. Typ. Max.
Average Operating DeVice Currenta
DC Active DeVice Currentb
Standby DeVice CurrentC
Output Voltage Low-Level
Output Voltaqe Hloh-Level
Input Low Voltaoe
Input Hlqh Voltaoe
InQut Leakage Current (Any Input)
3-State Ouw_ut Leakage Current
InQut Capacitance
Output Capacitance
IOPERl d
IOPER2 e
IACTld
IACT2e
ISBYl d
ISBY2e
VOL
VOH
VIL
VIH
liN
lOUT
CIN
COUT
VIN = VIL. VIH, CE = VIH, (CE = VIL)
teye = 1 J1S
teye = 250 ns
VIN = 0 2 V, Vaa -0 2 V, CE = Vaa -0 2 V,
(CE = 0.2 V)
teye = 1 /1S
teye = 250 ns
VIN = VIL, VIH, CE = VIH, tCE = VIL)
VIN = 0 2 V, Vaa -0 2 V,
CE = Vaa -0 2 V, fCE = 0 2 V)
VIN = VIL, VIH, CE = VIL, (CE = VIH)
VIN = 0 2 V, VaD -0.2V, CE = 0 2 V,
fCE = Vaa -0 2 V)
IOL = 3 2 mA
IOH = -3 2 mA
-
-
VSS < VIN :S Vaa
VSS :S VOUT :S Vaa
1=1 MHz, TA = 25°C
1= 1 MHz, TA=25°C
--
--
--
--
--
--
--
-2
--
2.4 -
--
22 -
--
--
-5
-6
15
35
10
30
15
50
15
50
04
-
08
-
±1
±1
10
12
mA
mA
pA
mA
pA
V
pA
pF
-TYPical values are lor TA = 25° C and nominal Vaa
aAddresslnputs toggling, chip enabled outputs open circuit.
blnputs stable, chip enabled, outputs open circuit
clndependent 01 address Input activity, chip disabled
dTTL Inputs
eCMOS Inputs
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85° C, Voo = 5 V ± 10%,
Input tr, II = 10 ns; CL = 100 pF, and 1 TTL Load; Input Pulse Levels: 0.8 V to 2.2 V - See Fig. 2
CHARACTERISTIC
LIMITS
CDM5364
Min. Max.
UNITS
Address Access Time
Chip Enable to Output Active
Chip Enable Access
Data Hold after Address
Chip Disable to Output High Z
Cycle Time
tAVQV
tEVQX
tEVQV
tAXQX
tEXQZ
tCYC
-
0
-
10
-
250
250
-
250
-
90
-
ns
AO-AI2
CE/eE
NOTES:
(1) Assumes tEVQV is satisfied.
(2) Output Active requires Chip Enable Active.
(3) Assumes tAVQV Is satisfied.
(4) Invalid Chip Enable causes Output High Z.
(5) Generates 10-ns Valid Output Pulses
(I.e., tCYC-tAVQV+tAXQX)'
NOTE TIMING MEASUREMENT REFERENCE LEVEL [S [.5 V
92CM-36699
Fig. 2 - Timing waveforms
_________________________________________________________________ 711


CDM5364A (GE)
CMOS 8192-Word by 8-Bit LSI Static ROMS

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Read-Only Memories (ROMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDM5364, CDM5364A
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +850 C, VDD = 5 V ± 10%, Except as noted
CHARACTERISTIC
Average Operating Device Currenta
DC Active Device Currentb
Quiescent Device CurrentC
Output Voltage Low-Level
Output VoltaQe HiQh-Level
Input Low VoltaQe
Input Hiqh Voltage
Inout Leakaqe Current (Anv Input)
3-State Output Leakage Current
Input Capacitance
Output Capacitance
IOPERl d
IOPER2 e
IACTl d
IACT2e
lOOSe
VOL
VOH
Vil
VIH
liN
lOUT
CIN
COUT
CONDITIONS
VIN = Vll, VIH; CS = VIH; (~= VIL)
teye=1/./S
teye = 250 ns
VIN = 0.2 V, Voo -0.2 V; CS = Voo -0.2 V;
(CS = 0.2 V)
teye=1/./S
teye = 250 ns
VIN = Vll, VIH; CS = VIH; (CS = VIL)
VIN = 0.2 V, Voo -0.2 V;
CS = Voo -0.2 V; (CS = 0.2 V)
VIN = 0.2 V, Voo -0.2V; CS = 0.2 V;
(CS = voo -0 2 V)
IOl = 3.2 mA
IOH = -3 2 mA
-
-
VSS < VIN < Voo
vss < VOUT < Voo
1= 1 MHz, TA = 250 C
1= 1 MHz, TA = 25' C
LIMITS
CDM5384A
UNITS
-Min. Typ. Max.
- - 15
- - 35
- - 10
- - 30
- - 15
- - 50
- 2 50
--
-2.4
--
0.4
-
0.8
2.2 - -
- - ±1
- - ±1
- 5 10
- 6 12
mA
mA
J-IA
J-IA
V
J-IA
pF
-Typical values are lor TA = 25°C and nominal Voo.
a Address inputs toggling, chip selected outputs open circuit.
blnputs stable, chip selected outputs open CirCUit
clnputs stable, chip deselected.
dTTL inputs.
eCMOS inputs.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +850 C, VDD = 5 V ± 10%,
Input I., tf = 10 ns; Cl = 100 pF, and 1 TTL Load; Input Pulse Levels: 0.8 V to 2.2 V - See Fig. 3
CHARACTERISTIC
e----'
Add ress Access Ti me
Chip Select to Output Active
Chip Select to Output Valid
Data Hold after Address
Chip Deselect to Output High Z
Cycle Time
I
ICYCI_5 _1 ---t--l
tAVQV
tSVQX
tSVQV
tAXQX
tSXQZ
tCYC
LIMITS
CDM5384A
Min. Max.
- 250
0-
- 90
10 -
- 70
250 -
UNITS
ns
----~
AO-At2
estcs
r--------
NOTES:
(1) Assume. tSVQV I. satllfled.
(2) Output Active requires Chip, Select Active.
(3) Assumes tAVQV Is satllfled.
(4) Invalid Chip Select causes Output High Z.
(5) Generates 10-ns Valid Output Pul...
(I.e., tCYC-tAVQV+tAJ(QX)'
tsvax (2)
DATAOUT--------~--~~~?K=====t~~~
t $XQZ (4)
NOTE: TIMING MEASUREMENT REFERENCE LEV£L IS 1.5 V
92CM-36700
Fig 3 - Tlmmg waveforms
712 _________________________________________________________________


CDM5364A (GE)
CMOS 8192-Word by 8-Bit LSI Static ROMS

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Read-Only Memories (ROMs)
CDM5364, CDM5364A
APPLICATION INFORMATION
CS3
C"S2
~
r-------------------1-~am
CDPI883
LATCH I
DECODER
ROM
CDM5364
RAM
CPU
COPISOO
SERIES
8- BIT BIDIRECTIONAL DATA BUS
92CM-36701
Fig. 4 - Typical CDP1800 series microprocessor system.
Oecoupllng Capacitors
The CDM5364 and CDM5364A operate with a low average
dc power supply current that varies with cycle time.
However, the CDM5364 and CDM5364A are large ROMs
with many internal nodes. Precharging of selected nodes
during portions of the memory cycle results in short
duration peak currents that can be much higher than the
average dc value. The rise and fall times of the peak current
pulses can have a value sufficient to generate unwanted
system noise components. To minimize or eliminate the
effects of the current spikes, a 0.1 IlF ceramic decoupling
capacitor is recommended between the Voo and Vss pins of
every ROM device.
_______________________________________________________________ 713




CDM5364A.pdf
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