AD5750-1 (Analog Devices)
Industrial Current/Voltage Output Driver

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Data Sheet
Industrial Current/Voltage Output Driver
with Programmable Ranges
AD5750/AD5750-1/AD5750-2
FEATURES
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA
to 24 mA, ±20 mA, and ±24 mA
±0.03% full-scale range (FSR) total unadjusted error (TUE)
±5 ppm/°C typical output drift
Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V
with 20% overrange
±0.02% FSR TUE
±3 ppm/°C typical output drift
Flexible serial digital interface
On-chip output fault detection
Packet error checking (PEC)
Asynchronous CLEAR function
Flexible power-up condition to 0 V or tristate
Power supply range
AVDD: +12 V (± 10%) to +24 V (± 10%)
AVSS: −12 V (± 10%) to −24 V (± 10%)
Output loop compliance to AVDD − 2.75 V
Temperature range: −40°C to +105°C
32-lead, 5 mm × 5 mm LFCSP package
APPLICATIONS
Process controls
Actuator controls
PLCs
GENERAL DESCRIPTION
The AD5750/AD5750-1/AD5750-2 are single-channel, low cost,
precision voltage/current output drivers with hardware- or
software-programmable output ranges. The software ranges are
configured via an SPI-/MICROWIRE™-compatible serial interface.
The AD5750/AD5750-1/AD5750-2 target applications in PLC
and industrial process control. The analog input to the AD5750/
AD5750-1/AD5750-2 is provided from a low voltage, single-supply
digital-to-analog converter (DAC) and is internally conditioned
to provide the desired output current/voltage range. Analog input
ranges available are 0 V to 2.5 V (AD5750-1/AD5750-2) or 0 V
to 4.096 V (AD5750).
The output current range is programmable across five current
ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA, ±20 mA,
and ±24 mA. An overrange of 2% is available on the unipolar
current ranges.
Voltage output is provided from a separate pin that can be
configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V
output ranges. An overrange of 20% is available on the voltage
ranges.
Analog outputs are short-circuit and open-circuit protected and
can drive capacitive loads of 1 µF and inductive loads of 0.1 H.
The devices are specified to operate with a power supply range
from ±12 V to ±24 V. Output loop compliance is 0 V to AVDD
2.75 V.
The flexible serial interface is SPI and MICROWIRE compatible
and can operate in 3-wire mode to minimize the digital isolation
required in isolated applications. The interface also features an
optional PEC feature using CRC-8 error checking, useful in
industrial environments where data communication corruption
can occur.
The devices also include a power-on-reset function, ensuring that
the devices power up in a known state (0 V or tristate), and an
asynchronous CLEAR pin that sets the outputs to a zero scale/mid-
scale voltage output or the low end of the selected current range.
The HW SELECT pin is used to configure the parts for hardware
or software mode on power-up.
Table 1. Related Devices
Part Number Description
AD5422
Single channel, 16-bit, serial input current
source and voltage output DAC
AD5751
Industrial I/V output driver, single supply, 55 V
maximum supply, programmable ranges
AD5420
Single channel, 16-bit, serial input, 4 mA to
20 mA current source DAC
Rev. F
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AD5750-1 (Analog Devices)
Industrial Current/Voltage Output Driver

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AD5750/AD5750-1/AD5750-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Voltage Output............................................................................ 13
Current Output ........................................................................... 17
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 23
Software Mode ............................................................................ 23
Current Output Architecture.................................................... 25
Driving Inductive Loads............................................................ 25
Power-On State of AD5750/AD5750-1/AD5750-2................... 25
Default Registers at Power-On ................................................. 26
Reset Function ............................................................................ 26
REVISION HISTORY
9/14—Rev. E to Rev. F
Changes to Accuracy, Internal RSET Parameter, Table 2............... 6
Changes to Table 4.......................................................................... 10
Changes to Figure 4........................................................................ 11
Changes to Figure 46...................................................................... 20
Changes to Asynchronous Clear (CLEAR) Section................... 29
Changes to Thermal Consideration Section............................... 31
Updated Outline Dimensions ....................................................... 33
Changes to Ordering Guide .......................................................... 33
6/12—Rev. D to Rev. E
Changes to Figure 3.......................................................................... 9
Changes to Status Bit Read Operation Section........................... 28
Updated Outline Dimensions ....................................................... 33
4/12—Rev. C to Rev. D
Added AD5750-2................................................................Universal
Changes to Table 2............................................................................ 4
Updated Outline Dimensions ....................................................... 33
Changes to Ordering Guide .......................................................... 33
Data Sheet
OUTEN........................................................................................ 26
Software Control ........................................................................ 26
Hardware Control ...................................................................... 28
Transfer Function....................................................................... 28
Detailed Description of Features.................................................. 29
Output Fault Alert—Software Mode ....................................... 29
Output Fault Alert—Hardware Mode ..................................... 29
Voltage Output Short-Circuit Protection................................ 29
Asynchronous Clear (CLEAR) ................................................. 29
External Current Setting Resistor ............................................ 30
Programmable Overrange Modes............................................ 30
Packet Error Checking............................................................... 30
Applications Information .............................................................. 31
Transient Voltage Protection .................................................... 31
Thermal Considerations............................................................ 31
Layout Guidelines....................................................................... 31
Galvanically Isolated Interface ................................................. 32
Microprocessor Interfacing....................................................... 32
Outline Dimensions ....................................................................... 33
Ordering Guide .......................................................................... 33
7/10—Rev. B to Rev. C
Added Leakage Current in Voltage Output Characteristics
Parameter (Table 2) ...........................................................................5
Added Leakage Current in Current Output Characteristics
Parameter (Table 2) ...........................................................................6
6/10—Rev. A to Rev. B
Changes to Table 1.............................................................................1
Changes to Table 2, Power Requirements ......................................7
8/09—Rev. 0 to Rev. A
Added AD5750-1................................................................Universal
Changes to Features and General Description Sections ..............1
Changes to Table 2.............................................................................4
Changes to Theory of Operation Section and Figure 51 .......... 23
Change to Figure 52 and Table 6 Title ......................................... 24
Changes to Current Output Architecture Section and Power-On
State of AD5750/AD5750-1 .......................................................... 25
Changes to Transfer Function Section ........................................ 28
Changes to Programmable Overrange Modes Section ............. 30
Changes to Ordering Guide .......................................................... 33
7/09—Revision 0: Initial Version
Rev. F | Page 2 of 36


AD5750-1 (Analog Devices)
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Data Sheet
AD5750/AD5750-1/AD5750-2
FUNCTIONAL BLOCK DIAGRAM
DVCC GND AVDD GND COMP1 COMP2
CLEAR
CLRSEL
SCLK/OUTEN*
SDIN/R0*
SYNC/RSET*
SDO/VFAULT *
HW SELECT
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
STATUS
REGISTER
AD5750/AD5750-1/AD5750-2
VSENSE+
VOUT RANGE
SCALING
VOUT
SHORT FAULT
VOUT
VSENSE–
VIN
VREF
R2
VDD
R3
RESET
IOUT RANGE
SCALING
RSET
Vx**
REXT1
REXT2
IOUT
FAULT/ TEMP*
NC/IFAULT *
OVERTEMP
VOUT SHORT FAULT
IOUT OPEN FAULT
POWER-
ON RESET
VSS
IOUT
OPEN FAULT
AD2/R1* AD1/R2* AD0/R3*
AVSS
* DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT, HARDWARE MODE
DENOTED BY ITALIC TEXT. FOR EXAMPLE, FOR FAULT/ TEMP PIN, IN SOFTWARE MODE, THIS
PIN TAKES ON FAULT FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ON TEMP FUNCTION.
** Vx IS AN INTERNAL BIAS VOLTAGE (CAN BE GROUND OR OTHER VOLTAGE) THAT IS USED
TO GENERATE THE INTERNAL SENSE CURRENTS NEEDED FOR THE CURRENT OUTPUTS.
Figure 1.
Rev. F | Page 3 of 36


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AD5750/AD5750-1/AD5750-2
Data Sheet
SPECIFICATIONS
AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter1
INPUT VOLTAGE RANGE
Input Leakage Current
REFERENCE INPUT
Reference Input Voltage
Min
−1
Input Leakage Current
VOLTAGE OUTPUT
Output Voltage Ranges
Output Voltage Overranges
−1
0
0
−5
−10
0
Accuracy
Total Unadjusted Error (TUE)
B Version2
A Version2
Relative Accuracy (INL)
Bipolar Zero Error (Offset at Midscale)
Bipolar Zero Error Temperature
Coefficient3
Zero-Scale Error
0
−6
−12
−2.5
−0.1
−0.05
−0.3
−0.1
−0.02
−10
−8
−5
−4
−10
−8
−5
−4
Typ Max
0 to 4.096
0 to 2.5
+1
4.096
2.5
1.25
+1
5
10
+5
+10
6
12
+6
+12
+2.5
±0.02
±0.05
±0.005
±0.5
±0.3
±1.5
±0.5
±0.3
+0.1
+0.05
+0.3
+0.1
+0.02
+10
+8
+5
+4
+10
+8
+5
+4
Unit Test Conditions/Comments
Output unloaded
V AD5750
AD5750-1/AD5750-2
µA
V AD5750; external reference must
to be exactly as stated; otherwise,
accuracy errors show up as error
in output
V AD5750-2; external reference needs
to be exactly as stated; otherwise,
accuracy errors show up as error
in output
V AD5750-1; external reference needs
to be exactly as stated; otherwise,
accuracy errors show up as error
in output
µA
V
V AVDD needs to have minimum
1.3 V headroom or >11.3 V
V
V AVDD/AVSS needs to have minimum
1.3 V headroom or >±11.3 V
V Programmable overranges; see the
Detailed Description of Features
section
V
V
V
V
% FSR
% FSR
% FSR
% FSR
% FSR
mV
mV
mV
mV
ppm FSR/°C
TA = 25°C
TA = 25°C
±10 V range
TA = 25°C, ±10 V range
±5 V range
TA = 25°C, ± 5 V range
All bipolar ranges
mV ±10 V range
mV TA = 25°C, ±10 V range
mV ± 5 V range
mV TA = 25°C, ±5 V range
Rev. F | Page 4 of 36


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Data Sheet
Parameter1
Zero-Scale Error Temperature
Coefficient3
Zero-Scale/Offset Error
Offset Error Temperature Coefficient3
Gain Error
Min
−5
−4
−3
−2.2
−0.05
−0.07
−0.04
Gain Error Temperature Coefficient3
Full-Scale Error
−0.05
Full-Scale Error Temperature
Coefficient3
VOLTAGE OUTPUT CHARACTERISTICS3
Headroom
Short-Circuit Current
Load
Capacitive Load Stability
RLOAD = ∞
RLOAD = 2 kΩ
RLOAD = ∞
−0.04
−0.07
1
DC Output Impedance
Leakage Current
0 V to 5 V Range, ¼ to ¾ Step
0 V to 5 V Range, 40 mV Input Step
Slew Rate
Output Noise
Output Noise Spectral Density
AC PSRR
DC PSRR
CURRENT OUTPUT
Output Current Ranges
Output Current Overranges
−110
0
0
4
−20
−24
0
0
4
Typ
±1
±0.5
±0.3
±2
±0.015
±0.5
±0.015
±1.5
Max
+5
+4
+3
+2.2
+0.05
+0.07
+0.04
+0.05
+0.04
+0.07
1.3
15
1
1
2
0.12
+110
7
4.5
2
2.5
45.5
165
−65
10
24
20
20
+20
+24
24.5
20.4
20.4
AD5750/AD5750-1/AD5750-2
Unit Test Conditions/Comments
ppm FSR/°C All bipolar ranges
mV
mV
mV
mV
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR/°C
0 V to 10 V range
TA = 25°C, 0 V to 10 V range
0 V to 5 V range
TA = 25°C, 0 V to 5 V range
All unipolar ranges
All bipolar/unipolar ranges,
AD5750 and AD5750-1
AD5750-2
TA = 25°C, AD5750, AD5750-1, and
AD5750-2
All bipolar/unipolar ranges,
AD5750 and AD5750-1
TA = 25°C, AD5750 and AD5750-1
AD5750-2
V
mA
nF
nF
µF
Ω
nA
µs
µs
V/µs
µV rms
µV rms
nV/√Hz
dB
µV/V
mA
mA
mA
mA
mA
mA
mA
mA
Output unloaded
TA = 25°C
External compensation capacitor
required; see the Driving Inductive
Loads section
Output disabled; leakage to ground
Specified with 2 kΩ || 220 pF, ±0.05%
Specified with 2 kΩ || 220 pF, ±0.05%
Specified with 2 kΩ || 220 pF
0.1 Hz to 10 Hz bandwidth
100 kHz bandwidth
Measured at 10 kHz; specified with
2 kΩ || 220 pF
200 mV, 50 Hz/60 Hz sine wave super-
imposed on power supply voltage
Outputs unloaded
See the Detailed Description of
Features section
See the Detailed Description of
Features section
See the Detailed Description of
Features section
Rev. F | Page 5 of 36


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AD5750/AD5750-1/AD5750-2
Parameter1
ACCURACY, INTERNAL RSET
Total Unadjusted Error (TUE)
B Version2
A Version2
Relative Accuracy (INL)
Offset Error
Offset Error Temperature Coefficient3
Bipolar Zero Error
Bipolar Zero Temperature Coefficient3
Gain Error
Gain Temperature Coefficient3
Full-Scale Error
Full-Scale Temperature Coefficient3
ACCURACY, EXTERNAL RSET
Total Unadjusted Error (TUE)
B Version2
A Version2
Relative Accuracy (INL)
Offset Error
Min
−0.2
−0.1
−0.5
−0.3
−0.02
−0.03
−16
−10
−50
−26
−35
−24
−0.2
−0.25
−0.03
−0.2
−0.125
−0.1
−0.08
−0.3
−0.1
−0.02
−0.03
−14
−11
−20
Offset Error Temperature Coefficient3
Bipolar Zero Error
Bipolar Zero Temperature Coefficient3
Gain Error
Gain Temperature Coefficient
Full-Scale Error
Full-Scale Temperature Coefficient3
−32
−22
−0.08
−0.07
−0.1
−0.07
Typ Max
±0.03
±0.15
±0.01
±0.015
+5
+8
±3
+15
±0.5
±0.006
±8
±0.02
±4
+0.2
+0.1
+0.5
+0.3
+0.02
+0.03
+16
+10
+50
+26
+35
+24
+0.2
+0.25
+0.03
+0.2
+0.125
±0.03
±0.02
±0.01
±0.015
+5
+8
±2
+12
±0.5
±0.02
±1
±0.02
±2
+0.1
+0.08
+0.3
+0.1
+0.02
+0.03
+14
+11
+20
+15
+32
+22
+0.08
+0.07
+0.1
+0.07
Data Sheet
Unit Test Conditions/Comments
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
µA
µA
µA
µA
ppm FSR/°C
µA
µA
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
TA = 25°C
TA = 25°C
Unipolar ranges
Bipolar ranges
4 mA to 20 mA, 0 mA to 20 mA,
0 mA to 24 mA ranges
TA = 25°C
±20 mA, ±24 mA ranges
TA = 25°C
All ranges
±20 mA, ±24 mA ranges
TA = 25°C
4 mA to 20 mA, 0 mA to 20 mA,
0 mA to 24 mA ranges
±20 mA, ±24 mA ranges
TA = 25°C
All ranges
All ranges
TA = 25°C
All ranges
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
µA
µA
µA
µA
ppm FSR/°C
µA
µA
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
TA = 25°
TA = 25°C
4 mA to 20 mA, 0 mA to 20 mA,
0 mA to 24 mA ranges
±20 mA, ±24 mA ranges
4 mA to 20 mA, 0 mA to 20 mA,
0 mA to 24 mA ranges
TA = 25°C
±20 mA, ±24 mA ranges
TA = 25°C
All ranges
All ranges
TA = 25°C
All ranges
TA = 25°C
All ranges
All ranges
TA = 25°C
All ranges
Rev. F | Page 6 of 36


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Data Sheet
AD5750/AD5750-1/AD5750-2
Parameter1
CURRENT OUTPUT CHARACTERISTICS3
Current Loop Compliance Voltage
Resistive Load
Inductive Load
Min Typ Max Unit
0 AVDD − 2.75 V
See test conditions/comments column
See test conditions/comments column
Settling Time
4 mA to 20 mA, Full-Scale Step
4 mA to 20 mA, 120 µA Step
DC PSRR
Output Impedance
Leakage Current
VOUT/VSENSE− Error
−12
0.9994
8.5
1.2
130
1
+12
1.0006
µs
µs
µA/V
nA
Gain
DIGITAL INPUT
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current
Pin Capacitance
DIGITAL OUTPUTS3
FAULT, IFAULT, TEMP, VFAULT
Output Low Voltage, VOL
2
−1
Output High Voltage, VOH
SDO
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Output Capacitance
High Impedance Leakage Current
POWER REQUIREMENTS
AVDD
AVSS
DVCC
Input Voltage
AIDD
3.6
0.5
DVCC − 0.5
−1
12
−12
2.7
AISS
0.8
+1
5
0.4
0.6
0.5
DVCC − 0.5
3
+1
24
−24
5.5
4.4 5.6
5.2 6.2
5.2 6.2
2.0 2.5
V
V
µA
pF
V
V
V
V
V
pF
µA
V
V
V
mA
mA
mA
mA
DICC
Power Dissipation
2.0 3.5
2.5 3
2.5 3
0.3 1
108
mA
mA
mA
mA
mW
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 Specification includes gain and offset errors over temperature and drift after 1000 hours, TA = 125°C.
3 Guaranteed by characterization, but not production tested.
Test Conditions/Comments
Chosen such that compliance is
not exceeded
Needs appropriate capacitor at
higher inductance values; see the
Driving Inductive Loads section
250 Ω load
250 Ω load
Output disabled; leakage to ground
Error in VOUT voltage due to changes
in VSENSE−; specified as gain, for
example, if VSENSE− moves by 1 V,
VOUT moves by 0.9994 V
JEDEC compliant
Per pin
Per pin
10 kΩ pull-up resistor to DVCC
At 2.5 mA
10 kΩ pull-up resistor to DVCC
Sinking 200 µA
Sourcing 200 µA
±10%
±10%
Output unloaded, output disabled,
R3, R2, R1, R0 = 0, 1, 0, 1; RSET = 0
Current output enabled
Voltage output enabled
Output unloaded, output disabled,
R3, R2, R1, R0 = 0, 1, 0, 1; RSET = 0,
AD5750 and AD5750-1
AD5750-2
Current output enabled
Voltage output enabled
VIH = DVCC, VIL = GND
AVDD/AVSS = ±24 V, outputs unloaded
Rev. F | Page 7 of 36


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AD5750/AD5750-1/AD5750-2
Data Sheet
TIMING CHARACTERISTICS
AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ, CL = 200 pF, IOUT: RLOAD =
300 Ω. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
t1
t2
t3
t4
t5
t6
t7
t8
t9, t10
t11
t12
t13
Limit at TMIN, TMAX
20
8
8
5
10
5
5
5
1.5
5
40
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs max
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC)
Minimum SYNC high time (write mode)
Data setup time
Data hold time
CLEAR pulse low/high activation time
Minimum SYNC high time (read mode)
SCLK rising edge to SDO valid (SDO CL = 15 pF)
RESET pulse low time
1 Guaranteed by characterization, but not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
Rev. F | Page 8 of 36


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Data Sheet
Timing Diagrams
SCLK
SYNC
SDIN
1
t6
t4
2
t7
D15
t3
t8
t1
t2
16
t5
D0
AD5750/AD5750-1/AD5750-2
CLEAR
VOUT
t10
t9
RESET
SCLK
SYNC
SDIN
SDO
t11
t13
Figure 2. Write Mode Timing Diagram
A2 A1
A0 R = 1 0
R3 R2
R1
R0 CLRSEL OUTEN CLEAR RSET RESET
0
0
t12
X
X
X
X
X
R3
R2
R1
R0
CLRSEL OUTEN
RSET
PEC
ERROR
OVER
TEMP
IOUT VOUT
FAULT FAULT
Figure 3. Readback Mode Timing Diagram
Rev. F | Page 9 of 36


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AD5750/AD5750-1/AD5750-2
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter
Rating
AVDD to GND
AVSS to GND
AVDD to AVSS
DVCC to GND
VSENSE+ to GND
VSENSE− to GND
Digital Inputs to GND
−0.3 V to +30 V
+0.3 V to −28 V
−0.3 V to +58 V
−0.3 V to +7 V
AVSS to AVDD
±5.0 V
−0.3 V to DVCC + 0.3 V or
+7 V (whichever is less)
Digital Outputs to GND
VREF to GND
−0.3 V to DVCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to +7 V
VIN to GND
VOUT, IOUT to GND
Operating Temperature Range,
Industrial
−0.3 V to +7 V
AVSS to AVDD
−40°C to +105°C
Storage Temperature Range
−65°C to +150°C
Junction Temperature (TJ max)
32-Lead LFCSP Package
125°C
θJA Thermal Impedance1
Lead Temperature
Soldering
ESD (Human Body Model)
42°C/W
JEDEC industry standard
J-STD-020
3 kV
1 Simulated data based on a JEDEC 2S2P board with thermal vias.
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. F | Page 10 of 36


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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5750/AD5750-1/AD5750-2
SDO/VFAULT 1
CLRSEL 2
CLEAR 3
DVCC 4
GND 5
SYNC/RSET 6
SCLK/OUTEN 7
SDIN/R0 8
AD5750/
AD5750-1/
AD5750-2
TOP VIEW
(Not to Scale)
24 VSENSE+
23 VOUT
22 VSENSE–
21 AVSS
20 COMP1
19 COMP2
18 IOUT
17 AVDD
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE IS TIED TO AVSS.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 SDO/VFAULT Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin
is a CMOS output.
Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is
asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to
a pull-up resistor.
2
CLRSEL
In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.
3
CLEAR
Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the
range selected (user selectable). CLEAR is a logic OR with the internal clear bit.
In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage
channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details.
4 DVCC
Digital Power Supply.
5 GND
Ground Connection.
6 SYNC/RSET Positive Edge Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data
into the AD5750/AD5750-1/AD5750-2, also updating the output.
Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current sense resistor is
used. If RSET = 0, the external sense resistor is chosen, and if RSET = 1, the internal sense resistor is chosen.
7 SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of
SCLK. This pin operates at clock speeds up to 50 MHz.
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.
8
SDIN/R0
Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output
current/voltage range setting on the part.
9
AD2/R1
Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight
devices to be addressed on one bus.
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output
current/voltage range setting on the part.
10
AD1/R2
Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0, allows up to eight
devices to be addressed on one bus.
Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output
current/voltage range setting on the part.
Rev. F | Page 11 of 36


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AD5750/AD5750-1/AD5750-2
Data Sheet
Pin No.
11
12, 13
14
15
16
17
18
19, 20
21
22
23
24
25, 26,
27, 28
29
30
31
32
Mnemonic
AD0/R3
REXT2, REXT1
VREF
VIN
GND
AVDD
IOUT
COMP2,
COMP1
AVSS
VSENSE−
VOUT
VSENSE+
NC
Description
Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to eight
devices to be addressed on one bus.
Range Decode Bit (R3). In hardware mode, this pin, in conjunction with R0, R1, and R2, selects the output
current/voltage range setting on the part.
A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to improve the
IOUT temperature drift performance.
Buffered Reference Input.
Buffered Analog Input (0 V to 4.096 V).
Ground Connection.
Positive Analog Supply.
Current Output.
Optional Compensation Capacitor Connections for the Voltage Output Buffer. These pins are used to drive
higher capacitive loads on the output. They also reduce overshoot on the output. Care should be taken when
choosing the value of the capacitor connected between the COMP1 and COMP2 pins because it has a direct
influence on the settling time of the output. See the Driving Large Capacitive Loads section for further details.
Negative Analog Supply.
Sense Connection for the Negative Voltage Output Load Connection. This pin must stay within ±3.0 V of
ground for correct operation.
Buffered Analog Output Voltage.
Sense Connection for the Positive Voltage Output Load Connection.
No Connect. Can be tied to GND.
HW SELECT
RESET
FAULT/TEMP
NC/IFAULT
EPAD
This pin is used to configure the part to hardware or software mode. HW SELECT = 0 selects software control,
and HW SELECT = 1 selects hardware control.
Resets the part to its power-on state.
Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an open-
circuit error, short-circuit error, overtemperature error, or PEC interface error is detected. This pin is an open-
drain output and must be connected to a pull-up resistor.
Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is asserted
low when an overtemperature error is detected. This pin is an open-drain output and must be connected to a
pull-up resistor.
No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND.
Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is asserted
low when an open-circuit error is detected. This pin is an open-drain output and must be connected to a pull-
up resistor.
The exposed paddle is tied to AVSS.
Rev. F | Page 12 of 36


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Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE OUTPUT
0.0020
AVDD = +24V
0.0015 AVSS = –24V
0.0010
0.0005
0
–0.0005
–0.0010
–0.0015
–0.0020
–0.0025
–0.0030
0
+5V
+10V
±5V
±10V
0.585 1.170 1.755 2.341 2.926 3.511
VIN (V)
Figure 5. Integral Nonlinearity Error vs. VIN
4.096
0.005
AVDD = +24V
0.004 AVSS = –24V
0.003
+5V LINEARITY, NO LOAD
+10V LINEARITY, NO LOAD
±5V LINEARITY, NO LOAD
±10V LINEARITY, NO LOAD
0.002
0.001
0
–0.001
–0.002
–0.003
–0.004
–0.005
–40 25 105
TEMPERATURE (°C)
Figure 6. Integral Nonlinearity Error vs. Temperature
0.006
AVDD = +24V
AVSS = –24V
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
+5V
+10V
±5V
±10V
–0.010
0
0.585 1.170 1.755 2.341 2.926 3.511
VIN (V)
Figure 7. Total Unadjusted Error (TUE) vs. VIN
4.096
AD5750/AD5750-1/AD5750-2
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
+5V POSITIVE TUE, NO LOAD
+10V POSITIVE TUE, NO LOAD
±5V POSITIVE TUE, NO LOAD
±10V POSITIVE TUE, NO LOAD
+5V NEGATIVE TUE, NO LOAD
+10V NEGATIVE TUE, NO LOAD
±5V NEGATIVE TUE, NO LOAD
±10V NEGATIVE TUE, NO LOAD
–40 25
TEMPERATURE (°C)
105
Figure 8. Total Unadjusted Error (TUE) vs. Temperature
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
+5V RANGE, FULL-SCALE ERROR
+10V RANGE, FULL-SCALE ERROR
±5V RANGE, FULL-SCALE ERROR
±10V RANGE, FULL-SCALE ERROR
–40 25 105
TEMPERATURE (°C)
Figure 9. Full-Scale Error vs. Temperature
2.5
AVDD = +24V
2.0 AVSS = –24V
1.5
1.0
±10V ZERO ERROR
0.5
0
–0.5
–1.0
–1.5
–2.0
±5V ZERO ERROR
–2.5
–40 25 105
TEMPERATURE (°C)
Figure 10. Bipolar Zero Error vs. Temperature
Rev. F | Page 13 of 36


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AD5750/AD5750-1/AD5750-2
0.020
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
–0.025
AVDD = +24V
AVSS = –24V
+5V GAIN, NO LOAD
+10V GAIN, NO LOAD
±5V GAIN, NO LOAD
±10V GAIN, NO LOAD
–40 25
TEMPERATURE (°C)
105
Figure 11. Gain Error vs. Temperature
2.5
AVDD = +24V
2.0 AVSS = –24V
OUTPUT UNLOADED
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
+5V RANGE
+10V RANGE
–2.5
±5V RANGE
–3.0
±10V RANGE
–40
25
TEMPERATURE (°C)
105
Figure 12. Zero-Scale Error (Offset Error) vs. Temperature
0.003
0.002
0.001
+5V LINEARITY, NO LOAD
+10V LINEARITY, NO LOAD
±5V LINEARITY, NO LOAD
±10V LINEARITY, NO LOAD
0
–0.001
–0.002
–0.003
+11.2/–10.8
±15.0
±24.0
±26.4
SUPPLY VOLTAGES (AVDD/AVSS)
Figure 13. Integral Nonlinearity Error vs. Supply Voltage
Data Sheet
0.10
+5V POSITIVE TUE, NO LOAD
0.08 +10V POSITIVE TUE, NO LOAD
±5V POSITIVE TUE, NO LOAD
0.06 ±10V POSITIVE TUE, NO LOAD
+5V NEGATIVE TUE, NO LOAD
0.04 +10V NEGATIVE TUE, NO LOAD
±5V NEGATIVE TUE, NO LOAD
0.02 ±10V NEGATIVE TUE, NO LOAD
0
–0.02
–0.04
–0.06
–0.08
–0.10
+11.2/–10.8
±15.0
±24.0
±26.4
SUPPLY VOLTAGES (AVDD/AVSS)
Figure 14. Total Unadjusted Error (TUE) vs. Supply Voltages
1.2
1.0
0.8
±10V VDD HEADROOM, LOAD OFF
0.6
0.4
0.2
0
–40 25 105
TEMPERATURE (°C)
Figure 15. AVDD Headroom, ±10 V Range, Output Set to 10 V, Load Off
0.05
+5V RANGE
0.04 ±10V RANGE
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15
SOURCE/SINK CURRENT (mA)
Figure 16. Source and Sink Capability of Output Amplifier
Rev. F | Page 14 of 36


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Data Sheet
12
10
8
6
4
2
0
–8 –3
2
7 12 17 22 27
TIME (µs)
Figure 17. Full-Scale Positive Step
12
10
8
6
4
2
0
–8 –3
2
7 12 17 22 27
TIME (µs)
Figure 18. Full-Scale Negative Step
40
35
30
25
20
15
10
5
0
–5
–1.0
–0.5
0
0.5 1.0 1.5 2.0 2.5
TIME (ms)
Figure 19. VOUT vs. Time on Power-Up, Load = 2 kΩ || 200 pF
AD5750/AD5750-1/AD5750-2
1
2
CH1 5.00V CH2 20.0mV BW M1.0µs
A CH1 3.00V
Figure 20. VOUT Enable Glitch, Load = 2 kΩ || 1 nF
5µV/DIV
1s/DIV
Figure 21. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
100µV/DIV
1s/DIV
Figure 22. Peak-to-Peak Noise (100 kHz Bandwidth)
Rev. F | Page 15 of 36


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AD5750/AD5750-1/AD5750-2
4.0 1.0
3.5
0.8
3.0
VDD
0.6
2.5
2.0 0.4
1.5
0.2
1.0
VOUT
0
0.5
0
–1.5
–1.0
–0.5
0
–0.2
0.5 1.0 1.5 2.0
TIME (ms)
Figure 23. VDD and VOUT vs. Time on Power-Up
Data Sheet
Rev. F | Page 16 of 36


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Data Sheet
CURRENT OUTPUT
0.004
0.002
AVDD = +24V
AVSS = –24V
0
–0.002
–0.004
–0.006
–0.008
–0.010
0
+4mA TO +20mA
0mA TO +20mA
0mA TO +24mA
±20mA
±24mA
0.585 1.170
1.755 2.341
VIN (V)
2.926
3.511
4.096
Figure 24. Integral Nonlinearity Error vs. VIN, External RSET Resistor
0.004
AVDD = +24V
AVSS = –24V
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010
–0.012
0
+4mA TO +20mA
0mA TO +20mA
0mA TO +24mA
±20mA
±24mA
0.585 1.170
1.755
2.341
2.926
3.511
4.096
VIN (V)
Figure 25. Integral Nonlinearity Error vs. VIN, Internal RSET Resistor
0.010
0.008
0.006
0.004
+4mA TO +20mA EXTERNAL RSET LINEARITY
0mA TO +20mA EXTERNAL RSET LINEARITY
0mA TO +24mA EXTERNAL RSET LINEARITY
±20mA EXTERNAL RSET LINEARITY
±24mA EXTERNAL RSET LINEARITY
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010
+11.2/–10.8
±15.0
±24.0
±26.4
SUPPLY VOLTAGES (AVDD/AVSS)
Figure 26. Integral Nonlinearity Error, Current Mode,
External RSET Sense Resistor
AD5750/AD5750-1/AD5750-2
0.010
0.008
0.006
0.004
+4mA TO +20mA INTERNAL RSET LINEARITY
0mA TO +20mA INTERNAL RSET LINEARITY
0mA TO +24mA INTERNAL RSET LINEARITY
±20mA INTERNAL RSET LINEARITY
±24mA INTERNAL RSET LINEARITY
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010
+11.2/–10.8
±15.0
±24.0
±26.4
SUPPLY VOLTAGES (AVDD/AVSS)
Figure 27. Integral Nonlinearity Error, Current Mode,
Internal RSET Sense Resistor
0.010
AVDD = +24V
0.008 AVSS = –24V
0.006
+4mA TO +20mA
0mA TO +20mA
0mA TO +24mA
±20mA
±24mA
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
0
0.585 1.170 1.755 2.341 2.926 3.511 4.096
VIN (V)
Figure 28. Total Unadjusted Error (TUE) vs. VIN, External RSET Resistor
0.015
AVDD = +24V
AVSS = –24V
0.010
0.005
+4mA TO +20mA
0mA TO +20mA
0mA TO +24mA
±20mA
±24mA
0
–0.005
–0.010
–0.015
0
0.585 1.170 1.755 2.341 2.926 3.511 4.096
VIN (V)
Figure 29. Total Unadjusted Error vs. VIN, Internal RSET Resistor
Rev. F | Page 17 of 36


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AD5750/AD5750-1/AD5750-2
0.10
0.08
0.06
0.04
+4mA TO +20mA EXTERNAL RSET POSITIVE TUE
0mA TO +20mA EXTERNAL RSET POSITIVE TUE
0mA TO +24mA EXTERNAL RSET POSITIVE TUE
±20mA EXTERNAL RSET POSITIVE TUE
±24mA EXTERNAL RSET POSITIVE TUE
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
+4mA TO +20mA EXTERNAL RSET NEGATIVE TUE
0mA TO +20mA EXTERNAL RSET NEGATIVE TUE
0mA TO +24mA EXTERNAL RSET NEGATIVE TUE
±20mA EXTERNAL RSET NEGATIVE TUE
±24mA EXTERNAL RSET NEGATIVE TUE
+11.2/–10.8
±15.0
±24.0
±26.4
SUPPLY VOLTAGES (AVDD/AVSS)
Figure 30. Total Unadjusted Error (TUE), Current Mode,
External RSET Sense Resistor
0.10
0.08
0.06
0.04
+4mA TO +20mA INTERNAL RSET POSITIVE TUE
0mA TO +20mA INTERNAL RSET POSITIVE TUE
0mA TO +24mA INTERNAL RSET POSITIVE TUE
±20mA INTERNAL RSET POSITIVE TUE
±24mA INTERNAL RSET POSITIVE TUE
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
+4mA TO +20mA INTERNAL RSET NEGATIVE TUE
0mA TO +20mA INTERNAL RSET NEGATIVE TUE
0mA TO +24mA INTERNAL RSET NEGATIVE TUE
±20mA INTERNAL RSET NEGATIVE TUE
±24mA INTERNAL RSET NEGATIVE TUE
+11.2/–10.8
±15.0
±24.0
±26.4
SUPPLY VOLTAGES (AVDD/AVSS)
Figure 31. Total Unadjusted Error (TUE), Current Mode,
Internal RSET Sense Resistor
0.010
0.008
0.006
0.004
+4mA TO +20mA INTERNAL RSET LINEARITY
0mA TO +20mA INTERNAL RSET LINEARITY
0mA TO +24mA INTERNAL RSET LINEARITY
±20mA INTERNAL RSET LINEARITY
±24mA INTERNAL RSET LINEARITY
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010
AVDD = +24V
AVSS = –24V
–40
25
TEMPERATURE (°C)
105
Figure 32. INL vs. Temperature, Internal RSET Sense Resistor
Data Sheet
0.010
0.008
0.006
0.004
+4mA TO +20mA EXTERNAL RSET LINEARITY
0mA TO +20mA EXTERNAL RSET LINEARITY
0mA TO +24mA EXTERNAL RSET LINEARITY
±20mA EXTERNAL RSET LINEARITY
±24mA EXTERNAL RSET LINEARITY
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010
AVDD = +24V
AVSS = –24V
–40
25
TEMPERATURE (°C)
105
Figure 33. INL vs. Temperature, External RSET Sense Resistor
0.10
0.08
0.06
0.04
+4mA TO +20mA INTERNAL RSET POSITIVE TUE
0mA TO +20mA INTERNAL RSET POSITIVE TUE
0mA TO +24mA INTERNAL RSET POSITIVE TUE
±20mA INTERNAL RSET POSITIVE TUE
±24mA INTERNAL RSET POSITIVE TUE
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
+4mA TO +20mA INTERNAL RSET NEGATIVE TUE
0mA TO +20mA INTERNAL RSET NEGATIVE TUE
0mA TO +24mA INTERNAL RSET NEGATIVE TUE
±20mA INTERNAL RSET NEGATIVE TUE
±24mA INTERNAL RSET NEGATIVE TUE
–40 25
TEMPERATURE (°C)
105
Figure 34. Total Unadjusted Error (TUE) vs. Temperature,
Internal RSET Sense Resistor
0.10
0.08
0.06
0.04
+4mA TO +20mA EXTERNAL RSET POSITIVE TUE
0mA TO +20mA EXTERNAL RSET POSITIVE TUE
0mA TO +24mA EXTERNAL RSET POSITIVE TUE
±20mA EXTERNAL R SET POSITIVE TUE
±24mA EXTERNAL R SET POSITIVE TUE
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
+4mA TO +20mA EXTERNAL RSET NEGATIVE TUE
0mA TO +20mA EXTERNAL RSET NEGATIVE TUE
0mA TO +24mA EXTERNAL RSET NEGATIVE TUE
±20mA EXTERNAL R SET NEGATIVE TUE
±24mA EXTERNAL R SET NEGATIVE TUE
–40 25 105
TEMPERATURE (°C)
Figure 35. Total Unadjusted Error (TUE) vs. Temperature,
External RSET Sense Resistor
Rev. F | Page 18 of 36


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Data Sheet
6
AVDD = +24V
AVSS = –24V
4
+4mA TO +20mA EXTERNAL RSET
0mA TO +20mA EXTERNAL RSET
0mA TO +24mA EXTERNAL RSET
2
0
–2
–4
±20mA EXTERNAL RSET
±24mA EXTERNAL RSET
–6
–40 25
TEMPERATURE (°C)
105
Figure 36. Zero-Scale Error vs. Temperature, External RSET Sense Resistor
25
20
15
10 AVDD = +24V
AVSS = –24V
5
+4mA TO +20mA INTERNAL RSET
0mA TO +20mA INTERNAL RSET
0mA TO +24mA INTERNAL RSET
0
–5
–10
–15 ±20mA INTERNAL RSET
±24mA INTERNAL RSET
–20
–40 25
TEMPERATURE (°C)
105
Figure 37. Zero-Scale Error vs. Temperature, Internal RSET Sense Resistor
3
2
1
±24mA, EXTERNAL RSET
0
–1
–2
±20mA, EXTERNAL RSET
–3
–4
AVDD = +24V
AVSS = –24V
–5
–40
25
TEMPERATURE (°C)
105
Figure 38. Bipolar Zero-Scale Error vs. Temperature,
External RSET Sense Resistor
AD5750/AD5750-1/AD5750-2
2
1
0
±20mA, INTERNAL RSET
–1
–2
±24mA, INTERNAL RSET
–3
–4
–5
AVDD = +24V
AVSS = –24V
–6
–40
25
TEMPERATURE (°C)
105
Figure 39. Bipolar Zero-Scale Error vs. Temperature,
Internal RSET Sense Resistor
0.04
0.03
+4mA TO +20mA EXTERNAL RSET
0mA TO +20mA EXTERNAL RSET
0mA TO +24mA EXTERNAL RSET
0.02
AVDD = +24V
0.01 AVSS = –24V
0
–0.01
–0.02
–0.03
–0.04
±20mA EXTERNAL RSET
±24mA EXTERNAL RSET
–40 25
TEMPERATURE (°C)
105
Figure 40. Full-Scale Error vs. Temperature, External RSET Sense Resistor
0.04
0.03
0.02
0.01
+4mA TO +20mA INTERNAL RSET
0mA TO +20mA INTERNAL RSET
0mA TO +24mA INTERNAL RSET
±20mA INTERNAL RSET
±24mA INTERNAL RSET
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
AVDD = +24V
AVSS = –24V
–40 25 105
TEMPERATURE (°C)
Figure 41. Full-Scale Error vs. Temperature, Internal RSET Sense Resistor
Rev. F | Page 19 of 36


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AD5750/AD5750-1/AD5750-2
0.020
0.015
+4mA TO +20mA EXTERNAL RSET
0mA TO +20mA EXTERNAL RSET
0mA TO +24mA EXTERNAL RSET
0.010
0.005
0
–0.005
–0.010
–0.015
AVDD = +24V
AVSS = –24V
–40
±20mA EXTERNAL RSET
±24mA EXTERNAL RSET
25
TEMPERATURE (°C)
105
Figure 42. Gain Error vs. Temperature, External RSET Sense Resistor
0.08
0.06
0.04
+4mA TO +20mA INTERNAL RSET
0mA TO +20mA INTERNAL RSET
0mA TO +24mA INTERNAL RSET
±20mA INTERNAL RSET
±24mA INTERNAL RSET
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
AVDD = +24V
AVSS = –24V
–40
25
TEMPERATURE (°C)
105
Figure 43. Gain Error vs. Temperature, Internal RSET Sense Resistor
1.4
1.2
AVDD COMPLIANCE
1.0
0.8
AVSS COMPLIANCE
0.6
0.4
0.2
0
–40 25 105
TEMPERATURE (°C)
Figure 44. Output Compliance vs. Temperature
Tested When IOUT = 10.8 mA, ±24 mA Range Selected
Data Sheet
12 0.000010
0.000008
10
0.000006
8 0.000004
6
IOUT
4
0.000002
0
–0.000002
2 –0.000004
0
VDD
–0.000006
–0.000008
–2 –0.000010
–10 –8 –6 –4 –2 0 2 4 6 8 10
TIME (ms)
Figure 45. VDD and Output Current (IOUT) vs. Time-On Power-Up
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–2 –1 0 1 2 3 4 5 6 7 8
TIME (µs)
Figure 46. Output Current (IOUT) vs. Time-On Output Enable
0.025
0.020
0.015
0.010
0.005
0
–12 –6 1
8 14 21 28 34 41 48 54 61
TIME (µs)
Figure 47. 4 mA to 20 mA Output Current Step
68
Rev. F | Page 20 of 36


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Data Sheet
3000
2500
2000
1500
DVCC = 5V
1000
500
0
0
DVCC = 3V
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOGIC LEVEL (V)
Figure 48. DICC vs. Logic Input Voltage
6
5
AIDD
4
3
2
1
0
–1
–2
–3
±10.8
AISS
±15.0
±24.0
AVDD/AVSS (V)
±26.4
Figure 49. AIDD/AISS vs. AVDD/AVSS, VOUT = 0 V
AD5750/AD5750-1/AD5750-2
6
5
AIDD
4
3
2
1
0
–1
–2
–3
±10.8
AISS
±15.0
±24.0
AVDD/AVSS (V)
±26.4
Figure 50. AIDD/AISS vs. AVDD/AVSS, IOUT = 0 mA
Rev. F | Page 21 of 36


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AD5750/AD5750-1/AD5750-2
TERMINOLOGY
Total Unadjusted Error (TUE)
TUE is a measure of the output error taking all the various
errors into account: INL error, offset error, gain error, and
output drift over supplies, temperature, and time. TUE is
expressed as a percentage of full-scale range (% FSR).
Relative Accuracy or Integral Nonlinearity (INL)
INL is a measure of the maximum deviation, in % FSR, from a
straight line passing through the endpoints of the output driver
transfer function. A typical INL vs. input voltage plot can be
seen in Figure 5.
Bipolar Zero Error
Bipolar zero error is the deviation of the actual vs. ideal half-scale
output of 0 V/0 mA with a bipolar range selected. A plot of
bipolar zero error vs. temperature can be seen in Figure 10.
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero TC is a measure of the change in the bipolar zero error
with a change in temperature. It is expressed in ppm FSR/°C.
Full-Scale Error
Full-scale error is the deviation of the actual full-scale analog
output from the ideal full-scale output. Full-scale error is
expressed as a percentage of full-scale range (% FSR).
Full-Scale Temperature Coefficient (TC)
Full-scale TC is a measure of the change in the full-scale error
with a change in temperature. It is expressed in ppm FSR/°C.
Gain Error
Gain error is a measure of the span error of the output. It is the
deviation in slope of the output transfer characteristic from the
ideal expressed in % FSR. A plot of gain error vs. temperature
can be seen in Figure 11.
Gain Error Temperature Coefficient (TC)
Gain error TC is a measure of the change in gain error with
changes in temperature. Gain error TC is expressed in ppm
FSR/°C.
Data Sheet
Zero-Scale Error
Zero-scale error is the deviation of the actual zero-scale analog
output from the ideal zero-scale output. Zero-scale error is
expressed in millivolts (mV).
Zero-Scale TC
Zero-scale TC is a measure of the change in zero-scale error
with a change in temperature. Zero-scale error TC is expressed
in ppm FSR/°C.
Offset Error
Offset error is a measurement of the difference between the
actual VOUT and the ideal VOUT, expressed in millivolts (mV)
in the linear region of the transfer function. It can be negative
or positive.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a half-scale input change.
Slew Rate
The slew rate of a device is a limitation in the rate of change of the
output voltage. The output slewing speed is usually limited by the
slew rate of the amplifier used at its output. Slew rate is measured
from 10% to 90% of the output signal and is expressed in V/µs.
Current Loop Voltage Compliance
Current loop voltage compliance is the maximum voltage at
the IOUT pin for which the output current is equal to the
programmed value.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5750/AD5750-1/AD5750-2 are powered on.
It is specified as the area of the glitch in nV-sec.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output is affected by changes in the
power supply voltage.
Rev. F | Page 22 of 36


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Data Sheet
THEORY OF OPERATION
The AD5750/AD5750-1/AD5750-2 are single-channel, precision
voltage/current output drivers with hardware- or software-
programmable output ranges. The software ranges are configured
via an SPI-/MICROWIRE-compatible serial interface. The analog
input to the AD5750/AD5750-1/AD5750-2 is provided from a
low voltage, single-supply DAC and is internally conditioned to
provide the desired output current/voltage range. Analog input
ranges available are 0 V to 2.5 V (AD5750-1/AD5750-2) or 0 V
to 4.096 V (AD5750).
The output current range is programmable across five current
ranges: +4 mA to +20 mA, 0 mA to +20 mA, 0 mA to +24 mA,
±20 mA, and ±24 mA.
The voltage output is provided from a separate pin that can be
configured to provide 0 V to +5 V, 0 V to +10 V, ±5 V, or ±10 V
output ranges. An overrange of 20% is available on the voltage
ranges. An overrange of 2% is available on the 4 mA to 20 mA,
0 mA to 20 mA, and 0 mA to 24 mA current ranges. The current
and voltage outputs are available on separate pins. Only one
output can be enabled at one time. The output range is selected
by programming the R3 to R0 bits in the control register (see
Table 7 and Table 8).
AD5750/AD5750-1/AD5750-2
Figure 51 and Figure 52 show a typical configuration of the
AD5750/AD5750-1/AD5750-2 in software mode and in hardware
mode, respectively, in an output module system. The HW SELECT
pin selects whether the part is configured in software or hardware
mode. The analog input to the AD5750/AD5750-1/AD5750-2 is
provided from a low voltage, single-supply DAC, such as the
AD506x or AD566x, which provides an output range of 0 V to
4.096 V. The supply and reference for the DAC, as well as the
reference for the AD5750/AD5750-1/AD5750-2, can be supplied
from a reference such as the ADR392. The AD5750/AD5750-1/
AD5750-2 can operate from supplies up to ±26.4 V.
SOFTWARE MODE
In current mode, software-selectable output ranges include
±20 mA, ±24 mA, 0 mA to +20 mA, +4 mA to +20 mA, and
0 mA to +24 mA.
In voltage mode, software-selectable output ranges include 0 V
to +5 V, 0 V to +10 V, ±5 V, and ±10 V.
VDD AGND VSS
MCU
ADP1720
ADR392
VDD REFIN
SCLK
SDI/DIN
SDO
SYNC1
AD506x
AD566x
AD5750/
AD5750-1/
AD5750-2
VREF
VIN
SCLK
SDIN
SDO
SYNC
SERIAL
INTERFACE
AVDD GND AVSS
VSENSE+
VSENSE–
VOUT
RANGE
SCALE
VOUT
0V TO +5V, 0V TO +10V,
±5V, ±10V
IOUT
RANGE
SCALE
VOUT SHORT FAULT
IOUT OPEN FAULT
OVERTEMP FAULT
IOUT
0mA TO +20mA,
0mA TO +24mA,
+4mA TO +20mA
±20mA, ±24mA
STATUS REGISTER
HW SELECT
FAULT
Figure 51. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs)
Rev. F | Page 23 of 36


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AD5750/AD5750-1/AD5750-2
MCU
ADP1720
ADR392
SCLK VDD REFIN
SDI/DIN
SDO
SYNC1
AD506x
AD566x
DVCC
VDD AGND VSS
Data Sheet
AD5750/
AD5750-1/
AD5750-2
VREF
AVDD
GND AVSS
VSENSE+
VSENSE–
VOUT
RANGE
SCALE
VIN
VOUT
0V TO +5V, 0V TO +10V,
±5V, ±10V
HW SELECT
OUTEN
IOUT
RANGE
SCALE
TEMP
VFAULT
IFAULT
IOUT
0mA TO +20mA,
0mA TO +24mA,
+4mA TO +20mA
±20mA, ±24mA
R3
R2 OUTPUT RANGE
R1 SELECT PINS
R0
Figure 52. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs)
Table 6. Suggested Parts for Use with AD5750, AD5750-1, and AD5750-2
DAC
Reference
Power
Accuracy
Description
AD5660
Internal
ADP17201
12-bit INL
Midend system, single channel, internal reference
AD5664R Internal
Not applicable
Not applicable
Midend system, quad channel, internal reference
AD5668
Internal
Not applicable
Not applicable
Midend system, octal channel, internal reference
AD5060
ADR434
ADP17201
16-bit INL
High end system, single channel, external reference
AD5064
ADR434
Not applicable
Not applicable
High end system, quad channel, external reference
AD5662
ADR3922
ADR3922
12-bit INL
Midend system, single channel, external reference
AD5664
ADR3922
Not applicable
Not applicable
Midend system, quad channel, external reference
1 The input range of the ADP1720 is up to 28 V.
2 The input range of the ADR392 is up to 15 V.
Rev. F | Page 24 of 36


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Data Sheet
AD5750/AD5750-1/AD5750-2
CURRENT OUTPUT ARCHITECTURE
The voltage input from the analog input VIN pin (0 V to 4.096 V
for AD5750 and 0 V to 2.5 V for the AD5750-1/AD5750-2) is
either converted to a current (see Figure 53), which is then
mirrored to the supply rail so that the application simply sees
a current source output with respect to an internal reference
voltage, or it is buffered and scaled to output a software-selectable
unipolar or bipolar voltage range (see Figure 54). The reference
is used to provide internal offsets for range and gain scaling.
The selectable output range is programmable through the
digital interface.
RANGE DECODE
FROM INTERFACE
R2
VDD
R3
VIN
VREF
IOUT
RANGE
SCALING
RSET
Vx
REXT1
REXT2
IOUT
R1 VSS R4
IOUT
OPEN FAULT
VIN
(0V TO 4.096V)
VREF
Figure 53. Current Output Configuration
RANGE DECODE
FROM INTERFACE
VOUT RANGE
SCALING
VOUT
SHORT FAULT
VSENSE+
VOUT
Figure 54. Voltage Output
VSENSE–
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, connect a 0.01 μF
capacitor between IOUT and GND. This ensures stability with
loads beyond 50 mH. There is no maximum capacitance limit.
The capacitive component of the load may cause slower settling.
Voltage Output Amplifier
The voltage output amplifier is capable of generating both unipolar
and bipolar output voltages. It is capable of driving a load of 1 kΩ
in parallel with 1.2 μF (with an external compensation capacitor
on the COMP1 and COMP2 pins). The source and sink capabilities
of the output amplifier can be seen in Figure 16. The slew rate
is 2 V/μs.
Internal to the device, there is a 2.5 MΩ resistor connected
between the VOUT and VSENSE+ pins and, similarly, between
the VSENSE− pin and the internal device ground. If a fault
condition occurs, these resistors act to protect the AD5750/
AD5750-1/AD5750-2 by ensuring that the amplifier loop is closed
so that the part does not enter into an open-loop condition.
The VSENSE− pin can work in a common-mode range of ±3 V
with respect to the remote load ground point.
The current and voltage are output on separate pins and cannot
be output simultaneously. This allows the user to tie both the
current and voltage output pins together and configure the end
system as a single channel output.
Driving Large Capacitive Loads
The voltage output amplifier is capable of driving capacitive loads
of up to 1 μF with the addition of a nonpolarized compensation
capacitor between the COMP1 and COMP2 pins.
Without the compensation capacitor, up to 20 nF capacitive loads
can be driven. Care should be taken to choose an appropriate
value for the CCOMP capacitor. This capacitor, while allowing the
AD5750/AD5750-1/AD5750-2 to drive higher capacitive loads
and reduce overshoot, increases the settling time of the part
and, therefore, affects the bandwidth of the system. Considered
values of this capacitor should be in the range 100 pF to 4 nF,
depending on the trade-off required between settling time,
overshoot, and bandwidth.
POWER-ON STATE OF AD5750/AD5750-1/AD5750-2
On power-up, the AD5750/AD5750-1/AD5750-2 sense whether
hardware or software mode is loaded and set the power-up
conditions accordingly.
In software SPI mode, the power-up state of the output is
dependent on the state of the CLEAR pin. If the CLEAR pin is
pulled high, the part powers up, driving an active 0 V on the
output. If the CLEAR pin is pulled low, the part powers up with
the voltage output channel in tristate mode. In both cases, the
current output channel powers up in the tristate condition (0 mA).
This allows the voltage and current outputs to be connected
together, if desired.
To put the part into normal operation, the user must set the
OUTEN bit in the control register to enable the output and, in
the same write, set the output range configuration using the R3
to R0 range bits. If the CLEAR pin is still high (active) during
this write, the part automatically clears to its normal clear state
as defined by the programmed range and by the CLRSEL pin or
the CLRSEL bit (see the Asynchronous Clear (CLEAR) section
for more details). To operate the part in normal mode, take the
CLEAR pin low.
The CLEAR pin is typically driven directly from a microcontroller.
In cases where the power supply for the AD5750/AD5750-1/
AD5750-2 supply may be independent of the microcontroller
power supply, connect a weak pull-up resistor to DVCC or a pull-
down resistor to ground to ensure that the correct power-up
condition is achieved independent of the microcontroller. A
10 kΩ pull-up/pull-down resistor on the CLEAR pin should be
sufficient for most applications.
If hardware mode is selected, the part powers up to the conditions
defined by the R3 to R0 range bits and the status of the OUTEN
or CLEAR pin. It is recommended to keep the output disabled
when powering up the part in hardware mode.
Rev. F | Page 25 of 36


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AD5750/AD5750-1/AD5750-2
DEFAULT REGISTERS AT POWER-ON
The AD5750/AD5750-1/AD5750-2 power-on-reset circuit
ensures that all registers are loaded with zero code.
In software SPI mode, the part powers up with all outputs
disabled (OUTEN bit = 0). The user must set the OUTEN bit in
the control register to enable the output and, in the same write,
to set the output range configuration using the R3 to R0 bits.
If hardware mode is selected, the part powers up to the
conditions defined by the R3 to R0 bits and the status of the
OUTEN pin. It is recommended to keep the output disabled
when powering up the part in hardware mode.
RESET FUNCTION
In software mode, the part can be reset using the RESET pin
(active low) or the reset bit (reset = 1). A reset disables both the
current and voltage outputs to their power-on condition. The
user must write to the OUTEN bit to enable the output and, in
the same write, to set the output range configuration. The RESET
pin is a level-sensitive input; the part stays in reset mode as long
as the RESET pin is low. The reset bit clears to 0 following a
reset command to the control register.
In hardware mode, there is no reset. If using the part in hardware
mode, tie the RESET pin high.
Data Sheet
OUTEN
In software mode, the output can be enabled or disabled using
the OUTEN bit in the control register. When the output is
disabled, both the current and voltage channels go into tristate.
The user must set the OUTEN bit to enable the output and
simultaneously set the output range configuration.
In hardware mode, the output can be enabled or disabled using
the OUTEN pin. When the output is disabled, both the current
and voltage channels go into tristate. The user must write to the
OUTEN pin to enable the output. It is recommended that the
output be disabled when changing the ranges.
SOFTWARE CONTROL
Software control is enabled by connecting the HW SELECT pin
to ground. In software mode, the AD5750/AD5750-1/AD5750-2
are controlled over a versatile 3-wire serial interface that operates at
clock rates up to 50 MHz. It is compatible with SPI, QSPI™,
MICROWIRE, and DSP standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device MSB first as a 16-bit word under the control of the serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
The input shift register consists of 16 control bits, as shown in
Table 7. The timing diagram for this write operation is shown in
Figure 2. The first three bits of the input shift register are used to
set the hardware address of the AD5750/AD5750-1/AD5750-2
device on the printed circuit board (PCB). Up to eight devices
can be addressed per board.
Bit D11, Bit D1, and Bit D0 must always be set to 0 during any
write sequence.
Table 7. Input Shift Register Contents for a Write Operation—Control Register
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
D5
A2 A1 A0 R/W 0
R3 R2 R1 R0 CLRSEL OUTEN
D4
Clear
D3
RSET
D2
Reset
LSB
D1 D0
00
Table 8. Input Shift Register Descriptions
Bit Description
A2, A1, A0
Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system
controller.
A2 A1 A0 Function
0 0 0 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0.
0 0 1 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1.
0 1 0 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0.
0 1 1 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1.
1 0 0 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0.
1 0 1 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1.
1 1 0 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0.
1 1 1 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1.
R/W Indicates a read from or a write to the addressed register.
Rev. F | Page 26 of 36


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Data Sheet
AD5750/AD5750-1/AD5750-2
Bit
R3, R2, R1, R0
CLRSEL
OUTEN
Clear
RSET
Reset
Description
Selects the output configuration in conjunction with RSET.
RSET R3 R2 R1 R0 Output Configuration
0 0 0 0 0 4 mA to 20 mA (external 15 kΩ current sense resistor).
0 0 0 0 1 0 mA to 20 mA (external 15 kΩ current sense resistor).
0 0 0 1 0 0 mA to 24 mA (external 15 kΩ current sense resistor).
0 0 0 1 1 ±20 mA (external 15 kΩ current sense resistor).
0 0 1 0 0 ±24 mA (external 15 kΩ current sense resistor).
0 0 1 0 1 0 V to 5 V.
0 0 1 1 0 0 V to 10 V.
0 0 1 1 1 ±5 V.
0 1 0 0 0 ±10 V.
0 1 0 0 1 0 V to 6.0 V (20% overrange).
0 1 0 1 0 0 V to 12.0 V (20% overrange).
0 1 0 1 1 ±6.0 V (20% overrange).
0 1 1 0 0 ±12.0 V (20% overrange).
0 1 1 0 1 ±2.5 V.
0 1 1 1 0 Not applicable; if selected, output drives between 0 V and −1 V.
0 1 1 1 1 Not applicable; if selected, output drives between 0 V and −1 V.
1 0 0 0 0 4 mA to 20 mA (internal current sense resistor).
1 0 0 0 1 0 mA to 20 mA (internal current sense resistor).
1 0 0 1 0 0 mA to 24 mA (internal current sense resistor).
1 0 0 1 1 ±20 mA (internal current sense resistor).
1 0 1 0 0 ±24 mA (internal current sense resistor).
1 0 1 0 1 0 V to 5 V.
1 0 1 1 0 0 V to 10 V.
1 0 1 1 1 ±5 V.
1 1 0 0 0 ±10 V.
1 1 0 0 1 0 V to 6.0 V (20% overrange).
1 1 0 1 0 0 V to 12.0 V (20% overrange).
1 1 0 1 1 ±6.0 V (20% overrange).
1 1 1 0 0 ±12.0 V (20% overrange).
1 1 1 0 1 3.92 mA to 20.4 mA (internal current sense resistor).
1 1 1 1 0 0 mA to 20.4 mA (internal current sense resistor).
1 1 1 1 1 0 mA to 24.5 mA (internal current sense resistor).
Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section.
CLRSEL
Function
0 Clear to 0 V.
1 Clear to midscale in unipolar mode; clear to zero scale in bipolar mode.
Output enable bit. This bit must be set to 1 to enable the outputs.
Software clear bit, active high.
Select internal/external current sense resistor.
RSET
Function
1 Select internal current sense resistor; used with R3 to R0 bits to select range.
0 Select external current sense resistor; used with R3 to R0 bits to select range.
Resets the part to its power-on state.
Rev. F | Page 27 of 36


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AD5750/AD5750-1/AD5750-2
Status Bit Read Operation
A read of the status bits can be initiated as part of a normal write
operation. The read is activated by selecting the correct device
address (A2, A1, A0) and then setting the R/W bit to 1. By
default, the SDO pin is disabled. After having addressed the
AD5750/AD5750-1/AD5750-2 and setting R/W to 1 the SDO
pin is enabled and data is clocked out on the 5th rising edge of
SCLK. After all the data has been clocked out on SDO, a rising
edge on SYNC disables (tristates) the SDO pin again. Status
register data (see Table 9) and control register data are both
available during the same read cycle. Data contained in Bit D10
to Bit D0 of the write operation are still valid and can be used to
change the operating mode of the AD5750/AD5750-1/AD5750-2
if required.
The status bits comprise three read-only bits. They are used to
notify the user of specific fault conditions that occur, such as an
open circuit or short circuit on the output, an overtemperature
error, or an interface error. If any of these fault conditions occur,
a hardware FAULT is also asserted low, which can be used as a
hardware interrupt to the controller.
See the Detailed Description of Features section for a full
explanation of fault conditions.
Data Sheet
HARDWARE CONTROL
Hardware control is enabled by connecting the HW SELECT
pin to DVCC. In this mode, the R3, R2, R1, and R0 pins, in
conjunction with the RSET pin, are used to configure the
output range per Table 8.
In hardware mode, there is no status register. The fault conditions
(open circuit, short circuit, and overtemperature) are available
on the IFAULT, VFAULT, and TEMP pins. If any one of these
fault conditions are set, a low is asserted on the specific fault pin.
IFAULT, VFAULT, and TEMP are open-drain outputs and,
therefore, can be connected together to allow the user to generate
one interrupt to the system controller to communicate a fault.
If hardwired in this way, it is not possible to isolate which fault
occurred in the system.
TRANSFER FUNCTION
The AD5750/AD5750-1/AD5750-2 consist of an internal signal
conditioning block that maps the analog input voltage to a
programmed output range. The available analog input ranges are
0 V to 4.096 V (AD5750) and 0 V to 2.5 V (AD5750-1/AD5750-2).
For all ranges, both current and voltage, the AD5750, AD5750-1,
and AD5750-2 implement a straight linear mapping function,
where 0 V maps to the lower end of the selected range and 4.096 V
(or 2.5 V for AD5750-1/AD5750-2) maps to the upper end of the
selected range.
Table 9. Input Shift Register Contents for a Read Operation—Status Register
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
A2 A1 A0 1 0 R3 R2 R1 R0 CLRSEL OUTEN RSET
D3
PEC
Error
D2
OVER
TEMP
D1
IOUT
Fault
LSB
D0
VOUT
Fault
Table 10. Status Bit Options
Bit Description
PEC Error
This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section.
OVER TEMP This bit is set if the AD5750/AD5750-1/AD5750-2 core temperature exceeds approximately 150°C.
IOUT Fault This bit is set if there is an open circuit on the IOUT pin.
VOUT Fault This bit is set if there is a short circuit on the VOUT pin.
Rev. F | Page 28 of 36


AD5750-1 (Analog Devices)
Industrial Current/Voltage Output Driver

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Data Sheet
AD5750/AD5750-1/AD5750-2
DETAILED DESCRIPTION OF FEATURES
OUTPUT FAULT ALERT—SOFTWARE MODE
In software mode, the AD5750/AD5750-1/AD5750-2 are equipped
with one FAULT pin; this is an open-drain output allowing several
AD5750/AD5750-1/AD5750-2 devices to be connected together
to one pull-up resistor for global fault detection. In software mode,
the FAULT pin is forced active low by any one of the following
fault scenarios:
The voltage at IOUT attempts to rise above the compliance
range due to an open-loop circuit or insufficient power supply
voltage. The internal circuitry that develops the fault output
avoids using a comparator with window limits because this
requires an actual output error before the fault output becomes
active. Instead, the signal is generated when the internal
amplifier in the output stage has less than approximately
1 V of remaining drive capability. Thus, the fault output
activates slightly before the compliance limit is reached.
Because the comparison is made within the feedback loop
of the output amplifier, the output accuracy is maintained
by its open-loop gain, and an output error does not occur
before the fault output becomes active.
A short is detected on the voltage output pin (VOUT). The
short-circuit current is limited to 15 mA.
An interface error is detected due to PEC failure. See the
Packet Error Checking section.
The core temperature of the AD5750/AD5750-1/AD5750-2
exceeds approximately 150°C.
OUTPUT FAULT ALERT—HARDWARE MODE
In hardware mode, the AD5750/AD5750-1/AD5750-2 are
equipped with three fault pins: VFAULT, IFAULT, and TEMP.
These are open-drain outputs allowing several AD5750/AD5750-1/
AD5750-2 devices to be connected together to one pull-up resistor
for global fault detection. In hardware control mode, these fault
pins are forced active by any one of the following fault scenarios:
An open circuit is detected. The voltage at IOUT attempts
to rise above the compliance range, due to an open-loop
circuit or insufficient power supply voltage. The internal
circuitry that develops the fault output avoids using a
comparator with window limits because this requires an
actual output error before the fault output becomes active.
Instead, the signal is generated when the internal amplifier
in the output stage has less than approximately 1 V of
remaining drive capability. Thus, the fault output activates
slightly before the compliance limit is reached. Because the
comparison is made within the feedback loop of the output
amplifier, the output accuracy is maintained by its open-
loop gain, and an output error does not occur before the
fault output becomes active. If this fault is detected, the
IFAULT pin is forced low.
A short is detected on the voltage output pin (VOUT). The
short-circuit current is limited to 15 mA. If this fault is
detected, the VFAULT pin is forced low.
The core temperature of the AD5750/AD5750-1/AD5750-2
exceeds approximately 150°C. If this fault is detected, the
TEMP pin is forced low.
VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION
Under normal operation, the voltage output sinks and sources
up to 12 mA and maintains specified operation. The maximum
current that the voltage output delivers is 15 mA; this is the
short-circuit current.
ASYNCHRONOUS CLEAR (CLEAR)
CLEAR is an active high clear that allows the output to be
cleared to either zero-scale code or midscale code and is user-
selectable via the CLRSEL pin or the CLRSEL bit of the input shift
register, as described in Table 8. (The clear select feature is a
logical OR function of the CLRSEL pin and the CLRSEL bit).
The current loop output clears to the bottom of its programmed
range. When the CLEAR signal is returned low, the output returns
to its programmed value or to a new programmed value. A clear
operation can also be performed via the clear command in the
control register (see Table 11).
Table 11. CLRSEL Options
CLRSEL Unipolar Output Voltage Range
0 0V
1 Midscale
Output Clear Value
Unipolar Current Output Range
Bipolar Output Range
Zero scale; for example,
4 mA on the 4 mA to 20 mA range,
0 mA on the 0 mA to 20 mA range
Negative full scale
Midscale; for example,
0V
12 mA on the 4 mA to 20 mA range,
10 mA on the 0 mA to 20 mA range
Bipolar Current Output Range
Zero scale; for example,
−24 mA on the ±24 mA range
Midscale; for example,
0 mA on the ±24 mA range
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AD5750/AD5750-1/AD5750-2
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 1, RSET is an internal sense resistor and is
part of the voltage-to-current conversion circuitry. The nominal
value of the internal current sense resistor is 15 kΩ. To allow for
overrange capability in current mode, the user can also select
the internal current sense resistor to be 14.7 kΩ, giving a nominal
2% overrange capability. This feature is available in the 0 mA to
+20 mA, +4 mA to +20 mA, and ±20 mA current ranges.
The stability of the output current value over temperature is
dependent on the stability of the value of RSET. As a method of
improving the stability of the output current over temperature,
an external low drift resistor can be connected to the REXT1
and REXT2 pins of the AD5750/AD5750-1/AD5750-2, which
can be used instead of the internal resistor. The external resistor
is selected via the input shift register. If the external resistor option
is not used, leave the REXT1 and REXT2 pins floating.
PROGRAMMABLE OVERRANGE MODES
The AD5750/AD5750-1/AD5750-2 contain an overrange mode
for most of the available ranges. The overranges are selected by
configuring the R3, R2, R1, and R0 bits (or pins) accordingly.
In voltage mode, the overranges are typically 20%, providing
programmable output ranges of 0 V to +6 V, 0 V to +12 V, ±6 V,
and ±12 V. The analog input remains the same.
In current mode, the overranges are typically 2%. In current
mode, the overrange capability is available on only three ranges,
0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. For these
ranges, the analog input also remains the same (0 V to 4.096 V
for the AD5750, and 0 V to 2.5 V for the AD5750-1/AD5750-2).
Data Sheet
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5750/AD5750-1/AD5750-2 offer the option of error
checking based on an 8-bit cyclic redundancy check (CRC-8).
The device controlling the AD5750/AD5750-1/AD5750-2 should
generate an 8-bit frame check sequence using the following
polynomial:
C(x) = x8 + x2 + x1 + 1
This is added to the end of the data-word, and 24 data bits are
sent to the AD5750/AD5750-1/AD5750-2 before taking SYNC
high. If the AD5750/AD5750-1/AD5750-2 receive a 24-bit data
frame, the parts perform the error check when SYNC goes high.
If the check is valid, the data is written to the selected register. If
the error check fails, the FAULT pin goes low, and Bit D3 of the
status register is set. After reading this register, this error flag is
cleared automatically, and the FAULT pin goes high again.
SYNC
UPDATE ON SYNC HIGH
SCLK
SDIN
D15
(MSB)
16-BIT DATA
D0
(LSB)
16-BIT DATA TRANSER—NO ERROR CHECKING
SYNC
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
SCLK
SDIN
D23
(MSB)
16-BIT DATA
D8
(LSB)
D7 D0
8-BIT FCS
FAULT
FAULT GOES LOW IF
ERROR CHECK FAILS
16-BIT DATA TRANSER WITH ERROR CHECKING
Figure 55. PEC Error Checking Timing
Rev. F | Page 30 of 36




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