LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Compressed Audio Signal Processor IC
with USB Host Controller
Overview
The LC786820E integrates ARM7TDMI-S™, USB host processing, SD
memory card host processing, compressed audio decode processing, audio
signal processing and a flash memory which stores the program for
ARM7TDMI-S™ and the various data. The sophisticated programs in the
flash memory for the USB host processing for the SD memory card
processing or audio signal processing etc. make the process of external main
microcontroller easier and very helpful to develop a much features/high
performance audio player system.
Main Features
1. USB host/device function (Full speed : 12Mbps),
SD memory card host function
2. MP3*, WMA*, AAC*, FLAC* decoder processing function
3. Audio input functions such as Analog (stereo 3ch)/digital 3ch input
(Sampling rate convertible)
4. Audio processing functions such as 20 bands equalizer (stereo 1ch),
subwoofer processing, high-frequency range extendable filter and etc.
5. Audio output functions such as Electronical Volume output 5 ch
(for LF, LR, RF, RR, SW), or DAC output 3ch (Lch, Rch, SW)
6. ARM7TDMI-S™ as internal CPU core, flash memory for program and
various data storage
7. Operational voltage source: 3.3V single power supply
8. Operational temperature: 40 to +85 C
9. Package: QIP100E (1420) Pb-Free and Halogen Free type
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PQFP100 14x20 / QIP100E
* MP3
MPEG Layer-3 Audio Coding
* WMA
Windows Media Audio
* AAC
Advanced Audio Coding
* FLAC
Free Lossless Audio Codec
* This product is licensed from Silicon Storage Technology, Inc. (USA).
© Semiconductor Components Industries, LLC, 2016
June 2016 - Rev. 1
1
Publication Order Number:
LC786820E/D


LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Detail Functions
[ Compressed audio functions ]
<Audio processing block>
MP3 decode (ISO/IEC 11172-3, ISO/IEC 13818-3)
Supported sampling rate : MPEG1-Layer1/2/3 (32kHz, 44.1kHz, 48kHz)
MPEG2-Layer1/2/3 (16kHz, 22.05kHz, 24kHz)
MPEG2.5-Layer3 ( 8kHz, 11.025kHz, 12kHz)
Supported bit rate
: All Bit Rate (Variable Bit Rate support)
MPEG header read supported
WMA decode (Version 9.2 standard)
Supported sampling rate : 8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz, 44.1kHz, 48kHz
Supported bit rate
: 5kbps to 384kbps (Variable Bit Rate support)
AAC decode (ISO/IEC 14496-3, ISO/IEC 13818-7)
Profile
: MPEG4-AAC-LowComplexity
Supported sampling rate : 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
Supported bit rate
: Monaural 8kbps to 160kbps (Variable bit rate support)
Stereo 16kbps to 320kbps (Variable bit rate support)
* Depending on the condition, sampling rate can be supported up to 96kHz.
FLAC decode (FLAC 1.3.0)
Supported format
: Block size: up to 4608
Quantized number of bits: 8/16/24 bit per sample
Supported sampling rate: 8kHz to 48kHz
Supported channel
: 1/2ch
[ Audio processing functions ]
<Audio data digital processing block>
Equalizer function
Supports max of 20-band (stereo 1ch) and unused band can be used for not only the voice output but also
used for other processing
Supports signal processing for subwoofer
Sampling conversion (Fs=32/44.1/48kHz) when playing compressed audio, High band extended
processing supported
Mute (/12dB), attenuator
De-emphasis filter
Embedded level/peak hold circuit and can hold up to 8 data
Noise cancel/Echo cancel function
Supports noise cancel/echo cancel at Fs=8kHz
Supports input/output of Fs=16kHz voice data
<Audio input processing block>
Analog Audio data input (3-channels by stereo)
Single Ended input
: 2 channels
Differential input
: 1 channel
Input Gain
: 12.5dB to +18.5dB (1dB step)
24bit accuracy AD converter
Digital audio input (Stereo input: Max of 3 channels)
Supports digital 3-line (LR clock, bit clock, audio data) connection and clock can be master or slave
Data format supports IIS/MSB first right justified and etc.
Input data can support 8kHz to 96kHz, and by sampling conversion, converts to the suitable Fs
(Playback Fs=32/44.1/48kHz etc.)
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
<Audio output processing block>
Analog Audio data output (One channel for stereo, and one channel for Sub-Woofer)
Eight-fold over-sampling digital filter (24bit)
Secondary LPF for audio output
Electronic Volume/Fader
5ch outputs (Lch-Front (LF)/Rear(LR), Rch-Front (RF)/Rear (RR), Sub-Woofer)
Output Range: 0dB to 0dB, 
0dB to 32dB
: Analog control, 0.25dB step
32dB to 70dB
: Analog control, 1.0dB step
70dB to 90dB
: Digital attenuator control
Decrease the noise at the volume change timing by the digital and analog composite control.
Individual output for 5 channels control is available
Digital Audio data output
Digital 3-line interface with IIS/MSB first right justification and etc.
LR clock, Bit clock, Data 1
Clock can be master or slave
Capable of outputting 384Fs clock
[ External interface functions ]
<USB host/device control block>
Open Host Controller Interface 1.0a
Universal Serial Bus Specification 2.0 Full Speed
Supports four kinds of transfer type (Control/Bulk/Interrupt/Isochronous)
Supports 2 Ports. USB1=Host or Device, USB2=Host only
USB Charger (USB1 only)
Supports detection of CDP (Charging Downstream Port) of USB Charger Specification 1.2
Charge (supplying current) is not supported
PHY block: Internal Pull-Down/Pull-Up resisters built-in
<SD memory card host control block>
Multimedia Card Specification v2.11
Secure Digital Memory Card Physical Layer Specification v0.96
* Individual contract is necessary to use SD memory card controller.
[ Internal Microcontroller functions ]
<Sequencer control>
USB, SD memory card playback/write control
USB/SD files analysis, etc.
Audio playback control
Compressed audio playback control, various filter control and etc.
<Communication control between main controller>
Main communication format is SIO (4-line)
Capable of direct control of oscillation stop/start from main microcontroller
Capable of some special command can be used even when oscillation is stopped
<Peripheral interface block>
GPIO ports
37 ports maximum
(Shared with other functions. Some part of pins can be used even when the clock is halted)
External interrupt pins 4 pins maximum (Shared with other functions)
Serial interface
SIO
clock synchronized full duplex (3 lines)
3 channels
UART
full duplex
2 channels
IIC master function
1 channel
<Program memory block>
Program memory for the internal sequencer built-in
Program version up from the external media (USB and etc.) or main controller is available.
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
<Others>
Watch Dog Timer
Notify to outside from the pin or internal reset.
Sleep Mode (2 kinds)
(1) Only CPU core operates at slow clock and clocks for other blocks are stopped.
(2) All clocks are stopped by the main microcontroller control.
[ Useful functions for CD-DSP IC connection usage ]
<CD TEXT processing block>
Buffers CD-TEXT data
Starts buffering from desired ID3/ID4 of CD-TEXT data.
* Necessary to connect subcode synchronization signals (SBSY and SFSY), shift clock (SBCK) and data (PW).
<CD-ROM processing block>
Up to 4speed operation available
Supports CD-ROM decoding (Mode1, Mode2 <form1, form2>)
Supports output of CD-ROM decoded data
* Necessary to connect three signals (LRCK, BCK and DATA).
It is possible if desired to connect C2 error flag.
[ Others ]
<Internal power supply>
Regulator for internal blocks (VDD for internal=1.2V, VDD for Flash=1.8V) built-in
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Absolute Maximum at Ta=25C, DVSS=AVSS1=AVSS2=XVSS=0V
Item
Maximum
supply voltage
Input voltage
Output voltage
Symbol
VDD max
VIN
VOUT
Pin Name
DVDD, AVDD1, AVDD2, XVDD,
VVDD2
All digital input pins
All digital output/input-output pins
Allowable
power
dissipation
Pd max
Operating
temperature
Topr
Storage
temperature
Tstg
(*) Reference PCB: 114.3mm 76.1mm 1.6mm, glass epoxy resin
Condition
Ta 85C
Mounted
reference
PCB(*)
Ratings
0.3 to +3.95
0.3 to DVDD+0.3
0.3 to DVDD+0.3
519
Unit
V
mW
40 to +85
40 to +125
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta=40C to 85C, DVSS=AVSS1=AVSS2=XVSS=0V
Item
Supply voltage
Symbol
VDD1
High-level input
voltage
VIH
Low-level input
voltage
VIL
Oscillator Frequency FX
Pin Name
DVDD, AVDD1, AVDD2,
XVDD, VVDD2
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, JTMS,
JTRSTB, JTCK, JTDI,
GP30, GP31, GP32, GP33,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
GP44, GP45, GP46, GP47,
GP50, GP51, GP52, GP53
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, JTMS,
JTRSTB, JTCK, JTDI,
GP30, GP31, GP32, GP33,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
GP44, GP45, GP46, GP47,
GP50, GP51, GP52, GP53,
TEST0, TEST1
XIN
XOUT
Condition
MIN
3.00
TYP
Schmitt 2.00
Schmitt 0.00
Oscillator
circuit
12.0000
MAX
3.60
Unit
VDD1
V
0.80
MHz
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Electrical Characteristics at Ta=40C to 85C, VDD1=3.0V to 3.6V, DVSS=AVSS1=AVSS2=XVSS=0V
Item
Current drain
Symbol
IDD1
High-level
input current
IIH
Low-level
input current
IIL
High-level
VOH(1)
output voltage
VOH(2)
Low-level
VOL(1)
output voltage
VOL(2)
Built-in Pull-
down resistor
RPD
Pin Name
DVDD, AVDD1, AVDD2,
XVDD, VVDD2
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, JTMS,
JTRSTB, JTCK, JTDI,
GP30, GP31, GP32, GP33,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
GP44, GP45, GP46, GP47,
GP50, GP51, GP52, GP53
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, GP30, GP31,
GP32, GP33, GP34, GP35,
GP36, GP37, GP40, GP41,
GP42, GP43, GP44, GP45,
GP46, GP47, GP50, GP51,
GP52, GP53, JTMS,
JTRSTB, JTCK, JTDI,
TEST0, TEST1
GP04, GP05, GP06, GP07,
GP12, GP13, GP14, GP15, GP30,
GP31, GP32, GP33, GP34,
GP35, GP36, GP37, GP40,
GP41, GP42, GP43, GP44,
GP45, GP46, GP47, GP50,
GP51, GP52, GP53
SIFDI, SIFDO, SIFCE,
BUSYB, GP03, GP10, GP11,
JTDO, JTRTCK
GP04, GP05, GP06, GP07,
GP12, GP13, GP14, GP15, GP30,
GP31, GP32, GP33, GP34,
GP35, GP36, GP37, GP40,
GP41, GP42, GP43, GP44,
GP45, GP46, GP47, GP50,
GP51, GP52, GP53
SIFDI, SIFDO, SIFCE,
BUSYB, GP03, GP10, GP11,
JTDO, JTRTCK
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, GP30, GP31,
GP32, GP33, GP34, GP35,
GP36, GP37, GP40, GP41,
GP42, GP43, GP44, GP45,
GP46, GP47, GP50, GP51,
GP52, GP53
Condition
Schmitt
VIN=VDD1
Built-in Pull-
down resistor
OFF
Schmitt
VIN=0.0V
CMOS
IOH=2mA
CMOS
IOH=4mA
CMOS
IOL=2mA
CMOS
IOL=4mA
MIN
10.00
VDD1
0.6
50
TYP
100
100
MAX
150
10.00
0.40
0.40
200
Unit
mA
μA
V
V
V
k
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Item
Output off-
leakage
current
Symbol
IOFF
(1)
IOFF
(2)
AFILT
SIFDO
Pin Name
Condition
Hi-Z Out
Hi-Z Out
MIN
10.00
10.00
TYP
MAX
10.00
10.00
Unit
μA
Charge
pump output
current
IAFH
IAFL
AFILT
AFILT
195.0
195.0
μA
<Note>
Place an internal pull-down resistor or external pull-down resistor or external pull-up resistor to the SIFDO pin if its
output condition is set to 3-State mode.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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Package Dimensions
unit : mm
PQFP100 14x20 / QIP100E
CASE 122BV
ISSUE A
LC786820E
23.20.2
20.00.1
12
0.65
(0.58)
0.30.05
0.13
0.15
0.10
0 to10
SOLDERING FOOTPRINT*
22.30
(Unit: mm)
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
YMDDD
0.65
0.43
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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PIN Assignment
LC786820E
NC
AVDD1
AVSS1
LRREF
DACOUTR
RVRIN
RROUT
RFOUT
DACOUTS
SWIN
SWOUT
VREF_ADC
AVSS2
AVDD2
L3INP
L3INN
R3INP
R3INN
L2IN
R2IN
L1IN
R1IN
TEST0
TEST1
DVDD18_2
GP15
GP50
GP51
GP52
GP53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80 DVSS
79 VVDD2
78 NC
77 AFILT
76 XVSS
75 XOUT
74 XIN
73 XVDD
72 UDP1
71 UDM1
70 DVSS
69 UDP2
68 UDM2
67 DVDD
66 DVSS
65 GP47
64 GP46
63 GP45
62 GP44
61 GP43
60 GP42
59 GP41
58 GP40
57 GP03
56 BUSYB
55 SIFCE
54 SIFDO
53 SIFDI
52 SIFCK
51 RESB
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Pin Description
Pin
No.
Pin name
1 NC
2 AVDD1
3 AVSS1
4 LRREF
5 DACOUTR
6 RVRIN
7 RROUT
8 RFOUT
9 DACOUTS
10 SWIN
11 SWOUT
12 VREF_ADC
13 AVSS2
14 AVDD2
15 L3INP
I/O
AO
AO
AI
AO
AO
AO
AI
AO
AO
AI
16 L3INN
17 R3INP
18 R3INN
19 L2IN
20 R2IN
21 L1IN
22 R1IN
23 TEST0
24 TEST1
25 DVDD18_2
26 GP15
AI
AI
AI
AI
AI
AI
AI
I
I
AO
I/O
27 GP50
I/O
28 GP51
I/O
29 GP52
I/O
30 GP53
31 DVDD
32 DVSS
I/O
State when
"Reset"
AVDD1/2
Unknown
Input
Unknown
Unknown
Unknown
Input
Unknown
AVDD2/2
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
H
Input(L)
Input(L)
Input(L)
Input(L)
Input(L)
Function
NC pin. This pin must be left open.
Analog system (ADC) power supply
Analog system (ADC) ground. This pin must be connected to the 0V level.
Capacitor connection pin for reference voltage for Audio DAC and
Electronic Volume.
Audio DAC : Right channel output
Electronic Volume : Right channel volume input
Electronic Volume : Right channel Rear output
Electronic Volume : Right channel Front output
Audio DAC : Sub-Woofer output
Electronic Volume : Sub-Woofer volume input
Electronic Volume : Sub-Woofer output
Capacitor connection pin for audio ADC reference voltage
Analog system (ADC) ground. This pin must be connected to the 0V level.
Analog system (ADC) power supply
Analog stereo Left channel Differential input (Positive) /
Analog stereo Left channel Single Ended input
Analog stereo Left channel Differential input (Negative)
Analog stereo Right channel Differential input (Positive) /
Analog stereo Right channel Single Ended input
Analog stereo Right channel Differential input (Negative)
Analog stereo Left channel Single Ended input
Analog stereo Right channel Single Ended input
Analog stereo Left channel Single Ended input
Analog stereo Right channel Single Ended input
Test input. This pin must be connected to the 0V level.
Test input. This pin must be connected to the 0V level.
Capacitor connection pin for internal regulator (1.8V for Flash)
General purpose I/O port with pull down resistor
Various signal monitoring output
General purpose I/O port with pull down resistor
LR clock input/output 1 for Audio interface
LR clock input 1 for Stream data interface
Transmit data output for serial communication 3 (exclusive with GP34)
Over current detection signal input for USB 1 (exclusive with GP44)
General purpose I/O port with pull down resistor
Bit clock input/output 1 for Audio interface
Bit clock input/output 1 for Stream data interface
Master clock output for serial communication 3 (exclusive with GP35)
Power supply signal output for USB 1 (exclusive with GP45)
General purpose I/O port with pull down resistor
Data input/output 1 for Audio interface
Data input 1 for Stream data interface
Receive data input for serial communication 3 (exclusive with GP36)
Over current detection signal input for USB 2 (exclusive with GP46)
General purpose I/O port with pull down resistor
Clock (Fs384) input/output 1 for Audio DAC
Request flag input/output 1 for Stream data interface
Power supply signal output for USB 2 (exclusive with GP47)
Digital system power supply
Digital system ground. This pin must be connected to the 0V level.
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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Pin
No.
Pin name
33 GP30
34 GP31
35 GP32
36 GP33
37 GP34
38 GP35
39 GP36
40 GP37
41 DVDD
42 DVSS
43 REG1EXTR
44 DVDD12_2
45 GP10
46 GP11
47 GP12
48 GP13
LC786820E
I/O
State when
"Reset"
Function
General purpose I/O port with pull down resistor
UART2 data transmit (exclusive with GP46)
I/O
Input(L)
External interruption function 3
(exclusive with GP13, GP31, GP43 and GP47)
LR clock input/output 2 for Audio interface
LR clock input 2 for Stream data interface
General purpose I/O port with pull down resistor
UART2 data receive (exclusive with GP47)
I/O
Input(L)
External interruption function 3
(exclusive with GP13, GP30, GP43 and GP47)
Bit clock input/output 2 for Audio interface
Bit clock input/output 2 for Stream data interface
General purpose I/O port with pull down resistor
I/O
Input(L)
Data 1 input/output for SD memory card
Data input/output 2 for Audio interface
Data input/output 2 for Stream data interface
General purpose I/O port with pull down resistor
I/O
Input(L)
Data 0 input/output for SD memory card
Clock(Fs384) input/output 2 for Audio DAC
Request flag input/output 2 for Stream data interface
General purpose I/O port with pull down resistor
Clock output for SD memory card
I/O Input(L) Transmit data output for serial communication 3 (exclusive with GP50)
Block synchronization signal (SBSY) input for CD subcode
(exclusive with GP44)
General purpose I/O port with pull down resistor
Command input/output for SD memory card
I/O Input(L) Master clock output for serial communication 3 (exclusive with GP51)
Frame synchronization signal (SFSY) input for CD subcode
(exclusive with GP45)
General purpose I/O port with pull down resistor
I/O
Input(L)
Data 3 input/output for SD memory card
Receive data input for serial communication 3 (exclusive with GP52)
Data (PW) input for CD subcode (exclusive with GP46)
General purpose I/O port with pull down resistor
I/O Input(L) Data 2 input/output for SD memory card
Data transmit clock (SBCK) output for CD subcode (exclusive with GP47)
  Digital system power supply
  Digital system ground. This pin must be connected to the 0V level.
AO Unknown Reserved pin for internal regulator. This pin must be left open.
AO H Capacitor connection pin for internal regulator (1.2V for internal)
General purpose I/O port with pull down resistor
I/O Input(L) UART1 data transmit (exclusive with GP06)
IIC (master) clock output (exclusive with GP04 and GP40)
General purpose I/O port with pull down resistor
I/O Input(L) UART1 data receive (exclusive with GP07)
IIC (master) data input/output (exclusive with GP05 and GP41)
General purpose I/O port with pull down resistor
I/O
Input(L)
External interruption function 2 (exclusive with GP42 and GP46)
Clock control input 1
Watch Dog Timer state monitor output
General purpose I/O port with pull down resistor
External interruption function 3
I/O Input(L) (exclusive with GP30, GP31, GP43 and GP47)
Clock control input 2
Watch Dog Timer state monitor output
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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Pin
No.
Pin name
49 DVDD
50 DVSS
51 RESB
52 SIFCK
53 SIFDI
54 SIFDO
55 SIFCE
56 BUSYB
57 GP03
58 GP40
59 GP41
60 GP42
61 GP43
62 GP44
63 GP45
LC786820E
I/O
State when
"Reset"
Function
  Digital system power supply
  Digital system ground. This pin must be connected to the 0V level.
I
IC reset input ("L"-active)
This pin must be set low once after power is first applied.
Host-I/F
I Input
Data transmit clock input for serial communication 1
Data transmit clock input for IIC communication
Host-I/F
I/O Input
Data input for serial communication 1
Data input/output for IIC communication
Host-I/F
I/O Input
Data output for serial communication 1 (CMOS or 3-State output)
General purpose I/O port with pull down resistor (GP00)
Host -I/F
I/O Input
Enable signal input for serial communication 1 ("H"-active)
General purpose I/O port with pull down resistor (GP01)
Host -I/F
I/O Input(L)
System busy signal output ("L"-active)
General purpose I/O port with pull down resistor (GP02)
External interruption function 0 (exclusive with GP40 and GP44)
General purpose I/O port with pull down resistor
I/O
Input(L)
Watch Dog Timer state monitor output
USB device detection flag output
External interruption function 1 (exclusive with GP14, GP41 and GP45)
General purpose I/O port with pull down resistor
External interruption function 0 (exclusive with GP02 and GP44)
I/O Input(L) IIC (master) clock output (exclusive with GP04 and GP10)
LR clock input/output 3 for Audio interface
LR clock input 3 for Stream data interface
General purpose I/O port with pull down resistor
External interruption function 1 (exclusive withGP03, GP14 and GP45)
I/O Input(L) IIC (master) data input/output (exclusive with GP05 and GP11)
Bit clock input/output 3 for Audio interface
Bit clock input/output 3 for Stream data interface
General purpose I/O port with pull down resistor
External interruption function 2 (exclusive with GP12 and GP46)
I/O Input(L) Watch Dog Timer state monitor output
Data input/output 3 for Audio interface
Data input/output 3 for Stream data interface
General purpose I/O port with pull down resistor
External interruption function 3
I/O Input(L) (exclusive with GP13, GP30, GP31 and GP47)
Clock (Fs384) input/output 3 for Audio DAC
Request flag input/output 3 for Stream data interface
General purpose I/O port with pull down resistor
External interruption function 0 (exclusive with GP02 and GP40)
I/O Input(L) Over current detection signal input for USB 1(exclusive with GP50)
Block synchronization signal (SBSY) input for CD subcode
(exclusive with GP34)
General purpose I/O port with pull down resistor
External interruption function 1 (exclusive withGP03, GP14 and GP41)
I/O Input(L) Power supply signal output for USB 1(exclusive with GP51)
Frame synchronization signal (SFSY) input for CD subcode
(exclusive with GP35)
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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Pin
No.
Pin name
64 GP46
65 GP47
66 DVSS
67 DVDD
68 UDM2
69 UDP2
70 DVSS
71 UDM1
72 UDP1
73 XVDD
74 XIN
75 XOUT
76 XVSS
77 AFILT
78 NC
79 VVDD2
80 DVSS
81 DVDD
82 GP04
83 GP05
84 GP06
85 GP07
86 GP14
87 DVDD12_1
88 DVDD
89 DVSS
90 DVDD18_1
LC786820E
I/O
State when
"Reset"
Function
General purpose I/O port with pull down resistor
UART2 data transmit (exclusive with GP30)
I/O
Input(L)
External interruption function 2 (exclusive with GP12 and GP42)
Over current detection signal input for USB 2 (exclusive with GP52)
Emphasis flag input/output for Audio (exclusive with GP14)
Data (PW) input for CD subcode (exclusive with GP36)
General purpose I/O port with pull down resistor
UART2 data receive (exclusive with GP31)
External interruption function 3
I/O Input(L) (exclusive with GP13, GP30, GP31 and GP43)
Power supply signal output for USB 2 (exclusive with GP53)
CD_C2 error flag input (exclusive with GP14)
Data transmit clock (SBCK) output for CD subcode (exclusive with GP37)
  Digital system ground. This pin must be connected to the 0V level.
  Digital system power supply
I/O USB data input/output 2 Dsignal connection
I/O USB data input/output 2 D+ signal connection
  Digital system ground. This pin must be connected to the 0V level.
I/O
USB data input/output 1 Dsignal connection
Charge detection (CDP detection) input/output 1
I/O
USB data input/output 1 D+ signal connection
Charge detection (CDP detection) input/output 1
  Oscillator power supply
I Oscillation X'tal oscillator connection
O Oscillation X'tal oscillator connection
  Oscillator ground. This pin must be connected to the 0V level.
AO Unknown PLL2 charge pump output (for filter connection)
  NC pin. This pin must be left open.
  PLL2 power supply
  Digital system ground. This pin must be connected to the 0V level.
  Digital system power supply
General purpose I/O port with pull down resistor
I/O Input(L) Master clock output for serial communication 2
IIC (master) clock output (exclusive with GP10 and GP40)
General purpose I/O port with pull down resistor
I/O Input(L) Receive data input for serial data communication 2
IIC (master) data input/output (exclusive with GP11 and GP41)
General purpose I/O port with pull down resistor
I/O Input(L) Transmit data output for serial communication 2
UART1 data transmit (exclusive with GP10)
I/O
Input(L)
General purpose I/O port with pull down resistor
UART1 data receive (exclusive with GP11)
General purpose I/O port with pull down resistor
External interruption function 1 (exclusive withGP03, GP41 and GP45)
I/O
Input(L)
Watch Dog Timer state monitor output
USB device detection flag output
Emphasis flag input/output for Audio (exclusive with GP46)
CD_C2 error flag input (exclusive with GP47)
AO H Capacitor connection pin for internal regulator (1.2V for internal)
  Digital system power supply
  Digital system ground. This pin must be connected to the 0V level.
AO H Capacitor connection pin for internal regulator (1.8V for Flash)
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Pin
No.
Pin name
91 JTRSTB
92 JTCK
93 JTDI
94 JTMS
95 JTDO
96 JTRTCK
97 LFOUT
98 LROUT
99 LVRIN
100 DACOUTL
I/O
State when
"Reset"
Function
I
Input
JTAG reset input
(Connect to pull-down resistor or 0V level in normal mode.)
I
Input
JTAG clock input
(Connect to pull-down resistor or 0V level in normal mode.)
I
Input
JTAG data input
(Connect to pull-down resistor or 0V level in normal mode.)
I
Input
JTAG mode input
(Connect to pull-down resistor or DVDD level in normal mode.)
O L JTAG data output (Leave open in normal mode.)
O L JTAG return clock output (Leave open in normal mode.)
AO Unknown Electronic Volume : Left channel Front output
AO Unknown Electronic Volume : Left channel Rear output
AI
Input
Electronic Volume : Left channel volume input
AO Unknown Audio DAC : Left channel output
<Notes>
(1) For unused pins :
The unused input pins must be connected to the GND(0V) level if there is no individual note in the above table.
The unused output pins must be left open(No connection) if there is no individual note in the above table.
The unused input/output pins must follow the below conditions if there is no individual note in the above table:
Input setting
Leave open with internal pull-down resister ON.
With using internal pull-down resistor OFF, connect to GND (0V) or connect to power pins
for I/O.
However, use of individual pull-up or pull-down resistor is recommended as fail-safe.
Output setting
Leave them open.
(2) For power supply pins:
Same voltage level must be supplied to DVDD, AVDD1, AVDD2, XVDD and VVDD2 power supply pins.
(Refer to “Allowable operating ranges”)
(3) For “Reset” condition:
This IC is not reset only by making the RESB pin “Low”.
Refer to “Power on and Reset control” for detail of “Reset” condition.
(4) For “Analog Source” unused pins (15 pin to 22 pin) :
The “Analog Source” unused pins (15 pin to 22 pin) must be connected to the GND (0V) level through the input
coupling capacitor or be left open (No connection).
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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Block Diagram
LC786820E
X'tal
(12MHz)
PLL1
PLL2
ASS
&
ADC
Flash
memory
CDROM
Decoder
CDTEXT
Decoder
External Input
Data Interface
ARM7 Core
Cache
BUFRAM
I/F
USB
Host
/Device
Controller
Boot
ROM
Work
RAM
USB-I/F
(CDP-Det)
SD
Memory
Card
Controller
Host-I/F
(SIO/IIC)
Watch
Dog
Interrupt
UART
IIC
SIO
GPIO
Regulator
1.2V
1.8V
3.3V
Buffer
SRAM
DATA
Trans
Controller
MP3/WMA/AAC
FLAC
/Decoder
Audio
Data-I/F
SRC
&
HFC-
Audio Control
20Band-EQ/
Sub-Woofer/
(Loudness/)
ATT/MUTE
Level/Peak
8Fs Digital Filter
Audio DAC
Analog LPF
EVR
EVR
EVR
EVR
EVR
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Power-ON/Reset Control
- Notes on Power-On
(1) Regarding Reset Pin
To stabilize the operation condition of the internal FlashROM, RESB pin must need to be “L”.
If RESB pin is “H” at the Power-On, operation condition of the Flash memory becomes unstable and the operation
of this LSI becomes unstable. In this case, Reset by RESET pin control does not return to the normal state, RESB
pin must be “L” at the Power-On.
(2) Regarding Volume Out
Volume output becomes unknown state when Power-On, external circuit must care by muting/etc. from external
circuit.
- Power-On/Power-Down/Reset Timing
3.3V Power supply
VDD1
vBOT
0V
tPWD
3.3V Power supply
VDD1
RESB Pin
tRESW1
At the Power-On
tRESW2
Normal Operation
(Clock oscillation stable)
Parameter
Symbol
Min
Typ
Power-On rise time
tPWD
10
Power-Down fall time
vBOT
0
Reset period (at Power-On)
tRESW1
20
Reset period (When normal
operation) (*1)
tRESW2
1
*1 : Reset period at normal operation is the period that clock is stablely oscillating.
Need to care about clock stable time when making clock OFF by commands.
Max
0.2
Unit
ms
V
ms
ms
- Regarding RESB pin control and internal Flash memory
As stated above, reset of the operation state of the flash memory in this LSI cannot be controlled by only RESB pin,
and needs Poer-On-Reset. Therefore, when flash memory goes to runaway state during the power is on, Power-On-
Reset must be done. In this case, users must power off the LSI and execute the Power-On-Reset.
On the other hand, reset control by RESB pin is effective to the circuit other than the flash memory. By making
RESB pin to “L” for the time period stated above with the stable clock, the circuit except flash memory is initialized.
Also, by this operation, flash memory becomes stand-by state and states of the memory cells are kept.
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Microcontroller Interface
Reception/Transmission from the host microcontroller is done by the SPI synchronous SIO communication.
The format of the data transmission is as below.
- Code of M5 to M0 at the ModeCode transmission must be followed by the specification of the internal software inside
this LSI.
When data input in M5 to M0 and value in the internal register matches, SIFDO becomes “L” (Ack) and communication
will be enabled. If no match, SIFDO becomes “H” (Nack) and communication will not be enabled.
- Judgement whether command transmission or reception will be done by the 7th bit data of the ModeCode transmission.
“L” means command transmission and “H” means data reception.
- Need to care the communication timing specification because the specification differs by operational mode (normal /
low speed) of the internal microcontroller.
- Communication interface with the host microcontroller
SIFCE
SIFCK
SIFDI
SIFDO
BUSYB
MODE
(Send)
Command Command
12
Ack
Command
N
MODE
(Receive)
Ack
Data
1
Data
2
- Transmission/Reception format with the host microcontroller
(1) Host: Command transmission
SIFCE
1 2 3 4 5 6 7 81 2 3
678
SIFCK
SIFDI
SIFDO
M5 M4 M3 M2 M1 M0 WR
D7 D6 D5
D2 D1 D0
Mode
Code
1st-data
Nack byte
Ack
Last-data
byte
BUSYB
(2) Host: Data reception
SIFCE
1 2 3 4 5 6 7 81 2 3
678
SIFCK
SIFDI
SIFDO
BUSYB
M5 M4 M3 M2 M1 M0 RD
Mode
Code
Nack
Ack D7 D6 D5
D2 D1 D0
1st-data
byte
Last-data
byte
Data
N
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
- Characteristics of Communication Timing With Host Microcontroller
SIFCE
(Input)
SIFCK
(Input)
SIFDI
(Input)
SIFDO
(Output)
BUSYB
(Output)
tCSU
tCKH
1/fCLK
tCKL
tCWSU tCWHD
tCDON
tCDOH
tCHD
tCRAS
tCBST
tCE
tCDOF
Parameter
Symbol
Pin Names
Communication Clock Frequency fCLK SIFCK
Communication Clock “H” Period tCKH SIFCK
Communication Clock “L” Period
Communication Start Allowable
Time
Communication Start Set Up
Time
Communication End Hold Time
tCKL
tCE
tCSU
tCHD
SIFCK
BUSYB, SIFCE
SIFCE, SIFCK
SIFCE, SIFCK
Data Input Set Up Time
tCWSU SIFDI, SIFCK
Data Input Hold Time
tCWHD SIFDI, SIFCK
Data Output “H” Level Rise Time tCDOH SIFDO, SIFCK
Min Typ
150
690
150
690
0
0
100
200
100
200
75
75
75
200
Data Output Settle Time
tCRAS SIFDO, SIFCK
Output ON Settle Timer *1
tCDON SIFDO, SIFCE
Output OFF Settle Timer *1
tCDOF SIFDO, SIFCE
BUSYB "L" Level Settle Time
tCBST BUSYB
*Internal Microcontroller Operation Mode Upper Value: Normal Mode
Lower Value: Low Speed Mode
Note1: tCDON/tCDOF are available only when setting SIFDO pin to 3-State output.
Max
3.3
0.725
100
350
100
350
100
100
150
150
150
350
Unit
MHz
ns
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
IIC can be used for the transmission/reception from the host microcontroller.
Supported modes are;
Normal Mode
: 100kbps
High Speed Mode : 400kbps
Slave address is 0x16 (7bit value).
- Condition for Communication(IIC) Timing With Host Microcontroller
SDA
[SIFDI]
(Inout)
SCL
[SIFCK]
(Input)
tF
tLOW
tHD;STAtR
Start Condition
tSU;DAT
tHIGH
tHD;DAT
tHD;STA
tSU;STA
ReStart Condition
tBUF
tR
tSU;STO
Stop Condition
Parameter
Symbol Normal (100kbps)
Min Max
SCL Frequency
fSCL
0 100
Bus Open Time
tBUF
4.7
SCL "L" Period
tLOW
4.7
SCL "H" Period
tHIGH
4.0
Start/ReStart Condition Hold Time
tHD;STA
4.0
Start/ReStart Condition Set-Up Time tSU;STA
4.7
SDA Hold Time
tHD;DAT
0
SDA Set-Up Time
tSU;DAT
250
SDA, SCL Rise Time
tR 1000
SDA, SCL Fall Time
tF 300
Stop Condition Set-Up Time
tSU;STO
4.0
Note: Cb is the total capacity added to each bus (Unit: pF)
High Speed
(400kbps)
Min Max
0 400
1.3
1.3
0.6
0.6
0.6
0
100
20+0.1Cb 300
20+0.1Cb 300
0.6
Unit
kHz
s
s
s
s
s
s
ns
ns
ns
s
When using IIC, SIFDO/SIFCE/BUSYB pins can be used as GPIOs as below;
SIFDO : GP00
SIFCE : GP01
BUSYB : GP02
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Serial Communication Ports
- Characteristics of Serial Communication (SIO) Master Mode Input/Output Timing
tSCL tSCH
1/fSCF
SSPCK
[GP04/GP35/GP51]
(Output)
SSPDO
[GP06/GP34/GP50]
(Output)
tSDO
SSPDI
[GP05/GP36/GP52]
(Input)
tSDS tSDH
Parameter
Symbol Signal Names
Min
SIO Clock Frequency
fSCF
SSPCK
0.008
SIO Clock “H” Period
tSCH SSPCK
100
SIO Clock "L" Period
tSCL
SSPCK
100
Data Output Settle Time
tSDO SSPDO, SSPCK
Data Input Set-Up Time
tSDS
SSPDI, SSPCK
50
Data Input Hold Time
tSDH SSPDI, SSPCK
75
Note: In the case that internal microcontroller operates in normal mode.
Typ Max Unit
5.0 MHz
62500
62500
90 ns
- Conditions for Input/Output Timing of Serial Communication (IIC) Master Mode
SDA
[GP05/GP11/GP41]
(Inout)
tF
SCL
[GP04/GP10/GP40]
(Output)
tLOW
tR
tHD;STA
Start Condition
tSU;DAT
tHIGH
tHD;DAT
tHD;STA
tSU;STA
ReStart Condition
tBUF
tR
tSU;STO
Stop Condition
Normal (100kbps)
Parameter
Symbol
Min Max
SCLFrequency
fSCL
0 100
Bus Open Time
tBUF
4.7
SCL "L" Period
tLOW
4.7
SCL "H" Period
tHIGH
4.0
Start/ReStart Condition Hold Time
tHD;STA
4.0
Start/ReStart Condition Set-Up Time
tSU;STA
4.7
SDA Hold Time
tHD;DAT
0
SDA Set-Up Time
tSU;DAT
250
SDA,SCL Rise Time
tR 1000
SDA,SCL Fall Time
tF 300
Stop Condition Set-Up Time
tSU;STO
4.0
Note: Cb is the total capacity added to each bus (Unit: pF)
High Speed
(400kbps)
Min Max
0 400
1.3
1.3
0.6
0.6
0.6
0
100
20+0.1Cb 300
20+0.1Cb 300
0.6
Unit
kHz
s
s
s
s
s
s
ns
ns
ns
s
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
USB Specification at Ta=40 to 85C, VDD1=3.0 to 3.6V, DVSS=AVSS1=AVSS2=XVSS=0V
Parameter
High-level input voltage
Low-level input voltage
Input leakage current
Differential input sensitivity
Common mode voltage range
High-level output voltage
Low-level output voltage
Output signal
Crossover voltage
USB data rising time
USB data falling time
D+/DPull-Down resistor
D+ Pull-Up resistor
Dsource voltage
Symbol
VIH(USB)
VIL(USB)
ILI
VDI
VCM
VOH(USB)
VOL(USB)
Pin Names
UDM1, UDP1,
UDM2, UDP2
VCR
TUR
TUF
RPD
RPUI
RPUR
VDMSRC
VLGC_SRC
UDP1
UDM1
Conditions
Output : OFF
|(UDP) (UDM)|
Includes VDI range
CL=50pF
Idle
Reception
MIN
2.0
10.0
0.2
0.8
2.8
0.0
1.3
4.0
4.0
14.25
0.9
1.425
0.5
0.8
TYP
MAX Unit
0.8 V
10.0 μA
V
2.5 V
3.6 V
0.3 V
2.0 V
20.0
20.0
24.8
1.575
3.09
0.7
2.0
ns
k
k
V
V
USB port peripheral circuit application
LC786820E
UDP1
/UDP2
UDM1
/UDM2
15
15
* The value of resistors in this circuit might be
needed to be adjusted for each application.
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
SD Memory Card Interface
- Characteristics of SD Memory Card Input/Output Timing
tSDCKL tSDCKH
SDCCLK
(Output)
1/fSDCKF
SDCMDIO
(Inout)
SDCDAT[3:0]
(Inout)
tSDCMS
tSDCMH
tSDCDS
tSDCDH
tSDCMO
tSDCDO
*Relationship between signal name and pin
SDCCLK
: GP34
SDCMDIO
SDCDAT[2] : GP37
SDCDAT[1]
: GP35
: GP32
SDCDAT[3] : GP36
SDCDAT[0] : GP33
Parameter
Symbol
Signal Names
Min Typ Max Unit
SDCCLK Clock Frequency
SDCCLK "H" Period
SDCCLK "L" Period
fSDCKF
tSDCKH
tSDCKL
SDCCLK
SDCCLK
SDCCLK
6.0 MHz
83.3
83.3
Command Input Set-Up Time
Command Input Hold Time
Command Output Settle Time
Data Input Set-Up Time
Data Input Hold Time
Data Output Settle Time
tSDCMS
tSDCMH
tSDCMO
tSDCDS
tSDCDH
tSDCDO
SDCMDIO, SDCCLK
SDCMDIO, SDCCLK
SDCMDIO, SDCCLK
SDCDAT[3:0], SDCCLK
SDCDAT[3:0], SDCCLK
SDCDAT[3:0], SDCCLK
30.0
30.0
30.0
30.0
30.0 ns
30.0
Note: Internal microcontroller (ARM7) must be used in normal mode. It cannot be used in low speed mode.
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Audio Data Input/Output Function
AC Electrical Characteristics
at Ta=25C, VDD1=3.3V, DVSS=AVSS1=AVSS2=XVSS=0V
Fs=44.1kHz, Audio Signal Frequency: 1kHz, Measurement Range: 10Hz to 20kHz
Parameter
(Input selector+ADC)
Full scale Analog Input Level
Input Impedance
Gain Setting Level
Gain Setting Step
Gain Setting Step Error
Signal to Noise Ratio
Dynamic Range
Total Harmonic
Distortion
Cross Talk1
Cross Talk2
(ADC Digital Filter)
Passband Frequency
Stopband Frequency
Passband Ripple
Stopband Attenuation
HPF Cut Off Frequency for DC
Offset cancelation
(Audio DAC)
Full scale Analog Output Level
Signal to Noise Ratio
Dynamic Range
Total Harmonic
Distortion
Cross Talk
(DAC Digital Filter)
Passband Frequency
Stopband Frequency
Passband Ripple
Stopband Attenuation
HPF Cut Off Frequency for DC
Offset cancelation
Symbol
Pin
Names
L1IN,
R1IN,
L2IN,
S/N R2IN,
L3INP,
L3INN,
DR R3INP,
R3INN
THD+N
CT1
CT2
S/N
DACOUTL,
DR
DACOUTR,
DACOUTS
THD+N
CT
Conditions
Min
Typ
Max
0dB Data,
20kHz-LPF,
A-filter
60dB Data,
20kHz-LPF,
A-filter
Input condition :
3dBFS
Between Channels
Between Sources
2.605
20
12
0.5
2.805
(0.85VDD1)
30
1
90 95
90 95
85
100
100
3.005
19
0.5
80
85
85
±0.04dB
>24.1kHz
0
0.5465
69
0.00002
0.4535
±0.04
0dB Data,
20kHz-LPF,
A-filter
60dB Data,
20kHz-LPF,
A-filter
0dB Data,
20kHz-LPF
0dB Data,
20kHz-LPF
±0.015dB
3dB
2.605
2.805
(0.85VDD)
3.005
106
106
85
100
80
85
0
0.5465
62
0.0000385
0.4535
±0.015
Unit
Vpp
k
dB
dB
dB
dB
dB
dB
dB
dB
Fs
Fs
dB
dB
Fs
Vpp
dB
dB
dB
dB
Fs
Fs
dB
dB
Fs
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Parameter
(Electronic Volume)
Input Impedance
Volume Setting range
Mute Level
Volume Setting Step
Volume Setting Step Error
Symbol
Pin
Names
LVRIN,
RVRIN,
SWIN
LFOUT,
LROUT,
RFOUT,
RROUT,
SWOUT
Conditions
Min
0 to 32dB
32 to 70dB
0 to 32dB
32 to 70dB
7.5
15
70
80
0.125
0.5
Typ
10
20
90
0.25
1.0
Max Unit
0
0.125
0.5
k
k
dB
dB
dB
dB
dB
dB
- Audio Digital Data Input/Output Function
- Audio Input/Output Supported Format
Mode
IIS
Input
MSB First Right Aligned
MSB First Left Aligned
Output
IIS
MSB First Right Aligned
MSB First Left Aligned
Bit Length
16bit
24bit
16bit
24bit
Slot Length
32fs, 48fs, 64fs
Fs384 Clock
Internal Clock
External Clock
32fs, 48fs, 64fs Fs384 Clock Output
- Applied Pins
LRCK
BCK
DATA
Fs384 Clock
GP30
GP31
GP32
GP33
Input
GP40
GP41
GP42
GP43
GP50
GP51
GP52
GP53
Output
GP30
GP40
GP50
GP31
GP41
GP51
GP32
GP42
GP52
GP33
GP43
GP53
Note: When each pin is set as audio input simultaneously, they will be processed as below priority;
(1) GP30 to 33, (2) GP40 to 43, (3) GP50 to 53
For example, if set all pins to audio input mode, audio data will be processed on only data in GP30 to 33.
- Other
Data in GP40 to 43, GP 50 to 53 will not be processed in the LSI.
- Audio output can be supported in 3 kinds of Fs (32kHz/44.1kHz/48kHz).
- When inputting external audio, GP14/GP46 can support input of emphasis signals.
- Characteristics of Audio Data Input Timing
tFCKIH
tFCKIL
1/fFCKI
Fs384ck
(=Fs384 clock)
tALRIH
tALRIS
LRCK
BCK
DATA
tABKIH
tABKIL
1/fABCKI
tADTIS tADTIH
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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Parameter
Fs384 Clock Frequency
Fs384 Clock "H" Period
Fs384 Clock "L" Period
Bit Clock Frequency
Bit Clock "H" Period
Bit Clock "L" Period
LRCK Input Set-Up Time
LRCK Input Hold Time
DATA Input Set-Up Time
DATA Input Hold Time
LC786820E
Symbol Signal Names Min Typ Max unit
fFCKI
Fs384ck
20.0 MHz
tFCKIH
Fs384ck
20
ns
tFCKIL
Fs384ck
20
ns
fABCKI
BCK
3.3 MHz
tABKIH
BCK
120
ns
tABKIL
BCK
120
ns
tALRIS LRCK, BCK
30
ns
tALRIH LRCK, BCK
30
ns
tADTIS DATA, BCK
30
ns
tADTIH DATA, BCK
30
ns
- Characteristics of Audio Data Output Timing
tFCKOH
tFCKOL
Fs384ck
(=Fs384 clock)
LRCK
BCK
tDL1
tABKOH tABKOL
tDL2
DATA
tDL3
1/fFCKO
1/fABCKO
Parameter
Fs384 Clock Frequency
Symbol
fFCKO
Signal Names
Fs384ck
Min
Fs384 Clock "H" Period
tFCKOH
Fs384ck
Fs384 Clock "L" Period
tFCKOL
Fs384ck
Bit Clock Frequency
fABCKO
BCK
Bit Clock "H" Period
tABKOH
BCK
Bit Clock "L" Period
tABKOL
BCK
LRCK Output Delay Time
tDL1
LRCK, Fs384ck
0
BCK Output Delay Time
tDL2
BCK, Fs384ck
0
DATA Output Delay Time
tDL3
DATA, Fs384ck
0
*1: In the case that output Fs=44.1kHz and slot length of output format 48fs.
Typ
16.9344
*1
29.5
*1
29.5
*1
2.1168
*1
236.2
*1
236.2
*1
Max unit
MHz
ns
ns
MHz
ns
ns
50 ns
50 ns
50 ns
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Compressed Audio Signal Processor IC

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LC786820E
Stream Data Input/Output Function
There are 2 ways to input/output the stream data.
(1) 4-wire method
Stream Input
: During STREQO="H" output, input STLRCKI/STBCKI/STDATI.
In the case of 4-wire method, STLRCKI/STBCKI/STDATI (input state) are normal audio
inputs/outputs. As same as the format, 4byte (32bit) data transmission/reception is done in one
period of STLRCKI (input state).
(2) 3-wire method
Stream Input : Input STBCKI/STDATI while STREQO="H" output.
Stream Output : Output STBCKO/STDATO while STREQI="H" input.
In the case of 3-wire method, depending on the state of STREQO, only inputs the bit clock and
data, or depending on the state of STREQI, only outputs the bit clock and data, and data
communication unit becomes 2byte (16bit). Also in the 3-wire method of the stream output, it is
possible that users just input the clock (STBCKI) and it will output the data only.
- Characteristics of Stream Data Input Timing
STREQO
(Output)
tSLRH tSLRS
STLRCKI
(Input)
tSTCKIN
1/fSCI
tSTCKL tSTCKH
STBCKI
(Input)
STDATI
(Input)
tSTDSU tSTDHD
*Relationship between signal name and pin
STREQO : GP33/GP43/GP53
STLRCKI : GP30/GP40/GP50
STBCKI : GP31/GP41/GP51
STDATI : GP32/GP42/GP52
Note: When each pin is set as stream input simultaneously, they will be processed as below priority;
(1) GP30 to 33, (2) GP40 to 43, (3) GP50 to 53
For example, if set all pins to stream input mode, stream data will be processed on only data in GP30 to 33.
Data in GP40 to 43, GP 50 to 53 will not be processed in the LSI.
Parameter
Symbol
Signal Names
Min Typ Max unit
STBCKI Clock Frequency
fSCI
STBCKI
4.24 MHz
Stream Input Start Time
tSTCKIN
STREQO,
STBCKI, STLRCKI
50
ns
STBCKI "H" Period
tSTCKH
STBCKI
100
ns
STBCKI "L" Period
tSTCKL
STBCKI
100
ns
STLRCKI Set-Up Time
tSLRS STLRCKI, STBCKI 75
ns
STLRCKI Hold Time
tSLRH STLRCKI, STBCKI 75
ns
STDATI Set-Up Time
tSTDSU STDATI, STBCKI
75
ns
STDATI Hold Time
tSTDHD STDATI, STBCKI
75
ns
Note: Above diagram shows the case of data input at rising edge of STBCKI. The timing is the same if using
falling edge synchronization.
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Compressed Audio Signal Processor IC

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LC786820E
- Characteristics of Stream Data Output Timing: STBCK Output Mode
STREQI
(Input)
tSTOAT
tSTCOH tSTCOL
1/fSCO
tSTOFF
STBCKO
(Output)
STDATO
(Output)
tSDODL
*Relationship between signal name and pin
STREQI : GP33/GP43/GP53
STBCKO : GP31/GP41/GP51
STDATO : GP32/GP42/GP52
Parameter
Symbol
Signal Names
Min Typ
Max
unit
STBCKO Clock Frequency
fSCO
STBCKO
4.24 MHz
Stream Output Start Time
Stream Output Stop Time
STBCKO "H" Period
tSTOAT
tSTOFF
tSTCOH
STREQI, STBCKO
STREQI, STBCKO
STBCKO
100
(1/fSCO)
48
(1/fSCO)
48
ns
ns
ns
STBCKO "L" Period
tSTCOL
STBCKO
100
ns
STDATO Output Delay Time tSDODL STDATO, STBCKO
0
50 ns
Note: Above diagram shows the case of data input at rising edge of STBCKO. The timing is the same if using
falling edge synchronization.
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Compressed Audio Signal Processor IC

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LC786820E
- Characteristics of Stream Data Output Timing: STBCK Input Mode
STREQI
(Input)
STBCKI
(Input)
STDATO
(Output)
tSTBCKIN
*Relationship between signal name and pin
STREQI : GP33/GP43/GP53
STBCKI : GP31/GP41/GP51
1/fSTBCI
tSTBCKL tSTBCKH
tSTDODL
STDATO : GP32/GP42/GP52
Parameter
Symbol
Signal Names
STBCKI Clock Frequency fSTBCI
STBCKI
STBCKI Input Start Time tSTBCKIN
STREQI,
STBCKI
STBCKI "H" Period
tSTBCKH
STBCKI
STBCKI "L" Period
tSTBCKL
STBCKI
STDATO Output Delay
Time
tSTDODL
STBCKI,
STDATO
Note: Above diagram shows STBCKI is starting from “L”.
Min Typ
1000
400
400
Max
1.25
250
<Additional Information>
Clock input mode supports 2 types and data output timing changes as below accordingly;
(1) Starting from STBCKI="L"
STDATO will be output synchronizing with the rising edge of STBCKI.
(2) Starting from STBCKI="H".
STDATO will be output synchronizing with the falling edge of SBCKI.
Using each mode of (1) or (2) does not change the output characteristics.
unit
MHz
ns
ns
ns
ns
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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LC786820E
Internal Voltage Regulator at Ta=40 to 85C, DVSS=AVSS1=AVSS2=XVSS=0V
Parameter
Symbol
Condition
Min Typ Max
Output Voltage
DVDD12 VDD1=3.0 to 3.6V
1.08 1.20 1.32
Load current
Iope VDD1=3.3V
200
Note : The specification of “load current” above is sum of the load current of two internal voltage regulator.
Example of 1.2V regulator circuit
Unit
V
mA
LC786820E
DVDD
DVSS
DVDD12
100F
C1
* Same circuit need to be mounted both for two regulator pins.
(No.44 and No.87)
* C1 is for capacitor to stop oscillation.
There is a possibility of oscillation due to temperature change and etc., so C1
must be greater than 50F and low ESR at the operational temperature.
(The recommended value is 100F)
Parameter
Output Voltage
Load current
Symbol
DVDD18
Iope
Condition
VDD1=3.0 to 3.6V
VDD1=3.3V
Min Typ Max
1.65 1.80 1.95
50
Unit
V
mA
Example of 1.8V regulator circuit
LC786820E
DVDD
DVSS
DVDD18
100F
C1
* Build a circuit shown at left for the regulator pin No. 90.
* C1 is for capacitor to stop oscillation.
There is a possibility of oscillation due to temperature change and etc., so C1
must be greater than 50F and low ESR at the operational temperature.
(The recommended value is 100F)
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LC786820E (ON Semiconductor)
Compressed Audio Signal Processor IC

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Oscillator
Example circuit for Oscillator
LC786820E
LC786820E
XVDD
XIN
XOUT
XVSS
Rd1
C1
C1
XIN/XOUT: 12.0000MHz
For System Main clock and USB control
Recommended Oscillator
Nihon Dempa Kogyo Co., Ltd.
Type
NX3225GA
Frequency
12MHz
Recommended constants
Rd1=1k, C1=12pF
<Notes>
Because the characteristics of oscillator could be changed according to the circuit board, ask evaluation with the
individual original circuit board to the oscillator maker.
The precision of oscillator used in XIN/ XOUT should meet the USB standard.
If oscillation clock is disturbed by noise or by the other factors, it may lead to operation failure. Hence, make
sure to connect resistor and capacitor for oscillation circuit as close as XIN/ XOUT and the wire should be as
short as possible. Also needs to select parts with caution so as to obtain stable external constant value within the
guaranteed operating temperature range because the variation of external constant due to temperature change
could affect the oscillation precision
About internal circuit for XIN/XOUT, refer to the "Analog Pin Internal Equivalent Circuits" section
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