74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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PRESETTABLE BCD/DECADE
UP/DOWN COUNTERS
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTERS
The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421)
Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16
Binary Counter. State changes of the counters are synchronous with the
LOW-to-HIGH transition of the Clock Pulse input.
An asynchronous Parallel Load (PL) input overrides counting and loads the
data present on the Pn inputs into the flip-flops, which makes it possible to use
the circuits as programmable counters. A Count Enable (CE) input serves as
the carry / borrow input in multi-stage counters. An Up / Down Count Control
(U/D) input determines whether a circuit counts up or down. A Terminal Count
(TC) output and a Ripple Clock (RC) output provide overflow/underflow
indication and make possible a variety of methods for generating
carry / borrow signals in multistage counter applications.
Low Power . . . 90 mW Typical Dissipation
High Speed . . . 25 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Parallel Load
Individual Preset Inputs
Count Enable and Up/ Down Control Inputs
Cascadable
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
16
P0
15
CP
14
RC
13
TC
12
PL
11
P2
10
P3
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
P1
2
Q1
3
Q0
4
CE
5
U/D
6
Q2
7
Q3
8
GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
CE Count Enable (Active LOW) Input
1.5 U.L.
0.7 U.L.
CP Clock Pulse (Active HIGH going edge) Input 0.5 U.L. 0.25 U.L.
U / D Up/Down Count Control Input
0.5 U.L.
0.25 U.L.
PL Parallel Load Control (Active LOW) Input
0.5 U.L.
0.25 U.L.
Pn Parallel Data Inputs
Qn Flip-Flop Outputs (Note b)
RC Ripple Clock Output (Note b)
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
TC Terminal Count Output (Note b)
10 U.L. 5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
FAST AND LS TTL DATA
5-341
SN54/74LS190
SN54/74LS191
PRESETTABLE BCD/ DECADE
UP/ DOWN COUNTERS
PRESETTABLE 4-BIT BINARY
UP/ DOWN COUNTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
11 15 1 10 9
5
4
14
PL
U/D
P0 P1 P2
P3
RC
CE
CP
Q0 Q1
TC
Q2 Q3
32 6 7
VCC = PIN 16
GND = PIN 8
13
12


74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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SN54/74LS190 SN54/74LS191
STATE DIAGRAMS
0123
15
14
13
12 11 10
9
LS190
4
5
6
7
8
UP:
DOWN:
LS190
⋅ ⋅TC = Q0 Q3 (U/D)
⋅ ⋅ ⋅ ⋅TC = Q0 Q1 Q2 Q3 (U/D)
UP:
DOWN:
LS191
⋅ ⋅ ⋅ ⋅TC = Q0 Q1 Q2 Q3 (U/D)
⋅ ⋅ ⋅ ⋅TC = Q0 Q1 Q2 Q3 (U/D)
COUNT UP
COUNT DOWN
0123
15
14
13
12 11 10
9
LS191
4
5
6
7
8
LOGIC DIAGRAMS
CP U/D
14 5
P0
15
CE
4
P1
1
P2
10
P3
9
PL
11
13 12
RC TC
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
J CLOCK K
PRESET CLEAR
QQ
3
Q0
J CLOCK K
PRESET CLEAR
QQ
J CLOCK K
PRESET CLEAR
QQ
26
Q1
Q2
DECADE COUNTER
LS190
J CLOCK K
PRESET CLEAR
QQ
7
Q3
FAST AND LS TTL DATA
5-342


74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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SN54/74LS190 SN54/74LS191
LOGIC DIAGRAMS (continued)
CP U/D
14
5
P0
15
CE
4
P1
1
P2
10
P3
9
PL
11
13
12
RC
TC
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
J CLOCK K
PRESET CLEAR
QQ
3
Q0
J CLOCK K
PRESET CLEAR
QQ
2
Q1
J CLOCK K
PRESET CLEAR
QQ
6
Q2
BINARY COUNTER
LS191
J CLOCK K
PRESET CLEAR
QQ
7
Q3
FAST AND LS TTL DATA
5-343


74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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SN54/74LS190 SN54/74LS191
FUNCTIONAL DESCRIPTION
The LS190 is a synchronous Up / Down BCD Decade
Counter and the LS191 is a synchronous Up / Down 4-Bit
Binary Counter. The operating modes of the LS190 decade
counter and the LS191 binary counter are identical, with the
only difference being the count sequences as noted in the
state diagrams. Each circuit contains four master / slave
flip-flops, with internal gating and steering logic to provide
individual preset, count-up and count-down operations.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information present
on the Parallel Data inputs (P0 – P3) is loaded into the counter
and appears on the Q outputs. This operation overrides the
counting functions, as indicated in the Mode Select Table.
A HIGH signal on the CE input inhibits counting. When CE is
LOW, internal state change are initiated synchronously by the
LOW-to-HIGH transition of the clock input. The direction of
counting is determined by the U/D input signal, as indicated in
the Mode Select Table. When counting is to be enabled, the
CE signal can be made LOW when the clock is in either state.
However, when counting is to be inhibited, the LOW-to-HIGH
CE transition must occur only while the clock is HIGH.
Similarly, the U / D signal should only be changed when either
CE or the clock is HIGH.
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the count-down
mode or reaches maximum (9 for the LS190, 15 for the LS191)
in the count-up mode. The TC output will then remain HIGH
until a state change occurs, whether by counting or presetting
or until U / D is changed. The TC output should not be used as
a clock signal because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When CE
is LOW and TC is HIGH, the RC output will go LOW when the
clock next goes LOW and will stay LOW until the clock goes
HIGH again. This feature simplifies the design of multi-stage
counters, as indicated in Figures a and b. In Figure a, each RC
output is used as the clock input for the next higher stage. This
configuration is particularly advantageous when the clock
source has a limited drive capability, since it drives only the
first stage. To prevent counting in all stages it is only necessary
to inhibit the first stage, since a HIGH signal on CE inhibits the
RC output pulse, as indicated in the RC Truth Table. A
disadvantage of this configuration, in some applications, is the
timing skew between state changes in the first and last stages.
This represents the cumulative delay of the clock as it ripples
through the preceding stages.
A method of causing state changes to occur simultaneously
in all stages is shown in Figure b. All clock inputs are driven in
parallel and the RC outputs propagate the carry / borrow
signals in ripple fashion. In this configuration the LOW state
duration of the clock must be long enough to allow the
negative-going edge of the carry / borrow signal to ripple
through to the last stop before the clock goes HIGH. There is
no such restriction on the HIGH state duration of the clock,
since the RC output of any package goes HIGH shortly after its
CP input goes HIGH.
The configuration shown in Figure c avoids ripple delays
and their associated restrictions. The CE input signal for a
given stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The simple
inhibit scheme of Figures a and b doesn’t apply, because the
TC output of a given stage is not affected by its own CE.
MODE SELECT TABLE
INPUTS
PL CE U / D CP
MODE
H LL
Count Up
H LH
Count Down
L X X X Preset (Asyn.)
H H X X No Change (Hold)
RC TRUTH TABLE
INPUTS
CE TC* CP
RC
OUTPUT
LH
H XX
X LX
H
H
* TC is generated internally
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
= LOW-to-HIGH Clock Transition
= LOW Pulse
FAST AND LS TTL DATA
5-344


74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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SN54/74LS190 SN54/74LS191
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
Guaranteed Input HIGH Voltage for
V All Inputs
54
VIL Input LOW Voltage 74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
2.5 3.5
2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIH
V IOL = 8.0 mA per Truth Table
Input HIGH Current
Other Inputs
IIH CE
Other Inputs
CE
20 µA VCC = MAX, VIN = 2.7 V
60
0.1
0.3
mA VCC = MAX, VIN = 7.0 V
Input LOW Current
IIL Other Inputs
CE
– 0.4 mA VCC = MAX, VIN = 0.4 V
– 1.2
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
35
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
mA VCC = MAX
FAST AND LS TTL DATA
5-345


74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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SN54/74LS190 SN54/74LS191
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
PL to Output Q
Data to Output Q
Clock to RC
Clock to Output Q
Clock to TC
U / D to RC
U / D to TC
CE to RC
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
tW
ts
th
trec
Parameter
CP Pulse Width
PL Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Limits
Min Typ Max
20 25
22 33
33 50
20 32
27 40
13 20
16 24
16 24
24 36
28 42
37 52
30 45
30 45
21 33
22 33
21 33
22 33
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Min Typ Max
25
35
20
5.0
40
Unit
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) is defined as the minimum time required for
the correct logic level to be present at the logic input prior to the
clock transition from LOW-to-HIGH in order to be recognized
and transferred to the outputs.
HOLD TIME (th) is defined as the minimum time following the
clock transition from LOW-to-HIGH that the logic level must be
maintained at the input in order to ensure continued recogni-
tion. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW-
to-HIGH and still be recognized.
RECOVERY TIME (trec) is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
FAST AND LS TTL DATA
5-346


74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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SN54/74LS190 SN54/74LS191
DIRECTION
CONTROL
ENABLE
CLOCK
U/D
CE
CP
RC
U/D
CE
CP
RC
U/D
CE
CP
RC
Figure a. n-Stage Counter Using Ripple Clock
DIRECTION
CONTROL
ENABLE
U/D
CE
CP
RC
U/D
CE
CP
RC
U/D
CE
CP
RC
CLOCK
Figure b. Synchronous n-Stage Counter Using Ripple Carry / Borrow
DIRECTION
CONTROL
ENABLE
CLOCK
U/D
CE
CP
TC
U/D
CE
CP
TC
U/D
CE
CP
TC
Figure c. Synchronous n-Stage Counter with Parallel Gated Carry / Borrow
FAST AND LS TTL DATA
5-347


74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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SN54/74LS190 SN54/74LS191
AC WAVEFORMS
CP
1.3 V
Q OR TC
1/f MAX
tW
tPHL
1.3 V
tPLH
1.3 V
1.3 V
Figure 1
CP OR CE
RC
1.3 V
tPHL
1.3 V
Figure 2
1.3 V
tPLH
1.3 V
Pn
tPHL
Qn
1.3 V
1.3 V
1.3 V
tPLH
NOTE: PL = LOW
Figure 3
PL
CP
1.3 V
tW trec
1.3 V
Q
Figure 5
U/D
tPLH
TC
tPHL
RC
1.3 V
1.3 V
1.3 V
Figure 7
tPHL
1.3 V
tPLH
1.3 V
Pn
PL 1.3 V
tPLH
Qn
tW
1.3 V
Figure 4
tPHL
Pn 1.3 V
1.3 V
ts(H)
PL
th(H)
1.3 V
ts(L)
th(L)
1.3 V
Qn
Q=P
Q=P
* The shaded areas indicate when the input is permitted
* to change for predictable output performance
Figure 6
CP
CE
1.3 V
CE MAY
CHANGE
ts(L)
(HĆL)
only
th(L)
1.3 V
CE MAY
CHANGE
th(H)
ts(H)
1.3 V
Figure 8
FAST AND LS TTL DATA
5-348


74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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Case 751B-03 D Suffix
16-Pin Plastic
SO-16
-A-
16 9
-B-
P 0.25 (0.010) M
BM
1
8 PL
8
G
-T-
D16 PL
0.25 (0.010) M T B S
AS
C
SEATING
PLANE
K
R X 45°
MF
J
Case 648-08 N Suffix
16-Pin Plastic
-A-
16 9
B
18
F
C
S
-T-
SEATING
PLANE
L
H
G
D 16 PL
K
0.25 (0.010) M T A M
J
M
Case 620-09 J Suffix
-A- 16-Pin Ceramic Dual In-Line
16 9
-B-
18
CL
-T-
SEATING
PLANE
F
E
G
D 16 PL
N
0.25 (0.010) M T A S
K
M
J 16 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. 751BĆ01 IS OBSOLETE, NEW STANDARD
751BĆ03.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0°Ă
0.25
7°Ă
5.80
6.20
0.25
0.50
INCHES
MIN MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0°Ă
0.009
7°Ă
0.229
0.244
0.010
0.019
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5. ROUNDED CORNERS OPTIONAL.
6. 648Ć01 THRU Ć07 OBSOLETE, NEW STANDARD
648Ć08.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
MILLIMETERS
MIN MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
0°
7.74
10°
0.51
1.01
INCHES
MIN MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.070
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0°
0.305
10°
0.020
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
5. 620Ć01 THRU Ć08 OBSOLETE, NEW STANDARD
620Ć09.
DIM
A
B
C
D
E
F
G
J
K
L
M
N
MILLIMETERS
MIN MAX
19.05 19.55
6.10
7.36
Ċ 4.19
0.39
0.53
1.27 BSC
1.40
1.77
2.54 BSC
0.23
0.27
Ċ 5.08
7.62 BSC
0° 15°
0.39
0.88
INCHES
MIN MAX
0.750
0.770
0.240
0.290
Ċ 0.165
0.015
0.021
0.050 BSC
0.055
0.070
0.100 BSC
0.009
0.011
Ċ 0.200
0.300 BSC
0° 15°
0.015
0.035
FAST AND LS TTL DATA
5-349


74LS191 (Motorola)
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
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FAST AND LS TTL DATA
5-350




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