YDA147 Datasheet PDF - YAMAHA CORPORATION

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YDA147
YAMAHA CORPORATION

Part Number YDA147
Description STEREO 5W-15W DIGITAL AUDIO POWER AMPLIFIER
Page 30 Pages


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YDA147
D- 515
STEREO 5W-15W DIGITAL AUDIO POWER AMPLIFIER
Overview
YDA147 (D-515) is a high-efficiency digital audio power amplifier IC with the maximum output of 15W × 2ch.
YDA147 has a “Pure Pulse Direct Speaker Drive Circuit” that directly drives speakers while reducing distortion of
pulse output signal and reducing noise on the signal, which realizes the highest standard low distortion rate
characteristics and low noise characteristics among digital amplifier ICs in the same class.
In addition, supporting filterless design allows circuit design with fewer external parts to be realized depending on use
conditions.
YDA147 features Power Limit Function, Non-clip Function, and DRC (Dynamic Range Control) Function that were
developed by Yamaha original digital amplifier technology.
YDA147 has overcurrent protection function for speaker output terminals, high temperature protection function, and
lowsupply voltage malfunction prevention function.
Features
Operating supply voltage range
PVDD: 8.0V to 16.5V
Maximum momentary output
20 W×2ch (VDDP=14V, RL=4, THD+N=10%)
15 W×2ch (VDDP=12V, RL=4, THD+N=10%)
Maximum continuous output
15 W*1×2ch
10.5W*1×2ch
(VDDP=15V, RL=8, THD+N=10%, Ta=70°C)
(VDDP=15V, RL=4, THD+N=10%, Ta=25°C)
Distortion Rate (THD+N)
0.01 % (VDDP=12V, RL=8, Po=0.1W, 1kHz)
Residual Noise
48µVrms (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
Efficiency
92 % (VDDP=12V, RL=8)
S/N Ratio
105 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
Channel separation
-80 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
PSRR
60dB (VDDP=12V,Vripple=100mV, 1kHz, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
Non-clip function/DRC function (switchable)
Power limit function
Clock External Synchronization Function
Master/Slave Synchronization Function using clock outputs
Over-current Protection Function, High Temperature Protection Function,
Low Voltage Malfunction Prevention Function, and DC Detection Function
Sleep Function using SLEEPN terminal and Output Mute Function using MUTEN terminal
Stereo/Monaural Switching Function
Spread Clock Function
Pop Noise Reduction Function
Package
Lead-free 48-pin Plastic SQFP (Exposed stage)
Note) *1: A value based on Yamaha's board implementation conditions (See Note *2 of page 25)
YDA147 CATALOG
CATALOG No.:LSI-4DA147A41
2007.9



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Terminal Configuration
YDA147
< 48-pin SQFP Top View >
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YDA147
Terminal Function
(Note) *1
*2
*3
*4
No. Name *4) I/O *1), *2), *3)
Function
1 NC
Normally, use this terminal in no-connection
2 NC
Normally, use this terminal in no-connection
3 PVDDREG
PVDD
Power supply terminal for regulators
4 AVDD
OA 3.3V regulator output terminal
5 INLP
IA Analog input terminal (Lch+)
6 INLM
IA Analog input terminal (Lch-)
7 VREF
OA Reference voltage output terminal
8 INRM
IA Analog input terminal (Rch-)
9 INRP
IA Analog input terminal (Rch+)
10 AVSS
GND
Analog ground terminal
11 PLIMIT
IA Power limit setting terminal
12 NC
Normally, use this terminal in no-connection
13 PVDDPR
PVDD
Power supply terminal for digital amplifier output (Rch+)
14 PVDDPR
PVDD
Power supply terminal for digital amplifier output (Rch+)
15 OUTPR
O Digital amplifier output terminal (Rch+)
16 OUTPR
O Digital amplifier output terminal (Rch+)
17 OUTPR
O Digital amplifier output terminal (Rch+)
18 PVSSR
GND
Ground terminal for digital amplifier output (Rch)
19 PVSSR
GND
Ground terminal for digital amplifier output (Rch)
20 OUTMR
O Digital amplifier output terminal (Rch-)
21 OUTMR
O Digital amplifier output terminal (Rch-)
22 OUTMR
O Digital amplifier output terminal (Rch-)
23 PVDDMR
PVDD
Power supply terminal for digital amplifier output (Rch-)
24 PVDDMR
PVDD
Power supply terminal for digital amplifier output (Rch-)
25 NC
Normally, use this terminal in no-connection
26 SLEEPN
I Sleep control terminal
27 PROTN
O/D Error flag output terminal
28 MUTEN
I MUTE control terminal
29 CKOUT
O Clock output terminal for synchronization
30 CKIN
I External clock input terminal
31 NCDRC0
I Non-clip/DRC1/DRC2 mode selection terminal 0
32 NCDRC1
I Non-clip/DRC1/DRC2 mode selection terminal 1
33 GAIN0
I GAIN setting terminal 0
34 GAIN1
I GAIN setting terminal 1
35 NC
Normally, use this terminal in no-connection
36 NC
Normally, use this terminal in no-connection
37 PVDDML
PVDD
Power supply terminal for digital amplifier output (Lch-)
38 PVDDML
PVDD
Power supply terminal for digital amplifier output (Lch-)
39 OUTML
O Digital amplifier output terminal (Lch-)
40 OUTML
O Digital amplifier output terminal (Lch-)
41 OUTML
O Digital amplifier output terminal (Lch-)
42 PVSSL
GND
Ground terminal for digital amplifier output (Lch)
43 PVSSL
GND
Ground terminal for digital amplifier output (Lch)
44 OUTPL
O Digital amplifier output terminal (Lch+)
45 OUTPL
O Digital amplifier output terminal (Lch+)
46 OUTPL
O Digital amplifier output terminal (Lch+)
47 PVDDPL
PVDD
Power supply terminal for digital amplifier output (Lch+)
48 PVDDPL
PVDD
Power supply terminal for digital amplifier output (Lch+)
I: Input terminal, O: Output terminal, A: Analog terminal, O/D: Open/Drain output terminal
PVDD should be connected each other on a board.
GND should be connected each other on a board.
Each output terminal with the same name (OUTPR, OUTMR, OUTPL, and OUTML) should be connected on a
board.
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Block Diagram
YDA147
4



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