X25170 Datasheet PDF - ICMIC


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X25170
ICMIC

Part Number X25170
Description SPI Serial E2PROM
Page 15 Pages

X25170 datasheet pdf
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This X25170 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmicTM
IC MICROSYSTEMS
16K
X25170
2K x 8 Bit
SPI Serial E 2PROM with Block Lock Protection
FEATURES
•5MHz Clock Rate
•SPI Modes (0,0 & 1,1)
•2K X 8 Bits
—32 byte page mode
•Low Power CMOS
—<1µA standby current
—<5mA active current
•2.5V To 5.5V Power Supply
•Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM array
Built-In Inadvertent Write Protection
—Power-up/power-down protection circuitry
—Write enable latch
—Write protect pin
•Self-Timed Write Cycle
—5ms write cycle time (typical)
•High Reliability
—Endurance: 100,000 cycles
—Data retention: 100 Years
—ESD protection: 2000V on all pins
•8-Lead PDlP Package
•8-Lead SOIC Package
14-Lead TSSOP Package
DESCRIPTION
The X25170 is a CMOS 16384-bit serial E2PROM,
internally organized as 2K x 8. The X25170 features a
Serial Peripheral Interface (SPI) and software protocol,
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25170 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25170 will ignore transitions on its
inputs, thus allowing the host to service higher prior-
ity interrupts. The WP input can be used as a hardwire input
to the X25170 (disabling all write attempts to the
status register), thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25170 utilizes Xicor’s proprietary Direct Write cell,
providing a minimum endurance of 100,000 cycles and a
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minimum data retention of 100 years.
BLOCK DIAGRAM
Status
Register
SO
SI
SCK
CS
HOLD
Command
Decode
and
Control
Logic
Write
Protect
Logic
Write
Control
and
WP
Timing
Logic
Direct Writeand Block LockProtection is a trademark of Xicor, Inc.
©Xicor, Inc. 2000 Patents Pending
9900-5004.9 5/26/00 EP
X Decode
Logic
16
2K Byte
Array
16 X 256
16
16 X 256
32
32 X 256
32 8
Y Decode
Data Register
Characteristics subject to change without notice. 1 of 15
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X25170
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
It should be noted that after power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
When CS is HIGH, the X25170 is deselected and the
SO output pin is at high impedance; unless an internal
write operation is underway, the X25170 will be in the
standby power mode. CS LOW enables the X25170,
placing it in the active power mode.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25170 status register are dis-
abled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25170 status reg-
ister. If the internal write cycle has already been initi-
ated, WP going LOW will have no effect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25170 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “1”.
Pin Names
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
NC
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
PIN CONFIGURATION
DIP/SOIC
CS 1
8 VCC
SO 2
7 HOLD
WP 3 X25170 6 SCK
VSS
4
5 SI
TSSOP
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CS 1
SO 2
14 VCC
13 HOLD
NC 3
12
NC 4 X25170 11
NC
NC
NC 5
10 NC
WP 6
VSS 7
9 SCK
8 SI
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
Characteristics subject to change without notice. 2 of 15
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X25170
PRINCIPLES OF OPERATION
The X25170 is a 2K x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25170 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising SCK. CS must be LOW and the HOLD
and WP inputs must be HIGH during the entire opera-
tion. The WP input is “don’t care” if WPEN is set “0”.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25170 into a “PAUSE” condition. After releasing
HOLD, the X25170 will resume operation from the
point when HOLD was first asserted.
Write Enable Latch
The X25170 contains a “write enable” latch. This latch
must be SET before a write operation will be com-
pleted internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status reg-
ister write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7 654 3 2 1 0
WPEN X X X BL1 BL0 WEL WIP
WPEN, BP0 and BP1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
The Write-In-Process (WIP) bit indicates whether the
X25170 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25170 is divided into four 4096-bit seg-
ments. One, two, or all four of the segments may be
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protected. That is, the user may read the segments but
will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated in
the following table.
Status Register Bits
BP1 BP0
00
01
10
11
Array Addresses
Protected
None
$0600–$07FF
$0400–$07FF
$0000–$07FF
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
0000 0110
Set the write enable latch (enable write operations)
WRDI
0000 0100
Reset the write enable latch (disable write operations)
RDSR
0000 0101
Read status register
WRSR
0000 0001
Write status register
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address (1 to 32 Bytes)
Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Characteristics subject to change without notice. 3 of 15
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X25170
Write-Protect Enable
The Write-Protect-Enable (WPEN) bit is available for
the X25170 as a nonvolatile enable bit for the WP pin.
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register con-
trol the programmable hardware write protect feature.
Hardware write protection is enabled when WP pin is
LOW, and the WPEN bit is “1”. Hardware write protec-
tion is disabled when either the WP pin is HIGH or the
WPEN bit is “0”. When the chip is hardware write pro-
tected, nonvolatile writes are disabled to the Status
Register, including the Block Protect bits and the
WPEN bit itself, as well as the block-protected sections
in the memory array. Only the sections of the memory
array that are not block-protected can be written.
Note: Since the WPEN bit is write protected, it cannot
be changed back to a “0”, as long as the WP pin is held
LOW.
WPEN
0
0
1
1
X
X
WP
X
X
LOW
LOW
HIGH
HIGH
WEL
0
1
0
1
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25170, followed by the
16-bit address of which the last 11 are used. After the
READ opcode and address are sent, the data stored in
the memory at the selected address is shifted out on the
SO line. The data stored in memory at the next address
can be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($07FF), the
addresswww.DataSheet.co.kr counter rolls over to address $0000, allowing
the read cycle to be continued indefinitely. The read
operation is terminated by taking CS HIGH. Refer to the
read E2PROM array operation sequence illustrated in
Figure 1.
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the con-
tents of the status register are shifted out on the SO
line. The read status register sequence is illustrated in
Figure 2.
Characteristics subject to change without notice. 4 of 15
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