UPD7800 Datasheet PDF - NEC Electronics

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UPD7800
NEC Electronics

Part Number UPD7800
Description High End Single Chip 8-Bit Microcomputer
Page 11 Pages


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NEe Microcomputers, Inc.
NEe
JLPD7800
DESCRIPTION
HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
ROM-LESS DEVELOPMENT DEVICE
The NEC tlPD7800 is an advanced 8-bit general purpose single-chip microcomputer
fabricated with N-channel Silicon Gate MOS Technology_ Intended as a ROM-less
development device for NEC tlPD7801/7802 designs, the tlPD7800 can also be used
as a powerful microprocessor in volume production enabling program memory flexi-
bility_ Basic on-chip functional blocks include 128 bytes of RAM data memory, 8-bit
ALU, 32 I/O lines, Serial I/O port, and 12-bit timer. Fully compatible with the
industry standard 8080A bus structure, expanded system operation can be easily
implemented using any of 8080A/8085A peripheral and memory products. Total
memory address space is 64K bytes.
FEATU RES
NMOS Silicon Gate Technology Requiring Single +5V Supply.
• Single-Chip Microcomputer with On-Chip ALU. RAM and I/O
- 128 Bytes RAM
- 32 I/O Lines
• Internal 12-Bit Programmable Timer
• On-Chip 1 MHz Serial Port
• Five-Level Vectored, Prioritized Interrupt Structure
- Serial Port
- Timer
- 3 External Interrupts
• Bus Expansion Capabilities
- Fully 8080A Bus Compatible
;- 64K Byte Memory Address Range
• Wait State Capability
• Alternate Z80™ Type Register Set
• Powerful 140 Instruction Set
• 8 Address Modes; Including Auto-Increment/Decrement
• Multi-Level Stack-Capabilities
• Fast 2 tls Cycle Time
• Bus Sharing Capabilities
PIN CONFIGURATION
AS,!
rr
DB-
DBt
DB!
DB.
D8~
DB;
DB
DB,
INT:
INT·
INT(
WAii
M
WR
m:
PCj
PC,
PC,
PC,
PC,
PC2
PC,
PCo
S'CK
SI
SO
Jmri'
STB
X,
Vss lov)
Vee (+5V)
AB'4
AB'3
A8'2
AB11
AB'0
ABO
ABB
AB7
AB.
ABS
AB,
ABJ
'B2
AB,
ABO
PB7
PBS
PBs
PB,
PBJ
PB2
PB,
PBo
PA7
PA6
PAS
PA,
PA,
PA2
PA,
PAo
239



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p.PD7800
PIN NO.
1,49·63
2
DESIGNATION
EAXBTO·AB1.5
3·10 DBO-DB7
11 INTO
12 INTl
13 INT2
14 WAIT
15 Ml
16 WR
17 RD
18-25
26
PCO-PC7
SCK
27 SI
28 SO
29 RESET
30 STB
31
33-40
41-48
Xl
PAO-PA7
PBO-PB7
FUNCTION
(Tri·State, Output) 16·bit address bus.
(Output) EXT is used to simulate IIPD780111802
external memory reference operation. EXT distin-
guishes between internal and external memory
references, and goes low when locations 4096
through 65407 are accessed.
(Tri-State Input/Output, active high) 8-bit true
bi-directional data bus used for external data
exchanges with I/O and memory.
(Input, active high) Level-sensitive interrupt input.
(Input, active high) Rising-edge sensitive interrupt
input. Interrupts are initiated on low-to-high transi-
tions, providing interrupts are enabled.
(Input) INT2 is an edge sensitive interrupt input
where the desired activation transition is pro-
grammable. By setting the ES bit in the Mask
Register'to a 1, INT2 is rising edge sensitive. When
ES is set to 0, INT2 is falling edge sensitive.
(Input, active low) WAIT, when active, extends
read or write timing to interface with slower
external memory or I/O. WAIT is sampled at
the end of T2, if active processor enters a wait
state TW and remains in that state as long as
WAIT is active.
(Output, active high) when active, Ml indicates
that the current machine cycle is an OP CODE
FETCH.
(Tri-State Output, active low) WR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external memory or I/O write
operations. WR goes to the high impedance state
during HALT, HOLD, or RESET.
(Tri-State Output, active low) Rij is used as a
strobe to ~e data from external devices on the
data bus. RD goes to the high impedance state
during HALT, HOLD, and RESET.
(Input/Output) 8-bit I/O configured as a nibble
I/O port or as control lines.
(Input/Output) SCK provides control clocks for
Serial Port Input/Output operations. Data on the
SI line is clocked into the Serial Register on the ris-
ing edge. Contents of the Serial Register is clocked
onto SO line on falling edges.
(Input) Serial data is input to the processor
through theSI line. Data is clocked into the Serial
Register MSB to LSB with the rising edge of SCK.
(Output) SO is the Serial Output Port. Serial data
is output on this \.ine on the falling edge of SCK,
MSB to LSB.
(Input, active low) RESET initializes the IIPD7801.
(Output) Used to simulate IIPD7801 Port E opera-
tion, indicating that a Port E operation is being
performed when active.
(I nput) Clock Input
(Output) 8-bit output port with latch capability.
(Tri-State Input/Output) 8-bit programmable I/O
port. Each line configurable independently as an
input or output.
PIN DESCRIPTION
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BLOCK DIAGRAM
. f - - - - l,NToo---.....
I N T 1 o - - -. . . . .- t
INT2o-----t
INT
CONTROL
INC/DEC
PC
OP
VA
C
0
H
VA
C
0
l MAIN
IG.A.
} ALT
G.R.
DATA
MEMORY
(128 BYTE)
jLPD7800
,. .~
ill
'"
AB6-16
ABQ..7
SIO----~~
S---C---K--~~SIO
0004~-----------J
PC3JSAK~
INST
DECODER
PA7-O
PC71 PCfj
HOLD HLDA
M1
Vee Vss x,
241



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}lJPD7800
Architecturally consistent with ,uPD7801/7802 devices, the ,uPD7800 uses a slightly
different pin-out to accommodate for the adEJfe~s bus and lack of on-chip clock
generator. For complete ,uPD7800 functional operation, please refer to ,uPD7801
product information. Listed below are function'aIi differences that exist between
,uPD7800 and ,uPD7801 dey ices.
,uPD7800/7801 Functional Differences
FUNCTIONAL DESCRIPTION
1. The functionality of ,uPD7801 Port E is somewhat different on the ,uPD7800_
Because the ,uPD7800 contains no progrilm memory, the address bus is made
accessible to address external prQgram memory. Thus, lines normally used for Port
E operation with the ,uPD7801 are used as the address bus on the ,uPD7800. ABO-
AB15 is active during memory access O~hrough 4095.
2. Consequently Port E instructions (PEX,-pEN, and PER) have different
functionality.
PEX Instruction - The contents of Band C register are output to the address bus.
The value 01 H is output to the data bus. STB becomes active.
PEN Instruction - B and ~>'register contents are output to the address bus. The
value 02H is output to the data bus. STB becomes active.
PER Instruction - The address bus goes to the high impedance state. The value
04H is output to the data bus. STB becomes active.
3. ON-CHIP CLOCK GENERATOR. The ,uPD7800 contains no internal clock gener-
ator. An external clock source is input to the Xl input.
4. PIN 30. This pin functions as the X:2;Crystal connection on the ,uPD7801. On the
,uPD7800, pin 30 functions as a strobe output (STB) and becomes active when a
Port E instruction is executed. This;~ontrol signal is useful in simulating ,uPD7801
Port E operation - indicating that a port E operation is being performed.
5. PIN 2. Functions as the 1> out clock output used for synchronizing system external
memory and I/O devices, on the ,uPD7801. On the ,uPD7800, this pin is used to
simulate external memory reference operation of the ,uPD7801. EXT is used to
distinguish between internal and external memory references and goes low when
location 4096 through 65407 are accessed.
RECOMMENDED CLOCK DRIVE CIRCUIT,.
200pF
I
242



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